FPGA-based polar coordinate format algorithm SAR imaging method

Abstract

This invention proposes a SAR imaging implementation method based on FPGA polar coordinate format algorithm for small UAV-borne SAR imaging processing, solving the problems of light payload, low power consumption, and fast calculation speed required for small platforms. The method includes the following steps: (1) calculating interpolation parameters; (2) performing range sinc interpolation calculation; (3) performing azimuth sinc interpolation calculation; (4) performing two-dimensional IFFT imaging; and (6) transmitting the imaging result data back to the host computer via Ethernet. This invention designs a reusable multi-channel parallel interpolation module that can obtain two sets of interpolation data in a single cycle and perform interpolation operations. The multi-channel interpolation kernel designed in this method ensures imaging accuracy while doubling the single interpolation speed compared to traditional schemes, and increasing the overall imaging speed by four times.

Description

Technical Field

[0001] This invention relates to an FPGA implementation method for a linear frequency modulated signal polar coordinate format imaging algorithm, belonging to the field of SAR imaging technology and field programmable logic device application field, and can be applied to real-time imaging of micro airborne spotlight SAR. Background Technology

[0002] Synthetic Aperture Radar (SAR) can acquire high-resolution ground images in all weather conditions and at all times, and has been widely used in both military and civilian fields. It is one of the most important development directions in modern radar technology. Spotlight-mode SAR imaging, also known as point-to-point imaging, utilizes the adjustment of the directional antenna beam to ensure that the electromagnetic beam always illuminates almost the entire area of ​​a ground target, thus obtaining high-resolution images of a small, fixed area. Polar Format Algorithm (PFA) is a commonly used fast imaging algorithm in spotlight SAR imaging. PFA is implemented through two-dimensional interpolation and two-dimensional inverse Fourier transform. While the processing is relatively simple, the algorithm has a large computational load, reaching n... 2 class.

[0003] With the development of drones, SAR imaging systems have also begun to be applied to real-time imaging on micro-drone platforms. These platforms require SAR imaging processing systems to be small in size, low in power consumption, and high in imaging speed. FPGA, or Field Programmable Gate Array, is a fully customizable, low-level hardware programmable device without an operating system, making it very suitable for hardware platforms used in this type of algorithm processing.

[0004] For example, patent application CN 105866774 A, entitled "FPGA Implementation Method of Polar Coordinate Format Imaging Algorithm for Linear Frequency Modulation Signals," discloses an FPGA-based method for implementing polar coordinate format imaging. This method uses PCS scaling in the range direction and sinc interpolation in the azimuth direction to process the two-dimensional resampling calculation of the PFA algorithm, then uses two one-dimensional IFFTs to obtain the imaging result. While this method can improve the imaging computation speed compared to DSP and PC software platforms while ensuring imaging quality, the computational load of the PCS method is greater than that of sinc interpolation, and it is not suitable for parallel computing on FPGAs. This results in a significant amount of imaging time being consumed in the range direction PCS calculation. Furthermore, the azimuth direction cannot be resampled using PCS, requiring two completely different computation modules for range and azimuth resampling, wasting a crucial area in FPGA design specifications, and consequently leading to resource waste and difficulty in improving clock speed. Summary of the Invention

[0005] The purpose of this invention is to overcome the defects of the existing technology and propose a polar coordinate format algorithm SAR imaging method based on FPGA to solve the technical problems of slow two-dimensional resampling process, complex and redundant modules that cannot reuse interpolation kernels and slow imaging speed in the existing technology.

[0006] To achieve the above objectives, the technical solution adopted by the present invention includes the following steps:

[0007] (1) Constructing a Field Programmable Gate Array (FPGA):

[0008] A field-programmable gate array (FPGA) is constructed, comprising a PS system processing unit and a PL logic processing unit. The PS system processing unit includes a TCP / IP network interface, a hard disk ROM, an A53 processor, and DDR4 memory connected in sequence. The PL logic processing unit includes a first data interface, an interpolation packet matching and lookup core, an interpolation operation core, and a second data interface connected in sequence. The second data interface is also connected to an IFFT operation core. The first data interface includes three AXI4 bus drivers: AXI4_COORD_32b, AXI4_SKEW_32b, and AXI4_SIG_32b, as well as floating-point... The system includes a fixed-point core (float2fixed) and a synchronization buffer FIFO for receiving data. The synchronization buffer FIFOs for receiving data include FIFO_COORD_32b, FIFO_SKEW_32b, and FIFO_SIG_32b. The interpolation packet matching and lookup core includes two sets of synchronization buffer FIFOs for interpolation packets: FIFO_PACK0_512b, FIFO_SKEW0_16b and FIFO_PACK1_512b, FIFO_SKEW1_16b. The second data interface includes AXI4_W1_64b and AXI4_W2_64b.

[0009] (2) The PS system processing end receives and stores data:

[0010] The TCP / IP network interface in the PS system processing unit receives single-precision echo data, pulse frequency history f, and relative azimuth θ and elevation angles of the radar beam and the imaging scene from the host computer, as well as the synthetic aperture radar (SAR) data. And stored in the hard disk ROM;

[0011] (3) The PS system processing end calculates the interpolation parameters:

[0012] The A53 processor in the PS system's processing unit receives pulse frequency history f, azimuth angle θ, and elevation angle from the TCP / IP network interface. Calculate the range interpolation coordinates coord_ran and range interpolation offset skew_ran, as well as the azimuth interpolation coordinates coord_azi and azimuth interpolation offset skew_azi;

[0013]

[0014] skew_ran = diff_Px - coord_ran

[0015] diff_Px=(P_Kx×sec(θ)-ones(nrn,1)×Kr_plane(1,1:end)) / d_kx

[0016] P_Kx=Kx_start+n·(Kx_end-Kx_start) / (nrn-1)

[0017] Kr=4πf / c

[0018]

[0019] d_Kx=(Kr_plane(nrn,1)-Kr_plane(1,1)) / (nrn-1)

[0020] Where Kr is the spatial wavenumber frequency; Kr_plane is the spatial wavenumber frequency projected onto the ground; nrn is the number of range sampling points; d_Kx is the spatial frequency difference between adjacent sampling points; Kx_start and Kx_end are the minimum and maximum values ​​of the interpolated range spatial frequency; P_Kx is the spatial frequency of each sampling point after interpolation; n is an integer ranging from 0 to nrn-1; and diff_Px is the distance difference before and after interpolation for each sampling point.

[0021] (4) The PL logic processing interpolation core performs range interpolation calculations on the radar echo data:

[0022] (4a) The three AXI4 high-speed buses in the first data interface of the PL logic processing terminal read the SAR echo data, range interpolation coordinates coord_ran and interpolation offset skew_ran stored in the DDR4 memory of the PS system processing terminal, and convert the single-precision SAR echo data into fixed-point data through the floating-point to fixed-point core, and then write the fixed-point data, range interpolation coordinates coord_ran and range interpolation offset skew_ran into the synchronous buffer FIFO respectively;

[0023] (4b) The interpolation data packet matching and lookup kernel matches the distance read from the synchronization buffer FIFO to the interpolation coordinate coord_ran and outputs two sets of interpolation data packets to the buffer FIFO: FIFO_PACK0_512b, FIFO_SKEW0_16b and FIFO_PACK1_512b, FIFO_SKEW1_16b; FIFO_PACK0_512b and FIFO_PACK1_512b store radar echo data to be interpolated, and FIFO_SKEW0_16b and FIFO_SKEW1_16b store the offset during interpolation calculation;

[0024] (4c) The interpolation operation core reads two data packets to be interpolated from the buffer FIFO of the interpolation packet matching lookup core. First, it looks up the corresponding sinc interpolation coefficient according to the range interpolation offset skew_ran stored in FIFO_SKEW0_16b and FIFO_SKEW1_16b in the data packet. Then, it performs interpolation calculation with the radar echo data stored in FIFO_PACK0_512b and FIFO_PACK1_512b according to the coefficient to obtain the range interpolated echo data SIG_ITR_RAN.

[0025] (4d) The distance interpolation result SIG_ITR_RAN is written back to the DDR4 memory on the PS side in transposed non-contiguous address order through the two AXI4 buses AXI4_W1_64b and AXI4_W2_64b in the second data interface;

[0026] (5) The PL logic processing terminal performs interpolation calculations to verify the range-interpolated echo data and then performs azimuth-interpolation calculations:

[0027] (5a) Read the range-interpolated radar echo data SIG_ITR_RAN, azimuth-interpolated coordinates coord_azi, and interpolation offset skew_azi from the DDR4 memory of the PS system processing terminal through the three AXI4 buses in the first data interface, and write them to their respective synchronous buffer FIFOs at the same time.

[0028] (5b) The interpolation data packet matching and lookup kernel reads radar echo data SIG_ITR_RAN, azimuth interpolation coordinates coord_azi and interpolation offset skew_azi from the synchronization buffer of the first data interface, and simultaneously matches and outputs two sets of interpolation data packets based on the azimuth interpolation coordinates coord_azi and writes them into the buffer FIFO.

[0029] (5c) The interpolation operation core reads two data packets to be interpolated from the buffer FIFO of the interpolation packet matching lookup core. First, it looks up the corresponding sinc interpolation coefficient according to the azimuth interpolation offset skew_azi stored in FIFO_SKEW0_16b and FIFO_SKEW1_16b in the data packet. Then, it performs interpolation calculation based on the coefficient and the radar echo data SIG_ITR_RAN in the interpolation data packet to obtain the azimuth interpolated echo data SIG_ITR_AZI.

[0030] (5d) The azimuth interpolation result SIG_ITR_AZI is written back to DDR4 memory in sequential address mode through the two AXI4 buses AXI4_W1_64b and AXI4_W2_64b in the second data interface;

[0031] (6) The IFFT core of the PL logic processing terminal performs azimuth IFFT processing on the radar echo data after two-dimensional interpolation:

[0032] (6a) The IFFT core reads the interpolated phase data SIG_ITR_AZI from the DDR4 memory through the AXI4 bus AXI4_W1_64b and AXI4_W2_64b in the second data interface, performs azimuth IFFT calculation, and obtains the echo data SIG_IFFT_AZI after azimuth IFFT calculation.

[0033] (6b) Write the orientation IFFT calculation result SIG_IFFT_AZI back to DDR4 memory via the second data interface with a transposed non-contiguous address;

[0034] (7) Obtain SAR imaging results:

[0035] (7a) The IFFT core reads the phase data SIG_IFFT_AZI that has completed the azimuth IFFT operation in DDR4 through the AXI4 bus AXI4_W1_64b and AXI4_W2_64b in the second data interface, and performs range IFFT calculation to obtain the imaging data SIG_IFFT_RAN.

[0036] (7b) After writing the distance-to-IFFT calculation result SIG_IFFT_RAN back to DDR4 in sequential address manner through the second data interface, the PS system processing end sends the SIG_IFFT_RAN data to the host computer through the Ethernet network interface.

[0037] Compared with the prior art, the present invention has the following advantages:

[0038] First, the present invention designs a multi-parallel sinc interpolation calculation circuit in FPGA to solve the problem of resampling operation speed. Compared with the method of using both PCS and sinc interpolation, the overall imaging operation speed is increased by four times.

[0039] Secondly, compared with the method of using PCS to solve the distance interpolation problem, the present invention saves multiple FFT operation modules, making the hardware modules for distance and azimuth directions interchangeable, greatly reducing hardware resource consumption, improving resource reuse rate, and also facilitating FPGA layout and routing. Correspondingly, the system clock can work at a higher frequency, with a maximum clock frequency of 333MHz, which is 50% faster than the 200MHz operating frequency of other inventions. Attached Figure Description

[0040] Figure 1 This is a flowchart illustrating the implementation of the present invention.

[0041] Figure 2 This is a schematic diagram of the Field Programmable Gate Array (FPGA) structure of the present invention.

[0042] Figure 3 This is a measured waveform diagram of the AXI4 protocol for reading data according to the present invention.

[0043] Figure 4 This is a flowchart illustrating the interpolation package matching and lookup process of the present invention.

[0044] Figure 5 The interpolation package matching and verification waveform diagram is shown in the present invention.

[0045] Figure 6 This is an image showing the imaging results of the present invention. Detailed Implementation

[0046] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0047] Reference Figure 1 The present invention includes the following steps.

[0048] Step 1) Construct the FPGA system, the structure of which is as follows: Figure 2 As shown:

[0049] An FPGA is constructed comprising a PS system processing unit and a PL logic processing unit. The PS system processing unit includes sequentially connected DDR4 memory, an A53 processor, and a TCP / IP network interface. The PL logic processing unit includes sequentially connected first data interface, interpolation packet matching and lookup core, interpolation operation core, and second data interface. The second data interface is also connected to an IFFT operation core. The first data interface includes three AXI4 bus drivers: AXI4_COORD_32b, AXI4_SKEW_32b, and AXI4_SIG_32b; floating-point conversion... The system includes a fixed-point core (float2fixed), and synchronous buffer FIFOs for receiving data: FIFO_COORD_32b, FIFO_SKEW_32b, and FIFO_SIG_32b; an interpolation packet matching and lookup core comprising two sets of synchronous buffer FIFOs for interpolation packets: FIFO_PACK0_512b, FIFO_SKEW0_16b, FIFO_PACK1_512b, and FIFO_SKEW1_16b; and a second data interface comprising AXI4_W1_64b and AXI4_W2_64b.

[0050] The TCP / IP network interface on the PS side is responsible for receiving radar echo data, pulse frequency history f, and the aircraft's azimuth θ and pitch angles. Information: The A53 processor calculates the sinc interpolation parameters based on the pulse frequency history f and the aircraft's flight azimuth and pitch angle information. The interpolation parameters include the interpolation coordinates (coord) and the interpolation distance offset (skew). The PL logic processing unit incorporates a data interface for communication with the PS system processing unit, an interpolation data packet matching and lookup core, an interpolation operation core, and an IFFT operation core.

[0051] There are three core computing modules.

[0052] First, the interpolation packet matching and lookup core. The computational efficiency of this core determines the speed of interpolation packet lookup and the number of interpolation packets that can be sent to the interpolation operation core per clock cycle, directly affecting the overall interpolation speed and being the key to doubling the interpolation speed.

[0053] Second, the interpolation kernel. This kernel is based on the 8-point sinc interpolation method and performs sinc interpolation on the input multi-channel interpolation data packets. The interpolation data packet contains the 8 complex data points to be interpolated and the offset of the target distance to be bridged by this interpolation. The sinc function parameters for different offsets are pre-stored in registers, and the interpolation offset skew is the coordinate for looking up this table. The interpolation coefficient table is shown in Table 1.

[0054] Table 1

[0055] sinc(-4) sinc(-4 + 1 / 16) sinc(-4 + 2 / 16) sinc(-4 + 3 / 16) …… sinc(-4 + 15 / 16) sinc(-3) sinc(-3 + 1 / 16) sinc(-3 + 2 / 16) sinc(-3 + 3 / 16) …… sinc(-3 + 15 / 16) sinc(-2) sinc(-2 + 1 / 16) sinc(-2 + 2 / 16) sinc(-2 + 3 / 16) …… sinc(-2 + 15 / 16) sinc(-1) sinc(-1 + 1 / 16) sinc(-1 + 2 / 16) sinc(-1 + 3 / 16) …… sinc(-1 + 15 / 16) sinc(0) sinc(0 + 1 / 16) sinc(0 + 2 / 16) sinc(0 + 3 / 16) …… sinc(0 + 15 / 16) sinc(1) sinc(1 + 1 / 16) sinc(1 + 2 / 16) sinc(1 + 3 / 16) …… sinc(1 + 15 / 16) sinc(2) sinc(2 + 1 / 16) sinc(2 + 2 / 16) sinc(2 + 3 / 16) …… sinc(2 + 15 / 16) sinc(3) sinc(3 + 1 / 16) sinc(3 + 2 / 16) sinc(3 + 3 / 16) …… sinc(3 + 15 / 16)

[0056] Third, the IFFT kernel. This kernel uses the Fast Fourier Transform algorithm to perform inverse Fourier transforms in the range and azimuth directions on the interpolated phase matrices to obtain the final image phase matrix required by the PFA algorithm. The kernel takes 8 input channels, reads 8 complex data points at a time, and performs calculations using a 1024-point inverse Fourier transform.

[0057] Step 2) The PS system processing end receives and stores the data:

[0058] The FPGA receives raw SAR radar echo data, pulse frequency history, azimuth angle θ, and elevation angle of the aircraft and imaging scene from the host computer via a network interface. Stored to the hard drive; the radar parameters of this embodiment are shown in Table 2 below;

[0059] Table 2

[0060]

[0061]

[0062] The PS system uses the FAT32 file protocol to read the single-precision floating-point radar echo data from the hard drive into a specified address in the DDR4 memory.

[0063] Step 3) The PS system processing end calculates the interpolation parameters:

[0064] The PS system processing unit calculates the azimuth angle θ and elevation angle between the radar and the imaging area. The pulse frequency history f received by the radar is used to calculate the interpolated coordinate matrix coord and the interpolated offset matrix skew in the range and azimuth directions.

[0065] Step 3a) Calculate the spatial frequency difference between the distance and adjacent sampling points;

[0066] Kr=4πf / c

[0067]

[0068] d_Kx=(Kr_plane(nrn,1)-Kr_plane(1,1)) / (nrn-1)

[0069] Where f is the frequency history of each radar pulse; Kr is the spatial wavenumber frequency; denoted as the relative elevation angle between the radar wavenumber and the imaging scene; Kr_plane is the spatial wavenumber frequency projected onto the ground; nrn is the number of range sampling points; d_Kx is the spatial frequency difference between adjacent sampling points.

[0070] Step 3b) Calculate the spatial frequency of each sampling point after resampling;

[0071] P_Kx=Kx_start+i·(Kx_end-Kx_start) / (nrn-1)

[0072] diff_Px = (P_Kx × sec(θ) - ones(nrn,1) × Kr_plane(1,1:end)) / d_kx, where Kx_start and Kx_end are the minimum and maximum values ​​of the spatial frequency in the range direction after resampling; P_Kx is the spatial frequency of each sampling point after resampling; i is an integer ranging from 0 to nrn-1; and diff_Px is the distance difference before and after resampling at each sampling point.

[0073] Step 3c) Calculate the interpolation coordinate matrix coord and the interpolation deviation matrix skew for each interpolation point using the following formula;

[0074]

[0075] skew = diff_Px-coord

[0076] Step 4) The PL logic processing unit performs range interpolation calculations on the radar echo data:

[0077] Step 4a) Design the packet matching and lookup kernel:

[0078] For distance-to-sinc interpolation, the three AXI4 protocol interfaces in data interface 1 first read the phase data and interpolation parameters from DDR4. The phase complex data reading interface has a width of 512 bits and can read eight single-precision complex data points at a time; the interpolation coordinate and interpolation offset reading interface has a width of 32 bits and reads two 16-bit interpolation coordinate information points at a time. The actual waveform of the AXI4 protocol reading data is shown below. Figure 3 As shown. For single-precision floating-point complex data, it needs to go through 16 floating-point to fixed-point converters to convert 8 complex data points and 16 floating-point numbers into fixed-point data, facilitating multiplication and addition calculations by the interpolation kernel. Then, the fixed-point complex data, interpolation coordinates, and interpolation offsets are stored in their respective synchronous FIFOs for caching. When the interpolation packet matching lookup kernel detects data in the FIFO, it begins reading in the interpolation coordinates, phase complex data, and interpolation offsets. The operation process of the interpolation packet matching lookup kernel is as follows: Figure 4 As shown.

[0079] The core needs to accurately find the corresponding 8 interpolated complex data points within the complex data based on the currently read interpolated coordinates. The distribution of interpolated coordinates follows a certain regularity, always increasing or remaining constant in the current row or column, with an increment of no more than 2. Based on this, a high-speed matching method can be designed by caching data. The first 8 read complex data points can correspond to interpolated coordinate 3 (assuming the interpolation center of the 8-point interpolation is 3), but interpolated coordinate 4 requires the next 8 complex data points starting from the second complex data point. If a data warehouse is set up, storing 16 complex data points, then the 8 consecutive complex data points starting from the first can correspond to coordinates 3, 4, 5, 6, 7, 8, 9, and 10, respectively. When coordinate 11 is read, the data warehouse needs to be updated first, overwriting the higher 8 complex data points with the lower 8, and then a new set of 8 complex data points is read into the lower 8. Then, this data warehouse can be matched with the interpolated coordinates of 11, 12, 13, 14, 15, 16, 17, and 18. Subtracting 3 from each of the first set of interpolated coordinates yields coordinates 0, 1, 2, 3, 4, 5, 6, 7 for the current update count. Subtracting the update count by 1 and then subtracting 3 from the interpolated coordinates corresponding to the data warehouse after one update also yields the same interpolated coordinates: 0, 1, 2, 3, 4, 5, 6, 7. The lower three bits of the binary interpolated coordinates, regardless of their size, cycle through eight values: 000, 001, 010, 011, 100, 101, 110, 111. This allows for matching using these eight lower three bits after each data warehouse update—a core design principle of this core. To match the data transmission bandwidth of the AXI4 bus, the core is configured to synchronously perform matching searches on two interpolated coordinates at a time. The transition from 1 to 2 introduces complexity, leading to situations where one interpolation coordinate can find the interpolation packet within the local data warehouse, while the other requires updating the data warehouse to find it. Furthermore, when complex data spans rows or columns, neither interpolation coordinate can find the data packet within the local data warehouse. Therefore, a 4-bit interpolation coordinate status register, COORD_STATE, was established, and its logical truth table is shown in Table 3.

[0080] Table 3

[0081]

[0082]

[0083] coord1 and coord0 are the two interpolation coordinates processed by this core in one operation. For a row or n columns of complex data, the corresponding interpolation coordinates are from 3 to n-5. When coord is outside this range, the high two bits of the COORD_STATE register will be pulled low. To determine whether the interpolation coordinates exceed the current data warehouse, two sets of registers need to be set to cache the previous set of interpolation coordinates: coord1_past, coord0_past, and coord1_3b_past, coord0_3b_past. When the interpolation coordinate coord1 or coord0 is greater than its previous state coord1_past or coord0_past, but its low three bits are less than the previous state, it indicates that a cycle has been completed, and the data warehouse needs to be updated to match and search for data packets for that interpolation coordinate.

[0084] Step 4b) Packet matching and lookup core operation:

[0085] like Figure 4 As shown, the core first reads 16 complex data values ​​into the data warehouse, then reads a set of two interpolation coordinates, storing the interpolation coordinate status in a 4-bit status register. The interpolation coordinate status is judged: when the status is 1111, 0xxx, or x0xx, the data packets for coordinates coord1 and coord0 are directly packaged; when the status register is 1101, the data packet corresponding to coordinate coord0 is packaged first, then the data warehouse is updated, and finally the data packet for coordinate coord1 is packaged; when the status register is 1100, the data warehouse is updated first, then the data packets corresponding to coord1 and coord0 interpolation coordinates are packaged. After the data packets corresponding to coord1 are packaged in all states, a new set of two interpolation coordinates is read, and this process is repeated until all data packets corresponding to all interpolation coordinates are matched. The measured waveform of the interpolation packet matching lookup core is shown below. Figure 5 As shown;

[0086] Step 4c) The interpolation kernel performs interpolation calculations on the interpolation data packets output by the data packet matching lookup kernel:

[0087] The interpolation packet matching lookup core first buffers the matched data packets into two separate sets of synchronous FIFOs. Then, the interpolation operation core uses the interpolation offset as the lookup table coordinate to find the sinc coefficient and perform a multiplication-addition sinc interpolation operation on the complex data, based on the complex data in the received interpolation packet and the interpolation offset, resulting in two 64-bit interpolation results. This result is then written to DDR4 in transposed address form via data interface 2. Assuming the matrix size is M×N, and the i-th interpolation result is written to transposed address j, the address mapping relationship is as follows:

[0088]

[0089] Step 5) The PL logic processing terminal performs interpolation calculations to verify the range-interpolated echo data and then performs azimuth-interpolation calculations:

[0090] After the range interpolation is completed, repeat step 5) to perform the azimuth interpolation, but the input data is the echo data after the range interpolation and the azimuth interpolation parameters, and the calculation results are directly written using sequential addresses;

[0091] Step 6) The IFFT core of the PL logic processing terminal performs azimuth IFFT processing on the radar echo data after two-dimensional interpolation:

[0092] After the azimuth interpolation is completed, an inverse Fourier transform is performed in the azimuth direction. The data read interface reads the two-dimensional resampled phase data from DDR4, converts it to floating-point number through a fixed-point to floating-point core, and then transmits the complex data to the IFFT operation core in an 8-channel manner. This operation core uses a 1024-point inverse Fourier transform, and the operation result is written back to the DDR4 cache from data interface 2 in the form of a transposed address.

[0093] Step 7) Obtain SAR imaging results:

[0094] After the azimuth IFFT operation is completed, the range inverse Fourier transform operation is performed in the same process. The result is directly written to DDR4 in the sequential address manner until the range IFFT calculation of all data is completed. The result of this inverse Fourier transform is also the SAR imaging result of the polar coordinate format algorithm.

[0095] Step 9) Finally, the imaging result data of the DDR4 memory is sent to the host computer via the network interface using the TCP protocol.

[0096] Figure 6 This is a rendering of the image from this embodiment. The image quality is consistent with the PC-based image. The time for a single interpolation operation on the 424*464 point sampled data is 0.4ms, and the total imaging time is 1.85ms, which is within the allowed range of the register settings. For data with more points, the calculation can be estimated linearly. The processing time for 32768*8192 points is approximately 2.5s. Under the same single-precision floating-point data processing accuracy, the interpolation speed is increased by 2 times compared to similar patented methods, and the overall imaging process speed is increased by approximately 4.5 times.

Claims

1. A SAR imaging method based on FPGA polar coordinate format algorithm, characterized in that, Includes the following steps: (1) Constructing a Field Programmable Gate Array (FPGA): A field-programmable gate array (FPGA) is constructed, comprising a PS system processing unit and a PL logic processing unit. The PS system processing unit includes a TCP / IP network interface, a hard disk ROM, an A53 processor, and DDR4 memory connected in sequence. The PL logic processing unit includes a first data interface, an interpolation packet matching and lookup core, an interpolation operation core, and a second data interface connected in sequence. The second data interface is also connected to an IFFT operation core. The first data interface includes three AXI4 bus drivers: AXI4_COORD_32b, AXI4_SKEW_32b, and AXI4_SIG_32b, as well as floating-point... The system includes a fixed-point core (float2fixed) and a synchronization buffer FIFO for receiving data. The synchronization buffer FIFOs for receiving data include FIFO_COORD_32b, FIFO_SKEW_32b, and FIFO_SIG_32b. The interpolation packet matching and lookup core includes two sets of synchronization buffer FIFOs for interpolation packets: FIFO_PACK0_512b, FIFO_SKEW0_16b and FIFO_PACK1_512b, FIFO_SKEW1_16b. The second data interface includes AXI4_W1_64b and AXI4_W2_64b. (2) The PS system processing end receives and stores data: The TCP / IP network interface in the PS system processing unit receives single-precision echo data and pulse frequency history from the host computer via the synthetic aperture radar (SAR). Relative azimuth angle between radar beam and imaging scene and pitch angle And stored in the hard disk ROM; (3) The PS system processing end calculates the interpolation parameters: The A53 processor in the PS system's processing unit receives pulse frequency data from the TCP / IP network interface. Azimuth Pitch angle Calculate distance interpolated coordinates and distance interpolation offset and azimuth interpolation coordinates and azimuth interpolation offset ; ； ； ； ； ； ； ； in The space wavenumber frequency; The spatial wavenumber frequency projected onto the ground; This represents the number of sampling points in the distance direction. The spatial frequency difference between adjacent sampling points; and These are the minimum and maximum values ​​of the interpolated spatial frequency in the range direction; The spatial frequencies of each sampling point after interpolation; Integers, ranging from 0 to ; This represents the distance difference between each sampling point before and after interpolation; (4) The PL logic processing end interpolation calculation core performs range interpolation calculation on the radar echo data: (4a) The three AXI4 high-speed buses in the first data interface of the PL logic processing terminal read the SAR echo data and range interpolation coordinates stored in the DDR4 memory of the PS system processing terminal. and interpolation offset The single-precision SAR echo data is converted into fixed-point data using a floating-point to fixed-point kernel, and then the fixed-point data is interpolated with range coordinates. and distance interpolation offset Write them separately to the synchronous buffer FIFO; (4b) The interpolation packet matching lookup kernel uses the distance read from the synchronization buffer FIFO to interpolate the coordinates. Simultaneously, two sets of interpolation data packets are matched and output, and written to the buffer FIFO: FIFO_PACK0_512b, FIFO_SKEW0_16b and FIFO_PACK1_512b, FIFO_SKEW1_16b; FIFO_PACK0_512b and FIFO_PACK1_512b store the radar echo data to be interpolated, while FIFO_SKEW0_16b and FIFO_SKEW1_16b store the offset used in the interpolation calculation. (4c) The interpolation operation core reads two data packets to be interpolated from the buffer FIFO of the interpolation packet matching lookup core, and first performs the interpolation offset according to the distance stored in FIFO_SKEW0_16b and FIFO_SKEW1_16b in the data packets. The corresponding sinc interpolation coefficient is obtained by looking up the table. Then, the interpolation calculation is performed based on the coefficient and the radar echo data stored in FIFO_PACK0_512b and FIFO_PACK1_512b to obtain the range-interpolated echo data SIG_ITR_RAN. (4d) The distance interpolation result SIG_ITR_RAN is written back to the DDR4 memory on the PS side in transposed non-contiguous address order through the two AXI4 buses AXI4_W1_64b and AXI4_W2_64b in the second data interface; (5) The PL logic processing terminal performs interpolation calculations to verify the range-interpolated echo data and then performs azimuth-interpolation calculations: (5a) Read the range-interpolated radar echo data SIG_ITR_RAN and the azimuth-interpolated sinc coordinates from the DDR4 memory of the PS system processing terminal through the three AXI4 buses in the first data interface. and interpolation offset And simultaneously write them to their respective synchronous buffer FIFOs; (5b) The interpolation data packet matching lookup kernel reads the radar echo data SIG_ITR_RAN and azimuth interpolation coordinates from the synchronization buffer of the first data interface. and interpolation offset Based on azimuth interpolation coordinates Simultaneously match and output two sets of interpolated data packets and write them to the buffer FIFO; (5c) The interpolation operation core reads two data packets to be interpolated from the buffer FIFO of the interpolation packet matching lookup core, and first performs interpolation based on the azimuth offset stored in FIFO_SKEW0_16b and FIFO_SKEW1_16b in the data packets. The corresponding sinc interpolation coefficient is obtained by looking up the table. Then, interpolation calculation is performed based on the coefficient and the radar echo data SIG_ITR_RAN in the interpolation data packet to obtain the azimuth interpolated echo data SIG_ITR_AZI. (5d) The azimuth interpolation result SIG_ITR_AZI is written back to DDR4 memory in sequential address mode through the two AXI4 buses AXI4_W1_64b and AXI4_W2_64b in the second data interface; (6) The IFFT core of the PL logic processing terminal performs azimuth IFFT processing on the radar echo data after two-dimensional interpolation: (6a) The IFFT core reads the interpolated phase data SIG_ITR_AZI from the DDR4 memory through the AXI4 bus AXI4_W1_64b and AXI4_W2_64b in the second data interface, performs azimuth IFFT calculation, and obtains the echo data SIG_IFFT_AZI after azimuth IFFT calculation. (6b) Write the orientation IFFT calculation result SIG_IFFT_AZI back to DDR4 memory via the second data interface with a transposed non-contiguous address; (7) Obtain SAR imaging results: (7a) The IFFT core reads the phase data SIG_IFFT_AZI that has completed the azimuth IFFT operation in DDR4 through the AXI4 bus AXI4_W1_64b and AXI4_W2_64b in the second data interface, and performs range IFFT calculation to obtain the imaging data SIG_IFFT_RAN; (7b) After writing the distance-to-IFFT calculation result SIG_IFFT_RAN back to DDR4 in sequential address manner through the second data interface, the PS system processing end sends the SIG_IFFT_RAN data to the host computer through the Ethernet network interface.

2. The SAR imaging method based on FPGA polar coordinate format algorithm according to claim 1, characterized in that, In step (5e), ​​the two interpolation results cached in the FIFO are written back to the DDR4 memory in transposed, non-contiguous address order via the two AXI4 buses in the second data interface. The transposition method is as follows: when the matrix size is... If the i-th interpolation result is written to the transpose address j, then the address mapping relationship is as follows: 。 3. The SAR imaging method based on FPGA polar coordinate format algorithm according to claim 1, characterized in that, Step (4b) The interpolation packet matching lookup kernel interpolates the coordinates based on the distance read from the synchronization buffer FIFO. To simultaneously match and output two sets of interpolated data packets, the steps are as follows: (4b1) The interpolation data packet matching and lookup kernel simultaneously reads radar echo data, two interpolation coordinates and corresponding interpolation offsets from the FIFO; and establishes an interpolation data warehouse based on the radar echo data; (4b2) Generate the status value of the interpolation coordinate status register based on the interpolation coordinates, determine the coordinate status, and perform interpolation coordinate matching on the data in the interpolation data warehouse based on the interpolation coordinate status register to obtain two channels of data to be interpolated.

4. The SAR imaging method based on FPGA polar coordinate format algorithm according to claim 1, characterized in that, Step (4c) involves interpolating the coefficient with the radar echo data stored in FIFO_PACK0_512b and FIFO_PACK1_512b. The steps are as follows: (4c1) Initialize the interpolation kernel, generate the sinc interpolation lookup table, adopt an 8-point interpolation structure, and the quantization shift is 1 / 16; (4c2) Read two interpolation packets from the two-way interpolation packet FIFO, and look up the interpolation coefficient in the sinc lookup table according to the interpolation offset; (4c3) The dual-channel 8-point complex data interpolation is calculated by 32 multipliers, and the multiplier outputs are pipelined through 3-stage adders to obtain the range-interpolated echo data SIG_ITR_RAN.

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