Power supply, light emitting display device and driving method thereof

Abstract

The present disclosure relates to a power supply, a light emitting display apparatus, and a driving method thereof. The light emitting display apparatus can include a display panel configured to display an image, a driver configured to drive the display panel, and a power supply configured to supply a high-level voltage to a first power line of the display panel. Further, the power supply includes a voltage controller configured to perform the steps of receiving a vertical synchronization signal and current amount information of the high-level voltage for driving the display panel from the driver, and boosting the high-level voltage to be supplied to the display panel during a vertical blanking period based on the vertical synchronization signal and the current amount information of the high-level voltage.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a power supply, a light emitting display apparatus, and a driving method thereof. BACKGROUND

[0002] According to the development of information technology, the market of display apparatuses, which are a medium for interconnecting users and information, is expanding. Accordingly, the use of display apparatuses such as light emitting display (LED) apparatuses, quantum dot display (QDD) apparatuses, liquid crystal display (LCD) apparatuses, and the like is increasing.

[0003] The above-described display apparatus includes a display panel including sub-pixels, a driver configured to output a driving signal for driving the display panel, and a power supply configured to generate power to be supplied to the display panel or the driver.

[0004] When a driving signal (e.g., a scan signal and a data signal) is supplied to the sub-pixels at the display panel formed in the display apparatus as described above, a selected one of the sub-pixels transmits light or directly emits light, so that the display apparatus can display an image. SUMMARY

[0005] The voltage drop can inappropriately affect the display apparatus, which can impair the image quality. For example, a high-level voltage supplied to the display panel can be affected by the voltage drop caused by the IR drop, so that there can be a voltage difference between different regions of the display panel, which is particularly evident in a large high-resolution display panel. The voltage drop caused by the IR drop gradually increases in a region farther away from a region to which the high-level voltage is directly supplied from the power supply to the display panel. For example, when the high-level voltage is supplied from the power supply to a lower end region of the display panel, the highest voltage drop can occur in an upper end region of the display panel, and the lowest voltage drop can occur in the lower end region of the display panel (e.g., when the high-level voltage is directly supplied to the upper end region of the display panel, the lowest voltage drop can occur in the upper end region of the display panel, and the highest voltage drop can occur in the lower end region of the display panel). When different regions of the display panel have different levels for the high-level voltage, the image quality can be impaired.

[0006] Accordingly, the disclosure relates to a power supply, a light emitting display apparatus, and a driving method thereof that substantially eliminate one or more problems resulting from limitations and disadvantages of the related art.

[0007] An object of the disclosure is to provide, based on a power supply capable of performing constant voltage driving and constant current driving corresponding to a driving period of a display panel, not only to eliminate the effects of IR drop or voltage drop, but also to stably supply a current for driving the display panel, thereby maintaining uniform display quality across the entire screen.

[0008] Additional advantages, objects, and features of the disclosure will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following or can be learned from practice of the disclosure. The objects and other advantages of the disclosure can be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0009] To achieve these objects and other advantages, and in accordance with the purposes of the disclosure, as embodied and broadly described herein, a light emitting display apparatus includes a display panel configured to display an image, a driver configured to drive the display panel, and a power supply configured to supply a high level voltage to a first power line of the display panel, wherein the power supply includes a voltage controller configured to receive a vertical synchronization signal and current amount information of the high level voltage for driving the display panel from the driver, and boost the high level voltage to be supplied to the display panel during a vertical blanking period based on the vertical synchronization signal and the current amount information of the high level voltage.

[0010] The voltage controller can receive a voltage fed back from the first power line while sensing a current from the first power line, can set an output current of the high level voltage based on the current amount information and the sensed current, and can internally store the fed back voltage for use as a reference value for boosting the high level voltage to be supplied to the display panel using the stored voltage.

[0011] The voltage controller can include an error amplifier configured to output a voltage control signal for controlling the high level voltage, an output current sensing circuit configured to provide a sensing result of a current from the first power line to a first inverting terminal of the error amplifier, a first control transistor configured to provide a reference voltage to a non-inverting terminal of the error amplifier in response to the vertical synchronization signal, a second control transistor configured to provide a compensation voltage stored in a compensation capacitor to a second inverting terminal of the error amplifier in response to an inverted vertical synchronization signal generated by inversion of the vertical synchronization signal, and a third control transistor configured to store the high level voltage fed back from the first power line in the compensation capacitor in response to an inverted and delayed vertical synchronization signal generated by delay of the inverted vertical synchronization signal.

[0012] The power supply can perform constant current driving when the display panel is driven, and can perform constant voltage driving when the display panel is not driven.

[0013] The power supply can turn off the first control transistor and the third control transistor and can turn on the second control transistor for boosting the high level voltage to be supplied to the display panel during a period in which constant voltage driving is performed.

[0014] The power supply can include a first constant current driving period in which the power supply turns on the first control transistor and the third control transistor and turns off the second control transistor for storing the high level voltage fed back from the first power line in the compensation capacitor during the period in which constant current driving is performed.

[0015] The power supply can include a second constant current driving period in which the power supply turns off the second control transistor and the third control transistor and turns on the first control transistor after the first constant current driving period is completed for satisfying a set current during the period in which constant current driving is performed.

[0016] In another aspect of the disclosure, a method for driving a light emitting display apparatus includes a constant voltage driving step of boosting a high level voltage to be supplied to a display panel during a vertical blanking period based on a vertical synchronization signal provided from a driver and current amount information of the high level voltage for driving the display panel, and a constant current driving step of driving the display panel by a constant current during a period in which the vertical synchronization signal is applied to the display panel.

[0017] The constant current driving step can include a first constant current driving period in which a high level voltage fed back from a first power line of the display panel is stored in a compensation capacitor of the power supply, and a second constant current driving period in which the display panel is constantly driven under a predetermined current condition of the power supply.

[0018] In the constant voltage driving step, the feedback high level voltage stored in the compensation capacitor can be used as a reference value for boosting the high level voltage to be supplied to the display panel.

[0019] In another aspect of the disclosure, a power supply includes a vertical synchronization signal input circuit configured to receive a vertical synchronization signal from an external apparatus, a voltage controller configured to receive current amount information of a high level voltage from the external apparatus and to output a voltage control signal during a vertical blanking period based on the vertical synchronization signal and the current amount information of the high level voltage, and a voltage output circuit configured to change the high level voltage during the vertical blanking period based on the voltage control signal and to output the changed high level voltage.

[0020] The voltage controller can include an error amplifier configured to output a voltage control signal, an output current sensing circuit configured to provide a result of sensing a current output from the voltage output circuit to a first inverting terminal of the error amplifier, a first control transistor configured to provide a reference voltage to a non-inverting terminal of the error amplifier in response to a vertical synchronization signal, a second control transistor configured to provide a compensation voltage stored in a compensation capacitor to a second inverting terminal of the error amplifier in response to an inverted vertical synchronization signal generated by inversion of the vertical synchronization signal, and a third control transistor configured to store an external feedback high level voltage in the compensation capacitor in response to an inverted and delayed vertical synchronization signal generated by delay of the inverted vertical synchronization signal.

[0021] When the first control transistor and the third control transistor are turned off and the second control transistor is turned on, a high level voltage can be boosted.

[0022] When the first control transistor and the third control transistor are turned on and the second control transistor is turned off, the compensation capacitor can store an external feedback high level voltage.

[0023] Based on the feedback high level voltage stored in the compensation capacitor, the voltage controller can boost a high level voltage.

[0024] According to an example embodiment of the disclosure, there is an effect that, based on a power supply capable of performing constant voltage driving and constant current driving corresponding to a driving period of a display panel, not only the influence of an IR drop is eliminated, but also a current for driving the display panel is stably provided, thereby maintaining uniform display quality on the entire screen even for a display panel having a very large size. In addition, according to an example embodiment of the disclosure, there is an effect that a power supply capable of adaptively controlling a voltage and a current corresponding to a driving period of a display panel is provided. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:

[0026] Figure 1 is a block diagram schematically illustrating a light emitting display apparatus according to an embodiment of the disclosure;

[0027] Figure 2 is a block diagram schematically illustrating a light emitting display apparatus according to an embodiment of the disclosure; Figure 1 is a diagram of a sub-pixel shown;

[0028] Figure 3 and Figure 4 is a diagram illustrating a configuration of a panel-in-gate type scan driver according to an embodiment of the present disclosure;

[0029] Figure 5A and Figure 5B is a diagram showing a setting example of a panel-in-gate type scan driver according to an embodiment of the present disclosure;

[0030] Figure 6 is a diagram exemplifying a configuration of a sub-pixel applicable to an embodiment of the present disclosure;

[0031] Figure 7 is a diagram briefly explaining a power supply of a light emitting display apparatus according to an embodiment of the present disclosure;

[0032] Figure 8 is a diagram showing an output voltage and an output current output from a power supply shown in Figure 7 ;

[0033] Figure 9 is a diagram more specifically explaining a power supply according to another embodiment of the present disclosure;

[0034] Figure 10 is a diagram showing a signal for driving a power supply shown in Figure 9 ;

[0035] Figures 11 to 13 is a diagram explaining a first operation period of a power supply according to an embodiment of the present disclosure;

[0036] Figures 14 to 16 is a diagram explaining a second operation period of a power supply according to an embodiment of the present disclosure;

[0037] Figures 17 to 19 is a diagram explaining a third operation period of a power supply according to an embodiment of the present disclosure; and

[0038] Figure 20 is a diagram explaining a power supply according to a comparative example.

[0039] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same element, feature, and structure. The relative dimensions of these elements and the descriptions may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0040] Reference will now be made in detail embodiments of the present disclosure, examples of which can be illustrated in the accompanying drawings. In the following description, detailed descriptions of known functions and configurations incorporated herein can be omitted when it is determined that such detailed description can unnecessarily obscure the gist of the present disclosure. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and can be changed as known in the art, except that the steps and / or operations must occur in a specific order. The same reference numbers are used throughout to represent the same elements. The names of the elements used in the following description are selected only for the convenience of writing the present specification and thus can be different from those used in actual products.

[0041] It should be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

[0042] The display apparatus according to example embodiments of the present disclosure can be implemented as a television, an image player, a personal computer (PC), a home theater, a car electronic apparatus, a smart phone, etc., without being limited thereto. The display apparatus according to example embodiments of the present disclosure can be implemented as a light emitting display (LED) apparatus, a quantum dot display (QDD) apparatus, a liquid crystal display (LCD) apparatus, etc. However, for convenience of description, the following description will be given in connection with a light emitting display apparatus configured to directly emit light, e.g., based on inorganic light emitting diodes or organic light emitting diodes. Also, all components of each display apparatus according to all embodiments of the present disclosure can be operatively coupled and configured. Also, "disclosure" and "invention" are used interchangeably herein.

[0043] Figure 1 is a block diagram schematically illustrating a light emitting display apparatus. Figure 2 is a block diagram schematically illustrating Figure 1 a sub-pixel.

[0044] As Figure 1 and As illustrated in Figure 2 The light emitting display apparatus can include an image provider 110 (e.g., a host system), a timing controller 120, a scan driver 130 (e.g., a gate driver), a data driver 140, a display panel 150, a power supply 180, etc.

[0045] The image provider 110 (e.g., a set system or a host system) can output various driving signals together with an image data signal provided from the outside thereof or an image data signal stored in an internal memory thereof. The image provider 110 can provide the data signal and the various driving signals to the timing controller 120.

[0046] The timing controller 120 can output a gate timing control signal GDC for controlling an operation timing of the scan driver 130, a data timing control signal DDC for controlling an operation timing of the data driver 140, various synchronization signals (e.g., a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC, etc.). The timing controller 120 can provide the data signal DATA provided from the image provider 110 and the data timing control signal DDC to the data driver 140. The timing controller 120 can take the form of an integrated circuit (IC), and as such can be mounted on a printed circuit board, without being limited thereto.

[0047] The scan driver 130 can output a scan signal (or a scan voltage) in response to the gate timing control signal GDC provided from the timing controller 120. The scan driver 130 can provide the scan signal to sub-pixels included in the display panel 150 through gate lines GL1 through GLm, where m can be a positive integer. The scan driver 130 can take the form of an IC, or can be directly formed on the display panel 150 in an in-panel gate manner, without being limited thereto.

[0048] The data driver 140 can sample and latch the data signal DATA in response to the data timing control signal DDC provided from the timing controller 120, can convert a resulting data signal having a digital form into a data voltage having an analog form based on a gamma reference voltage, and can output the data voltage. The data driver 140 can provide the data voltage to sub-pixels included in the display panel 150 through data lines DL1 through DLn, where n can be a positive integer. The data driver 140 can take the form of an integrated circuit (IC), and as such can be mounted on the display panel 150 or can be mounted on a printed circuit board, without being limited thereto.

[0049] The power supply 180 can generate a high-level voltage and a low-level voltage based on an external input voltage provided from the outside thereof. The power supply 180 can output the high-level voltage EVDD through a first power line and the low-level voltage EVSS through a second power line. The power supply 180 can not only generate and output the high-level voltage and the low-level voltage, but also generate and output a voltage for driving the scan driver 130 (e.g., a gate voltage including a gate high voltage and a gate low voltage), a voltage for driving the data driver 140 (e.g., a drain voltage and a drain voltage including a half drain voltage), etc.

[0050] The display panel 150 can display an image corresponding to a driving signal including a scan signal and a data voltage, a driving voltage including a high-level voltage and a low-level voltage, etc. A sub-pixel of the display panel 150 can directly emit light. The display panel 150 can be manufactured based on a substrate having rigidity or ductility such as glass, silicon, polyimide, etc. The light-emitting sub-pixel can be composed of a red sub-pixel, a green sub-pixel, and a blue sub-pixel or a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0051] For example, one sub-pixel SP can include a pixel circuit connected to a first data line DL1, a first gate line GL1, a first power line, and a second power line, while including a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode, etc. The sub-pixel SP used in the light-emitting display apparatus has a complex circuit configuration because the sub-pixel SP directly emits light. Further, the compensation circuit configured to compensate not only the deterioration of the light-emitting organic light-emitting diode but also the deterioration of the driving transistor, etc. configured to provide the organic light-emitting diode with a driving current for driving the organic light-emitting diode is also diverse and can vary. However, for convenience of explanation, the sub-pixel SP is simply shown in the form of a block.

[0052] Further, in the above description, the timing controller 120, the scan driver 130, the data driver 140, etc. are respectively described as having separate configurations. However, according to the implementation type of the light-emitting display apparatus, one or more of the timing controller 120, the scan driver 130, and the data driver 140 can be integrated into one IC.

[0053] Figure 3 and Figure 4 is a diagram illustrating a configuration of a panel-in-gate type scan driver. Figure 5A and Figure 5B is a diagram showing a setting example of a panel-in-gate type scan driver. Figure 6 is a diagram exemplifying a configuration of a sub-pixel applicable to the example embodiments of the disclosure.

[0054] As Figure 3 indicated, the panel-in-gate type scan driver denoted by reference numeral "130" can include a shift register 131 and a level shifter 135. The level shifter 135 can generate a driving clock signal Clks, a start signal Vst, etc. based on signals and voltages output from the timing controller 120 and the power supply 180. The driving clock signal Clks can be generated on the condition that the driving clock signal Clks has J different phases (J is an integer of 2 or more), such as 2-phase, 4-phase, 8-phase, etc.

[0055] The shift register 131 can operate based on signals Clks and Vst output from the level shifter 135, and can output scan signals Scan[1] to Scan[m] capable of turning on or off transistors formed at the display panel. The shift register 131 can be formed in a thin film form on the display panel in a panel gate manner.

[0056] As shown in Figure 3 and Figure 4 , the level shifter 135 can be independently formed in an IC form, or can be included in the power supply 180 internally differently from the shift register 131. However, this configuration is merely illustrative, and example embodiments of the disclosure are not limited thereto.

[0057] As shown in Figure 5A and Figure 5B , in a panel gate type scan driver, the shift registers 131a and 131b outputting scan signals can be disposed in the non-display area NA of the display panel 150. The shift registers 131a and 131b can be disposed in the non-display areas NA of the left and right sides of the display panel 150 as shown in Figure 5A , or can be disposed in the non-display areas NA of the upper and lower sides of the display panel 150 as shown in Figure 5B . Further, although the shift registers 131a and 131b have been shown and described as being disposed in the non-display area NA in Figure 5A and Figure 5B , example embodiments of the disclosure are not limited thereto.

[0058] As shown in Figure 6 , a sub-pixel applicable to example embodiments of the disclosure can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitor CST, a driving transistor DT, and an organic light emitting diode OLED.

[0059] A sub-pixel applicable to example embodiments of the disclosure can be connected to a first gate line GL1 including a first scan line SCN1, a second scan line SCN2, and a first emission control line EM1. In this case, as the second scan line SCN2, a scan line not included in the sub-pixel shown in Figure 6 but included in a sub-pixel disposed at an upstream end or a downstream end of the sub-pixel shown in Figure 6 may be used.

[0060] The first transistor T1 and the second transistor T2 can be turned on in response to a first scan signal transmitted thereto through a first scan line SCN1. The fifth transistor T5 and the sixth transistor T6 can be turned on in response to a second scan signal transmitted thereto through a second scan line SCN2. The third transistor T3 and the fourth transistor T4 can be turned on in response to a first emission control signal transmitted thereto through a first emission control line EM1.

[0061] The first scan signal can be applied in a sampling period in which threshold voltage sampling of the driving transistor DT is performed and a write period in which a data voltage of the first data line DL1 is transmitted to a first node of the driving transistor DT. The second scan signal can be applied in an initialization period in which a voltage of the voltage line VAR is transmitted to a connection node between a gate of the driving transistor DT and the capacitor CST and an anode of the organic light emitting diode OLED. The first emission control signal can be applied in an emission period in which a high level voltage EVDD of the first power line is transmitted to a node of the driving transistor DT and a driving current generated from the driving transistor DT is transmitted to the anode of the organic light emitting diode OLED.

[0062] Of course, reference is made to Figure 6 The sub-pixel described is merely illustrative, and example embodiments of the present disclosure are applicable to almost any type of structure on a display panel, as long as the structure can be affected by IR drop or voltage drop. In addition, although the timing controller and the data driver are described as being implemented as one integrated driver, the timing controller and the data driver can be distinguished from each other for ease of description, as described with reference to Figure 1 .

[0063] Figure 7 FIG. 1 is a diagram briefly illustrating a power supply of an emission display apparatus according to a first embodiment of the present disclosure. Figure 8 FIG. 2 is a diagram describing an output voltage and an output current output from Figure 7 the power supply shown in FIG. 1.

[0064] As shown in Figure 7 , the emission display apparatus can include a constant current control type power supply 180. The power supply 180 can rapidly raise (step up) a high level voltage for driving the display panel 150 during (or immediately after) a vertical blanking period, based on a vertical synchronization signal VSYNC transmitted from the driver 160 and current amount information IEVDD of the display panel 150, thereby reducing and / or minimizing a problem caused by IR drop. For example, the power supply 180 can compensate for a voltage drop characteristic of the display panel 150.

[0065] The power supply 180 can include a vertical synchronization signal input unit (circuit) 181, a voltage output unit (circuit) 183, an output current setting unit (circuit) 185, an output current sensing unit (circuit) 187, a current / voltage control unit (circuit) 189, etc.

[0066] The vertical synchronization signal input unit 181 can be used to generate a circuit control signal capable of controlling the current / voltage control unit 189 based on the vertical synchronization signal VSYNC output from the driver 160.

[0067] The voltage output unit 183 can be used to output a high-level voltage and change the high-level voltage based on a voltage control signal output from the current / voltage control unit 189.

[0068] The output current setting unit 185 can be used to set an output current of the high-level voltage output from the power supply 180 based on the amount-of-current information IEVDD of the high-level voltage transferred from the driver 160, and transfer the output current setting value to the output current sensing unit 187. For reference, the amount-of-current information IEVDD of the high-level voltage for driving the display panel 150 can be calculated based on the analysis of the data signal by the driver 160 (for example, in the case where the timing controller and the data driver are distinguished from each other, the amount-of-current information of the high-level voltage can be calculated through the timing controller).

[0069] The output current sensing unit 187 can be used to sense the output current ISEN of the high-level voltage from the first power line, and output a sensing result value according to whether the sensed output current ISEN of the high-level voltage satisfies (approximates to) the output current setting value transferred from the output current setting unit 185.

[0070] The current / voltage control unit 189 can be used to generate a voltage control signal based on the vertical synchronization signal VSYNC transferred from the vertical synchronization signal input unit 181, the sensing result value transferred from the output current sensing unit 187, and the high-level voltage FEVDD fed back from the first power line. The voltage output unit 183 can control the high-level voltage based on the voltage control signal transferred from the current / voltage control unit 189.

[0071] In addition, although the vertical synchronization signal input unit 181, the voltage output unit 183, the output current setting unit 185, the output current sensing unit 187, and the current / voltage control unit 189 have been described in different manners, respectively, these units can be collectively referred to as one voltage controller.

[0072] As Figure 7 and Figure 8As shown, the power supply 180 can output a current (EVDD current) that satisfies (approximates) a high-level voltage of a set current (EVDD set current). Also, the power supply 180 can provide a high-level voltage EVDD that gradually changes from an upper end region of the display panel 150, which is farthest from a point at which the high-level voltage EVDD is provided, to a lower end region of the display panel 150, which is closest to the point at which the high-level voltage EVDD is provided.

[0073] The power supply 180 can provide the highest high-level voltage EVDD to the upper end region of the display panel 150, and can provide the lowest high-level voltage EVDD to the lower end region of the display panel 150. The reason for providing the high-level voltage EVDD in the above-described manner will be described below.

[0074] The scan operation Scan of the display panel 150 can start from a first gate line GL1 in an upper end region of the display panel 150 opposite to a lower end region of the display panel 150 in which the driver 160 is disposed, and can end at an Mth gate line GLm at the lower end region of the display panel 150. The display panel 150 can receive the high-level voltage EVDD through the lower end region thereof in which the driver 160 is disposed.

[0075] The high-level voltage EVDD provided to the display panel 150 can be affected by a voltage drop caused by an IR drop, and as such, there can be a voltage difference between different regions of the display panel 150 (e.g., particularly in a large high-resolution display panel). The voltage drop caused by the IR drop can gradually increase in regions farther away from the region in which the high-level voltage EVDD is provided. For example, when the high-level voltage is provided to the lower end region of the display panel 150, the highest voltage drop can occur in the upper end region of the display panel, and the lowest voltage drop can occur in the lower end region of the display panel 150.

[0076] Accordingly, to reduce and / or minimize the voltage drop problem caused by the IR drop, the power supply 180 can control the high-level voltage EVDD based on the high-level voltage FEVDD fed back from the first power line, the output current ISEN sensed from the first power line, the vertical synchronization signal VSYNC transmitted from the driver 160, and the amount of current information IEVDD of the high-level voltage transmitted from the driver 160.

[0077] Figure 9 is a diagram illustrating a power supply according to a second embodiment of the disclosure in more detail. Figure 10 is a diagram illustrating a power supply according to a second embodiment of the disclosure in more detail. Figure 9 is a diagram illustrating a power supply according to a second embodiment of the disclosure in more detail.

[0078] As Figure 9 and Figure 10As illustrated, the current / voltage control unit 189 included in the power supply 180 can include an error amplifier ERA, a first control transistor Q1, a second control transistor Q2, a third control transistor Q3, an inverter INV, a compensation capacitor CA, a delay DEL, a first resistor R1, a second resistor R2, and the like.

[0079] The error amplifier ERA can include an output terminal connected to an input terminal of the voltage output unit 183, a first inverting terminal (-) connected to an output terminal of the output current sensing unit 187, a second inverting terminal (-) connected to a high-level voltage feedback terminal, and a non-inverting terminal (+) connected to a first electrode of the first control transistor Q1. The error amplifier ERA can generate a voltage control signal for controlling the voltage output unit 183 by comparing a larger one of a first input value input to the first inverting terminal (-) and a second input value input to the second inverting terminal (-) with a reference voltage transmitted through the first control transistor Q1.

[0080] The first control transistor Q1 can include a gate connected to an output terminal of the vertical synchronization signal input unit 181, a first electrode connected to the non-inverting terminal (+) of the error amplifier ERA, and a second electrode connected to a reference voltage line VREF. The first control transistor Q1 can transmit a reference voltage of the reference voltage line VREF to the non-inverting terminal (+) of the error amplifier ERA in correspondence with a vertical synchronization signal VSYNC output through the output terminal of the vertical synchronization signal input unit 181. During the first operation period P1 and the third operation period P3, the first control transistor Q1 can be turned on in response to the vertical synchronization signal VSYNC being logic high (H), and during the second operation period P2, the first control transistor Q1 can be turned off in response to the vertical synchronization signal VSYNC being logic low (L).

[0081] A period in which the vertical synchronization signal VSYNC of logic high (H) is applied can be included in a driving period for image display of the display panel, and a period in which the vertical synchronization signal VSYNC of logic low (L) is applied (corresponding to a vertical blanking period) can be included in a non-driving period for non-display of an image of the display panel.

[0082] The inverter INV can include an input terminal connected to an output terminal of the vertical synchronization signal input unit 181, and an output terminal connected to a gate of the second control transistor Q2 and an input terminal of the delay DEL. The inverter INV can invert the vertical synchronization signal VSYNC, and likewise, can output an inverted vertical synchronization signal IVSYNC.

[0083] The second control transistor Q2 can include a gate connected to the output terminal of the inverter INV, a first electrode connected to the non-inversion terminal (+) of the error amplifier ERA, and a second electrode connected to one end of the compensation capacitor CA. The second control transistor Q2 can transfer the compensation voltage stored in the compensation capacitor CA to the non-inversion terminal (+) of the error amplifier ERA in correspondence with the inverted vertical synchronization signal IVSYNC output from the inverter INV. The second control transistor Q2 can be turned off in response to the inverted vertical synchronization signal IVSYNC being logic low (L) during the first operation period P1 and the third operation period P3, and can be turned on in response to the inverted vertical synchronization signal IVSYNC being logic high (H) during the second operation period P2.

[0084] The delay DEL can include an input terminal connected to the output terminal of the inverter INV, and an output terminal connected to the gate of the third control transistor Q3. The delay DEL can transfer the inverted and delayed vertical synchronization signal IDVSYNC to the gate of the third control transistor Q3.

[0085] The third control transistor Q3 can include a gate connected to the output terminal of the delay DEL, a first electrode connected to the second inversion terminal (-) of the error amplifier ERA, and a second electrode connected to one end of the compensation capacitor CA. The third control transistor Q3 can transfer the compensation voltage stored in the compensation capacitor CA to the second inversion terminal (-) of the error amplifier ERA in correspondence with the inverted and delayed vertical synchronization signal IDVSYNC output from the delay DEL. The third control transistor Q3 can be turned off in response to the inverted and delayed vertical synchronization signal IDVSYNC being logic low (L) during the first operation period P1 and the second operation period P2, and can be turned on in response to the inverted and delayed vertical synchronization signal IDVSYNC being logic high (H) during the third operation period P3.

[0086] The compensation capacitor CA can include one end connected to the second electrode of the second control transistor Q2 and the second electrode of the third control transistor Q3, and the other end connected to the ground. The compensation capacitor CA can store a high-level voltage FEVDD fed back through the feedback terminal of the power supply 180.

[0087] The first resistor R1 can include one end connected to the first power line of the display panel 150, and the other end connected to the feedback terminal of the power supply 180. The second resistor R2 can include one end connected to the other end of the first resistor R1 and the feedback terminal of the power supply 180, and the other end connected to the ground line. The first resistor R1 and the second resistor R2 (e.g., a voltage divider) can divide a high-level voltage EVDD supplied through the first power line, and as such, can supply a resulting voltage to the feedback terminal of the power supply 180 as a feedback high-level voltage FEVDD. Although the first resistor R1 and the second resistor R2 are illustrated as being disposed outside the power supply 180, the first resistor R1 and the second resistor R2 can be internally included in the power supply 180.

[0088] Figures 11 to 13 is a diagram illustrating a first operation period of a power supply. Figures 14 to 16 is a diagram illustrating a second operation period of a power supply. Figures 17 to 19 is a diagram illustrating a third operation period of a power supply.

[0089] As shown in Figures 11 to 13 , during the first operation period P1 of the power supply 180, the first control transistor Q1 can be in a state turned on by the vertical synchronization signal VSYNC of a logic high (H). On the other hand, during the first operation period P1 of the power supply 180, the second control transistor Q2 can be in a state turned off by the inverted vertical synchronization signal IVSYNC of a logic low (L), and the third control transistor Q3 can be in a state turned off by the inverted and delayed vertical synchronization signal IDVSYNC of a logic low (L).

[0090] The first operation period P1 of the power supply 180 can be a constant current driving period (a second constant current driving period) after a scan operation of the display panel 150 is performed, and can be a period after the vertical synchronization signal VSYNC is applied. After the vertical synchronization signal VSYNC is applied, the display panel 150 can perform a scan operation Scan from an upper end region thereof to a lower end region thereof. That is, after the vertical synchronization signal VSYNC is applied, the display panel 150 can be in a driving state.

[0091] The voltage output unit 183 can raise or lower the high-level voltage EVDD according to the output current ISEN (or actual current) of the high-level voltage EVDD and the set current. For example, in the case of a set current > actual current, the high-level voltage EVDD can be raised, and in the case of a set current < actual current, the high-level voltage EVDD can be lowered. In this case, the high-level voltage EVDD can be output such that the high-level voltage EVDD has the highest level at the upper end region of the display panel 150 and has a level that gradually decreases as the display panel 150 extends toward the lower end region thereof. This can be seen by referring to the output of the high-level input voltage (EVDD input voltage) in a gradually decreasing state. In other words, the voltage output unit 183 can dynamically and gradually adjust the high-level voltage EVDD of different regions of the display panel such that the actual measured current from the display panel can be compensated to optimally match the set current set by the power supply 180. For example, when scanning each row of sub-pixels, the power supply 180 can fine-tune and continuously adjust the high-level voltage EVDD, thereby providing more uniform image quality.

[0092] When the high-level voltage EVDD output from the power supply 180 is controlled as described above, the pixels of the display panel 150 that start sampling can perform a sampling operation based on substantially the same high-level voltage (EVDD voltage of the sampling pixel (sampling PIX)). Also, the pixels of the display panel 150 that start emitting light can also perform an emission operation based on substantially the same high-level voltage (EVDD voltage of the emission pixel (emission PIX)).

[0093] In this case, the output current (EVDD current) of the high-level voltage output from the power supply 180 can be maintained at a level that is approximately the same as the level of the set current (EVDD set current). Of course, there is a difference between the period in which the emission operation of the pixel is performed and the period in which the sampling operation of the pixel is performed, which substantially corresponds to one gate line (one scan line). This can be seen from the difference between the emission operation of the pixel connected to the previous stage gate line (e.g., GLi-1) and the sampling operation of the pixel connected to the current stage gate line (e.g., GLi) performed during the emission operation of the pixel connected to the previous stage gate line.

[0094] For this reason, the output current (EVDD current) of the high-level voltage output from the power supply 180 can exhibit a slightly increasing tendency between gate lines. That is, the output current (EVDD current) of the high-level voltage applied to the current stage gate line (e.g., GLi) can initially slightly increase in correspondence with the sampling operation of the next stage gate line (e.g., GLi+1).

[0095] However, the pixels connected to the corresponding gate lines can perform the sampling operation and the light emitting operation based on the high level voltage having substantially the same level, and the time current increments produced at the approximate or equal level can be removed after averaging. Thus, a condition for realizing a uniform image representation can be established.

[0096] As shown in FIG. 1A, the first control transistor Q1 can be in a state of being turned off by the vertical synchronization signal VSYNC of a logic low L, and the third control transistor Q3 can be in a state of being turned off by the inverted and delayed vertical synchronization signal IDVSYNC of a logic low L during the first operation period P1 of the power supply 180. On the other hand, the second control transistor Q2 can be in a state of being turned on by the inverted vertical synchronization signal IVSYNC of a logic high H. Figures 14 to 16

[0097] The second operation period P2 of the power supply 180 is a period for constant voltage driving, and can be a period after entering the vertical blank period Vblank. After entering the vertical blank period Vblank, the display panel 150 can be in a non-driving state in which the display panel 150 does not perform the scan operation Scan. In other words, entering the vertical blank period Vblank means that the scan operation Scan to the Mth gate line GLm has been completed, and then a preparation time for the scan operation Scan starting from the first gate line GL1 can be provided. For example, after the last row of sub-pixels (e.g., GLm) in the display panel have been scanned, the power supply 180 can rapidly increase the high level voltage EVDD during the vertical blank period Vblank, thereby effectively using the vertical blank period Vblank as a reset period type of the power supply 180.

[0098] After entering the vertical blank period Vblank, the high level voltage EVDD can be in a state of being greatly reduced. The output current setting unit 185 can set the output current amount to be higher than the maximum output current amount required by the display panel 150 in order to rapidly compensate for the reduced high level voltage EVDD. To this end, the error amplifier ERA can receive a set current value set to be higher through its first inverting terminal (-). For example, the power supply can rapidly reset the high level voltage EVDD during the vertical blank period Vblank in preparation for the next display period.

[0099] After entering the vertical blank period Vblank, the second control transistor Q2 can be turned on, and the compensation voltage charged in the compensation capacitor CA can be provided to the non-inverting terminal (+) of the error amplifier ERA through the turned-on second control transistor Q2. The error amplifier ERA can output a voltage control signal based on the two values provided to its first inverting terminal (-) and its non-inverting terminal (+).

[0100] ​The voltage output unit 183 can rapidly raise the high-level voltage EVDD output from the power supply 180 based on the voltage control signal output from the error amplifier ERA. In this case, the voltage output unit 183 can raise the high-level voltage EVDD to the level of the compensation voltage charged in the compensation capacitor CA. In this case, the level of the compensation voltage can vary according to the resistance values of the first resistor R1 and the second resistor R2.

[0101] As such, by rapidly raising the high-level voltage EVDD output from the power supply 180 after entering the vertical blank period Vblank, it is possible to prevent the problem of performing a sampling operation or a light emission operation based on a low high-level voltage during the scan operation Scan of the display panel 150. For example, as shown in FIG. 6, the high-level voltage EVDD can be rapidly raised in a linear manner during the vertical blank period Vblank, but is not limited thereto. Figure 16

[0102] As shown in FIG. 5, during the third operation period P3 of the power supply 180, the first control transistor Q1 can be in a state turned on by the vertical synchronization signal VSYNC of logic high H, and the third control transistor Q3 can be in a state turned on by the inverted and delayed vertical synchronization signal IDVSYNC of logic high H. On the other hand, the second control transistor Q2 can be in a state turned off by the vertical synchronization signal IVSYNC of logic low L. Figures 17 to 19

[0103] The third operation period P3 of the power supply 180 is a constant current driving period (first constant current driving period) synchronized with the scan operation of the display panel 150, and can be a time point at which the vertical synchronization signal VSYNC is applied after entering the vertical blank period Vblank. Since the third operation period P3 is a time point at which the vertical synchronization signal VSYNC is applied after entering the vertical blank period Vblank, the display panel 150 can be in a driving state in which the display panel 150 performs the scan operation Scan from the first gate line GL1.

[0104] At the time point at which the vertical synchronization signal VSYNC is applied, the power supply 180 can set an output current amount corresponding to an output current amount required for the display panel 150 based on the current amount information IEVDD provided from the driver 160.

[0105] ​​The output current sensing unit 187 can sense an output current flowing through the first power line, and can deliver a sensing result to the current / voltage control unit 189. The current / voltage control unit 189 can store, in the compensation capacitor CA, a high-level voltage EVDD at a time point when an output current (actual current) of the high-level voltage becomes approximately or equal to a set current of the high-level voltage (e.g., due to the first gate line GL1 experiencing little or no IR drop). To this end, a delay value of the delay generator DEL generating an inverted and delayed vertical synchronization signal IDVSYNC can be set to a time satisfying "set current of high-level voltage = output current (actual current) of high-level voltage".

[0106] The high-level voltage EVDD divided by the first resistor R1 and the second resistor R2 can be stored in the compensation capacitor CA through the operation of the third control transistor Q3. The compensation voltage stored in the compensation capacitor CA is a voltage for applying a correct high-level voltage EVDD to the upper end region of the display panel 150, and as such, can correspond to a voltage for enhancing accuracy in a sampling operation of a pixel (e.g., an EVDD voltage level for a correct sampling operation). The compensation voltage stored in the compensation capacitor CA can be referred to as a "reference value", which can be referred to in order to rapidly raise the high-level voltage EVDD in the first operation period P1 of the power supply 180. After completion of the first constant current driving period as the third operation period P3 of the power supply 180, the second constant current driving period as the first operation period P1 can follow.

[0107] Figure 20 is a diagram illustrating a power supply according to a comparative example.

[0108] As Figure 20 indicated, the power supply according to the comparative example does not include a configuration for changing a high-level voltage EVDD corresponding to a driving period of a display panel, and as such, can raise the high-level voltage EVDD from a time point at which a scan operation of the first gate line GL1 is started. In this case, due to a lack of time when a voltage change for raising the high-level voltage EVDD is performed, the upper end region of the display panel can be darker than other regions. In addition, pixels connected to gate lines (e.g., GL1 and GL2) of the upper end region of the display panel can suffer from an insufficient current amount phenomenon (since the EVDD input voltage and current are low, the charge amount of a capacitor is also insufficient).

[0109] With Figure 20In comparison with the illustrated comparative example, the power supply according to the embodiment of the disclosure can perform the constant voltage driving before the scan operation of the display panel, so as to quickly raise the high-level voltage in time before the next driving period, and then can perform the constant current driving, so as to realize the stable current supply together with the scan driving of the display panel. As a result, the power supply according to the embodiment of the disclosure can eliminate the influence of the IR drop, but it can stably provide the current for driving the display panel even at the start of the subsequent display period.

[0110] As is apparent from the above description, according to the example embodiment of the disclosure, there is an effect that, based on the power supply capable of performing the constant voltage driving and the constant current driving corresponding to the driving period of the display panel, not only the influence of the IR drop is eliminated, but also the current for driving the display panel is stably provided, thereby maintaining the uniform display quality on the entire screen even for the display panel having a very large size. In addition, according to the example embodiment of the disclosure, there is an effect that a power supply capable of adaptively controlling the voltage and the current corresponding to the driving period of the display panel is provided.

[0111] The foregoing description and drawings are given by way of illustration only. It will be understood by those skilled in the art that various modifications and changes can be made thereto without departing from the essential features of the present disclosure. Therefore, the foregoing embodiments disclosed in the present disclosure are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the present disclosure are intended to be embraced therein. It will be understood by those skilled in the art that the scope of the present disclosure should be defined by the appended claims and not by the foregoing description, and all equivalents thereof are intended to be within the scope of the present disclosure.

[0112] Cross Reference to Related Applications

[0113] This application claims priority to Korean Patent Application No. 10-2021-0192845, filed on December 30, 2021, in the Republic of Korea, the entire contents of which are incorporated herein by reference as if fully set forth in their entirety herein.

Claims

1. A light emitting display apparatus, the light emitting display apparatus comprising: a display panel configured to display an image; a driver configured to drive the display panel; and a power supply configured to provide a high level voltage to a first power line of the display panel; wherein the power supply comprises a voltage controller configured to: receive a vertical synchronization signal and current amount information of the high level voltage used to drive the display panel from the driver, and boost the high level voltage to be provided to the display panel during a vertical blanking period based on the vertical synchronization signal and the current amount information of the high level voltage, and wherein the voltage controller comprises: an error amplifier configured to output a voltage control signal used to regulate the high level voltage; an output current sensing circuit configured to provide a sensing result of a sensing current from the first power line to a first inverting terminal of the error amplifier; a first control transistor configured to provide a reference voltage to a non-inverting terminal of the error amplifier in response to the vertical synchronization signal; a second control transistor configured to provide a compensation voltage stored in a compensation capacitor to the non-inverting terminal of the error amplifier in response to an inverted vertical synchronization signal generated by inversion of the vertical synchronization signal; and a third control transistor configured to store the high level voltage fed back from the first power line in the compensation capacitor in response to an inverted and delayed vertical synchronization signal generated by delay of the inverted vertical synchronization signal. the power supply is configured to:

2. The light-emitting display device according to claim 1, wherein dynamically decrease the high level voltage used to drive the display panel from a start high level voltage to an end high level voltage during one display period, the end high level voltage being less than the start high level voltage, and boost the high level voltage from the end high level voltage back to the start high level voltage during the vertical blanking period and before a start of a next display period.

3. The light emitting display apparatus of claim 1, further comprising: a plurality of gate lines connected to a plurality of sub-pixels in the display panel, wherein the power supply is configured to: gradually decrease the high level voltage from scanning a first gate line among the plurality of gate lines until scanning a last gate line among the plurality of gate lines during one display period. a last group of sub-pixels connected to the last gate line is located in an area of the display panel closer to the first power line than a first group of sub-pixels connected to the first gate line.

4. The light-emitting display device according to claim 3, wherein the voltage controller is further configured to:

5. The light-emitting display device according to claim 1, wherein receive a feedback voltage fed back from the first power line while sensing the sensing current from the first power line, set an output current of the high level voltage based on the current amount information and the sensing current, and ​ stores the feedback voltage internally to be used as a reference value for boosting the high level voltage to be supplied to the display panel.

6. The light-emitting display device according to claim 1, wherein the power supply is further configured to: perform constant current driving when the display panel is driven, and perform constant voltage driving when the display panel is not driven.

7. The light-emitting display device according to claim 6, wherein During a period in which the constant voltage driving is performed, the power supply turns off the first control transistor and the third control transistor, and turns on the second control transistor for boosting the high level voltage to be supplied to the display panel.

8. The light-emitting display device according to claim 6, wherein During a period in which the constant current driving is performed, the power supply includes a first constant current driving period during which the power supply turns on the first control transistor and the third control transistor and turns off the second control transistor for storing the high level voltage fed back from the first power line in the compensation capacitor.

9. The light-emitting display device according to claim 8, wherein the power supply includes a second constant current driving period during which the power supply turns off the second control transistor and the third control transistor and turns on the first control transistor after the first constant current driving period is completed for setting a current for another constant current driving period. 10.A method for driving the light emitting display apparatus according to claim 1, the method comprising the steps of: receiving the vertical synchronization signal from the driver; receiving the current amount information for driving the high level voltage of the display panel in the light emitting display apparatus; performing constant voltage driving by boosting the high level voltage to be supplied to the display panel in the light emitting display apparatus during the vertical blanking period based on the vertical synchronization signal and the current amount information of the high level voltage; and performing constant current driving for driving the display panel by providing a constant current to the display panel during a period in which the vertical synchronization signal is applied to the display panel.

11. The method of claim 10, wherein, the constant current driving includes the steps of: storing a feedback high level voltage fed back from the first power line of the display panel in the compensation capacitor of the power supply during a first constant current driving period; and driving the display panel constantly under a predetermined current condition of the power supply during a second constant current driving period.

12. The method of claim 11, wherein, the feedback high level voltage stored in the compensation capacitor is used as a reference value for boosting the high level voltage to be supplied to the display panel during the constant voltage driving of the display panel. 13.A power supply, the power supply comprising: a vertical synchronization signal input circuit configured to receive a vertical synchronization signal from an external device; a voltage controller configured to: receive current amount information of a high level voltage from the external device; and output a voltage control signal during a vertical blanking period based on the vertical synchronization signal and the current amount information of the high level voltage; and a voltage output circuit configured to change the high-level voltage during the vertical blanking period based on the voltage control signal, and output the changed high-level voltage, wherein the voltage controller includes: an error amplifier configured to output the voltage control signal for adjusting the high-level voltage; an output current sensing circuit configured to provide a sensing result of a current output from the voltage output circuit to a first inverting terminal of the error amplifier; a first control transistor configured to provide a reference voltage to a non-inverting terminal of the error amplifier in response to the vertical synchronization signal; a second control transistor configured to provide a compensation voltage stored in a compensation capacitor to the non-inverting terminal of the error amplifier in response to an inverted vertical synchronization signal generated by inversion of the vertical synchronization signal; and a third control transistor configured to store an external feedback high-level voltage in the compensation capacitor in response to an inverted and delayed vertical synchronization signal generated by delay of the inverted vertical synchronization signal.

14. The power supply of claim 13, wherein, The voltage output circuit changes the high-level voltage during the vertical blanking period while maintaining a constant current to provide a constant-current driving period.

15. The power supply of claim 13, wherein, The high-level voltage is boosted when the first control transistor and the third control transistor are turned off and the second control transistor is turned on.

16. The power supply of claim 13, wherein, The compensation capacitor stores the external feedback high-level voltage when the first control transistor and the third control transistor are turned on and the second control transistor is turned off.

17. The power supply of claim 15, wherein, The voltage controller boosts the high-level voltage based on the external feedback high-level voltage stored in the compensation capacitor.

18. The power supply of claim 13, wherein, The power supply is configured to: dynamically decrease the high-level voltage for driving a display panel from a start high-level voltage to an end high-level voltage during one display period, the end high-level voltage being smaller than the start high-level voltage, and boost the high-level voltage from the end high-level voltage back to the start high-level voltage during the vertical blanking period and before a next display period starts.

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