Memory and reading circuit therefor

Abstract

The application discloses a memory and a reading circuit thereof. The memory comprises a plurality of memory arrays, each of which comprises a first array and a second array symmetrical with the structure of the first array. The reading circuit of the memory comprises a plurality of bit reading circuits corresponding to the plurality of memory arrays. Each bit reading circuit comprises a word line control circuit, a bit line control circuit and a current comparison circuit. The bit reading circuit can offset the sub-threshold leakage current introduced on the bit line, avoid the situation that the read values of the same memory bit are different in different scenes, and thus improve the reading accuracy of the variable resistance memory.

Description

Technical Field

[0001] This invention relates to the field of storage, and in particular to a memory and its read circuit. Background Technology

[0002] The storage mechanism of a variable-resistivity memory is based on the switching between low-resistance and high-resistance states of its storage device. A variable-resistivity memory contains multiple storage cells, and each storage cell contains multiple storage bits (used to store one binary digit). All storage bits within each storage cell are simultaneously read or written. For example... Figure 1 As shown, each storage bit of the variable resistance memory includes a variable resistor (used to store binary bits, which is in a high resistance state to represent the stored value of binary bit "1" and in a low resistance state to represent the stored value of binary bit "0") and a MOS switch (used to select the storage bit).

[0003] In a variable resistor memory, storage bits at the same location in different storage cells form the same storage array, and the storage bits of the same storage cell are arranged in the same position in different storage arrays. Each storage array contains multiple BLs (Bit Lines, each connecting to the source terminal of the storage bit in the same column of the storage array, i.e., the terminal of the variable resistor in the storage bit that is not connected to the MOS switch) and multiple WLs (Word Lines, each connecting to the gate of the MOS switch in the same row of the storage bits). The switching state of the MOS switch in the storage bit can be controlled through the WLs, and the voltage level of the storage bit can be obtained by turning on the BLs. Different storage bits can be selected through the coupling of the WLs and BLs. Each storage array selects only one storage bit at a time, and the specific storage bit selected is determined by the read address received by the variable resistor memory.

[0004] All storage bits on each BL of the variable resistive memory share a current comparison circuit. The current comparison circuit compares the current obtained from the connected BL with a preset reference current. If the obtained current is less than the preset reference current, it means that the selected storage bit on the BL is in a high-resistance state, and a signal indicating that the storage value of the currently selected storage bit is a binary bit "1" is output. If the obtained current is greater than the preset reference current, it means that the selected storage bit on the BL is in a low-resistance state, and a signal indicating that the storage value of the currently selected storage bit is a binary bit "0" is output, so as to realize the reading of stored data from the variable resistive memory.

[0005] As the capacity of variable resistor memory gradually increases, the length of the buffer line (BL) also increases. This increased BL length means a greater number of storage bits shared by the current comparator circuit, which can cause several negative effects. When reading a storage bit from a BL, although the MOS switches in other storage bits on that BL are off, these MOS switches all have subthreshold leakage current (the small leakage current between the source and drain when the MOS switch is in the cutoff region). This subthreshold leakage current accumulates on the BL, affecting the current obtained by the current comparator circuit. The longer the BL, the greater the impact. Furthermore, the subthreshold leakage current is affected by temperature; it is higher at higher temperatures than at lower temperatures. Therefore, even if the number of storage bits on the BL remains constant, the current obtained by the current comparator circuit will vary. However, the preset reference current of the current comparator circuit is fixed in different scenarios, so the stored value of the same storage bit may differ depending on the scenario, thus reducing the read accuracy of the variable resistor memory.

[0006] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that those skilled in the art need to solve at present. Summary of the Invention

[0007] The purpose of this invention is to provide a memory and its read circuit that can cancel out the subthreshold leakage current introduced into the bit line, thereby avoiding the situation where the stored value of the same memory bit is different in different scenarios, thus improving the read accuracy of the variable resistance memory.

[0008] To address the aforementioned technical problems, this invention provides a read circuit for a memory, applied to a memory comprising multiple memory arrays, each memory array including a first array and a second array structurally symmetrical to the first array; the read circuit for the memory includes multiple bit read circuits corresponding one-to-one with the multiple memory arrays; each bit read circuit includes:

[0009] Word line control circuits and bit line control circuits are respectively connected to the target memory array to be read;

[0010] A current comparison circuit connected to the bit line control circuit.

[0011] Optionally, the word line control circuit is connected to each word line of the first target array and the second target array in the target memory array, respectively, and is used to control the target word line where the target memory bit to be selected is located to close the first switching transistor in the target memory bit;

[0012] The bit line control circuit is connected to each bit line of the first target array and the second target array respectively, and is used to control the first bit line where the target storage bit is located and the second bit line which is structurally symmetrical with the first bit line to be turned on.

[0013] Optionally, the bit line control circuit includes:

[0014] Multiple second switching transistors are disposed on multiple bit lines of the first target array and the second target array; wherein, the first end of each second switching transistor is connected to the source end of the storage bit on the bit line, and the second end of each second switching transistor is connected to the current comparison circuit.

[0015] A switch control circuit, which is connected to the control terminals of a plurality of second switching transistors respectively, is used to control the second switching transistors located on the first bit line and the second bit line to close, so as to conduct the first bit line and the second bit line.

[0016] Optionally, the current comparison circuit includes:

[0017] A first current comparison sub-circuit, which is connected to the second terminals of a plurality of second switching transistors respectively, is used to enter a working state when the target storage bit is located in the first target array, to obtain the first current on the first bit line and the second current on the second bit line. If the current value obtained by superimposing the second current with a preset reference current is greater than the first current, a first signal representing that the storage value of the target storage bit is 1 is generated; otherwise, a second signal representing that the storage value of the target storage bit is 0 is generated.

[0018] A second current comparison sub-circuit, which is connected to the second terminals of multiple second switching transistors, is used to enter a working state when the target storage bit is located in the second target array, to obtain the first current and the second current. If the current value obtained by superimposing the second current with a preset reference current is greater than the first current, the first signal is generated; otherwise, the second signal is generated.

[0019] Optionally, the first current comparison sub-circuit includes a first switching device, a second switching device, a first reference resistor, and a first current-sensitive amplifier; wherein:

[0020] The first terminal of the first switching device is connected to the second terminals of a plurality of second switching transistors corresponding to the first target array. The second terminal of the first switching device is connected to the negative input terminal of the first current-sensitive amplifier. The first terminal of the second switching device is connected to the second terminals of a plurality of second switching transistors corresponding to the second target array. The second terminal of the second switching device is connected to the positive input terminal of the first current-sensitive amplifier and the first terminal of the first reference resistor. The second terminal of the first reference resistor is grounded. The first and second switching devices are closed when the target memory bit is located in the first target array and open when the target memory bit is located in the second target array.

[0021] The first current-sensitive amplifier is configured to output a high-level signal indicating that the storage value of the target storage bit is 1 if the current at its positive input terminal is greater than the current at its negative input terminal; otherwise, it outputs a low-level signal indicating that the storage value of the target storage bit is 0.

[0022] Optionally, the first current comparator sub-circuit further includes a third switch and a fourth switch; wherein:

[0023] The first terminal of the third switch is connected to the second terminal of the first switch device, the second terminal of the third switch is connected to the negative input terminal of the first current-sensitive amplifier, the control terminal of the third switch is connected to a first voltage, the first terminal of the fourth switch is connected to the first terminal of the first reference resistor and the second terminal of the second switch device, the second terminal of the fourth switch is connected to the positive input terminal of the first current-sensitive amplifier, and the control terminal of the fourth switch is connected to a second voltage; wherein, the resistance values ​​on the lines containing the third and fourth switches are adjusted accordingly by adjusting the first and second voltages.

[0024] Optionally, the second current comparator sub-circuit includes a third switching device, a fourth switching device, a second reference resistor, and a second current-sensitive amplifier; wherein:

[0025] The first terminal of the third switching device is connected to the second terminals of the plurality of second switching transistors corresponding to the second target array, and the second terminal of the third switching device is connected to the negative input terminal of the second current-sensitive amplifier. The first terminal of the fourth switching device is connected to the second terminals of the plurality of second switching transistors corresponding to the first target array, and the second terminal of the fourth switching device is connected to the positive input terminal of the second current-sensitive amplifier and the first terminal of the second reference resistor, the second terminal of the second reference resistor being grounded. The third and fourth switching devices are closed when the target memory bit is located in the second target array and open when the target memory bit is located in the first target array.

[0026] The second current-sensitive amplifier is used to output a high-level signal indicating that the storage value of the target storage bit is 1 if the current at its positive input terminal is greater than the current at its negative input terminal; otherwise, it outputs a low-level signal indicating that the storage value of the target storage bit is 0.

[0027] Optionally, the second current comparator sub-circuit further includes a fifth switch and a sixth switch; wherein:

[0028] The first terminal of the fifth switch is connected to the second terminal of the third switch, the second terminal of the fifth switch is connected to the negative input terminal of the second current-sensitive amplifier, the control terminal of the fifth switch is connected to a first voltage, the first terminal of the sixth switch is connected to the first terminal of the second reference resistor and the second terminal of the fourth switch, the second terminal of the sixth switch is connected to the positive input terminal of the second current-sensitive amplifier, and the control terminal of the sixth switch is connected to a second voltage; wherein, the resistance values ​​on the lines containing the fifth and sixth switches are adjusted accordingly by adjusting the first and second voltages.

[0029] Optionally, the first switching device, the second switching device, the third switching device, and the fourth switching device are all portals.

[0030] To address the aforementioned technical problems, the present invention also provides a memory, including multiple memory arrays and a read circuit for any of the aforementioned memory types.

[0031] Optionally, the memory is a phase-change memory, a magnetic random access memory, or a resistive random access memory.

[0032] This invention provides a read circuit for a memory, applied to a memory comprising multiple memory arrays, each memory array including a first array and a second array structurally symmetrical to the first array; the read circuit includes multiple bit read circuits corresponding one-to-one with the multiple memory arrays; each bit read circuit includes a word line control circuit, a bit line control circuit, and a current comparison circuit. The bit read circuit of this application can cancel out the subthreshold leakage current introduced into the bit line, avoiding the situation where the stored value of the same memory bit is different under different scenarios, thereby improving the read accuracy of the variable resistor memory.

[0033] The present invention also provides a memory that has the same beneficial effects as the read circuit described above. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the structure of a storage bit in the prior art;

[0036] Figure 2 This is a schematic diagram of the structure of a read circuit for a memory provided in an embodiment of the present invention;

[0037] Figure 3 A comparison diagram of the reference current window at different temperatures provided in an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of the specific structure of a read circuit for a memory provided in an embodiment of the present invention;

[0039] Figure 5 A schematic diagram of the working principle of a read circuit for a memory provided in an embodiment of the present invention;

[0040] Figure 6 A simplified schematic diagram of a read circuit for a memory provided in an embodiment of the present invention. Detailed Implementation

[0041] The core of this invention is to provide a memory and its read circuit that can cancel out the subthreshold leakage current introduced into the bit line, thereby avoiding the situation where the stored value of the same memory bit is different in different scenarios, thus improving the read accuracy of the variable resistance memory.

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a read circuit for a memory provided in an embodiment of the present invention.

[0044] The read circuit of this memory is applied to a memory (variable resistive memory, such as phase-change memory, magnetic random access memory, or resistive random access memory) containing multiple memory arrays. Each memory array includes a first array and a second array that is structurally symmetrical to the first array. The read circuit of the memory includes multiple bit read circuits corresponding one-to-one with the multiple memory arrays. Each bit read circuit includes:

[0045] The word line control circuit 100, which is connected to each word line of the first target array and the second target array in the target memory array to be read, is used to control the target word line where the target memory bit to be selected is located to close the first switch in the target memory bit.

[0046] The bit line control circuit 200, which is connected to each bit line of the first target array and the second target array respectively, is used to control the first bit line where the target storage bit is located and the second bit line which is structurally symmetrical to the first bit line to be turned on.

[0047] The current comparison circuit 300, connected to the bit line control circuit 200, is used to obtain the first current on the first bit line and the second current on the second bit line. If the current value obtained by superimposing the second current with the preset reference current is greater than the first current, a first signal representing that the storage value of the target storage bit is 1 is generated; otherwise, a second signal representing that the storage value of the target storage bit is 0 is generated.

[0048] Specifically, the memory of this application includes multiple memory arrays (the memory bits corresponding to the same position in different memory cells form the same memory array, and the arrangement position of each memory bit in the same memory cell is the same in different memory arrays), and each memory array includes a first array and a second array, and the first array and the second array are structurally symmetrical.

[0049] The memory's read circuitry includes multiple bit read circuits, each corresponding to one of the multiple memory arrays. Each bit read circuit reads the stored value of each bit in its corresponding memory array. Each bit read circuit reads the stored value of only one bit in its corresponding memory array at a time. Since all bits within each memory cell are read or written simultaneously, the multiple bit read circuits read the stored bits of the same memory cell one by one, thus obtaining the stored values ​​of each memory cell within the memory.

[0050] Based on this, each bit read circuit includes a word line control circuit 100, a bit line control circuit 200, and a current comparison circuit 300, and its working principle is as follows:

[0051] The word line control circuit 100 is connected to each word line of the first array (referred to as the first target array) and the second array (referred to as the second target array) in the corresponding read memory array (referred to as the target memory array). The word line control circuit 100 can control the word line (referred to as the target word line) where the selected memory bit (referred to as the target memory bit) is located to close the first switch transistor in the target memory bit (in fact, all the switch transistors connected to the target word line are closed).

[0052] Bit line control circuit 200 is connected to each bit line of the first target array and the second target array respectively. The target word line can control the bit line containing the target storage bit (called the first bit line) and the bit line that is structurally symmetrical to the first bit line (called the second bit line) to be turned on. If the target storage bit is located in the first target array, the first bit line is a bit line in the first target array, and the second bit line is a bit line in the second target array. The first bit line and the second bit line are structurally symmetrical. If the target storage bit is located in the second target array, the first bit line is a bit line in the second target array, and the second bit line is a bit line in the first target array. The first bit line and the second bit line are structurally symmetrical.

[0053] The current comparison circuit 300 is connected to the bit line control circuit 200. The current comparison circuit 300 can acquire the current on the first bit line (called the first current) and the current on the second bit line (called the second current), and superimpose the second current on the second bit line with a preset reference current to obtain a reference correction current. Then, the reference correction current is compared with the first current on the first bit line. If the reference correction current is greater than the first current, it indicates that the target storage bit selected on the first bit line is in a high-impedance state, and a first signal representing that the storage value of the target storage bit is 1 is generated. If the reference correction current is less than the first current, it indicates that the target storage bit selected on the first bit line is in a low-impedance state, and a second signal representing that the storage value of the target storage bit is 0 is generated.

[0054] It should be noted that the reason why existing memory read circuits may read different values ​​for the same memory bit under different scenarios is because: subthreshold leakage current is affected by temperature; the subthreshold leakage current at high temperatures is higher than that at low temperatures. Therefore, the condition for accurate characterization of bit data at high temperatures is: I data_HR +I data_lkg_hot <I ref data_LR +I data_lkg_hot Conditions for accurate characterization of metadata at low temperatures: I data_HR +I data_lkg_cold <I ref data_LR +I data_lkg_cold (I data_lkg_hot >I data_lkg_cold ); Conditions for accurate characterization of metadata under high and low temperatures: I ref_window =I ref_cold_window ∩I ref_hot_window Among them, I data_HR This refers to the current accumulated on the bit line of the first storage bit when the selected first storage bit is in a high-impedance state; I data_lkg_hot This refers to the subthreshold leakage current accumulated on the bit line containing the first storage bit at high temperatures; I ref Preset reference current; I data_LR This refers to the current accumulated on the bit line of the first storage bit when the selected first storage bit is in a low-impedance state; I data_lkg_cold This refers to the subthreshold leakage current accumulated on the bit line containing the first storage bit at low temperatures; I ref_cold_window Reference current I ref The first reading reference current window at low temperature; I ref_hot_window Reference current I ref The second reference current window at high temperature; I ref_window The intersection of the first and second reference current windows, i.e., the composite reference current window under high and low temperatures (reference). Figure 3 ).from Figure 3 It can be seen that the reference current reading window is inconsistent at different temperatures due to the variation in leakage current at high and low temperatures. Therefore, when the reference current I... ref When the first and second reference current windows are set to non-overlapping positions, there may be cases where the stored value of the same storage bit is different under different temperature scenarios.

[0055] ​​In the read circuit of the memory in this application, it can be understood that the second current on the second bit line is formed by the accumulation of the subthreshold leakage current of the switching transistor in each storage bit on the second bit line, which can roughly offset the subthreshold leakage current introduced in the first current on the first bit line. This eliminates the problem of inconsistent read reference current window at different temperatures caused by the change of leakage current at high and low temperatures, and avoids the situation where the stored value of the same storage bit is different under different scenarios.

[0056] It should also be noted that since multiple bit read circuits read each bit of the same memory cell one by one each time, and the arrangement position of each bit of the same memory cell is the same in different memory arrays, that is, the arrangement position of the selected memory bits in different memory arrays is the same each time, multiple bit read circuits can share the word line control circuit 100 and the bit line control circuit 200 to save circuit costs.

[0057] As can be seen, this application provides a read circuit for a memory, applied to a memory comprising multiple memory arrays, each memory array including a first array and a second array structurally symmetrical to the first array; the read circuit includes multiple bit read circuits corresponding one-to-one with the multiple memory arrays; each bit read circuit includes a word line control circuit, a bit line control circuit, and a current comparison circuit. The bit read circuit can cancel out the subthreshold leakage current introduced into the bit line, avoiding the situation where the stored value of the same memory bit is different under different scenarios, thereby improving the read accuracy of the variable resistive memory.

[0058] Based on the above embodiments:

[0059] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the specific structure of a read circuit for a memory provided in an embodiment of the present invention.

[0060] As an optional embodiment, the bit line control circuit 200 includes:

[0061] Multiple second switching transistors Q2 are disposed on multiple bit lines of the first target array and the second target array; wherein, the first end of each second switching transistor Q2 is connected to the source end of the storage bit on the bit line, and the second end of each second switching transistor Q2 is connected to the current comparison circuit 300.

[0062] A switch control circuit, which is connected to the control terminals of multiple second switch transistors Q2 respectively, is used to control the second switch transistors Q2 located on the first bit line and the second bit line to close, so as to conduct the first bit line and the second bit line.

[0063] Specifically, the bit line control circuit 200 of this application includes multiple second switching transistors Q2 and a switching control circuit, and its working principle is as follows:

[0064] Multiple second switches Q2 are disposed on multiple bit lines of the first target array and the second target array, and the switching states of the multiple second switches Q2 are controlled by a switch control circuit. The switch control circuit is used to control the second switches Q2 located on the first bit line where the selected target memory bit is located and on the second bit line that is structurally symmetrical to the first bit line to close, so as to turn on the first bit line and the second bit line.

[0065] As an optional embodiment, the current comparison circuit 300 includes:

[0066] A first current comparison sub-circuit, which is connected to the second terminals of multiple second switching transistors Q2 respectively, is used to enter the working state when the target storage bit is located in the first target array, in order to obtain the first current and the second current. If the current value obtained by superimposing the second current and the preset reference current is greater than the first current, then the first signal is generated; otherwise, the second signal is generated.

[0067] The second current comparison sub-circuit, which is connected to the second terminals of multiple second switching transistors Q2 respectively, is used to enter the working state when the target storage bit is located in the second target array, so as to obtain the first current and the second current. If the current value obtained by superimposing the second current and the preset reference current is greater than the first current, the first signal is generated; otherwise, the second signal is generated.

[0068] Specifically, the current comparison circuit 300 of this application includes a first current comparison sub-circuit and a second current comparison sub-circuit, and its working principle is as follows:

[0069] When the selected target memory bit is located in the first target array, the first current comparison sub-circuit enters the working state (at this time, the second current comparison sub-circuit does not work); when the selected target memory bit is located in the second target array, the second current comparison sub-circuit enters the working state (at this time, the first current comparison sub-circuit does not work). The working principle of the first current comparison sub-circuit and the second current comparison sub-circuit is the same: the first current on the first bit line and the second current on the second bit line are obtained, and the second current on the second bit line is superimposed with a preset reference current to obtain a reference correction current. Then, the reference correction current is compared with the first current on the first bit line. If the reference correction current is greater than the first current, a first signal representing the storage value of the target memory bit is generated as 1; if the reference correction current is less than the first current, a second signal representing the storage value of the target memory bit is generated as 0.

[0070] As an optional embodiment, the first current comparator sub-circuit includes a first switching device K1, a second switching device K2, and a first reference resistor R. REF1 and the first current-sensitive amplifier SA1; where:

[0071] The first terminal of the first switching device K1 is connected to the second terminals of the plurality of second switching transistors Q2 corresponding to the first target array, and the second terminal of the first switching device K1 is connected to the negative input terminal of the first current-sensitive amplifier SA1. The first terminal of the second switching device K2 is connected to the second terminals of the plurality of second switching transistors Q2 corresponding to the second target array, and the second terminal of the second switching device K2 is connected to the positive input terminal of the first current-sensitive amplifier SA1 and the first reference resistor R. REF1 The first terminal is connected to the first reference resistor R. REF1 The second terminal is grounded; wherein, the first switching device K1 and the second switching device K2 are closed when the target memory bit is located in the first target array and open when the target memory bit is located in the second target array;

[0072] The first current-sensitive amplifier SA1 is used to output a high-level signal indicating that the storage value of the target storage bit is 1 if the current at its positive input terminal is greater than the current at its negative input terminal; otherwise, it outputs a low-level signal indicating that the storage value of the target storage bit is 0.

[0073] Specifically, the first current comparison sub-circuit of this application includes a first switching device K1, a second switching device K2, and a first reference resistor R. REF1 The first current-sensitive amplifier SA1 works as follows:

[0074] The first switching device K1 and the second switching device K2 are closed when the target storage bit is located in the first target array and open when the target storage bit is located in the second target array, so that the first current comparator sub-circuit only enters the working state when the target storage bit is located in the first target array.

[0075] The positive input terminal of the first current-sensitive amplifier SA1 is the first reference resistor R. REF1 The generated reference current is superimposed on the second current on the second bit line, which is the reference correction current; the negative input of the first current-sensitive amplifier SA1 is the first current on the first bit line. When the reference correction current is greater than the first current, the first current-sensitive amplifier SA1 outputs a high-level signal indicating that the storage value of the target storage bit is 1; when the reference correction current is less than the first current, it outputs a low-level signal indicating that the storage value of the target storage bit is 0.

[0076] As an optional embodiment, the first current comparator sub-circuit further includes a third switch Q3 and a fourth switch Q4; wherein:

[0077] The first terminal of the third switch Q3 is connected to the second terminal of the first switching device K1. The second terminal of the third switch Q3 is connected to the negative input terminal of the first current-sensitive amplifier SA1. The control terminal of the third switch Q3 is connected to the first voltage. The first terminal of the fourth switch Q4 is connected to the first reference resistor R.REF1 The first terminal of the first switch is connected to the second terminal of the second switch device K2, the second terminal of the fourth switch Q4 is connected to the positive input terminal of the first current sensitive amplifier SA1, and the control terminal of the fourth switch Q4 is connected to the second voltage; wherein, the resistance values ​​on the lines where the third switch Q3 and the fourth switch Q4 are located are adjusted accordingly by adjusting the first voltage and the second voltage.

[0078] Furthermore, the first current comparison sub-circuit of this application also includes a third switch Q3 and a fourth switch Q4, and its working principle is as follows:

[0079] The third switch Q3 and the fourth switch Q4 are mainly used to adjust the reference current setting during the initial debugging phase. Adjusting the first voltage (Vref) connected to the control terminal of the third switch Q3 adjusts its resistance, which is equivalent to adjusting the current in the circuit containing the third switch Q3. Similarly, adjusting the second voltage (Vclamp) connected to the control terminal of the fourth switch Q4 adjusts its resistance, which is equivalent to adjusting the current in the circuit containing the fourth switch Q4. It is understandable that the circuit parameter design of the first current comparator subcircuit only needs to ensure that the bit data is accurately represented.

[0080] As an optional embodiment, the second current comparator sub-circuit includes a third switching device K3, a fourth switching device K4, and a second reference resistor R. REF2 and the second current-sensitive amplifier SA2; where:

[0081] The first terminal of the third switching device K3 is connected to the second terminal of the plurality of second switching transistors Q2 corresponding to the second target array. The second terminal of the third switching device K3 is connected to the negative input terminal of the second current-sensitive amplifier SA2. The first terminal of the fourth switching device K4 is connected to the second terminal of the plurality of second switching transistors Q2 corresponding to the first target array. The second terminal of the fourth switching device K4 is connected to the positive input terminal of the second current-sensitive amplifier SA2 and the second reference resistor R. REF2 The first terminal is connected to the second reference resistor R. REF2 The second terminal is grounded; wherein, the third switching device K3 and the fourth switching device K4 are closed when the target memory bit is located in the second target array and open when the target memory bit is located in the first target array;

[0082] The second current-sensitive amplifier SA2 is used to output a high-level signal indicating that the storage value of the target storage bit is 1 if the current at its positive input terminal is greater than the current at its negative input terminal; otherwise, it outputs a low-level signal indicating that the storage value of the target storage bit is 0.

[0083] Specifically, the second current comparison sub-circuit of this application includes a third switching device K3, a fourth switching device K4, and a second reference resistor R. REF2 The second current-sensitive amplifier SA2 works as follows:

[0084] The third switching device K3 and the fourth switching device K4 are closed when the target storage bit is in the second target array and open when the target storage bit is in the first target array, so that the second current comparator sub-circuit only enters the working state when the target storage bit is in the second target array.

[0085] The positive input terminal of the second current-sensitive amplifier SA2 is the second reference resistor R. REF2 The generated reference current is superimposed on the second current on the second bit line, which is the reference correction current; the negative input of the second current sensitive amplifier SA2 is the first current on the first bit line. When the reference correction current is greater than the first current, the second current sensitive amplifier SA2 outputs a high-level signal indicating that the storage value of the target storage bit is 1; when the reference correction current is less than the first current, it outputs a low-level signal indicating that the storage value of the target storage bit is 0.

[0086] As an optional embodiment, the second current comparator circuit further includes a fifth switch Q5 and a sixth switch Q6; wherein:

[0087] The first terminal of the fifth switch Q5 is connected to the second terminal of the third switch K3. The second terminal of the fifth switch Q5 is connected to the negative input terminal of the second current-sensitive amplifier SA2. The control terminal of the fifth switch Q5 is connected to the first voltage. The first terminal of the sixth switch Q6 is connected to the second reference resistor R. REF2 The first terminal is connected to the second terminal of the fourth switching device K4, the second terminal of the sixth switching transistor Q6 is connected to the positive input terminal of the second current-sensitive amplifier SA2, and the control terminal of the sixth switching transistor Q6 is connected to the second voltage; wherein, the resistance values ​​on the lines where the fifth switching transistor Q5 and the sixth switching transistor Q6 are located are adjusted accordingly by adjusting the first voltage and the second voltage.

[0088] Furthermore, the second current comparison sub-circuit of this application also includes a fifth switch Q5 and a sixth switch Q6, and its working principle is as follows:

[0089] The fifth switch Q5 and the sixth switch Q6 are mainly used to adjust the reference current setting during the initial debugging phase. Adjusting the first voltage connected to the control terminal of the fifth switch Q5 adjusts its resistance, which is equivalent to adjusting the current in the circuit containing the fifth switch Q5. Similarly, adjusting the second voltage connected to the control terminal of the sixth switch Q6 adjusts its resistance, which is equivalent to adjusting the current in the circuit containing the sixth switch Q6. It is understandable that the circuit parameter design of the second current comparator subcircuit only needs to ensure that the bit data is accurately represented.

[0090] As an optional embodiment, the first switching device K1, the second switching device K2, the third switching device K3 and the fourth switching device K4 are all portals.

[0091] Specifically, the first switching device K1, the second switching device K2, the third switching device K3 and the fourth switching device K4 of this application can all be transmission gates, or other switching devices can be used. This application does not make any special restrictions here.

[0092] In addition, each switching transistor in the read circuit of the memory in this application can be a MOS transistor (specifically an NMOS transistor), or other switching transistors can be used. This application does not make any special restrictions here.

[0093] In summary, as Figure 4 As shown, the word line address range of the first array is 0 to y-1, and the word line address range of the second array is y to 2y-1. When accessing the target memory bit of the first array, if the valid word line is WL... y-2 The valid bit line is BL1, and BL1 in the second array is also valid, meaning NMOS CSL1 is in the closed state. Simultaneously, the gate control signal ctrl0 in the first array is valid, meaning gates K1 and K2 are in the open state; the gate control signal ctrl1 in the second array is invalid, meaning gates K3 and K4 are in the open state. The simplified circuit at this point is as follows: Figure 5 As shown.

[0094] At this time, the first reference resistor R at the reference terminal (positive input terminal) of the first current-sensitive amplifier SA1 REF1 It is connected in parallel with the y memory bit structures at the same address in the second array. During the read process, when there is a leakage current I in the other (y-1) memory bit structures on BL1 where the target memory bit in the first array is located, lkg_dataAt that time, since the reference terminal of the first sensitive amplifier has almost the same number of storage bits connected in parallel, almost the same leakage current is introduced at the reference terminal, and the leakage current of the two parts has the same temperature characteristics, so it can cancel out the influence of the leakage current of other unselected switching transistors on the first array BL1.

[0095] In other words, Figure 5 The circuit principle can be simplified to Figure 6 The structure of the first current-sensitive amplifier SA1, the current I at the data terminal (negative input terminal) data =I data' +(y-1)*I lkg_data ((y-1)*I lkg_data =I data_lkg The current I at the reference terminal of the first current-sensitive amplifier SA1 ref =I ref' +y*I lkg_ref (y*I lkg_ref =I ref_lkg ); Conditions for accurate characterization of bit data: I data_HR' +(y-1)*I lkg_data <I ref' +y*I lkg_ref data_LR' +(y-1)*I lkg_data ;I lkg_data =I lkg_ref When y is relatively large, we have: I data_HR' <I ref' data_LR' Among them, I data' For the current accumulated on the first line in the target storage bit; I ref' Reference current; I lkg_ref The current accumulated on the second bit line for one storage bit; I data_HR' This refers to the current accumulated on the first line of the target memory bit when the target memory bit is in a high-impedance state; I data_LR' When the target memory bit is in a low-resistance state, the current accumulated on the first line of the target memory bit.

[0096] This application also provides a memory, including multiple memory arrays and read circuitry for any of the aforementioned memory types.

[0097] As an optional embodiment, the memory is a phase-change memory, a magnetic random access memory, or a resistive random access memory.

[0098] For a description of the memory provided in this application, please refer to the above-described embodiment of the read circuit; further details will not be repeated here.

[0099] ​​It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0100] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A read circuit for a memory, characterized in that, Applied to a memory comprising multiple memory arrays, each of the memory arrays including a first array and a second array that is structurally symmetrical to the first array; The read circuit of the memory includes multiple bit read circuits that correspond one-to-one with the multiple memory arrays; Each of the aforementioned bit read circuits includes: Word line control circuits and bit line control circuits are respectively connected to the target memory array to be read; A current comparison circuit connected to the bit line control circuit; The bit line control circuit is connected to each bit line of the first target array and the second target array in the target memory array, respectively, and is used to control the first bit line where the target memory bit to be selected is located and the second bit line that is structurally symmetrical to the first bit line to be turned on. The bit line control circuit includes: Multiple second switching transistors are disposed on multiple bit lines of the first target array and the second target array; wherein, the first end of each second switching transistor is connected to the source end of the storage bit on the bit line, and the second end of each second switching transistor is connected to the current comparison circuit. A switch control circuit, which is connected to the control terminals of a plurality of second switching transistors respectively, is used to control the second switching transistors located on the first bit line and the second bit line to close, so as to conduct the first bit line and the second bit line; The current comparison circuit includes: A first current comparison sub-circuit, which is connected to the second terminals of a plurality of second switching transistors respectively, is used to enter a working state when the target storage bit is located in the first target array, to obtain the first current on the first bit line and the second current on the second bit line. If the current value obtained by superimposing the second current with a preset reference current is greater than the first current, a first signal representing that the storage value of the target storage bit is 1 is generated; otherwise, a second signal representing that the storage value of the target storage bit is 0 is generated. A second current comparison sub-circuit, which is connected to the second terminals of multiple second switching transistors, is used to enter a working state when the target storage bit is located in the second target array, to obtain the first current and the second current. If the current value obtained by superimposing the second current with a preset reference current is greater than the first current, the first signal is generated; otherwise, the second signal is generated.

2. The read circuit of the memory as described in claim 1, characterized in that, The word line control circuit is connected to each word line of the first target array and the second target array in the target memory array, respectively, and is used to control the target word line where the target memory bit to be selected is located to close the first switch in the target memory bit.

3. The read circuit of the memory as described in claim 1, characterized in that, The first current comparator sub-circuit includes a first switching device, a second switching device, a first reference resistor, and a first current-sensitive amplifier; wherein: The first terminal of the first switching device is connected to the second terminals of a plurality of second switching transistors corresponding to the first target array. The second terminal of the first switching device is connected to the negative input terminal of the first current-sensitive amplifier. The first terminal of the second switching device is connected to the second terminals of a plurality of second switching transistors corresponding to the second target array. The second terminal of the second switching device is connected to the positive input terminal of the first current-sensitive amplifier and the first terminal of the first reference resistor. The second terminal of the first reference resistor is grounded. The first and second switching devices are closed when the target memory bit is located in the first target array and open when the target memory bit is located in the second target array. The first current-sensitive amplifier is configured to output a high-level signal indicating that the storage value of the target storage bit is 1 if the current at its positive input terminal is greater than the current at its negative input terminal; otherwise, it outputs a low-level signal indicating that the storage value of the target storage bit is 0.

4. The read circuit of the memory as described in claim 3, characterized in that, The first current comparator sub-circuit further includes a third switch and a fourth switch; wherein: The first terminal of the third switch is connected to the second terminal of the first switch device, the second terminal of the third switch is connected to the negative input terminal of the first current-sensitive amplifier, the control terminal of the third switch is connected to a first voltage, the first terminal of the fourth switch is connected to the first terminal of the first reference resistor and the second terminal of the second switch device, the second terminal of the fourth switch is connected to the positive input terminal of the first current-sensitive amplifier, and the control terminal of the fourth switch is connected to a second voltage; wherein, the resistance values ​​on the lines containing the third and fourth switches are adjusted accordingly by adjusting the first and second voltages.

5. The read circuit of the memory as described in claim 3 or 4, characterized in that, The second current comparator sub-circuit includes a third switching device, a fourth switching device, a second reference resistor, and a second current-sensitive amplifier; wherein: The first terminal of the third switching device is connected to the second terminals of the plurality of second switching transistors corresponding to the second target array, and the second terminal of the third switching device is connected to the negative input terminal of the second current-sensitive amplifier. The first terminal of the fourth switching device is connected to the second terminals of the plurality of second switching transistors corresponding to the first target array, and the second terminal of the fourth switching device is connected to the positive input terminal of the second current-sensitive amplifier and the first terminal of the second reference resistor, the second terminal of the second reference resistor being grounded. The third and fourth switching devices are closed when the target memory bit is located in the second target array and open when the target memory bit is located in the first target array. The second current-sensitive amplifier is used to output a high-level signal indicating that the storage value of the target storage bit is 1 if the current at its positive input terminal is greater than the current at its negative input terminal; otherwise, it outputs a low-level signal indicating that the storage value of the target storage bit is 0.

6. The read circuit of the memory as described in claim 5, characterized in that, The second current comparator sub-circuit further includes a fifth switch and a sixth switch; wherein: The first terminal of the fifth switch is connected to the second terminal of the third switch, the second terminal of the fifth switch is connected to the negative input terminal of the second current-sensitive amplifier, the control terminal of the fifth switch is connected to a first voltage, the first terminal of the sixth switch is connected to the first terminal of the second reference resistor and the second terminal of the fourth switch, the second terminal of the sixth switch is connected to the positive input terminal of the second current-sensitive amplifier, and the control terminal of the sixth switch is connected to a second voltage; wherein, the resistance values ​​on the lines containing the fifth and sixth switches are adjusted accordingly by adjusting the first and second voltages.

7. The read circuit of the memory as described in claim 5, characterized in that, The first switching device, the second switching device, the third switching device, and the fourth switching device are all portals.

8. A memory, characterized in that, It includes multiple memory arrays and read circuitry for the memory as described in any one of claims 1-7.

9. The memory as claimed in claim 8, characterized in that, The memory is a phase-change memory, a magnetic random access memory, or a resistive random access memory.

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