A four-channel fin-type vertical silicon carbide device and a method of fabricating the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SIRIUS CORE SEMICON (CHENGDU) CO LTD
- Filing Date
- 2023-03-23
- Publication Date
- 2026-06-12
Smart Images
Figure CN116417500B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon carbide devices, and in particular to a four-channel fin-type vertical silicon carbide device and its fabrication method. Background Technology
[0002] Silicon carbide (SiC) materials possess excellent physical and electrical properties. With their unique advantages such as wide bandgap, high thermal conductivity, large saturation drift velocity, and high critical breakdown electric field, they have become ideal semiconductor materials for manufacturing high-power, high-frequency, high-voltage, high-temperature resistant, and radiation-resistant devices, and have broad application prospects in both military and civilian fields.
[0003] Silicon carbide MOSFETs (Metal Oxide Semiconductor Field-effect Transistors) offer advantages such as fast switching speed and low on-resistance. They also achieve high breakdown voltage levels with a relatively small drift layer thickness, reducing the size of power switching modules and lowering energy consumption, making them particularly advantageous in power switching and converter applications. With the rapid development of emerging electronic information industries such as 5G communication, smart home appliances, and autonomous driving, the importance of silicon carbide MOSFETs is increasingly prominent, demanding that power MOSFETs advance towards higher rated power, faster switching speeds, and lower drive power consumption. Existing MOSFETs (PIC7) utilize dummy regions on both sides to effectively protect the gate and improve device performance, but this leads to an increased device area and reduced power per unit area, resulting in lower device power. Summary of the Invention
[0004] In view of this, the present invention provides a four-channel fin-type vertical silicon carbide device to increase the current channels and improve the device power. Specifically, it is a four-channel fin-type vertical silicon carbide device with an N-type substrate layer;
[0005] An N-type doped drift layer is located on the upper surface of the N-type substrate layer;
[0006] Two fin-shaped silicon walls are provided, which are spaced apart and parallel to each other and formed on the upper surface of the drift layer. The two fin-shaped silicon walls are symmetrical about the centerline of the device. The fin-shaped silicon walls include an N-type doped buffer layer, a P-well layer, an N+ region, and a P+ region. The N-type doped buffer layer is located on the upper surface of the N-type doped drift layer, and the P-well layer is located on the upper surface of the N-type doped buffer layer. A source region is provided on the upper surface of the P-well layer, which includes two N+ regions and one P+ region. The P+ region is located between the two N+ regions.
[0007] P-type shielding regions, at least two of them, are symmetrical about the centerline of the device and are located in a portion of the upper part of the N-type doped drift layer. One of the P-type shielding regions is located at the bottom of one fin silicon wall on the side away from the other fin silicon wall.
[0008] The gate oxide layer is located on the upper surface of the P-type shielding region, the side surfaces of the two fin silicon walls, and the upper surface of the N-type doped buffer layer between the two fin silicon walls.
[0009] A polysilicon gate layer is located on the inner surface of the gate oxide layer, and the upper surface of the polysilicon gate layer between the two finned silicon walls is flush with the upper surface of the source region.
[0010] The first conductive material is located on the lower surface of the N-type substrate layer, forming the drain electrode;
[0011] The second conductive material is located on the upper surface of the polysilicon gate layer between the two finned silicon walls, forming the gate;
[0012] The third conductive material is located on the upper surface of the source region, forming the source electrode.
[0013] Furthermore, the lower surface of the polysilicon gate layer between the two finned silicon walls is closer to the N-type substrate layer than the lower surface of the P-well layer.
[0014] Furthermore, it also includes a fourth conductive material located on the upper surface of the N-type doped drift layer where no P-type shielding region is provided, wherein the P-type shielding region is short-circuited to the source electrode.
[0015] Furthermore, a polysilicon gate layer located on the side of one finned silicon wall away from the other finned silicon wall forms a sidewall. The sidewall is disposed on a portion of the gate oxide layer above the P-type shielding region, and the farthest end of the sidewall from the N-type substrate layer is flush with the upper surface of the source region.
[0016] Furthermore, along the direction away from the N-type substrate layer, the cross-section of the polysilicon gate layer forming the sidewalls gradually decreases.
[0017] Furthermore, along the direction away from the N-type substrate layer, the slope of the cross-section of the polysilicon gate layer forming the sidewalls gradually decreases.
[0018] Furthermore, the thickness of the drift layer is 6 μm.
[0019] Furthermore, the doping element of the P-type shielding region is B or Al, and the doping concentration of the P-type shielding region is higher than that of the P-well layer.
[0020] Furthermore, the doping concentration of the P-type shielding region is 1e17, and its thickness is 0.2 μm.
[0021] A method for fabricating the above-mentioned four-channel fin-type vertical silicon carbide device is also proposed, the method comprising the following steps:
[0022] S1. An N-type doped drift layer is grown on the upper surface of an N-type substrate. Subsequently, P+ is implanted in the corresponding region on the upper surface of the N-type doped drift layer to form a P-type shielding region.
[0023] S2. Continue to grow an N-type doped buffer layer on the upper surface of the N-type doped drift layer, grow a P-well layer on the upper surface of the N-type doped buffer layer, and implant N+ and P+ on the upper surface of the P-well layer to form a source region.
[0024] S3. Etching to form two fin-shaped silicon walls, specifically etching trench one between the two fin-shaped silicon walls and trench two on the outer side of the fin-shaped silicon walls to form two spaced and parallel fin-shaped silicon walls.
[0025] S4. Gate oxide is formed by filling the upper surface of the P-type shielding region, the N-type doped drift layer, the side surfaces of the two fin silicon walls, and the upper surface of the N-type doped buffer layer between the two fin silicon walls with gate oxide; polysilicon is then filled on the upper surfaces of the gate oxide and the source region.
[0026] S5. Etch polysilicon to retain the polysilicon located on the inner surface of the gate oxide layer, forming a polysilicon gate layer;
[0027] S6. Deposit conductive materials: deposit a first conductive material on the lower surface of the N-type substrate to form the drain, deposit a second conductive material on the upper surface of the polysilicon gate layer between the two finned silicon walls to form the gate, and deposit a third conductive material on the upper surface of the source region to form the source.
[0028] Compared with the prior art, the beneficial effects of the present invention are:
[0029] 1. By setting two fin silicon walls and setting a source region on each fin silicon wall, the source region includes two N+ regions and one P+ region. The P+ region is set between the two N+ regions, which increases the number of current channels of the device from the original two channels to four channels, thereby improving the power of the device.
[0030] 2. The depletion region is generated by the JFET effect between the P-type buried layers formed by the P-well layer 105 below the source region, which blocks the electric field lines and can effectively protect the gate structure. At the same time, it can also effectively protect the integrated SBD diode and improve the reverse performance of the device.
[0031] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 A schematic diagram of the structure of a four-channel fin-type vertical silicon carbide device provided in an embodiment of the present invention is shown.
[0034] Figure 2 The diagram illustrates the fabrication process of a four-channel fin-type vertical silicon carbide device provided in an embodiment of the present invention.
[0035] Explanation of reference numerals in the attached figures:
[0036] 101 N-type substrate layer; 102 N-type doped drift layer; 103 P-type shielding region; 104 N-type doped buffer layer; 105 P-well layer; 106 N+ region; 107 P+ region; 108 gate oxide layer; 109 polysilicon gate layer; 110 conductive material. Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0038] The four-channel fin-type vertical silicon carbide device provided in this embodiment of the invention, see [link to relevant documentation]. Figure 1 ,include,
[0039] N-type substrate layer 101;
[0040] An N-type doped drift layer 102 is located on the upper surface of the N-type substrate layer 101;
[0041] Two fin-shaped silicon walls are provided, which are spaced apart and parallel to each other and formed on the upper surface of the N-type doped drift layer 102. The two fin-shaped silicon walls are symmetrical about the centerline of the device. The fin-shaped silicon walls include an N-type doped buffer layer 104, a P-well layer 105, an N+ region 106, and a P+ region 107. The N-type doped buffer layer 104 is located on the upper surface of the N-type doped drift layer 102, and the P-well layer 105 is located on the upper surface of the N-type doped buffer layer 104. A source region is provided on the upper surface of the P-well layer 105. The source region includes two N+ regions 106 and one P+ region 107. The P+ region 107 is disposed between the two N+ regions 106.
[0042] P-type shielding region 103, at least two P-type shielding regions 103 are provided, the P-type shielding regions 103 are symmetrical about the centerline of the device, and are located in a portion of the upper part of the N-type doped drift layer 102, one of the P-type shielding regions 103 is located at the bottom of one fin silicon wall on the side away from the other fin silicon wall.
[0043] Gate oxide 108 is located on the upper surface of the P-type shielding region 103, the side surfaces of the two fin silicon walls, and the upper surface of the N-type doped buffer layer 104 between the two fin silicon walls.
[0044] A polysilicon gate layer 109 is located on the inner surface of the gate oxide layer 108, and the upper surface of the polysilicon gate layer 108 between the two fin silicon walls is flush with the upper surface of the source region.
[0045] The first conductive material is located on the lower surface of the N-type substrate layer 101, forming the drain electrode;
[0046] The second conductive material is located on the upper surface of the polysilicon gate layer 109 between the two finned silicon walls, forming the gate.
[0047] The third conductive material is located on the upper surface of the source region, forming the source electrode.
[0048] This invention features two finned silicon walls, with a source region on each finned silicon wall. The source region includes two N+ regions 106 and one P+ region 107. The P+ region 107 is positioned between the two N+ regions 106, increasing the number of current channels from two to four, thereby improving the device's power. Furthermore, the JFET effect between the P-type buried layers formed by the P-well layer 105 below the source region generates a depletion region, blocking the power lines and effectively protecting the gate structure. It also effectively protects the integrated SBD diode, improving the device's reverse performance.
[0049] The lower surface of the polysilicon gate layer 109 between the two finned silicon walls is closer to the N-type substrate layer 101 than the lower surface of the P-well layer 105; the P-well layer 105 is mainly used for charge coupling to provide voltage protection for the SBD.
[0050] It also includes a fourth conductive material located on the upper surface of the N-type doped drift layer 102 where no P-type shielding region 103 is provided. The P-type shielding region 103 is short-circuited to the source. The P-type shielding region short-circuited to the source can suppress the deterioration of the dynamic characteristics of the device.
[0051] A polysilicon gate layer located on the side of one finned silicon wall away from the other finned silicon wall forms a sidewall. The sidewall is disposed on a portion of the gate oxide layer 108 above the P-type shielding region 103. The farthest end of the sidewall from the N-type substrate layer 101 is flush with the upper surface of the source region. The sidewall is used to protect the surface of the gate oxide layer 108 to reduce damage to the gate oxide layer 108 during the subsequent etching process for forming the source and drain structures.
[0052] Along the direction away from the N-type substrate 101, the cross-section of the polysilicon gate layer forming the sidewall gradually decreases; along the direction away from the N-type substrate 101, the slope of the cross-section of the polysilicon gate layer forming the sidewall gradually decreases. The sidewall is fabricated using the Spacer process to prevent damage to the sidewall surface during the semiconductor structure formation process and extend the service life of the sidewall.
[0053] The doping element of the P-type shielding region 103 is either boron (B) or aluminum (Al). The doping concentration of the P-type shielding region 103 is higher than that of the P-well layer, causing a depletion region to form in the P-type shielding region 103. 。
[0054] In one embodiment, the N-type substrate layer 101 is an N-type doped 4H-SiC substrate, the drift layer has a thickness of 6 μm, and the doping element of the P-well layer is either boron (B) or al. ； The P-type shielding region is doped with boron (B) or al (Al) at a doping concentration of 1e17 and has a thickness of 0.2 μm. ， The conductive material 110 of the source, gate, and drain is copper or aluminum.
[0055] Based on this embodiment, performance testing of the four-channel fin-type vertical silicon carbide device under normal temperature conditions can effectively improve the device's power.
[0056] The fabrication method of the above-mentioned four-channel fin-type vertical silicon carbide device is as follows, see below. Figure 2 Specifically, it includes the following steps:
[0057] S1. An N-type doped drift layer 102 is grown on the upper surface of the N-type substrate layer 101. Subsequently, P+ is implanted into the corresponding region on the upper surface of the N-type doped drift layer 102 using ion implantation technology to form a P-type shielding region 103. See below. Figure 2 (a) in the middle;
[0058] S2. An N-type doped buffer layer 104 is further grown on the upper surface of the N-type doped drift layer 102. A P-well layer 105 is then grown on the upper surface of the N-type doped buffer layer 104. N+ and P+ are implanted into the upper surface of the P-well layer 105 to form a source region layer. ， See Figure 2 In (b), the doping concentration of the N-type doped buffer layer 104 is higher than that of the N-type doped drift layer 102. Specifically, the doping concentration of the N-type doped buffer layer 104 is slightly higher than that of the N-type doped drift layer 102. Due to the depletion effect of the P-type shielding region 103, the channel will become narrower. Therefore, it is necessary to increase the doping concentration of the N-type doped buffer layer 104 to reduce the channel resistance.
[0059] S3. Etching forms two finned silicon walls, specifically etching trench one between the two finned silicon walls and trench two on the outer part of the finned silicon walls, forming two spaced and parallel finned silicon walls; the lower surface of trench one is located between the lower surface of the P-well layer 105 and the upper surface of the N-type doped drift layer 102, and the lower surface of trench two is flush with the upper surface of the N-type doped drift layer 102, see [link to documentation]. Figure 2 (c) in the middle;
[0060] Trenches are formed using traditional etching techniques, such as etching with a hard mask or a soft mask.
[0061] S4. Gate oxide 108 is formed by filling the upper surface of the P-type shielding region 103, the N-type doped drift layer 102, the side surfaces of the two fin silicon walls, and the upper surface of the N-type doped buffer layer 104 between the two fin silicon walls with gate oxide; polysilicon is then filled into the upper surface of the gate oxide layer 108 and the source region, see [reference]. Figure 2 In (d), the polysilicon extends to a certain height on both the gate oxide layer 108 and the upper surface of the source region.
[0062] S5. Etch polysilicon, retaining the polysilicon located on the inner surface of the gate oxide layer 108, to form the polysilicon gate layer 109. See below. Figure 2 (e) in;
[0063] In particular, after etching, the upper surface of the polysilicon gate layer between the two finned silicon walls is flush with the upper surface of the source region;
[0064] A polysilicon gate layer located on the side of one finned silicon wall away from the other finned silicon wall forms a sidewall. The sidewall is disposed on a portion of the gate oxide layer 108 above the P-type shielding region 103. The farthest end of the sidewall from the N-type substrate layer 101 is flush with the upper surface of the source region. Along the direction away from the N-type substrate layer 101, the cross-section of the polysilicon gate layer forming the sidewall gradually decreases, and along the direction away from the N-type substrate layer 101, the slope of the cross-section of the polysilicon gate layer forming the sidewall gradually decreases.
[0065] S6. Deposit conductive material 110: Deposit a first conductive material on the lower surface of the N-type substrate 101 to form the drain; deposit a second conductive material on the upper surface of the polysilicon gate layer between the two finned silicon walls to form the gate; deposit a third conductive material on the upper surface of the source region to form the source. See [link to relevant documentation]. Figure 2 (f) in the middle;
[0066] In addition, step S6 also includes depositing a fourth conductive material on the upper surface of the N-type doped drift layer 102 where no P-type shielding region 103 is provided, wherein the P-type shielding region 103 is short-circuited to the source.
[0067] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A four-channel fin-type vertical silicon carbide device, characterized in that, include: N-type substrate layer; An N-type doped drift layer is located on the upper surface of the N-type substrate layer; Two fin-shaped silicon walls are provided, which are spaced apart and parallel to each other and formed on the upper surface of the drift layer. The two fin-shaped silicon walls are symmetrical about the centerline of the device. The fin-shaped silicon walls include an N-type doped buffer layer, a P-well layer, an N+ region, and a P+ region. The N-type doped buffer layer is located on the upper surface of the N-type doped drift layer, and the P-well layer is located on the upper surface of the N-type doped buffer layer. A source region is provided on the upper surface of the P-well layer, which includes two N+ regions and one P+ region. The P+ region is located between the two N+ regions. P-type shielding regions, at least two of them, are symmetrical about the centerline of the device and are located in a portion of the upper part of the N-type doped drift layer. One of the P-type shielding regions is located at the bottom of one fin silicon wall on the side away from the other fin silicon wall. The gate oxide layer is located on the upper surface of the P-type shielding region, the side surfaces of the two fin silicon walls, and the upper surface of the N-type doped buffer layer between the two fin silicon walls. A polysilicon gate layer is located on the inner surface of the gate oxide layer, and the upper surface of the polysilicon gate layer between the two finned silicon walls is flush with the upper surface of the source region. The first conductive material is located on the lower surface of the N-type substrate layer, forming the drain electrode; The second conductive material is located on the upper surface of the polysilicon gate layer between the two finned silicon walls, forming the gate; The third conductive material is located on the upper surface of the source region, forming the source electrode.
2. The four-channel fin-type vertical silicon carbide device as described in claim 1, characterized in that, The lower surface of the polysilicon gate layer between the two finned silicon walls is closer to the N-type substrate layer than the lower surface of the P-well layer.
3. The four-channel fin-type vertical silicon carbide device as described in claim 1, characterized in that, It also includes a fourth conductive material located on the upper surface of the N-type doped drift layer where no P-type shielding region is provided, wherein the P-type shielding region is short-circuited to the source electrode.
4. A four-channel fin-type vertical silicon carbide device as described in claim 1, characterized in that, A polysilicon gate layer located on the side of one finned silicon wall away from another finned silicon wall forms a sidewall. The sidewall is disposed on a portion of the gate oxide layer above the P-type shielding region. The farthest end of the sidewall from the N-type substrate layer is flush with the upper surface of the source region.
5. A four-channel fin-type vertical silicon carbide device as described in claim 4, characterized in that, Along the direction away from the N-type substrate, the cross-section of the polysilicon gate layer forming the sidewalls gradually decreases.
6. A four-channel fin-type vertical silicon carbide device as described in claim 5, characterized in that, Along the direction away from the N-type substrate, the slope of the cross-section of the polysilicon gate layer forming the sidewalls gradually decreases.
7. A four-channel fin-type vertical silicon carbide device as described in claim 1, characterized in that, The thickness of the drift layer is 6 μm.
8. A four-channel fin-type vertical silicon carbide device as described in claim 1, characterized in that, The doping element of the P-type shielding region is B or Al, and the doping concentration of the P-type shielding region is higher than that of the P-well layer.
9. A four-channel fin-type vertical silicon carbide device as described in claim 8, characterized in that, The doping concentration of the P-type shielding region is 1e17, and the thickness is 0.2um.
10. A method for fabricating a four-channel fin-type vertical silicon carbide device as described in any one of claims 1-9, characterized in that, The method includes the following steps: S1. An N-type doped drift layer is grown on the upper surface of an N-type substrate. Subsequently, P+ is implanted in the corresponding region on the upper surface of the N-type doped drift layer to form a P-type shielding region. S2. Continue to grow an N-type doped buffer layer on the upper surface of the N-type doped drift layer, grow a P-well layer on the upper surface of the N-type doped buffer layer, and implant N+ and P+ on the upper surface of the P-well layer to form a source region. S3. Etching to form two fin-shaped silicon walls, specifically etching trench one between the two fin-shaped silicon walls and trench two on the outer side of the fin-shaped silicon walls to form two spaced and parallel fin-shaped silicon walls. S4. Gate oxide is formed by filling the upper surface of the P-type shielding region, the N-type doped drift layer, the side surfaces of the two fin silicon walls, and the upper surface of the N-type doped buffer layer between the two fin silicon walls with gate oxide; polysilicon is then filled on the upper surfaces of the gate oxide and the source region. S5. Etch polysilicon to retain the polysilicon located on the inner surface of the gate oxide layer, forming a polysilicon gate layer; S6. Deposit conductive materials: deposit a first conductive material on the lower surface of the N-type substrate to form the drain, deposit a second conductive material on the upper surface of the polysilicon gate layer between the two finned silicon walls to form the gate, and deposit a third conductive material on the upper surface of the source region to form the source.