Control system of pulse sequence control triangular wave current mode soft switching buck converter
By controlling the triangular wave current mode of the Buck converter with pulse sequence, and using the PT controller and circuit components to control the negative current, soft switching of the Buck converter is achieved, which solves the problem that traditional Buck converters cannot increase the switching frequency and improves the power density and efficiency of the converter.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XI AN JIAOTONG UNIV
- Filing Date
- 2022-11-17
- Publication Date
- 2026-05-29
Smart Images
Figure CN115912863B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power electronic converter technology and relates to a control system for a Pulse Train (PT) controlled Triangle Current Mode (TCM) soft-switching Buck converter. Background Technology
[0002] In the current era of rapid development in power conversion devices, increasingly higher efficiency and power density have become the main directions for the development of switching converters. With the development of third-generation wide-bandgap semiconductor devices, switching frequencies have gradually reached the MHz level, increasing the power density of converters. In a range of non-isolated DC-DC converter applications, Buck converters are widely used in such switching power supplies due to their simple structure. However, the inability of traditional Buck converters to achieve soft switching limits the improvement of switching frequencies, which in turn limits the improvement of converter power density.
[0003] Current technological advancements have led to several methods for implementing soft switching in Buck converters. The first method employs a synchronous rectified Buck converter, operating in forced continuous current mode (CCM) to reverse the current flow in inductor L1, thereby achieving soft switching of the first switch S1. However, this method typically operates at a fixed switching frequency, making it impossible to control the magnitude of the negative current. A larger negative current results in higher circulating current losses, reducing converter efficiency. The second method involves adding an auxiliary switching network. When the current in inductor L1 drops to a smaller negative value, the auxiliary switching network provides freewheeling for the inductor L1 current, achieving soft switching of the first switch S1 while reducing circulating current losses. However, this method requires additional components, increasing the complexity of the circuit and controller. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a control system for a pulse sequence controlled triangular wave current mode soft-switching Buck converter. This system can control the magnitude of the negative current and has a relatively simple structure.
[0005] To achieve the above objectives, the present invention provides a control system for a pulse sequence controlled triangular wave current mode soft-switching Buck converter. The Buck converter includes a DC input power supply, a first switching transistor, a second switching transistor, an inductor, an output capacitor, and a load. The positive terminal of the DC input power supply is connected to one end of the second switching transistor and one end of the inductor via the first switching transistor. The other end of the inductor is connected to one end of the output capacitor and one end of the load. The other ends of the output capacitor, the load, and the second switching transistor are all connected to the negative terminal of the DC input power supply. The system is characterized by including a PT controller, a voltmeter for detecting and acquiring voltage signals across the load, and an ammeter for acquiring inductor current. The input terminal of the PT controller is connected to the output terminals of the ammeter and the voltmeter, and the output terminal of the PT controller is connected to the control terminals of the first and second switching transistors.
[0006] The PT controller includes an attenuation module, a first comparator, a D flip-flop, a third comparator, a second comparator, a D flip-flop, a first AND gate, a second AND gate, an OR gate, a third AND gate, and an NOT gate;
[0007] The output of the voltmeter is connected to the input of the first comparator via an attenuation module. The low-voltage reference signal input is also connected to the input of the first comparator. The output of the first comparator is connected to the D pin of the D flip-flop. The output of the ammeter is connected to the inputs of the second and third comparators. The output of the second comparator is connected to the CP pin of the flip-flop. The Q pin of the D flip-flop is connected to the input of the first AND gate. The -Q pin of the D flip-flop is connected to the input of the second AND gate. The outputs of the first and second AND gates are connected to the input of the OR gate. The outputs of the third comparator and the OR gate are connected to the input of the third AND gate. The output of the third AND gate is connected to the input of the NOT gate and the control terminal of the first switching transistor. The output of the NOT gate is connected to the control terminal of the second switching transistor.
[0008] The voltage signal across the load is collected by a voltmeter and used as the feedback signal. The signal V is then attenuated by a factor of k. s With reference signal V ref When comparing, when V s Below V ref When the time is right, the output of the first comparator will be high.
[0009] Under normal operating conditions, the current i in the inductor L1 Less than the preset maximum inductor current i L1_peak When the third comparator outputs a high pulse, and the OR gate (C) outputs a high level, the first switch is turned on, the second switch is turned off, and the voltage across the inductor is V. in -V oThe current in the inductor increases.
[0010] The slope of the current rise in the inductor is:
[0011]
[0012] When the high pulse time ends, the inductor current reaches its highest value in the current switching cycle. As the first switch turns off and the second switch turns on, the inductor current begins to decrease.
[0013] The slope of the decrease in inductor current is as follows:
[0014]
[0015] When the inductor current drops to a preset negative value i L1_th When the output of the second comparator is high, a rising edge is generated, triggering the D flip-flop. At this time, the output of the first comparator selects between a high and low pulse, ensuring the output voltage is within V. ref The voltage changes in the vicinity until the output steady-state voltage reaches V. ref The result.
[0016] Preset negative value i L1_th It can achieve soft switching of the first switching transistor, and satisfies the following:
[0017] |i L1_th |t dead >(C oss,S1 +C oss,S2 V in (3)
[0018] Among them, t dead C represents the dead time of the first and second switching transistors. oss,S1 C is the output parasitic capacitance of the first switching transistor. oss,S2 This is the output parasitic capacitance of the second switching transistor.
[0019] When the inductor current is higher than the preset maximum inductor current i L1_peak When the third comparator outputs a low level, the output of the third AND gate is v. g When the signal is low, the first switching transistor is turned off.
[0020] The present invention has the following beneficial effects:
[0021] The control system of the pulse sequence controlled triangular wave current mode soft-switching Buck converter described in this invention achieves rapid input / output voltage regulation capability without adding any extra circuitry during operation, minimizes negative circulating current while maintaining soft switching of all switching transistors, reduces circuit conduction losses, has a fast dynamic response, and exhibits low electromagnetic interference. Attached Figure Description
[0022] Figure 1 This is the circuit schematic diagram of the present invention;
[0023] Figure 2 Key waveform diagrams for pulse sequence control TCM soft-switching Buck converter;
[0024] Figure 3a This is a structural diagram of the original state;
[0025] Figure 3b This is a schematic diagram of mode 1;
[0026] Figure 3c This is a schematic diagram of mode 2;
[0027] Figure 3d This is a schematic diagram of mode 3. Detailed Implementation
[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, not all embodiments, and are not intended to limit the scope of the present invention. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion regarding the concepts disclosed in the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort should fall within the scope of protection of the present invention.
[0029] The accompanying drawings show structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not drawn to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0030] It should be noted that the Buck converter includes a DC input power supply Vin, a first switch S1, a second switch S2, an inductor L1, an output capacitor Co, and a load RL. The positive terminal of the DC input power supply Vin is connected to one end of the second switch S2 and one end of the inductor L1 via the first switch S1. The other end of the inductor L1 is connected to one end of the output capacitor Co and one end of the load RL. The other end of the output capacitor Co, the other end of the load RL, and the other end of the second switch S2 are all connected to the negative terminal of the DC input power supply Vin.
[0031] refer to Figure 1 and Figure 2 The control system of the pulse sequence controlled triangular wave current mode soft-switching Buck converter of the present invention includes an attenuation module K, a first comparator T1, a D flip-flop E, a third comparator T3, a second comparator T2, a D flip-flop E, a first AND gate B1, a second AND gate B2, an OR gate C, a third AND gate B3, an NOT gate A, a voltmeter for acquiring the voltage signal across the load, and an ammeter for acquiring the current of inductor L1.
[0032] The output of the voltmeter is connected to the input of the first comparator T1 via the attenuation module K. The low-voltage reference signal input is also connected to the input of the first comparator T1. The output of the first comparator T1 is connected to the D pin of the D flip-flop E. The output of the ammeter is connected to the inputs of the second comparator T2 and the third comparator T3. The output of the second comparator T2 is connected to the CP pin of the D flip-flop E. The Q pin of the D flip-flop E is connected to the input of the first AND gate B1. The pin is connected to the input of the second AND gate B2. The output of the first AND gate B1 and the output of the second AND gate B2 are connected to the input of the OR gate C. The output of the third comparator T3 and the output of the OR gate C are connected to the input of the third AND gate B3. The output of the third AND gate B3 is connected to the input of the NOT gate A and the control terminal of the first switch S1. The output of the NOT gate A is connected to the control terminal of the second switch S2.
[0033] The specific working process of this invention is as follows:
[0034] The voltage signal across the load RL is collected as the feedback signal, and the signal V is attenuated by a factor of k. s With reference signal V ref When comparing, when V s Below V ref When the first comparator T1 outputs a high level, the D flip-flop E will select a high pulse, and the OR gate C will output a high pulse signal. Under normal operating conditions, the current i of inductor L1... L1 Less than the preset maximum inductor current i L1_peak At this time, the output signal of the third comparator T3 is a high pulse, the first switch S1 is turned on, the second switch S2 is turned off, and the voltage across the inductor L1 is V. in -V o The current in inductor L1 increases, and the slope of the increase is:
[0035]
[0036] When the high pulse period ends, the current in inductor L1 reaches its highest value in the current switching cycle. As the first switch S1 turns off and the second switch S2 turns on, the current in inductor L1 begins to decrease, with the following slope:
[0037]
[0038] When the current in inductor L1 drops to a preset negative value i L1_th When the output of the second comparator T2 is high, a rising edge is generated to trigger the D flip-flop E. At this time, the output of the first comparator T1 selects between a high or low pulse, thus controlling the output voltage at V. ref The voltage changes in the vicinity until the output steady-state voltage reaches V. ref The result.
[0039] Preset negative value i L1_th It only needs to be able to achieve soft switching of the first switching transistor S1, that is, it should satisfy:
[0040] |i L1_th |t dead >(C oss,S1 +C oss,S2 V in (3)
[0041] Among them, t dead C is the dead time of the first switch S1 and the second switch S2. oss,S1 C is the output parasitic capacitance of the first switching transistor S1. oss,S2 This is the output parasitic capacitance of the second switching transistor S2.
[0042] The third comparator T3 is used to provide peak current limiting protection for the current of inductor L1. When the current of inductor L1 exceeds the preset maximum inductance current i... L1_peak When the time is right, the output of the third comparator T3 is low, and the output of the third AND gate B3 is low. g When the signal is low, the first switch S1 is turned off, which protects the converter.
[0043] like Figure 3a , Figure 3b , Figure 3c and Figure 3d As shown, the present invention has three main operating modes. In mode 1, the first switch S1 is turned on and the second switch S2 is turned off. After the first switch S1 is turned on for a long pulse or short pulse time, the current in the inductor L1 reaches the positive peak value within one switching cycle. At this time, the first switch S1 is turned off, and the dead time t... dead Within the dead time t, the current in inductor L1 needs to be forward freewheeling. Because the forward peak value of the current in inductor L1 is relatively large, the second switch S2... deadWhen the internal circuit is turned on, it provides a freewheeling path for the current in inductor L1. At this time, the second switch S2 is turned on, mode 1 ends, and the soft switching of the second switch S2 is realized.
[0044] After entering mode 2, the current in inductor L1 decreases until the current i in inductor L1 reaches a certain level. L1 When the value decreases to zero, mode 2 ends and mode 3 begins;
[0045] In mode 3, the rated current i of inductor L1 L1 Continue decreasing until it decreases to less than i. L1_th When the second switch S2 is turned off, the current i in inductor L1... L1 The current is negative, and the current in inductor L1 can completely draw away the charge on the first switch S1 within the dead time. Therefore, the first switch S1 is turned on, and the current i in the negative inductor L1 is... L1 Provide a freewheeling path. At this time, the first switch S1 is turned on, mode 3 ends, and the soft switching of the first switch S1 is realized.
[0046] In this invention, the first switch S1 and the second switch S2 are wide bandgap semiconductor devices, field-effect transistors, or bipolar transistors.
[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A control system for a pulse sequence controlled triangular wave current mode soft-switching Buck converter, the Buck converter comprising a DC input power supply (Vin), a first switch (S1), a second switch (S2), an inductor (L1), an output capacitor (Co), and a load (RL), wherein the positive terminal of the DC input power supply (Vin) is connected to one end of the second switch (S2) and one end of the inductor (L1) via the first switch (S1), the other end of the inductor (L1) is connected to one end of the output capacitor (Co) and one end of the load (RL), and the other ends of the output capacitor (Co), the load (RL), and the second switch (S2) are all connected to the negative terminal of the DC input power supply (Vin), characterized in that, It includes a PT controller, a voltmeter for detecting and acquiring voltage signals across the load (RL), and an ammeter for acquiring current in an inductor (L1). The input terminal of the PT controller is connected to the output terminal of the ammeter and the output terminal of the voltmeter, and the output terminal of the PT controller is connected to the control terminal of the first switch (S1) and the control terminal of the second switch (S2). The PT controller includes an attenuation module (K), a first comparator (T1), a third comparator (T3), a second comparator (T2), a D flip-flop (E), a first AND gate (B1), a second AND gate (B2), an OR gate (C), a third AND gate (B3), and a NOT gate (A). The output of the voltmeter is connected to the input of the first comparator (T1) via an attenuation module (K). The input of the output voltage reference signal is connected to the input of the first comparator (T1). The output of the first comparator (T1) is connected to the D pin of the D flip-flop (E). The output of the ammeter is connected to the negative inputs of the second comparator (T2) and the third comparator (T3). The positive input of the second comparator (T2) is connected to a preset negative value. The positive input of the third comparator (T3) is connected to a preset maximum inductor current. The output of the second comparator (T2) is connected to the CP pin of the D flip-flop (E). The Q pin of the D flip-flop (E) is connected to the input of the first AND gate (B1). The pin is connected to the input of the second AND gate (B2). The outputs of the first AND gate (B1) and the second AND gate (B2) are connected to the input of the OR gate (C). The output of the third comparator (T3) and the output of the OR gate (C) are connected to the input of the third AND gate (B3). The output of the third AND gate (B3) is connected to the input of the NOT gate (A) and the control terminal of the first switch (S1). The output of the NOT gate (A) is connected to the control terminal of the second switch (S2).
2. The control system for the pulse sequence controlled triangular wave current mode soft-switching Buck converter according to claim 1, characterized in that, The voltage signal across the load (RL) collected by the voltmeter is used as the feedback signal, which is then attenuated by a factor of k. V s With output reference signal V ref When comparing, V s Below V ref When the output of the first comparator (T1) is high, the high pulse at the Q terminal of the D flip-flop (E) is selected. The high pulse with a long conduction signal passes through the OR gate (C) and enters the third AND gate (B3) with the output signal of the third comparator (T3), forming the switch control signal vg to control the first switch. vg then passes through the first NOT gate to form the control signal for the second switch. The first switch (S1) is turned on and the second switch (S2) is turned off.
3. The control system for the pulse sequence controlled triangular wave current mode soft-switching Buck converter according to claim 1, characterized in that, Under normal operating conditions, the current in the inductor (L1) i L1 Less than the preset maximum inductor current i L1_peak At this time, the output signal of the third comparator (T3) is a high pulse. When the first switch (S1) is turned on, the second switch (S2) is turned off, and the voltage across the inductor (L1) is... V in - V o The current in the inductor (L1) increases.
4. The control system for the pulse sequence controlled triangular wave current mode soft-switching Buck converter according to claim 3, characterized in that, The rising slope of the current in inductor L1 is: (1)。 5. The control system for the pulse sequence controlled triangular wave current mode soft-switching Buck converter according to claim 1, characterized in that, When the high pulse time ends, the current in the inductor (L1) reaches its highest value in the current switching cycle. As the first switch (S1) turns off and the second switch (S2) turns on, the current in the inductor (L1) begins to decrease.
6. The control system for the pulse sequence controlled triangular wave current mode soft-switching Buck converter according to claim 5, characterized in that, The slope of the current decrease in inductor (L1) is as follows: (2)。 7. The control system for the pulse sequence controlled triangular wave current mode soft-switching Buck converter according to claim 1, characterized in that, When the current in the inductor (L1) drops to a preset negative value i L1_th When the output of the second comparator (T2) is high, a rising edge is generated to trigger the D flip-flop (E). At this time, the output of the first comparator (T1) selects between a high or low pulse, causing the output voltage to... V ref Nearby changes, to reach a steady-state output voltage of V ref The result.
8. The control system for the pulse sequence controlled triangular wave current mode soft-switching Buck converter according to claim 7, characterized in that, Preset negative value i L1_th A soft switch for the first switching transistor (S1) is achieved, satisfying the following: (3) in, t dead The dead time is for the first switch (S1) and the second switch (S2). C oss,S1 The output parasitic capacitance of the first switching transistor (S1) C oss,S2 This is the output parasitic capacitance of the second switching transistor (S2).
9. The control system for the pulse sequence controlled triangular wave current mode soft-switching Buck converter according to claim 1, characterized in that, When the current in the inductor (L1) is higher than the preset maximum inductor current i L1_peak When the time is right, the output of the third comparator (T3) is low, and the output of the third AND gate (B3) is low. v g When the signal is low, the first switch (S1) is turned off.