Comparator, image sensor readout circuit, and readout method

Abstract

The application discloses a comparator, an image sensor readout circuit and a readout method, the comparator is used for receiving a ramp signal from a ramp generator and receiving an output signal from a dual conversion gain pixel circuit, the comparator comprises a first differential input pair tube and a second differential input pair tube in parallel, the comparator receives the ramp signal and a low conversion gain reset signal or a low conversion gain pixel signal through the first differential input pair tube to output a comparison signal, and the comparator receives the ramp signal and a high conversion gain pixel signal or a high conversion gain reset signal through the second differential input pair tube to output a comparison signal. The application realizes frame rate doubling under the condition that the number of comparators used in the image sensor is unchanged.

Description

Technical Field

[0001] This invention relates to the field of CMOS image sensor technology, specifically to a comparator, an image sensor readout circuit, and a readout method. Background Technology

[0002] High dynamic range is key to improving the imaging quality of image sensors. It can output scene image information over a wider range of light intensity, presenting richer image details, and enabling image sensors to simultaneously represent the highlights and shadows in a single image.

[0003] In existing image capture devices, the pixel array requires multiple consecutive exposures to achieve HDR (High Dynamic Range). There are various design approaches to improve the high dynamic range output of image sensors, such as setting up a dual conversion gain (DCG) unit in the circuit to achieve high dynamic range output images using high conversion gain and low conversion gain readout modes.

[0004] The DCG pixel gain high dynamic range scheme implements LCG and HCG readout. Existing technology uses two independent comparators for image signal readout of each column bitline. One comparator is an LCG comparator, used to quantize the low conversion gain reset signal and the low conversion gain pixel signal to achieve corelated dural sampling (CDS). The other comparator is an HCG comparator, used to quantize the high conversion gain reset signal and the high conversion gain pixel signal to achieve CDS. When the column bitline outputs the high conversion gain signal (HCG) and low conversion gain signal (LCG), a switch selects the corresponding comparator. In the prior art, the output signal sequence of the column bitline is low conversion gain reset signal, high conversion gain reset signal, low conversion gain pixel signal, and low conversion gain pixel signal. After quantizing the low conversion gain reset signal, the LCG comparator disconnects from the column bitline, waiting for the high conversion gain reset signal and the high conversion gain pixel signal to be quantized by the HCG comparator before reconnecting to the column bitline. It is evident that the HCG and LCG comparators are only active when quantizing the corresponding signals, and otherwise remain idle, indicating low utilization rates for the HCG and LCG comparators.

[0005] Therefore, existing CMOS image sensing technology needs improvement. Summary of the Invention

[0006] Based on this, in order to solve the technical problems existing in the prior art, the present invention proposes a pixel gain high dynamic range frame rate enhancement method that can double the frame rate, a comparator, a readout circuit, and an HDR image sensor with gain compensation.

[0007] In a first aspect, this embodiment provides a comparator for receiving a ramp signal from a ramp generator and an output signal from a dual-conversion-gain pixel circuit. The output signal includes a low conversion gain signal (LCG) and a high conversion gain signal (HCG). The low conversion gain signal includes a low conversion gain reset signal and a low conversion gain pixel signal, and the high conversion gain signal includes a high conversion gain reset signal and a high conversion gain pixel signal. The comparator includes a first differential input pair and a second differential input pair connected in parallel. The comparator receives the ramp signal and the low conversion gain reset signal or the low conversion gain pixel signal through the first differential input pair to output a comparison signal. The comparator receives the ramp signal and the high conversion gain pixel signal or the high conversion gain reset signal through the second differential input pair to output a comparison signal.

[0008] Secondly, embodiments of this application provide an image sensor readout circuit, including a counter, a memory, and the aforementioned comparator, wherein the comparator, the counter, and the memory are connected in sequence;

[0009] The comparator is coupled to receive a ramp signal from a ramp generator and an output signal from a dual-conversion-gain pixel circuit to output a comparison signal. The output signal of the pixel circuit includes a low conversion-gain signal (LCG) and a high conversion-gain signal (HCG).

[0010] The counter is coupled to receive the comparison signal output by the comparator and counts according to the comparison signal;

[0011] The memory is coupled to store the counting result of the counter.

[0012] Thirdly, embodiments of this application provide an HDR image sensor with gain compensation, the image sensor including a pixel array, a control circuit, and an image sensor readout circuit as described in the second aspect;

[0013] The control circuit is connected to the pixel array, and the control circuit controls the sequential reading of the low conversion gain reset signal, high conversion gain reset signal, high conversion gain pixel signal and low conversion gain pixel signal output by the pixel array.

[0014] Fourthly, embodiments of this application provide a readout method applied to an image sensor readout circuit, characterized by comprising the following steps:

[0015] The pixel circuit provides pixel output according to the CDS (Correlated Double Sampling) timing sequence. The output signal sequence is low conversion gain reset signal, high conversion gain reset signal, high conversion gain pixel signal, and low conversion gain pixel signal.

[0016] A comparator as described in the first aspect is provided to receive a ramp signal from a ramp generator and an output signal from the pixel circuit, the comparator including a first differential input pair and a second differential input pair;

[0017] The low conversion gain reset signal is first sampled and stored through the first differential input pair transistor;

[0018] The high conversion gain reset signal and the high conversion gain pixel signal are sampled, compared and quantized sequentially through the second differential input pair transistor;

[0019] The low conversion gain reset signal is compared and quantized using the first differential input pair transistors;

[0020] The low conversion gain pixel signal is sampled, compared, and quantized through the first differential input pair transistor.

[0021] The pixel gain high dynamic range frame rate enhancement method, comparator, readout circuit, and image sensor of this application embodiment are configured with two differential input pairs in a comparator circuit. The two differential input pairs operate in the same timing sequence. One differential input pair first samples and stores the low conversion gain reset signal in the LCG signal. After the other differential input pair completes the quantization of the HCG signal, the LCG signal is quantized. The data readout of the LCG signal and HCG signal can be completed in a single comparator circuit, and the frame rate is doubled without changing the number of comparators used in the image sensor. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] in:

[0024] Figure 1 This is a schematic diagram of the main process of the pixel gain high dynamic range frame rate enhancement method in this embodiment;

[0025] Figure 2 This is a system architecture diagram for an HDR image sensor;

[0026] Figure 3 This is a schematic diagram of the HDR image sensor module in this embodiment;

[0027] Figure 4 This is a circuit diagram of the comparator in this embodiment;

[0028] Figure 5 This is the timing diagram of the comparator circuit in this embodiment. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0033] Please refer to Figure 2 The following detailed description of the invention, in conjunction with the accompanying drawings, is provided for reference. The image sensor 100 includes a readout circuit 102 and a control circuit 104 connected to a pixel array 101. The readout circuit 102 and the control circuit 104 are connected to an output interface 105 to control the reading of the pixel array 101.

[0034] Pixel array 101 includes multiple pixel units in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). The pixel signals output by pixel array 101 are output to readout circuit 102 via column lines. In one embodiment, after each pixel unit acquires image data, the image data is read out by readout circuit 102 with a set readout mode. In one embodiment, readout circuit 102 can be configured along readout column lines, such as… Figure 1 As indicated by the horizontal arrow, one line of image data is read out at a time. For example, control circuit 104 generates a shutter signal to control image acquisition. In some applications, this shutter signal can be a global exposure signal that allows all pixels of pixel array 101 to acquire their image data simultaneously through a single acquisition window. In other applications, this shutter signal can be a rolling exposure signal, where each pixel line is read out continuously through the acquisition window.

[0035] Figure 3 This is a system block diagram of the Correlated Double Sampling (CDS) CMOS Image Sensor (CIS) of the present invention. The pixel array of the image sensor contains multiple pixel units arranged in rows and columns. The photosensitive pixel in each pixel unit includes a photodiode and a transfer transistor. The transfer transistor transfers electrons generated by the photodiode PD through the photoelectric effect to the floating diffusion point.

[0036] like Figure 3 As shown, the gain-compensated HDR image sensor of this embodiment includes a pixel array 101, a control circuit 104, and an image sensor readout circuit 50. The image sensor readout circuit 50 includes a comparator 51, a counter 53, and a memory 53.

[0037] The comparator of the image sensor readout circuit is coupled to receive a ramp signal from a ramp generator and an output signal from a dual-conversion-gain pixel circuit, the output signal including a low conversion-gain signal (LCG) and a high conversion-gain signal (HCG); the counter is coupled to receive the output of the comparator; and the memory is coupled to receive the output of the counter.

[0038] The control circuit connects row scan 61 and column scan 62. The column bit lines of the image signal output by column scan 62 are connected to the corresponding comparator; in this embodiment, comparator 51 is used as an example. Each comparator is connected to a ramp generator 71 that generates a ramp signal. The image data read by the image sensor is output to an external processor via the FPGA USB serial port.

[0039] The control circuit 104 provides each comparator, such as comparator 51, to sequentially read the low-conversion-gain reset signal, high-conversion-gain reset signal, high-conversion-gain pixel signal, and low-conversion-gain pixel signal output from the pixel array bitline.

[0040] Please refer to further information. Figure 4 The diagram shows the specific circuit of the comparator in this embodiment.

[0041] The comparator design in this embodiment integrates two differential input pairs. One of these pairs samples and temporarily stores the low conversion gain reset signal. Simultaneously, the comparator 51, in conjunction with the connected counter 52, sequentially quantizes the high conversion gain signal and the low conversion gain signal. This comparator receives a ramp signal from the ramp generator and an output signal from the dual conversion gain pixel circuit. The output signal includes both a low conversion gain signal (LCG) and a high conversion gain signal (HCG).

[0042] In this embodiment, the low conversion gain signal is divided into a low conversion gain reset sample, a low conversion gain reset signal, and a low conversion gain pixel signal. The high conversion gain signal includes a high conversion gain reset signal and a high conversion gain pixel signal.

[0043] The comparator includes a first differential input pair 1 and a second differential input pair 2 connected in parallel. The comparator receives the ramp signal and the low conversion gain reset signal or the low conversion gain pixel signal through the first differential input pair 1 to output a comparison signal. The comparator receives the ramp signal and the high conversion gain pixel signal or the high conversion gain reset signal through the second differential input pair 2 to output a comparison signal.

[0044] The comparator 51 includes a first differential input pair 1 and a second differential input pair 2 for storing the low conversion gain reset signal. In this embodiment, the second differential input pair 2 stores the low conversion gain sampled voltage. Please refer to [further details omitted]. Figure 5 The first differential input pair 1 and the second differential input pair 2 operate within the CDS timing of the same pixel array. During the quantization period, the first differential input pair 1 first samples and stores the low conversion gain reset signal, such as the low conversion gain reset sampling voltage, and then, after the second differential input pair 2 completes the full quantization of the high conversion gain signal, it proceeds to quantize the low conversion gain reset signal and the low conversion gain pixel signal.

[0045] The pixel circuit sequentially outputs a low conversion gain reset signal, a high conversion gain reset signal, a high conversion gain pixel signal, and a low conversion gain pixel signal. Within the same quantization cycle, the comparator first samples and stores the low conversion gain reset signal through the first differential input pair. After comparing and quantizing the high conversion gain reset signal and the high conversion gain pixel signal through the second differential input pair, it then compares and quantizes the low conversion gain reset signal and the low conversion gain pixel signal again through the first differential input pair.

[0046] The first differential input pair 1 includes a first NMOS transistor M1 and a second NMOS transistor M2. The second differential input pair 2 includes a third NMOS transistor M3 and a second fourth NMOS transistor M4.

[0047] The gates of the first NMOS transistor M1 and the second NMOS transistor M2 serve as the first and second input terminals of the first differential input pair 1, respectively. The gates of the third NMOS transistor M3 and the fourth NMOS transistor M4 serve as the first and second input terminals of the second differential input pair 2, respectively. The drains of the first NMOS transistor M1 and the second NMOS transistor M2 serve as the first and second output terminals of the first differential input pair 1, respectively. The drains of the third NMOS transistor M3 and the fourth NMOS transistor M4 serve as the first and second output terminals of the second differential input pair 2, respectively. The sources of the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are grounded through the same tail current source. In other embodiments, transistors M1, M2, M3, and M4 can also be PMOS transistors, and the sources of transistors M1, M2, M3, and M4 are connected to a voltage through the same tail current source.

[0048] like Figure 4As shown, in the circuit structure, the first differential input pair transistor 1 is connected to the load circuit through the first load connection switch load_sw_1, and the second differential input pair transistor 2 is connected to the same load circuit through the second load connection switch load_sw_2. The load circuit then outputs the quantized image signal to the counter 52. The first load connection switch load_sw_1 includes a first load switch K5 and a second load switch K6. The first load switch K5 is connected to output terminal A, and the second load switch K6 is connected to output terminal B. The second load connection switch load_sw_2 includes a third load switch K7 and a fourth load switch K8. The third load switch K7 is connected to output terminal C, and the fourth load switch K8 is connected to output terminal D. In terms of connection, the output terminal A of the first load switch is connected to the output terminal C of the third load switch, and the output terminal B of the second load switch is connected to the output terminal D of the fourth load switch. In other embodiments, the first load connection switch load_sw_1 and the second load connection switch load_sw_2 can also be replaced by two single-pole double-throw switches. That is, the first differential input pair 1 and the first differential input pair 2 can be selectively connected to the load circuit of the comparator through two single-pole double-throw switches.

[0049] The first input of the first differential input pair transistor 1 is connected in series with the first ramp switch ramp_sw_1 and the first capacitor C1, thus selectively coupling to the ramp signal line (ramp). The second input is connected in series with the first bitline switch bitline_sw_1 and the second capacitor C2, thus coupling to the bitline. The third input of the second differential input pair transistor 2 is connected in series with the second ramp switch ramp_sw_2 and the third capacitor C3, thus selectively coupling to the ramp signal line (ramp). The fourth input is connected in series with the second bitline switch bitline_sw_2 and the fourth capacitor C4, thus selectively coupling to the bitline. The first differential input pair transistor 1 and the second differential input pair transistor 2 are connected to the same tail current source S. The selective coupling to the input bitline and ramp voltage by the switches receives the image charge voltage signals on the RAMP and bitline. In another embodiment, the second capacitor C2 and the first bitline switch bitline_sw_1 are also grounded through a capacitor to make the voltage of this node more stable.

[0050] The ramp signal line is coupled to one input terminal of the first differential input pair 1 via a first capacitor C1, and the output signal is coupled from the column bitline to the other input terminal of the first differential input pair 1 via a second capacitor C2. The ramp signal line is coupled to one input terminal of the second differential input pair 2 via a third capacitor C3, and the output signal is coupled from the column bitline to the other input terminal of the second differential input pair 2 via a fourth capacitor C4.

[0051] The first reset switch az_1 is used to reset the first differential input pair transistor 1 before the low conversion gain reset signal is quantized, and the second reset switch az_2 is used to reset the second differential input pair transistor 2 before the high conversion gain reset signal is quantized. In one embodiment, the first reset switch az_1 includes two switches, which are respectively connected to the gate and drain of the first NMOS transistor M1 and the second NMOS transistor M2 of the first differential input pair transistor 1. The second reset switch az_2 is connected to the gate and drain of the three NMOS transistor M3 and the two four NMOS transistor M4 of the second differential input pair transistor 2.

[0052] In this embodiment, the pixel array 101 provides pixel output according to the CDS timing sequence, which is low conversion gain reset sampling, high conversion gain reset signal, high conversion gain pixel signal, low conversion gain reset signal, and low conversion gain pixel signal.

[0053] Each comparator receives a ramp signal from ramp generator 71 and an output signal from column pixel output circuit. The first differential input pair 1 and the second differential input pair 2 operate according to the CDS timing. During the quantization period, the first differential input pair 1 first samples and stores the low conversion gain reset signal, such as the low conversion gain sampling voltage. After the second differential input pair 2 completes the quantization of the high conversion gain reset signal and the high conversion gain pixel signal, it then completes the quantization process of the low conversion gain reset signal and the low conversion gain pixel signal. The comparator then reads out the LCG and HCG, thus doubling the frame rate.

[0054] Please refer to Figure 1 The image shows the pixel gain high dynamic range frame rate enhancement method in this embodiment:

[0055] The pixel gain high dynamic range frame rate enhancement method includes the following steps:

[0056] Step 1: The pixel array provides pixel output according to the CDS timing sequence, which is low conversion gain reset signal, high conversion gain reset signal, high conversion gain pixel signal, and low conversion gain pixel signal.

[0057] Step 2: Provide a comparator to receive a ramp signal from the ramp generator and an output signal from the pixel output circuit. The comparator includes a first differential input pair 1 and a second differential input pair 2 that can store the low conversion gain reset signal.

[0058] Step 3: Sample and store the low conversion gain reset signal through the first differential input pair transistor;

[0059] Step 4: The high conversion gain reset signal and the high conversion gain pixel signal are sampled, compared and quantized sequentially through the second differential input pair transistors;

[0060] Step 5: Compare and quantize the low conversion gain reset signal using the first differential input pair transistors;

[0061] Step 6: The low conversion gain pixel signal is sampled, compared and quantized through the first differential input pair transistor.

[0062] Please refer to this as well. Figure 5 In this embodiment, the CDS timing sequence is as follows: low conversion gain reset sampling (LCG RSTSMPL), high conversion gain reset quantization (HCG RST CNT), high conversion gain image quantization (HCG SIG CNT), low conversion gain reset quantization (LCG RST CNT), and low conversion gain image quantization (LCG SIG CNT).

[0063] It can be seen that the timing of the low conversion gain reset signal (LCG RST) is split into low conversion gain reset sampling timing (LCG RST SMPL) and low conversion gain reset quantization timing (LCG RST CNT).

[0064] During the quantization period, the first differential input pair transistor 1 samples and stores the low conversion gain reset signal, such as the low conversion gain reset sampling voltage, during the low conversion gain reset sampling timing (LCG RSTSMPL).

[0065] like Figure 5As shown, this timing diagram is used to illustrate the operation of comparator 51 and pixel Px. The timing diagram includes control signals that control the operation of array pixel Px and control signals that control the operation of comparator 51 of readout circuit 102. The control signals controlling the pixel include RST, DCG, and TX, and the control signal controlling comparator 51 is the DCG control signal. Although the DCG control signal is depicted as a single control signal, in some embodiments, the DCG control signal includes multiple control signals that can be sequenced to individually control various functional areas of comparator 51 in a desired sequence. For example, the desired sequence can be arranged to maintain current stability in comparator 210. The column lines and RAMP show the changes in voltage on the corresponding inputs of comparator 51, where the waveforms on the column line inputs represent image data received by comparator 51 from pixel Px. The timing diagram shows the sequence of reset voltages and signal voltages used to determine low conversion gain (LCG) mode and high conversion gain (HCG) mode for combining to provide DCG-based image data.

[0066] Figure 5 This is the timing diagram of the image sensor circuit provided in this invention, combined with... Figure 4 The circuit given in the document is implemented as follows:

[0067] At time t0, the row selection signal rowsel is set to high level, the transistor RS is turned on, and the bitline signal is connected to the comparator.

[0068] At time t1, the first load connection switch load_sw_1, the first bitline switch bitline_sw_1, and the first ramp switch ramp_sw_1 of the differential input pair 1 are all turned on. Differential input pair 1 enters the working state.

[0069] At time t2, the first auto-zero switch (az_1) of the differential input pair transistor 1 is turned on, connecting the gates and drains of the left and right input pairs of the differential input pair transistor 1, and determining the upper plate voltage of the input coupling capacitors (first capacitor C1 and second capacitor C2) in the differential input pair transistor 1.

[0070] At time t3, the reset signal rst is set to low level to obtain the bitline image reset signal under the low conversion gain reset timing (LCG RST). The low conversion gain reset signal, which in this embodiment is the low conversion reset sampling voltage, is applied to the lower plate of the differential input pair transistor 1.

[0071] At time t4, the first reset switch az_1 of the differential input pair transistor 1 is turned off, completing the sampling of the upper plate voltage of the coupling capacitor of the differential input pair transistor 1.

[0072] At time t5, the first load connection switch load_sw_1, the first bitline switch bitline_sw_1, and the first ramp switch ramp_sw_1 at the ramp signal vramp terminal of differential input pair 1 are all turned off, completing the sampling of the lower plate voltage of differential input pair 1. At this time, the connection between differential input pair 1 and the load circuit, bitline signal, and vramp signal is disconnected, and the LCGRST signal is sampled and held in differential input pair 1. Differential input pair 1 temporarily exits the working state.

[0073] At time t6, the second load connection switch load_sw_2, the second bitline switch bitline_sw_2, and the second ramp switch ramp_sw_2 of the differential input pair 2 are all turned on. Differential input pair 2 enters the working state.

[0074] At time t7, the second auto-zero switch (az_2) of the differential input pair 2 is turned on, connecting the gate and drain of the two input pairs of the differential input pair 2, thus determining the upper plate voltage of the coupling capacitor in the differential input pair 2.

[0075] At time t8, the conversion gain control signal dcg is set to low level, and the bitline signal of HCG RST is obtained. The voltage of the lower plate of the differential input pair transistor 2 is the HCG RST signal.

[0076] At time t9, the second reset switch az_2 of the differential input pair transistor 2 is turned off, completing the sampling of the upper plate voltage of the coupling capacitor of the differential input pair transistor 2.

[0077] At time t10, the count enable (count_en) is set to high, the ramp signal (vramp) begins to decrease, and the HCG RST signal begins to be quantized through differential input pair 2, and the counter starts counting.

[0078] At time t11, the count enable (count_en) is set to low, the ramp signal (vramp) stops decreasing, and the quantization process of HCG RST is completed.

[0079] From time t12 to t13, the control signal tx is turned on, loading the signal voltage stored on the photodiode PD onto the bitline. After a period of setup, the bitline forms the HCG SIG voltage, which is applied to the lower plate of the coupling capacitor in the differential input pair transistor 2. From time t11 to t12, the control signal tx is set to a high level, the transmission transistor TX is turned on, and the image signal transmission begins. The pixel output pixout is coupled to the comparator Vinn through a capacitor, resulting in an image signal with high conversion gain.

[0080] At time t14, the count enable (count_en) is set to high, the ramp signal (vramp) begins to decrease, and the HCG SIG signal begins to be quantized through differential input pair transistor 2, and the counter starts counting.

[0081] At time t15, the count enable (count_en) is set to low, the ramp signal (vramp) stops decreasing, and the quantization process of HCG SIG is completed.

[0082] At time t16, the second load connection switch load_sw_2, the second bitline switch bitline_sw_2, and the second ramp switch ramp_sw_2 of the ramp signal vramp are all turned off. Differential input pair 2 then exits its operating state.

[0083] At time t17, the first load connection switch load_sw_1 of the differential input pair 1 connected to the load circuit and the first ramp switch ramp_sw_1 of the ramp signal vramp are turned on. Differential input pair 1 re-enters the working state.

[0084] At time t18, the count enable `count_en` is set high, the ramp signal `vramp` begins to decrease, and the LCG RST signal begins to be quantized through differential input pair transistor 1, and the counter starts counting. At this time, the first bit line switch `bitline_sw_1` is not open, and the bitline signal cannot be applied to the lower plate of the coupling capacitor of differential input pair transistor 1. The quantized LCG RST signal is held by the sample previously taken by differential input pair transistor 1.

[0085] At time T19, the count enable (count_en) is set to low, the ramp signal (vramp) stops decreasing, and the quantization process of LCG RST is completed.

[0086] At time t20, the conversion gain control signal dcg is set to high level, and the first bitline switch bitline_sw_1 in differential input pair transistor 1 is turned on. At this time, the bitline signal is connected to the lower plate of the coupling capacitor in differential input pair transistor 1. The bitline signal is switched to LCG mode.

[0087] From time t21 to t22, the control signal tx switch is turned on, loading the signal voltage stored on the photodiode PD onto the bitline. After a period of time, the bitline forms the LCG SIG signal, which is loaded onto the lower plate of the coupling capacitor in the differential input pair transistor 1.

[0088] At time t23, the count enable (count_en) is set to high, the ramp signal (vramp) begins to decrease, and the LCG SIG is quantized through differential input transistor 1. The counter starts counting.

[0089] At time t24, the count enable (count_en) is set to low, the ramp signal (vramp) stops decreasing, and the quantization process of LCG SIG is completed.

[0090] The above description discloses only preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A comparator for receiving a ramp signal from a ramp generator and an output signal from a dual-conversion-gain pixel circuit, the output signal comprising a low-conversion-gain signal LCG and a high-conversion-gain signal HCG, the low-conversion-gain signal comprising a low-conversion-gain reset signal and a low-conversion-gain pixel signal, the high-conversion-gain signal comprising a high-conversion-gain reset signal and a high-conversion-gain pixel signal, characterized in that, The dual-conversion-gain pixel circuit sequentially outputs a low-conversion-gain reset signal, a high-conversion-gain reset signal, a high-conversion-gain pixel signal, and a low-conversion-gain pixel signal; The comparator includes a first differential input pair and a second differential input pair connected in parallel. The comparator receives the ramp signal and the low conversion gain reset signal or the low conversion gain pixel signal through the first differential input pair to output a comparison signal. The comparator receives the ramp signal and the high conversion gain pixel signal or the high conversion gain reset signal through the second differential input pair to output a comparison signal. The timing of the low conversion gain reset signal includes a low conversion gain reset sampling timing and a low conversion gain reset quantization timing. During the quantization period, the first differential input pair completes sampling and storage of the low conversion gain reset signal during the low conversion gain reset sampling timing. The second differential input pair is also configured to store the low conversion gain reset signal; Within the same quantization cycle, the comparator first samples and stores the low conversion gain reset signal through the first differential input pair transistor, and after comparing and quantizing the high conversion gain reset signal and the high conversion gain pixel signal through the second differential input pair transistor, it then compares and quantizes the low conversion gain reset signal and the low conversion gain pixel signal again through the first differential input pair transistor.

2. The comparator according to claim 1, characterized in that, The first differential input pair includes a first transistor and a second transistor, and the second differential input pair includes a third transistor and a fourth transistor. The first terminals of the first transistor and the second transistor serve as the first input terminal and the second input terminal of the first differential input pair, respectively. The first terminals of the third transistor and the fourth transistor serve as the first input terminal and the second input terminal of the second differential input pair, respectively. The second terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor are connected to a first potential through the same tail current source. The third terminals of the first transistor and the second transistor serve as the first output terminal and the second output terminal of the first differential input pair, respectively. The third terminals of the third transistor and the fourth transistor serve as the first output terminal and the second output terminal of the second differential input pair, respectively.

3. The comparator according to claim 2, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are NMOS transistors; the first terminal of the first transistor, the second transistor, the third transistor, and the fourth transistor is the gate of the NMOS transistor; the second terminal of the first transistor, the second transistor, the third transistor, and the fourth transistor is the source of the NMOS transistor, and the first potential is ground; the third terminal of the first transistor, the second transistor, the third transistor, and the fourth transistor is the drain of the NMOS transistor.

4. The comparator according to claim 1, characterized in that, The comparator also includes a first ramp switch, a second ramp switch, a first bit line switch, a second bit line switch, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first input terminal of the first differential input pair transistor is connected to the first ramp switch through the first capacitor to selectively connect to the ramp signal line to receive the ramp signal. The second input terminal of the first differential input pair transistor is connected to the first bit line switch through the second capacitor to selectively connect to the column bit line to receive the low conversion gain reset signal or the low conversion gain pixel signal. The first input terminal of the second differential input pair is connected to the second ramp switch via the third capacitor to selectively connect to the ramp signal line to receive the ramp signal. The second input terminal of the second differential input pair is connected to the second bit line switch via the fourth capacitor to selectively connect to the column bit line to receive the high conversion gain reset signal or the high conversion gain pixel signal.

5. The comparator according to claim 4, characterized in that, The second capacitor is also grounded through a fifth capacitor to the first bit line switch.

6. The comparator according to claim 1, characterized in that, The comparator further includes a first load connection switch and a second load connection switch; The output terminals of the first differential input pair and the second differential input pair are selectively connected to a load circuit via the first load connection switch and the second load connection switch.

7. The comparator according to claim 6, characterized in that, The output terminals of the first differential input pair are selectively connected to the load circuit via the first load connection switch, and the output terminals of the second differential input pair are selectively connected to the load circuit via the second load connection switch.

8. The comparator according to claim 7, characterized in that, The first load connection switch includes a first load switch and a second load switch, and the second load connection switch includes a third load switch and a fourth load switch; the output terminals of the first differential input pair are selectively connected to the load circuit through the first load switch and the second load switch; The output terminals of the second differential input pair are selectively connected to the load circuit through the third load switch and the fourth load switch; the output terminal of the first load switch is connected to the output terminal of the third load switch, and the output terminal of the second load switch is connected to the output terminal of the fourth load switch.

9. The comparator according to claim 1, characterized in that, The comparator also includes a first reset switch and a second reset switch; The first reset switch is used to reset the first differential input pair transistors before the low conversion gain reset signal is quantized, and the second reset switch is used to reset the second differential input pair transistors before the high conversion gain reset signal is quantized.

10. The comparator according to claim 9, characterized in that, The first reset switch is connected to the gate and drain of the first differential input pair transistor, and the second reset switch is connected to the gate and drain of the second differential input pair transistor.

11. An image sensor readout circuit, characterized in that, It includes a counter, a memory, and a comparator as described in any one of claims 1-10, wherein the comparator, the counter, and the memory are connected in sequence. The comparator is coupled to receive a ramp signal from a ramp generator and an output signal from a dual-conversion-gain pixel circuit to output a comparison signal. The output signal of the dual-conversion-gain pixel circuit includes a low conversion gain signal LCG and a high conversion gain signal HCG. The counter is coupled to receive the comparison signal output by the comparator and counts according to the comparison signal; The memory is coupled to store the counting result of the counter.

12. An image sensor, characterized in that, The image sensor includes a pixel array, a control circuit, and an image sensor readout circuit as described in claim 11; The control circuit is connected to the pixel array, and the control circuit controls the pixel array to sequentially output a low conversion gain reset signal, a high conversion gain reset signal, a high conversion gain pixel signal, and a low conversion gain pixel signal.

13. A readout method applied to the image sensor readout circuit as described in claim 11, characterized in that, Includes the following steps: The dual-conversion-gain pixel circuit provides pixel output according to the relevant dual-sampling CDS timing. The output signal sequence is low conversion gain reset signal, high conversion gain reset signal, high conversion gain pixel signal, and low conversion gain pixel signal. A comparator as described in any one of claims 1-10 is provided to receive a ramp signal from a ramp generator and an output signal from the dual-conversion gain pixel circuit, the comparator comprising a first differential input pair and a second differential input pair; The low conversion gain reset signal is first sampled and stored through the first differential input pair transistor; The high conversion gain reset signal and the high conversion gain pixel signal are sampled, compared and quantized sequentially through the second differential input pair transistor; The low conversion gain reset signal is compared and quantized using the first differential input pair transistors; The low conversion gain pixel signal is sampled, compared, and quantized through the first differential input pair transistor.

14. The readout method of the image sensor readout circuit according to claim 13, characterized in that, When sampling and storing the low conversion gain reset signal through the first differential input pair transistor, the method further includes: The comparator is cleared by using the first differential input pair.

15. The readout method of the image sensor readout circuit according to claim 13, characterized in that, Before quantizing the high conversion gain reset signal via the second differential input pair transistor, the method further includes: The comparator is cleared by the second differential input pair.

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