A constant current output control system and method

Abstract

The application provides a constant current output control system and method. When the bus voltage changes, the compensation current proportional to the bus voltage obtained by the voltage-to-current module and the line compensation current also change accordingly. The line compensation voltage module generates a line compensation voltage according to the line compensation current. The sampling voltage collected by the feedback detection circuit is the sum of the line compensation voltage and the feedback voltage. The error amplification signal obtained by comparing the sampling voltage with the reference voltage by the feedback detection circuit reflects the bus voltage change. The pulse width modulator is used to shape the on-time of the transistor according to the compensation current and the error amplification signal, so that the output current does not change with the bus voltage change when the total harmonic distortion compensation is performed, the constant current output is ensured, and the total harmonic distortion value is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, in particular, to a constant current output control system and method. BACKGROUND

[0002] Harmonic distortion refers to the harmonic components that are more than the input signal, and the sum of all additional harmonic levels is called total harmonic distortion (THD). Harmonic distortion is caused by the fact that the system is not completely linear. Total harmonic distortion is related to frequency. Harmonics are superimposed on the actual input signal, and the output signal at the output end is not simply the same as the input signal, but includes harmonic components. The comparison of these excess harmonic components with the actual input signal is expressed as a percentage, which is called total harmonic distortion.

[0003] Total harmonic distortion will distort the voltage waveform of the power grid, thereby affecting the entire power supply system and other power users. Therefore, in some power supply driving fields, the total harmonic distortion is required to be less than a certain range. For example, in the field of LED power supply driving, THD≤15% is required.

[0004] In the prior art, an active power factor correction method is used to compensate THD by using a fixed conduction time to make the average value of the grid input voltage and the input current in a proportional relationship. However, the change of the output current caused by the change of the bus voltage after the grid input voltage is rectified by the rectifier cannot guarantee constant current output. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a constant current output control system and method to solve the problem of output current change caused by the change of bus voltage after the grid input voltage is rectified by the rectifier when compensating THD in the prior art.

[0006] The constant current output control system provided by the embodiments of the present application includes a voltage-to-current module, a line compensation voltage module, a feedback detection circuit, and a pulse width modulator.

[0007] The voltage-to-current module is connected to the bus, and is used to generate a compensation current proportional to the bus voltage and a line compensation current.

[0008] The line compensation voltage module is connected to the voltage-to-current module, and is used to generate a line compensation voltage according to the line compensation current.

[0009] The feedback detection circuit is connected to the pulse width modulator, and is used to obtain a sampling voltage by compensating a feedback voltage according to the line compensation voltage, and compare the sampling voltage with a reference voltage to obtain an error amplification signal.

[0010] A pulse width modulator is configured to output a PWM signal according to the compensation current and the error amplification signal, so as to adjust the on time of the transistor.

[0011] In the technical solution, when the bus voltage changes, the compensation current and the line compensation current obtained by the voltage-to-current module are proportional to the bus voltage, the line compensation voltage is generated by the line compensation voltage module according to the line compensation current, the sampling voltage collected by the feedback detection circuit is the sum of the line compensation voltage and the feedback voltage, the error amplification signal obtained by comparing the sampling voltage with the reference voltage reflects the change of the bus voltage, and the pulse width modulator is used to adjust the on time of the transistor according to the compensation current and the error amplification signal, so that the output current does not change with the change of the bus voltage when the THD compensation is performed, the constant current output is ensured, and the THD value is effectively reduced.

[0012] In some optional embodiments, the control system further comprises a time sampling circuit and a time adjusting circuit.

[0013] The input end of the time sampling circuit is connected to the output end of the pulse width modulator, and the output end of the time adjusting circuit is connected to the input end of the pulse width modulator.

[0014] The time sampling circuit is configured to sample a time signal at the output end of the pulse width modulator.

[0015] The time adjusting circuit is configured to perform calculation and processing on the time signal to obtain a time adjusting signal.

[0016] The pulse width modulator is configured to adjust the on time according to the time adjusting signal.

[0017] In the technical solution, the time sampling circuit is used to collect the time signal, and the time adjusting circuit is used to input the time adjusting signal to the pulse width modulator, so that the THD compensation can be achieved when the system is in any working state, the THD value in the power supply system is effectively reduced, and the stability and efficiency of the power supply system are improved.

[0018] In some optional embodiments, the time sampling circuit comprises a time compensation current source, a time sampling switch and a time sampling capacitor.

[0019] The time compensation current source is connected to one end of the time sampling capacitor, the other end of the time sampling capacitor is grounded, one end of the time sampling switch is connected to the common end of the time compensation current source and the time sampling capacitor, and the other end of the time sampling switch is grounded.

[0020] The time compensation current source is configured to charge the time sampling capacitor, and the time sampling switch is triggered to be turned on when the time sampling moment is reached, so that the time sampling capacitor is discharged and outputs the time signal representing the sampling time.

[0021] In the technical solution, the triangular wave signal formed by charging the time sampling capacitor by the time compensation current source triggers the time sampling switch to conduct when reaching the time sampling moment, and the time sampling capacitor discharges and outputs the time signal representing the sampling time. The time sampling circuit has simple structure, stable and reliable sampling work, and ensures the accuracy of the sampling time signal.

[0022] In some optional embodiments, the time adjustment circuit comprises an operation module, and the time sampling circuit is configured to sample the first time signal and the second time signal at the output end of the pulse width modulator, wherein the first time signal represents the on time, and the second time signal represents the sum of the on time and the off time.

[0023] The operation module is configured to divide the second time signal by the first time signal to obtain the duty cycle, and divide the value of (1-dutycycle)×dutycycle by the first time signal to obtain the time adjustment signal.

[0024] In the technical solution, the operation module in the time adjustment circuit can efficiently process and calculate the time signal, and ensure the accuracy of the time adjustment signal.

[0025] In some optional embodiments, the operation module comprises a divider, and the divider is configured to divide the second time signal by the first time signal, so as to obtain the time adjustment signal inversely proportional to the duty cycle.

[0026] In the technical solution, the divider in the time adjustment circuit can efficiently process and calculate the time signal, and ensure the accuracy of the time adjustment signal.

[0027] In some optional embodiments, the pulse width modulator comprises a voltage compensation capacitor and an operational amplifier.

[0028] The output end of the time adjustment circuit is connected to the first end of the voltage compensation capacitor, the first end of the voltage compensation capacitor is also connected to the voltage-to-current module, the second end of the voltage compensation capacitor is grounded, and the current Isd output by the time adjustment circuit is superimposed with the compensation current output by the voltage-to-current module to charge the voltage compensation capacitor.

[0029] The first input end of the operational amplifier is connected to the first end of the voltage compensation capacitor, and the second input end of the operational amplifier is connected to the output end of the feedback detection circuit. The operational amplifier is configured to compare the error amplification signal with the capacitor voltage of the voltage compensation capacitor to obtain the PWM signal.

[0030] In the technical solution, the compensation current output by the voltage-to-current module is superimposed on the current Isd output by the time adjustment circuit, and the voltage compensation capacitor is charged. Since the compensation current is proportional to the bus voltage, the greater the bus voltage, the greater the current for charging the voltage compensation capacitor, the faster the charging speed of the voltage compensation capacitor, and the greater the slope of the triangular wave. The voltage of the voltage compensation capacitor reaches the voltage value of the error amplification signal faster, which makes the on time smaller, thereby shaping the on time, reducing the value at the peak of the on time waveform, and reducing the THD value.

[0031] In some optional embodiments, the detection circuit is further included.

[0032] The detection circuit includes a first voltage dividing resistor and a second voltage dividing resistor.

[0033] The first end of the first voltage dividing resistor is connected to the bus, the second end of the first voltage dividing resistor is connected to the first end of the second voltage dividing resistor, and the second end of the second voltage dividing resistor is grounded.

[0034] The second end of the first voltage dividing resistor is also connected to the input end of the voltage-to-current module.

[0035] In some optional embodiments, the voltage-to-current module includes a line compensation error amplifier, a line compensation resistor, a line compensation transistor, and a current mirror circuit.

[0036] The second end of the first voltage dividing resistor R1 is connected to the non-inverting input end of the line compensation error amplifier, the gate of the line compensation transistor is connected to the output end of the line compensation error amplifier, the source of the line compensation transistor is connected to the inverting input end of the line compensation error amplifier and grounded through the line compensation resistor, and the drain of the line compensation transistor is connected to the current mirror circuit.

[0037] In the technical solution, the first voltage dividing resistor and the second voltage dividing resistor form a voltage dividing resistor, so that the voltage-to-current module can generate a voltage dividing current proportional to the bus voltage, thereby obtaining a line compensation current and a compensation current proportional to the bus voltage.

[0038] In some optional embodiments, a rectifier, an LED load, a driver, a sampling resistor, and a transistor are further included.

[0039] The input of the rectifier is connected to an alternating current power source, the output of the rectifier is connected to the LED load, the LED load is connected to the drain of the transistor, and the source of the transistor is grounded through the sampling resistor.

[0040] The feedback detection circuit is connected to the common end of the source of the transistor and the sampling resistor through the line compensation voltage module, the output end of the driver is connected to the gate of the transistor, and the input end of the driver is connected to the output end of the pulse width modulator.

[0041] In some alternative embodiments, the line compensation voltage module comprises a line compensation internal resistance;

[0042] A first end of the line compensation internal resistance is connected to a common end of the sampling resistance, a second end of the line compensation internal resistance is connected to an input end of the feedback detection circuit, and the second end of the line compensation internal resistance is also connected to a second output end of the voltage-to-current module, which is used to output a line compensation current.

[0043] In some alternative embodiments, the feedback detection circuit comprises a sample-and-hold circuit and a compensation error amplifier;

[0044] An input end of the sample-and-hold circuit is connected to a second end of the line compensation voltage module, a first end of the line compensation voltage module is connected to a common end of the sampling resistance, and the sample-and-hold circuit is used to collect a sampling voltage obtained by compensating a feedback voltage with the line compensation voltage;

[0045] An output end of the sample-and-hold circuit is connected to one input end of the compensation error amplifier, another input end of the compensation error amplifier is used to input a reference reference voltage, and the compensation error amplifier is used to compare the sampling voltage with the reference reference voltage to obtain an error amplification signal.

[0046] The control method for constant current output provided by the embodiments of the present application comprises:

[0047] generating a compensation current and a line compensation current proportional to a bus voltage;

[0048] generating a line compensation voltage according to the line compensation current and a line compensation internal resistance;

[0049] obtaining a sampling voltage by compensating a feedback voltage with the line compensation voltage, and comparing the sampling voltage with a reference reference voltage to obtain an error amplification signal;

[0050] adjusting the on-time according to the compensation current and the error amplification signal.

[0051] In the above technical solution, when the bus voltage changes, the compensation current and the line compensation current proportional to the bus voltage also change accordingly, the line compensation voltage is generated according to the line compensation current and the line compensation internal resistance, the sampling voltage is the sum of the line compensation voltage and the feedback voltage, the error amplification signal obtained by comparing the sampling voltage with the reference reference voltage reflects the change of the bus voltage, and the on-time of the transistor is shaped by using the pulse width modulator according to the compensation current and the error amplification signal, so that the output current does not change with the change of the bus voltage when the THD compensation is performed, the constant current output is ensured, and the THD value is effectively reduced.

[0052] In some alternative embodiments, the control method further comprises:

[0053] a first time signal and a second time signal of an output end of the sampling pulse width modulator, wherein the first time signal represents the on time, and the second time signal represents the sum of the on time and the off time;

[0054] divide the second time signal by the first time signal to obtain a duty cycle, and divide the value of (1-dutycycle)×dutycycle by the first time signal to obtain a time adjustment signal;

[0055] adjust the on time according to the time adjustment signal.

[0056] In the technical solution, for BUCK (voltage reduction circuit) application, I IN (input current) is the average value of the transistor M0 current, Ipk is the inductance peak current (equal to the peak current of the transistor M0), Ton is the on time, and Ts is the sum of the on time and the off time. Assuming that the duty cycle D=VOUT / VIN=Ton / Ts, then: I IN =0.5×Ipk×Ton / Ts=0.5L×Vin×D(1-D). Therefore, because the embodiment of the application realizes Therefore, the input current is proportional to the input voltage, and the THD compensation is effectively performed, and the THD value is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments of the application. It should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0058] Figure 1 a structure schematic diagram of a constant current output control system provided by the embodiment of the application;

[0059] Figure 2 a circuit connection structure schematic diagram of a voltage-to-current module and a detection circuit;

[0060] Figure 3 a structure schematic diagram of a constant current output control system provided by another embodiment of the application;

[0061] Figure 4 a circuit connection structure diagram of a time sampling circuit provided by the embodiment of the application;

[0062] Figure 5 a control system structure schematic diagram of a load circuit with an isolated transformer provided by the embodiment of the application;

[0063] Figure 6 This is a schematic diagram of the circuit connection structure of the pulse width modulator and the feedback detection circuit;

[0064] Figure 7 A flowchart illustrating the steps of a constant current output control method provided in this application embodiment.

[0065] Icons: 10-Rectifier, 20-Detection circuit, 30-Feedback detection circuit, 31-Sample-hold circuit, 40-Pulse width modulator, 50-Voltage to current conversion module, 51-Current mirror circuit, 60-Line voltage compensation module, 70-Time adjustment circuit, 80-Time sampling circuit, 90-LED load. Detailed Implementation

[0066] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0067] One or more embodiments of this application provide a constant current output control system and method that compensates and adjusts the conduction time to avoid changes in output current caused by changes in the bus voltage after the grid input voltage is rectified by the rectifier.

[0068] Please refer to Figure 1 , Figure 1 A schematic diagram of a constant current output control system provided in this application embodiment includes a voltage-to-current module 50, a line-compensated voltage module 60, a feedback detection circuit 30, and a pulse width modulator 40;

[0069] The voltage-to-current module 50 is connected to the busbar and is used to generate a compensation current I and a line compensation current I that are proportional to the busbar voltage Vm. 线补 The line compensation voltage module 60 is connected to the voltage-to-current module 50, and is used to calculate the line compensation current I. 线补 A line compensation voltage is generated; the feedback detection circuit 30 is connected to the pulse width modulator 40, which is used to obtain the sampling voltage based on the line compensation voltage to compensate the feedback voltage, and compare the sampling voltage with the reference voltage to obtain the error amplification signal Vcomp; the pulse width modulator 40 is used to output a PWM signal based on the compensation current and the error amplification signal to adjust the conduction time of the transistor M0.

[0070] In this embodiment, when the bus voltage Vm changes, the voltage-to-current module 50 acquires a compensation current I and a line compensation current I that are proportional to the bus voltage Vm. 线补 The line compensation voltage module also changes accordingly based on the line compensation current I. 线补The line compensation voltage is generated, and the sampling voltage collected by the feedback detection circuit is the sum of the line compensation voltage and the feedback voltage. The error amplification signal Vcomp obtained by comparing the sampling voltage with the reference voltage by the feedback detection circuit reflects the bus voltage variation. The pulse width modulator is used to shape the on-time of the transistor M0 according to the compensation current and the error amplification signal Vcomp, so that the output current does not change with the bus voltage variation when the THD compensation is performed, thereby ensuring the constant current output and effectively reducing the THD value.

[0071] As Figure 1 The constant current output control system further comprises a rectifier 10, an LED load 90, a driver U0 and a transistor M0.

[0072] The input of the rectifier 10 is connected with an alternating current power supply, the output of the rectifier 10 is connected with the LED load 90, the LED load 90 is connected with the drain of the transistor M0, the source of the transistor M0 is connected with the ground through a sampling resistor RCS; the feedback detection circuit is connected with the common terminal of the source of the transistor M0 and the sampling resistor RCS through a line compensation voltage module, the output of the driver U0 is connected with the gate of the transistor M0, and the input of the driver U0 is connected with the output of a pulse width modulator.

[0073] In some optional embodiments, a detection circuit is further included; please refer to Figure 2 , Figure 2 FIG. 4 is a circuit connection structure diagram of the voltage-to-current module 50 and the detection circuit 20.

[0074] The detection circuit comprises a first voltage dividing resistor R1 and a second voltage dividing resistor R2; the first end of the first voltage dividing resistor R1 is connected with a bus, the second end of the first voltage dividing resistor R1 is connected with the first end of the second voltage dividing resistor R2, and the second end of the second voltage dividing resistor R2 is connected with the ground; and the second end of the first voltage dividing resistor R1 is further connected with the input of the voltage-to-current module 50. That is, the detection circuit 20 adopts the voltage dividing resistor formed by the first voltage dividing resistor R1 and the second voltage dividing resistor R2, so that the voltage-to-current module 50 can generate a voltage dividing voltage proportional to the bus voltage, thereby obtaining the compensation current I and the line compensation current I 线补 .

[0075] The voltage-to-current module 50 comprises a line compensation error amplifier U3, a line compensation resistor R3, a line compensation transistor M1 and a current mirror circuit 51.

[0076] The second end of the first voltage division resistor R1 is connected to the non-inverting input terminal of the line compensation error amplifier U3, the gate of the line compensation transistor M1 is connected to the output terminal of the line compensation error amplifier U3, the source of the line compensation transistor M1 is connected to the inverting input terminal of the line compensation error amplifier U3 and grounded through the line compensation resistor R3, and the drain of the line compensation transistor M1 is connected to the current mirror circuit 51, so that the current Ie4 of the drain of the line compensation transistor M1 is Vm×R2 / (R3×(R1+R2)). 线补 The compensation current I is proportional to Vm, that is, the line compensation current I 线补 The compensation current I is proportional to Vm, that is, the line compensation current I 线补 The compensation current I is proportional to Vm, that is, the line compensation current I

[0077] Please refer to Figure 3 , Figure 3 The structure schematic diagram of a constant current output control system provided by another embodiment of the present application can be seen, and the system further includes a time sampling circuit 80 and a time adjusting circuit 70.

[0078] The output terminal of the pulse width modulator 40 is connected to the input terminal of the time sampling circuit 80, and the output terminal of the time adjusting circuit 70 is connected to the input terminal of the pulse width modulator 40; the time sampling circuit 80 is used for sampling a time signal at the output terminal of the pulse width modulator 40; the time adjusting circuit 70 is used for calculating and processing the time signal to obtain a time adjusting signal; and the pulse width modulator 40 is further used for adjusting the on time according to the time adjusting signal.

[0079] In the embodiment of the present application, the time sampling circuit 80 collects the time signal, and the time adjusting circuit 70 inputs the time adjusting signal to the pulse width modulator 40, so that the THD compensation can be realized when the system is in any working state, the THD value in the power system is effectively reduced, and the stability and efficiency of the power system are improved.

[0080] Please refer to Figure 4 , Figure 4 The circuit connection structure diagram of the time sampling circuit provided by the embodiment of the present application is shown in the figure, and the time sampling circuit 80 includes a time compensation current source Ichg, a time sampling switch SN and a time sampling capacitor C2.

[0081] The time compensation current source Ichg is connected with one end of the time sampling capacitor C2, the other end of the time sampling capacitor C2 is grounded, one end of the time sampling switch SN is connected with the common end of the time compensation current source Ichg and the time sampling capacitor C2, and the other end of the time sampling switch SN is grounded; the time compensation current source Ichg is used for charging the time sampling capacitor C2, and when the time sampling moment is reached, the time sampling switch SN is triggered to be turned on, at this time, the time sampling capacitor C2 is discharged and outputs the time signal representing the sampling time.

[0082] In the embodiment, the triangular wave signal formed by charging the time sampling capacitor C2 by the time compensation current source Ichg, when the time sampling moment is reached, the time sampling switch SN is triggered to be turned on, at this time, the time sampling capacitor C2 is discharged and outputs the time signal representing the sampling time. The structure of the time sampling circuit 80 is simple, the sampling work is stable and reliable, and the accuracy of the sampling time signal is ensured.

[0083] The time adjustment circuit 70 includes one or more dividers and one or more multipliers, the time signal Vcap at the output end of the pulse width modulator 40 is sampled, the voltage-to-current conversion and the calculation processing of the multiplier or the divider are performed on the time signal Vcap to obtain the time adjustment signal (that is, the current Isd), the time adjustment signal (the current Isd) is input into the pulse width modulator 40, and then the on-time Ton is adjusted.

[0084] For BUCK (voltage reduction circuit) application, when the input voltage V IN is less than the output voltage VOUT, the dead zone is entered, the rectifier bridge is reversed biased, and the input current I IN has no effect on the bridge circuit, and the current I IN will have a platform period, and the current at this time is the current for charging and discharging the cbb capacitor in front of the bridge. Therefore, the THD compensation can only be compensated in the interval of |VIN|>VOUT. Therefore, better THD compensation is required for buck application to achieve THD≤15%.

[0085] In the embodiment, some multipliers and dividers in the time adjustment circuit 70 form an operation module, the operation module is used for dividing the second time signal (the sum of the on-time and the off-time) by the first time signal (the on-time) to obtain the duty cycle, and dividing the value of (1-dutycycle)×dutycycle by the first time signal to obtain the time adjustment signal.

[0086] In the above technical solution, for BUCK (voltage reduction circuit) application, when the input voltage V INThe input current is the average value of the transistor M0 current, Ipk is the inductance peak current (equal to the transistor M0 peak current), Ton is the on time of the transistor M0, and Ts is the period. Assuming that the duty cycle D = VOUT / VIN = Ton / Ts, then:

[0087] I IN = 0.5 x Ipk x Ton / Ts = 0.5L x Vin x D (1-D)

[0088] Therefore, because the embodiments of the present application realize the input current is proportional to the input voltage, the THD compensation is effectively performed, and the THD value is reduced.

[0089] It should be noted that in addition to the above constant current output control system for the BUCK circuit, one or more embodiments of the present application are also applicable to load circuits with an isolated transformer, such as Figure 5 .

[0090] In some optional embodiments, the operation module includes a divider for dividing the second time signal by the first time signal, thereby obtaining a time adjustment signal inversely proportional to the duty cycle.

[0091] In the embodiments of the present application, the time signal Vcap is sampled at the output end of the pulse width modulator, the time signal Vcap is calculated and processed to obtain the time adjustment signal (current Isd), and the time adjustment signal (current Isd) is input into the pulse width modulator, thereby realizing the adjustment of the on time Ton. Preferably, sampling the time signal Vcap at the output end of the pulse width modulator includes sampling the first time signal and the second time signal at the output end of the pulse width modulator; the operation and processing of the time signal Vcap to obtain the time adjustment signal (current Isd) includes dividing the second time signal by the first time signal, thereby obtaining a time adjustment signal (current Isd) inversely proportional to the duty cycle D, so that the adjusted on time Ton is inversely proportional to the duty cycle D. Wherein, the first time signal represents the on time Ton, and the second time signal represents the adjustment time Ts, that is, the sum of the on time Ton and the off time Toff; in addition, the on time Ton and the off time Toff can also be sampled at the output end of the pulse width modulator, the on time Ton is taken as the first time signal, and the sum of the on time Ton and the off time Toff is taken as the second time signal. The THD compensation method of the present application processes the time sampling signal, thereby realizing a simple and reliable on time adjustment method, and the adjustment process is accurate and stable, which realizes that the system THD value can be effectively reduced regardless of the working state of the system, thereby improving the system working efficiency.

[0092] Please refer toFigure 6 Figure 6 Fig. 2 is a schematic diagram of a circuit connection structure of the pulse width modulator 40 and the feedback detection circuit 30.

[0093] The pulse width modulator 40 comprises a voltage compensation capacitor C1 and an operational amplifier U1. The output end of the time adjustment circuit 70 is connected to the first end of the voltage compensation capacitor C1. The first end of the voltage compensation capacitor C1 is also connected to the voltage-to-current module 50. The second end of the voltage compensation capacitor C1 is grounded. The current Isd output by the time adjustment circuit 70 is superimposed with the compensation current output by the voltage-to-current module 50 to charge the voltage compensation capacitor C1. The first input end of the operational amplifier U1 is connected to the first end of the voltage compensation capacitor C1. The second input end of the operational amplifier U1 is connected to the output end of the feedback detection circuit 30. The operational amplifier U1 is used to compare the error amplification signal Vcomp with the capacitor voltage of the voltage compensation capacitor C1 to obtain the PWM signal.

[0094] In the embodiment, the compensation current I output by the voltage-to-current module 50 is superimposed on the current Isd output by the time adjustment circuit to charge the voltage compensation capacitor C1. Since the compensation current I is proportional to the bus voltage, the greater the bus voltage Vm, the greater the current for charging the voltage compensation capacitor, the faster the charging speed of the voltage compensation capacitor C1, and the greater the slope of the triangular wave formed by the charging, which makes the capacitor voltage of the voltage compensation capacitor C1 reach the voltage value of the error amplification signal Vcomp faster, so that the on time Ton is smaller, thereby shaping the on time Ton, reducing the value at the peak of the on time waveform, and reducing the THD value.

[0095] In some optional embodiments, the feedback detection circuit 30 comprises a sample-and-hold circuit 31 and a compensation error amplifier U4.

[0096] The input end of the sample-and-hold circuit 31 is connected to the second end of the line compensation voltage module. The first end of the line compensation voltage module is connected to the common end of the sampling resistor RCS. The sample-and-hold circuit 31 is used to collect the sampling voltage obtained by the line compensation voltage compensation feedback voltage. The output end of the sample-and-hold circuit 31 is connected to one input end of the compensation error amplifier U4. The other input end of the compensation error amplifier U4 is used to input the reference reference voltage. The compensation error amplifier U4 is used to compare the sampling voltage with the reference reference voltage to obtain the error amplification signal.

[0097] In some optional embodiments, as shown in Figure 6 the line compensation voltage module 60 in the embodiment comprises a line compensation internal resistance R4.

[0098] ​The first end of the line compensation internal resistance R4 is connected to the common end of the sampling resistance RCS, the second end of the line compensation internal resistance R4 is connected to the input end of the feedback detection circuit 30, and the second end of the line compensation internal resistance R4 is also connected to the second output end of the voltage-to-current module 50, which is used to output the line compensation current. In the embodiment, the line compensation voltage is generated according to the line compensation current I 线补 and the line compensation internal resistance R4.

[0099] Please refer to Figure 7 , Figure 7 A constant current output control method provided by the embodiment of the application is shown in a flow chart, which includes:

[0100] Step 1, generating a compensation current proportional to the bus voltage and a line compensation current;

[0101] Step 2, generating a line compensation voltage according to the line compensation current and the line compensation internal resistance;

[0102] Step 3, compensating the feedback voltage according to the line compensation voltage to obtain a sampling voltage, and comparing the sampling voltage with a reference voltage to obtain an error amplification signal;

[0103] Step 4, adjusting the on-time according to the compensation current and the error amplification signal.

[0104] In the embodiment of the application, when the bus voltage changes, the compensation current proportional to the bus voltage and the line compensation current also change accordingly, the line compensation voltage is generated according to the line compensation current and the line compensation internal resistance, the sampling voltage is the sum of the line compensation voltage and the feedback voltage, the error amplification signal obtained by comparing the sampling voltage with the reference voltage reflects the change of the bus voltage, and the on-time of the transistor is shaped according to the compensation current and the error amplification signal by using the pulse width modulator, so that the output current does not change with the change of the bus voltage when the THD compensation is performed, the constant current output is ensured, and the THD value is effectively reduced.

[0105] In some optional real-time modes, the constant current output control method further includes:

[0106] sampling the first time signal and the second time signal at the output end of the pulse width modulator, wherein the first time signal represents the on-time, and the second time signal represents the sum of the on-time and the off-time; dividing the second time signal by the first time signal to obtain the duty cycle, and then dividing the value of (1-dutycycle)×dutycycle by the first time signal to obtain a time adjustment signal; and adjusting the on-time according to the time adjustment signal.

[0107] In the embodiment of the application, for the BUCK (buck circuit) application, I IN(Iin) is the average value of the transistor M0 current, Ipk is the inductor peak current (equal to the peak current of the transistor M0), Ton is the on time, and Ts is the sum of the on time and the off time. Assuming that the duty cycle D = VOUT / VIN = Ton / Ts, then: I IN = 0.5 x Ipk x Ton / Ts = 0.5L x Vin x D (1-D). Therefore, because the embodiment of the application realizes Therefore, the input current is proportional to the input voltage, the THD compensation is effectively performed, and the THD value is reduced.

[0108] In the embodiments provided by the present application, it should be understood that the disclosed apparatus and method can be implemented in other manners. The embodiments described above are merely schematic, and should not be construed as limiting the present application. For example, the division of the units is only a logical function division, and there can be another division manner in actual implementation; for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, and electrical, mechanical or other forms of coupling or communication connections can be supported.

[0109] In addition, the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. In actual implementation, some or all of the units can be selected according to the actual needs to achieve the purposes of the embodiments.

[0110] In addition, each functional module in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0111] In this document, the terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations.

[0112] The above only describes the embodiments of the present application, and is not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A constant current output control system, characterized by, The voltage-to-current module (50), the line compensation voltage module (60), the feedback detection circuit (30) and the pulse width modulator (40) are connected in series. The voltage-to-current module (50) is connected with the bus, and is used for generating a compensation current and a line compensation current proportional to the bus voltage. The line compensation voltage module (60) is connected with the voltage-to-current module (50), and is used for generating a line compensation voltage according to the line compensation current. The feedback detection circuit (30) is connected with the pulse width modulator (40), and is used for adding the line compensation voltage and a feedback voltage to obtain a sampling voltage, and comparing the sampling voltage with a reference voltage to obtain an error amplification signal. The pulse width modulator (40) is used for outputting a PWM signal according to the compensation current and the error amplification signal, so as to adjust the on time of the transistor (M0). The source of the transistor (M0) is connected with the ground through a sampling resistor (RCS), and the voltage of the sampling resistor (RCS) is the feedback voltage.

2. The system of claim 1, wherein, The time sampling circuit (80) and the time adjustment circuit (70) are further included. The input end of the time sampling circuit (80) is connected with the output end of the pulse width modulator (40), and the output end of the time adjustment circuit (70) is connected with the input end of the pulse width modulator (40). The time sampling circuit (80) is used for sampling a time signal at the output end of the pulse width modulator (40). The time adjustment circuit (70) is used for calculating and processing the time signal to obtain a time adjustment signal. The pulse width modulator (40) is used for adjusting the on time according to the time adjustment signal.

3. The system of claim 2, wherein, The time adjustment circuit (70) includes an operation module, and the time sampling circuit (80) is used for sampling a first time signal and a second time signal at the output end of the pulse width modulator (40) respectively, wherein the first time signal represents the on time, and the second time signal represents the sum of the on time and the off time. The operation module is used for dividing the second time signal by the first time signal to obtain a duty cycle, and dividing the value of (1-dutycycle)×dutycycle by the first time signal to obtain the time adjustment signal.

4. The system of claim 2, wherein, The pulse width modulator (40) includes a voltage compensation capacitor (C1) and an operational amplifier (U1). The output end of the time adjustment circuit (70) is connected with the first end of the voltage compensation capacitor (C1), the first end of the voltage compensation capacitor (C1) is also connected with the voltage-to-current module (50), the second end of the voltage compensation capacitor (C1) is connected with the ground, and the current Isd output by the time adjustment circuit (70) charges the voltage compensation capacitor (C1) after being superimposed with the compensation current output by the voltage-to-current module (50). The first input end of the operational amplifier (U1) is connected with the first end of the voltage compensation capacitor (C1), the second input end of the operational amplifier (U1) is connected with the output end of the feedback detection circuit (30), and the operational amplifier (U1) is used for comparing the error amplification signal with the capacitor voltage of the voltage compensation capacitor (C1) to obtain the PWM signal.

5. The system of claim 1, wherein, Further comprising a detection circuit (20); The detection circuit (20) comprises a first voltage dividing resistor (R1) and a second voltage dividing resistor (R2); the first end of the first voltage dividing resistor (R1) is connected with a bus, the second end of the first voltage dividing resistor (R1) is connected with the first end of the second voltage dividing resistor (R2), and the second end of the second voltage dividing resistor (R2) is grounded; and the second end of the first voltage dividing resistor (R1) is further connected with the input end of the voltage-to-current module (50).

6. The system of claim 5, wherein, The voltage-to-current module (50) comprises a line compensation error amplifier (U3), a line compensation resistor (R3), a line compensation transistor (M1) and a current mirror circuit (51); The second end of the first voltage dividing resistor (R1) is connected with the non-inverting input end of the line compensation error amplifier (U3), the gate of the line compensation transistor (M1) is connected with the output end of the line compensation error amplifier (U3), the source of the line compensation transistor (M1) is connected with the inverting input end of the line compensation error amplifier (U3) and grounded through the line compensation resistor (R3), and the drain of the line compensation transistor (M1) is connected with the current mirror circuit (51).

7. The system of claim 1, wherein, Further comprising a rectifier (10), an LED load (90), a driver (U0), a sampling resistor (RCS) and a transistor (M0); The input of the rectifier (10) is connected with an alternating current power supply, the output of the rectifier (10) is connected with the LED load (90), the LED load (90) is connected with the drain of the transistor (M0), and the source of the transistor (M0) is grounded through the sampling resistor (RCS); The feedback detection circuit (30) is connected with the common end of the source of the transistor (M0) and the sampling resistor (RCS) through the line compensation voltage module (60), the output end of the driver (U0) is connected with the gate of the transistor (M0), and the input end of the driver (U0) is connected with the output end of the pulse width modulator (40).

8. The system of claim 7, wherein, The line compensation voltage module (60) comprises a line compensation internal resistor (R4); The first end of the line compensation internal resistor (R4) is connected with the common end of the sampling resistor (RCS), the second end of the line compensation internal resistor (R4) is connected with the input end of the feedback detection circuit (30), and the second end of the line compensation internal resistor (R4) is further connected with the second output end of the voltage-to-current module (50), and the second output end of the voltage-to-current module (50) is used for outputting a line compensation current.

9. The system of claim 7, wherein, The feedback detection circuit (30) comprises a sample-and-hold circuit (31) and a compensation error amplifier (U4); An input end of the sample-and-hold circuit (31) is connected with a second end of the line compensation voltage module (60), a first end of the line compensation voltage module (60) is connected with a common end of the sampling resistor (RCS), and the sample-and-hold circuit (31) is used for collecting a line compensation voltage and compensating a feedback voltage by using the line compensation voltage to obtain a sampling voltage; An output end of the sample-and-hold circuit (31) is connected with one input end of the compensation error amplifier (U4), another input end of the compensation error amplifier (U4) is used for inputting a reference reference voltage, and the compensation error amplifier (U4) is used for comparing the sampling voltage with the reference reference voltage to obtain an error amplification signal.

10. A control method of constant current output, characterized by, Comprise: generating a compensation current and a line compensation current proportional to a bus voltage; generating a line compensation voltage according to the line compensation current and a line compensation internal resistance; adding the line compensation voltage and a feedback voltage to obtain a sampling voltage, and comparing the sampling voltage with a reference reference voltage to obtain an error amplification signal; adjusting a turn-on time of a transistor according to the compensation current and the error amplification signal; wherein a source of the transistor is connected with ground through a sampling resistor, and a voltage of the sampling resistor is the feedback voltage.

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