Methods, systems, storage media, and electronic devices for very large scale integration
By acquiring the netlist timing information of VLSI, scanning the worst timing path, and calculating the downsize prediction score of the cell node, the area and power consumption of VLSI are optimized, solving the problem of excessive area and power consumption in the prior art and achieving effective area reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI LIXIN SOFTWARE TECH CO LTD
- Filing Date
- 2023-01-09
- Publication Date
- 2026-04-28
AI Technical Summary
Existing physical design optimization methods result in excessive area and power consumption in very large-scale integrated circuits, making it difficult to reduce the total cell area while ensuring timing consistency.
By acquiring the netlist timing information of VLSI, scanning the worst timing path, calculating the downsize prediction score of the cell nodes, and performing descending sorting and downsize processing on the cell nodes, the area and power consumption are optimized.
While ensuring that the timing remains unchanged, the total area of the integrated circuit is reduced, resulting in a 5%-15% decrease in area density and solving the problem of excessive power consumption per unit area.
Smart Images
Figure CN116432582B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of automation technology for physical design of very large-scale integrated circuits, and specifically relates to a method, system, storage medium and electronic device for very large-scale integrated circuits. Background Technology
[0002] With the development of modern very large-scale integrated circuits, the number of units contained on a chip is increasing. For example, as the performance of mobile phone chips improves, the number of transistors they contain is also increasing. The most advanced mobile phone chips have reached the level of tens of billions of transistors. The challenges that follow are the total area of chip units and power consumption.
[0003] Currently, commonly used physical design optimization methods often focus more on timing optimization, which is usually accomplished by inserting buffers or replacing larger cells. This obviously leads to an excessively large total cell area, resulting in problems such as excessive area power consumption. Excessive power consumption is unacceptable in modern chip requirements.
[0004] While ensuring that the timing remains unchanged, how to reduce the area of each cell as much as possible to reduce the total cell area and thus reduce power consumption is also one of the urgent problems to be solved.
[0005] The background description is provided for the purpose of understanding the relevant technologies in this field and is not intended as an admission of prior art. Summary of the Invention
[0006] This invention overcomes one of the shortcomings of the prior art and provides a method, system, storage medium and electronic device for very large-scale integrated circuits. It can reduce the total area of the integrated circuit by reducing the area of each unit node, thereby solving the problem of excessive area power consumption caused by ensuring that the timing remains unchanged during the physical optimization design process.
[0007] According to one aspect of this disclosure, a method for very large-scale integrated circuits is proposed, the method comprising:
[0008] Step S1: Obtain the timing information TNS of the entire netlist of the VLSI;
[0009] Step S2: Obtain the worst-case timing path in the netlist that passes through each end node;
[0010] Step S3: Scan all unit nodes in the worst-case timing path and obtain the number of worst-case timing paths for each unit node, path_count;
[0011] Step S4: For each unit node on the worst timing path, obtain the slack value of the worst output pin of the unit node;
[0012] Step S5: Perform downsize estimation processing on the unit node, and obtain the downsize estimation score of the unit node based on the worst timing path count of the unit node and the slack value of the worst output pin.
[0013] Step S6: Sort the downsize estimated scores of the unit nodes in descending order, select the first N unit nodes for downsize processing, and calculate the timing information new_TNS of the entire netlist of the VLSI.
[0014] Step S7: Optimize the area power consumption in the physical optimization of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI.
[0015] In one possible implementation, obtaining the worst-case timing path through each end node in the netlist includes:
[0016] For each end node in the netlist, scan the slack value of all timing paths passing through the end node, and select the timing path corresponding to the smallest slack value as the worst timing path of the end node.
[0017] In one possible implementation, the timing information TNS of the entire netlist of the VLSI is the sum of the negative timing path slack values.
[0018] In one possible implementation, obtaining the worst-case time-series path count for each unit node includes:
[0019] For each unit node, scan all worst-case timing paths from the initial node to the end node that pass through the unit node, and use the total number of all worst-case timing paths that pass through the unit node as the number of worst-case timing paths for the unit node, path_count.
[0020] In one possible implementation, the cell node undergoes downsize estimation processing. Based on the worst-case timing path count (path_count) and the slack value of the worst-case output pin, a downsize estimation score for the cell node is obtained, including:
[0021] The unit node is downsized to estimate its area, and the area change value delta_area of the unit node is obtained.
[0022] Based on the product change value delta_area of the selected unit node, the number of worst timing paths path_count, and the slack value of the worst output pin, calculate the downsize estimated score of the worst timing path corresponding to the slack value of the worst output pin of the unit node.
[0023] The worst-case time-series path downsize prediction score is calculated as: slack * delta_area / path_count.
[0024] In one possible implementation, optimizing the area power consumption in the physical optimization of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI includes:
[0025] When the timing information new_TNS is greater than or equal to the timing information TNS, repeat steps S1-S6 until the timing information new_TNS is less than the timing information TNS, and restore the unit node that has undergone downsizing to the previous state of the current state.
[0026] In one possible implementation, the slack value of the worst-case output pin of the cell node is the smallest slack value among all worst-case timing paths passing through the cell node.
[0027] According to another aspect of this disclosure, an area and power consumption optimization system for very large-scale integrated circuits is proposed, the system comprising:
[0028] The first acquisition module is used to acquire the timing information (TNS) of the entire netlist of the VLSI;
[0029] The second acquisition module is used to acquire the worst-case timing path through each end node in the netlist;
[0030] The third acquisition module is used to scan all unit nodes in the worst time series path and obtain the number of worst time series paths for each unit node, path_count.
[0031] The fourth acquisition module is used to acquire the slack value of the worst output pin of each unit node on the worst timing path.
[0032] The estimation module is used to perform downsize estimation processing on the unit node, and obtain the downsize estimation score of the unit node based on the worst timing path count of the unit node and the slack value of the worst output pin.
[0033] The calculation module is used to sort the downsize estimated scores of the unit nodes in descending order, select the first N unit nodes for downsize processing, and then calculate the timing information new_TNS of the entire netlist of the VLSI.
[0034] The optimization acquisition module is used to optimize the area power consumption in the physical optimization of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI.
[0035] According to another aspect of this disclosure, a storage medium is provided on which a computer program is stored, which, when executed by a processor, implements the method described above.
[0036] According to another aspect of this disclosure, an electronic device is proposed, comprising: a processor and a memory storing a computer program, the processor being configured to implement the method described above when the computer program is executed.
[0037] The method disclosed herein for very large-scale integrated circuits includes the following steps: Step S1: Obtaining the timing information (TNS) of the entire netlist of the very large-scale integrated circuit; Step S2: Obtaining the worst timing path passing through each end node in the netlist; Step S3: Scanning all cell nodes in the worst timing path and obtaining the number of worst timing paths for each cell node (path_count); Step S4: For each cell node on the worst timing path, obtaining the slack value of the worst output pin of the cell node; Step S5: Performing downsize estimation on the cell node and calculating the slack value based on the number of worst timing paths (path_count) and the worst output pin (Output). Step S6: Obtain the downsize estimated score of the cell node from the slack value of the pin; Step S7: Sort the downsize estimated scores of the cell nodes in descending order, select the first N cell nodes for downsize processing, and calculate the timing information new_TNS of the entire netlist of the VLSI; Step S8: Optimize the area power consumption in the physical optimization of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI. This can reduce the total area of the integrated circuit by reducing the area of each cell node, thereby solving the problem of excessive area power consumption in the physical optimization design process while ensuring that the timing remains unchanged.
[0038] Other optional features and technical effects of the embodiments of the present invention are partly described below and partly apparent from reading this document. Attached Figure Description
[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The elements shown are not limited to the scale shown in the drawings, and the same or similar reference numerals in the drawings denote the same or similar elements, wherein:
[0040] Figure 1 A flowchart of a method for very large-scale integrated circuits according to an embodiment of the present disclosure is shown;
[0041] Figure 2 A timing path diagram of a very large-scale integrated circuit according to an embodiment of the present disclosure is shown;
[0042] Figure 3 A system principle block diagram for a very large-scale integrated circuit according to an embodiment of the present disclosure is shown;
[0043] Figure 4 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation
[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.
[0045] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.
[0046] Furthermore, the steps illustrated in the flowcharts of the accompanying drawings can be executed in a computer, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in a different order than that presented here.
[0047] Figure 1 A flowchart of a method for very large-scale integrated circuits according to an embodiment of the present disclosure is shown; this method can be used in the field of physical optimization design automation for very large-scale integrated circuits, such as area and power consumption optimization. The method is specifically as follows... Figure 1 As shown, it includes:
[0048] Step S1: Obtain the timing information TNS of the entire netlist of the VLSI. The timing information TNS (total negative slack) is the sum of the negative timing path slack values for the entire netlist of the VLSI, representing a performance range of the chip. The timing path slack value is the time margin, which is the result of subtracting the arrival time from the required time of the timing path of the electronic circuit. The slack value can be positive, 0, or negative. A positive slack value indicates that the timing path delay meets the requirements; a negative slack value indicates that the power consumption of the electronic components in the integrated circuit is too high, causing the time delay to not meet the requirements. Using the sum of all negative timing path slack values in the netlist of the integrated circuit as the timing information TNS of the timing netlist can better optimize the cell area problem corresponding to electronic components with excessive power consumption in physical optimization design.
[0049] Step S2: Obtain the worst-case timing path in the netlist that passes through each end node.
[0050] In one example, this step may specifically include: for each end node in the netlist, scanning the slack values of all timing paths passing through the end node, and selecting the timing path corresponding to the smallest slack value as the worst timing path of the end node. For example, for the end node endpoint, if there are 3 timing paths passing through the end node endpoint, and the slack values of these 3 timing paths are 10, 6, and 3 respectively, then the timing path with a slack value of 3 is selected as the worst timing path of the end node endpoint; similarly, if the slack values of the 3 timing paths passing through the end node endpoint are -10, -2, and 3 respectively, then the timing path with a slack value of -10 is selected as the worst timing path of the end node endpoint.
[0051] Step S3: Scan all unit nodes in the worst timing path and obtain the number of worst timing paths for each unit node, path_count.
[0052] Figure 2 A timing path diagram of a very large-scale integrated circuit according to an embodiment of the present disclosure is shown.
[0053] Step S2 can be used to obtain the worst timing path of each end node. Based on the timing path of the scanned VLSI, all cell nodes passed through each worst timing path can be obtained, namely the startpoint of the worst timing path, all intermediate cell nodes between the startpoint and the endpoint, and the endpoint.
[0054] For any intermediate unit node, the number of all worst-case timing paths passing through that unit node can be counted, and the total number of all worst-case timing paths passing through that unit node is taken as the number of worst-case timing paths for that unit node, path_count. For example, as... Figure 2 As shown, endpoint1 and endpoint2 each have a worst timing path with a slack value less than 0. Both of these worst timing paths pass through the cell node, so the number of worst timing paths of the cell node, path_count, is 2.
[0055] Step S4: For each cell node on the worst-case timing path, obtain the slack value of the worst-case output pin of that cell node. The slack value of the worst-case output pin of the cell node is the smallest slack value among all worst-case timing paths passing through that cell node. For example, a cell node has two output pins, output pins 1 and 2. There are two worst-case timing paths through output pin 1 with slack values of 1 and -3 respectively, and three worst-case timing paths through output pin 2 with slack values of 2, -1, and -5 respectively. Therefore, output pin 2 with a slack value of -5 is selected as the worst-case output pin of that cell node, and -5 is the slack value of the worst-case output pin of that cell node.
[0056] Step S5: Perform downsize estimation on the unit node, and obtain the downsize estimation score of the unit node based on the worst timing path count and the slack value of the worst output pin.
[0057] In one example, this step may include: performing downsize estimation on the unit node to obtain the area change value delta_area of the unit node;
[0058] Based on the product change value delta_area of the selected unit node, the number of worst timing paths path_count, and the slack value of the worst output pin, calculate the downsize estimated score of the worst timing path corresponding to the slack value of the worst output pin of the unit node. The estimated score is calculated as slack * delta_area / path_count.
[0059] Downsizing can be used for designing or manufacturing in smaller sizes, or reducing the external dimensions of devices. Downsizing a cell node can be estimated by replacing it with a smaller, functionally identical cell node, such as BUFX4 -> BUFX3. The area change value (delta_area) of the cell node can be calculated using the attribute values of different cells. For example, if the area attribute value of BUFX4 is 10 and that of BUFX3 is 7, then the area change value (delta_area) of the cell node is 3. The downsizing score is then calculated using the downsizing estimation score calculation method.
[0060] Step S6: Sort the estimated downsize scores of the cell nodes in descending order, select the first N cell nodes for downsizing, and calculate the timing information new_TNS of the entire netlist of the VLSI. Here, N is a positive integer, which can be 50, 30, etc., set according to the requirements of the VLSI, and is not limited here. The timing information new_TNS of the netlist is the sum of the negative slack values of all the latest timing paths of the VLSI after downsizing the cell nodes.
[0061] Step S7: Optimize the area power consumption in the physical optimization of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI.
[0062] In one example, this step may include: when the timing information new_TNS is greater than or equal to the timing information TNS, repeating the above steps S1-S6 until the timing information new_TNS is less than the timing information TNS, and restoring the cell node that has undergone downsizing to the previous state of the current state.
[0063] Specifically, the values of timing information new_TNS and timing information TNS are compared. When the timing information new_TNS is greater than or equal to the timing information TNS, it indicates that the area power consumption performance of the VLSI's cell node after downsizing has been optimized. Steps S1-S6 can be repeated to continue optimizing the area power consumption performance of the VLSI until the timing information new_TNS is less than the timing information TNS. Since the timing information new_TNS is less than the timing information TNS, it indicates that the area power consumption performance of the VLSI's cell node after downsizing has not been optimized and is greater than the area power consumption before the cell node was downsized, the VLSI's cell node is restored to its previous state before the downsizing, ending the VLSI's area power consumption performance optimization process.
[0064] The method disclosed herein for very large-scale integrated circuits includes the following steps: Step S1: Obtaining the timing information (TNS) of the entire netlist of the very large-scale integrated circuit; Step S2: Obtaining the worst timing path passing through each end node in the netlist; Step S3: Scanning all cell nodes in the worst timing path and obtaining the number of worst timing paths for each cell node (path_count); Step S4: For each cell node on the worst timing path, obtaining the slack value of the worst output pin of the cell node; Step S5: Performing downsize estimation on the cell node and calculating the slack value based on the number of worst timing paths (path_count) and the worst output pin (Output). Step S6: Obtain the downsize estimated score of the cell node from the slack value of the pin; Step S7: Sort the downsize estimated scores of the cell nodes in descending order, select the top N cell nodes for downsize processing, and calculate the timing information new_TNS of the entire netlist of the VLSI; Step S8: Optimize the area power consumption in the physical optimization of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI. This can reduce the total area of the integrated circuit by reducing the area of each cell node, thereby solving the problem of excessive area power consumption in the physical optimization design process while ensuring that the timing remains unchanged. It can also achieve a 5%-15% reduction in area density while maintaining the timing.
[0065] The above describes an embodiment of the apparatus described in this application, which can be used to execute the method embodiments described in this application. For details not disclosed in the apparatus embodiments described in this application, please refer to the method embodiments described in this application.
[0066] Figure 3 A system principle block diagram for a very large-scale integrated circuit according to an embodiment of the present disclosure is shown. Figure 3 As shown, the system may include:
[0067] The first acquisition module 301 is used to acquire the timing information TNS of the entire netlist of the VLSI;
[0068] The second acquisition module 302 is used to acquire the worst-case timing path through each end node in the netlist;
[0069] The third acquisition module 303 is used to scan all unit nodes in the worst timing path and acquire the number of worst timing paths for each unit node, path_count.
[0070] The fourth acquisition module 304 is used to acquire the slack value of the worst output pin of each unit node on the worst timing path.
[0071] The estimation module 305 is used to perform downsize estimation processing on the unit node, and obtain the downsize estimation score of the unit node based on the worst timing path count of the unit node and the slack value of the worst output pin.
[0072] The calculation module 306 is used to sort the downsize estimated scores of the unit nodes in descending order, select the first N unit nodes for downsize processing, and then calculate the timing information new_TNS of the entire netlist of the VLSI.
[0073] The optimization module 307 is used to optimize the area power consumption in the physical optimization of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI.
[0074] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0075] In some embodiments, the area power consumption optimization system apparatus for VLSI may incorporate the area power consumption optimization method features of any embodiment of VLSI, and vice versa, which will not be elaborated here.
[0076] In an embodiment of the present invention, an electronic device is provided, comprising: a processor and a memory storing a computer program, wherein the processor is configured to perform a method for area and power consumption optimization of a very large-scale integrated circuit according to any embodiment of the present invention when running the computer program.
[0077] Figure 4 The diagram illustrates a method for implementing embodiments of the present invention or an electronic device 1000 for implementing embodiments of the present invention. In some embodiments, it may include more or fewer electronic devices than illustrated. In some embodiments, it may be implemented using a single or multiple electronic devices. In some embodiments, it may be implemented using cloud-based or distributed electronic devices.
[0078] Figure 4 This is a schematic diagram of the structure of the electronic device 10 provided in an embodiment of this application. Figure 4As shown, the electronic device 1000 includes a processor 1001, which can perform various appropriate operations and processes based on programs and / or data stored in read-only memory (ROM) 1002 or programs and / or data loaded from storage portion 1008 into random access memory (RAM) 1003. The processor 1001 may be a multi-core processor or may contain multiple processors. In some embodiments, the processor 1001 may include a general-purpose main processor and one or more special coprocessors, such as a central processing unit (CPU), graphics processing unit (GPU), neural network processor (NPU), digital signal processor (DSP), etc. Various programs and data required for the operation of the electronic device 1000 are also stored in RAM 1003. The processor 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. An input / output (I / O) interface 1005 is also connected to bus 1004.
[0079] The processor and memory described above are used together to execute programs stored in the memory. When the program is executed by a computer, it can implement the methods, steps, or functions described in the above embodiments.
[0080] The following components are connected to I / O interface 1005: an input section 1006 including a keyboard, mouse, touchscreen, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to I / O interface 1005 as needed. A removable medium 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 1010 as needed so that computer programs read from it can be installed into storage section 1008 as needed. Figure 4 The diagram only shows a portion of the components and does not imply that the computer system 1000 only includes... Figure 4 The components shown.
[0081] The systems, devices, modules, or units described in the above embodiments can be implemented by a computer or its associated components. The computer may be, for example, a mobile terminal, smartphone, personal computer, laptop computer, in-vehicle human-machine interface device, personal digital assistant, media player, navigation device, game console, tablet computer, wearable device, smart TV, Internet of Things system, smart home, industrial computer, server, or a combination thereof.
[0082] Although not shown, in this embodiment of the invention, a storage medium is provided storing a computer program configured to execute, when run, any file-difference-based compilation method of this embodiment of the invention.
[0083] Storage media in embodiments of the present invention include articles that are permanent and non-permanent, removable and non-removable, capable of storing information by any method or technology. Examples of storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.
[0084] The methods, programs, systems, apparatuses, etc., in embodiments of the present invention can be executed or implemented in one or more networked computers, or practiced in a distributed computing environment. In the embodiments of this specification, in these distributed computing environments, tasks can be performed by remote processing devices connected via a communication network.
[0085] Those skilled in the art will understand that the embodiments described in this specification can be provided as methods, systems, or computer program products. Therefore, those skilled in the art will realize that the functional modules / units or controllers and related method steps described in the above embodiments can be implemented in software, hardware, or a combination of both.
[0086] Unless explicitly stated otherwise, the actions or steps of the methods and procedures described in the embodiments of the present invention do not necessarily have to be performed in a specific order and can still achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0087] This document describes several embodiments of the present invention; however, for the sake of brevity, the descriptions of the embodiments are not exhaustive, and identical or similar features or parts between the embodiments may be omitted. In this document, "one embodiment," "some embodiments," "example," "specific example," or "some examples" refers to embodiments applicable to at least one, but not all, of the present invention. The above terms do not necessarily refer to the same embodiments or examples. Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of the different embodiments or examples.
[0088] The exemplary systems and methods of the present invention have been specifically shown and described with reference to the above embodiments, which are merely examples of the best mode for implementing the systems and methods. Those skilled in the art will understand that various changes can be made to the embodiments of the systems and methods described herein without departing from the spirit and scope of the invention as defined in the appended claims when implementing the systems and / or methods.
Claims
1. A method for very large-scale integrated circuits, characterized in that, The method includes: Step S1: Obtain the timing information TNS of the entire netlist of the VLSI; Step S2: Obtain the worst-case timing path in the netlist that passes through each end node; Step S3: Scan all unit nodes in the worst-case timing path and obtain the number of worst-case timing paths for each unit node, path_count; Step S4: For each unit node on the worst timing path, obtain the slack value of the worst output pin of the unit node; Step S5: Perform downsize estimation processing on the unit node, and obtain the downsize estimation score of the unit node based on the worst timing path count of the unit node and the slack value of the worst output pin. Step S6: Sort the downsize estimated scores of the unit nodes in descending order, select the first N unit nodes for downsize processing, and calculate the timing information new_TNS of the entire netlist of the VLSI. Step S7: Optimize the area power consumption of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI.
2. The method according to claim 1, characterized in that, Obtaining the worst-case time-series path through each end node in the netlist includes: For each end node in the netlist, scan the slack value of all timing paths passing through the end node, and select the timing path corresponding to the smallest slack value as the worst timing path of the end node.
3. The method according to claim 2, characterized in that, The timing information TNS of the entire netlist of the VLSI is the sum of negative timing path slack values.
4. The method according to claim 1, characterized in that, The step of obtaining the worst-case time path count (path_count) for each unit node includes: For each unit node, scan all worst-case timing paths from the initial node to the end node that pass through the unit node, and use the total number of all worst-case timing paths that pass through the unit node as the number of worst-case timing paths for the unit node, path_count.
5. The method according to claim 1, characterized in that, The unit node is subjected to downsize prediction processing. Based on the worst-case timing path count (path_count) and the slack value of the worst-case output pin, the downsize prediction score of the unit node is obtained, including: The unit node is downsized to estimate its area, and the area change value delta_area of the unit node is obtained. Based on the area change value delta_area of the selected unit node, the number of worst timing paths path_count, and the slack value of the worst output pin, calculate the downsize estimated score of the worst timing path corresponding to the slack value of the worst output pin of the unit node, where the estimated score = slack * delta_area / path_count.
6. The method according to claim 5, characterized in that, The step of optimizing the area and power consumption of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI includes: When the timing information new_TNS is greater than or equal to the timing information TNS, repeat steps S1-S6 until the timing information new_TNS is less than the timing information TNS, and restore the unit node that has undergone downsizing to the previous state of the current state.
7. The method according to claim 1, characterized in that, The slack value of the worst output pin of the cell node is the smallest slack value among all worst timing paths passing through the cell node.
8. An area and power consumption optimization system for very large-scale integrated circuits, characterized in that, The system includes: The first acquisition module is used to acquire the timing information (TNS) of the entire netlist of the VLSI; The second acquisition module is used to acquire the worst-case timing path through each end node in the netlist; The third acquisition module is used to scan all unit nodes in the worst time series path and obtain the number of worst time series paths for each unit node, path_count. The fourth acquisition module is used to acquire the slack value of the worst output pin of each unit node on the worst timing path. The estimation module is used to perform downsize estimation processing on the unit node, and obtain the downsize estimation score of the unit node based on the worst timing path count of the unit node and the slack value of the worst output pin. The calculation module is used to sort the downsize estimated scores of the unit nodes in descending order, select the first N unit nodes for downsize processing, and then calculate the timing information new_TNS of the entire netlist of the VLSI. The optimization acquisition module is used to optimize the area and power consumption of the VLSI based on the timing information new_TNS and timing information TNS of the entire netlist of the VLSI.
9. A storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the method as described in any one of claims 1-7.
10. An electronic device, characterized in that, include: A processor and a memory storing a computer program, the processor being configured to implement the method of any one of claims 1-7 when the computer program is executed.
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