Source driver buffer output circuit, chip and electronic device

Abstract

The present disclosure proposes a source driver buffer output circuit, chip, and device. The source driver buffer output circuit includes an output control unit, a first transistor, and a second transistor. By using the output control unit to control the conduction state of the first transistor and the second transistor, it is possible to control whether a driving voltage is output to a display panel. In addition, the driving current output to the display panel does not need to pass through a switching component, thereby reducing the equivalent resistance of the driving current passing through the branch and reducing energy loss.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to a source driver buffer output circuit, a chip, and an electronic device. Background Art

[0002] With the advancement of electronic technology, display panels are becoming larger and larger, with higher resolutions. Consequently, the number of pixels that source drivers must drive within the same frame time is also increasing. Furthermore, as the display panel size increases, the panel capacitance that the source driver circuit must drive also increases, which in turn increases the temperature of the source driver chip. Summary of the Invention

[0003] This disclosure proposes a source driver buffer output circuit, chip, and electronic device. The specific solution is as follows:

[0004] In one aspect, an embodiment of the present disclosure provides a source driver buffer output circuit, comprising:

[0005] an output control unit, a first transistor, and a second transistor;

[0006] Wherein, the first input end of the output control unit is used to be connected to the first output end of the source driver buffer, the second input end of the output control unit is connected to the second output end of the source driver buffer, the third input end of the output control unit is connected to the third output end of the source driver buffer, the first output end of the output control unit is connected to the driving end of the first transistor, the second output end of the output control unit is connected to the driving end of the second transistor, and the third output end of the output control unit is connected to the connection end of the first transistor and the second transistor. The output control unit is used to control whether the first transistor and the second transistor output a driving current to the display panel;

[0007] The first connection terminal of the first transistor is connected to a first power supply, and the second connection terminal of the first transistor is connected to the first connection terminal of the second transistor;

[0008] The second connection terminal of the second transistor is connected to a second power supply.

[0009] In one aspect, an embodiment of the present disclosure provides a source driver buffer output chip, comprising: the source driver buffer output circuit described above.

[0010] In one aspect, an embodiment of the present disclosure provides a source driver buffer circuit, comprising n buffers and m source driver buffer output circuits as described above, wherein n and m are integers greater than or equal to 1.

[0011] In one aspect, an embodiment of the present disclosure provides a source driver buffer chip, comprising the source driver buffer circuit as described above.

[0012] In one aspect, an embodiment of the present disclosure provides a source driver circuit, including the source driver buffer circuit described above.

[0013] Another embodiment of the present disclosure provides an electronic device including the above-mentioned source driving circuit and a display panel.

[0014] The source driver buffer output circuit, chip and device of the embodiment of the present disclosure include an output control unit, a first transistor and a second transistor in the source driver buffer output circuit. By using the output control unit to control the conduction state of the first transistor and the second transistor, it is possible to control whether the driving voltage is output to the display panel, and the driving current output to the display panel does not need to pass through the switching component, thereby reducing the equivalent resistance of the driving current passing through the branch and reducing energy loss.

[0015] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present disclosure will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of a circuit structure between a source driving circuit and a display panel in a related art;

[0018] Figure 2 A schematic diagram of a circuit structure between a source driver buffer circuit and driven pixels in a related art;

[0019] Figure 3 A schematic structural diagram of a source driver buffer output circuit provided by an embodiment of the present disclosure;

[0020] Figure 4 A schematic structural diagram of another source driver buffer output circuit provided by an embodiment of the present disclosure;

[0021] Figure 5 Schematic diagram of another circuit structure between a source driver buffer circuit and driven pixels in the related art;

[0022] Figure 6 A schematic structural diagram of another source driver buffer output circuit provided by an embodiment of the present disclosure;

[0023] Figure 7A schematic structural diagram of a source driver buffer circuit provided by an embodiment of the present disclosure;

[0024] Figure 8 When C=0, A=0 Figure 7 The schematic diagram of the structure of the source driver buffer circuit shown;

[0025] Figure 9 When C=1 and B=0 Figure 7 The structural diagram of the source driver buffer circuit is shown in FIG. DETAILED DESCRIPTION

[0026] The following describes in detail embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0027] Figure 1 The figure is a schematic diagram of the circuit structure between a source driving circuit and a display panel in a related technology.

[0028] like Figure 1 As shown, the source driver circuit includes a driver array corresponding to each column of pixels in the display panel. Each driver array includes a digital-to-analog converter (DAC), a buffer, and an output switch (OUTSW). The output of the OUTSW is connected to each column of pixels in the display panel. When the input data of the source driver changes, the output switch cuts off the output of the buffer to prevent noise generated during data conversion from affecting the display panel.

[0029] in, Figure 1 In FIG, CH[1], CH[N], etc. respectively represent the first driving channel and the Nth driving channel in the driving array, that is, the driving channels for driving the first column of pixels and the Nth column of pixels in the display panel respectively.

[0030] in addition, Figure 1 R and C in the figure represent the equivalent driving resistance and capacitance corresponding to each pixel point. The numbers of R and C in the figure are only for schematic illustration.

[0031] Figure 2 The figure is a schematic diagram of the circuit structure between a source driver buffer circuit and driven pixels in a related technology.

[0032] like Figure 2 As shown in the buffer circuit, the buffer uses the power supply VDD according to the input (IN) to generate a driving current I a Through the output switch OUTSW, each pixel in the display panel is charged, or each pixel ( Figure 2 The charge in each capacitor shown in FIG is discharged through the output switch OUTSW and the buffer (I b ) to ground (GND). During display driving, the current flows through the components ( Figure 2 The transistors P1 and N1 in the display driver and the output switch OUTSW generate heat. The more current the display driver requires, the more heat is generated. In high-resolution and large-scale panels, the display driver requires more current, which increases the temperature of the source driver. Therefore, a solution to reduce the source driver temperature is urgently needed.

[0033] In response to the above-mentioned problems, the present disclosure proposes a source driver buffer output circuit, which controls whether the buffer outputs a driving voltage to the display panel by controlling whether the transistor outputs a driving current, thereby reducing the equivalent resistance in the driving circuit, thereby reducing energy loss and the temperature of the source driver.

[0034] Figure 3 This is a schematic diagram of the structure of a source driver buffer output circuit provided by an embodiment of the present disclosure. Figure 3 As shown, the source driver buffer output circuit provided by the present disclosure includes:

[0035] an output control unit 31 , a first transistor 32 , and a second transistor 33 .

[0036] Wherein, the first input end of the output control unit 31 is connected to the first output end of the source driver buffer 30, the second input end of the output control unit 31 is connected to the second output end of the source driver buffer 30, the third input end of the output control unit 31 is connected to the third output end of the source driver buffer 30, the first output end of the output control unit 31 is connected to the driving end of the first transistor 32, the second output end of the output control unit 31 is connected to the driving end of the second transistor 33, and the third output end of the output control unit 31 is connected to the connection end of the first transistor 32 and the second transistor 33. The output control unit 31 is used to control whether the first transistor 32 and the second transistor 33 output a driving current to the display panel;

[0037] The first connection terminal of the first transistor 32 is connected to the first power supply V1, and the second connection terminal of the first transistor 32 is connected to the first connection terminal of the second transistor 33;

[0038] The second connection terminal of the second transistor 33 is connected to the second power supply V2.

[0039] In some possible implementations, the first transistor 32 and the second transistor 33 may be transistors of the same type, for example, both may be N-type transistors, or both may be P-type transistors.

[0040] In some possible implementations, the first transistor 32 and the second transistor 33 may be different types of transistors, for example, the first transistor 32 is an N-type transistor and the second transistor 33 is a P-type transistor; or Figure 3 As shown, the first transistor 32 is a P-type transistor, and the second transistor 33 is an N-type transistor, which is not limited in the present disclosure.

[0041] It should be noted that, in order to achieve the functions to be achieved in the present disclosure, when the first transistor 32 and the second transistor 33 are of the same or different types, the signals output by the first output terminal and the second output terminal of the output control unit 31 can be the same or opposite.

[0042] The first output terminal and the second output terminal of the source driver buffer are respectively connected to the driving terminals of the two transistors in the source driver buffer. The third output terminal of the source driver buffer is a connecting terminal of the two transistors in the source driver buffer.

[0043] In some possible implementations, the second power source V2 may be a power ground.

[0044] It should be noted that Figure 3 The source driver buffer circuit shown is only used to drive a column of pixels (including the source driver buffer and the buffer output circuit). When driving the display panel, the actual source driver circuit needs to include multiple channels. Figure 3 The circuit shown is used to drive each column of pixels in the display panel separately.

[0045] In the source driver buffer output circuit provided in the embodiment of the present disclosure, by utilizing an output control unit to control the conduction state of the first transistor and the second transistor, it is possible to control whether the driving voltage is output to the display panel, and the driving current output to the display panel does not need to pass through the switching component, thereby reducing the equivalent resistance of the driving current passing through the branch and reducing energy loss.

[0046] Figure 4 This is a schematic diagram of another source driver buffer output circuit provided by an embodiment of the present disclosure. Figure 4 As shown, the output control unit 31 includes a first switch component SW1, a second switch component SW2 and a third switch component SW3.

[0047] One end of the first switch component SW1 is connected to the first output end of the source driver buffer 30 , and the other end of the first switch component SW1 is connected to the driving end of the first transistor 32 ;

[0048] One end of the second switch component SW2 is connected to the second output end of the source driver buffer 30 , and the other end of the second switch component SW2 is connected to the driving end of the second transistor 33 ;

[0049] One end of the third switch element SW3 is connected to the third output end of the source driver buffer 30 , and the other end of the third switch element SW3 is connected to the connection end of the first transistor 32 and the second transistor 33 .

[0050] Among them, the conduction states of SW1, SW2 and SW3 can be controlled by the same signal. When SW1, SW2 and SW3 are all turned on, the transistors P1 and N1 in the source driver buffer 30 and the first transistor 32 and the second transistor 33 in the output circuit provided by the embodiment of the present disclosure can output the driving current to the display panel. At this time, the driving current I0 output to the display panel is composed of the current I2 passing through the third switch component SW3 and the current I1 passing through the first switch transistor 32. That is to say, at this time, part of the driving current will still pass through SW3, but because the current I2 is less than the current I0, according to the current loss calculation formula

[0051] p=I 2 ×R

[0052] It can be seen that the current loss p is proportional to the square of the current I and the resistance R. When the resistance remains unchanged, as long as the current decreases, the power will decrease by a square multiple. If the current I2 passing through SW3 is 1 / 2 of I0, then the loss caused by the current passing through SW3 is Figure 1 or Figure 2 The current loss in the output switch OUTSW is shown as 1 / 4 of that in the figure.

[0053] Furthermore, when the on-resistance of SW3 is non-zero, the resistance of the branch generating current I1 is smaller than the resistance of the branch generating current I2. Therefore, current I1 is necessarily greater than current I2. In other words, I2 is less than 1 / 2 of I0, resulting in a loss that is less than 1 / 4 of the driving loss when using a switch component to control the output of a source driver register in the related art.

[0054] Furthermore, since the driving current is provided by the transistors in the buffer and the output circuit in parallel, the parallel circuit also reduces the equivalent resistance in the driving loop, which not only reduces energy loss but also improves the conversion rate of the driving signal.

[0055] Therefore, the source driver buffer output circuit provided by the embodiment of the present disclosure can greatly reduce source driver loss.

[0056] In addition, if the display panel to be driven is a liquid crystal display (LCD), in order to avoid polarization of the liquid crystal molecules, the LCD panel must alternately use positive buffers and negative buffers to drive the liquid crystal molecules. Generally, each pixel in the LCD panel can be driven by frame-by-frame inversion, row-by-row inversion, column-by-column inversion, or dot-by-dot inversion. And in order to reduce the scale of the driving circuit, such as Figure 5 As shown, two adjacent columns can share a set of positive and negative buffers.

[0057] Figure 5 Schematic diagram of another circuit structure between a source driver buffer circuit and driven pixels in the related art.

[0058] like Figure 5 As shown, the drive signals output by this buffer circuit can be used to drive two columns of pixels in an LCD display panel. OUTSW1 and OUTSW4 are controlled by the same signal, K, while OUTSW2 and OUTSW3 are controlled by the same signal, G. The K and G signals are mutually opposite. When the K signal is valid, OUTSW1 and OUTSW4 are simultaneously turned on, CH1 outputs the positive drive voltage generated by the positive buffer, and CH2 outputs the negative drive voltage generated by the negative buffer. When the G signal is valid, OUTSW2 and OUTSW3 are simultaneously turned on, CH1 outputs the negative drive voltage generated by the negative buffer, and CH2 outputs the positive drive voltage generated by the positive buffer. This achieves polarity reversal for the two columns of pixels driven by CH1 and CH2, respectively.

[0059] in, Figure 5 The VDDA, HVDD, and VSSA shown in the figure are all power supplies, and VDDA>HVDD>VSSA. For example, VSSA can be a power ground, and HVDD is about half the size of VDDA, which is not limited in this disclosure.

[0060] The source driver buffer output circuit provided by the above embodiment is used to replace Figure 5 When the four output switch components are shown in FIG, in order to ensure that each source driver buffer output circuit connected to the positive and negative buffers can work reliably, the embodiment of the present disclosure can also add a voltage switching unit ( Figure 3 or Figure 4 not shown).

[0061] In which, the voltage switching unit is respectively connected to the driving end of the first transistor 32, the substrate of the first transistor 32, the driving end of the second transistor 33, the substrate of the second transistor 33, the first power supply V1, the second power supply V2, the third power supply V3 and the fourth power supply V4, and is used to control the driving end and substrate of the first transistor 32 to be respectively connected to the first power supply V1 or the third power supply V3, and to control the driving end and substrate of the second transistor 33 to be respectively connected to the second power supply V2 or the fourth power supply V4.

[0062] In the embodiment of the present disclosure, a voltage switching unit is utilized to control the driving ends and substrates of the first transistor 32 and the second transistor 33 to be connected to different power supplies respectively. By switching the voltages of the driving ends and substrates of the first transistor 32 and the second transistor 33, the reliable on or off of the first transistor 32 and the second transistor 33 is ensured, so that the voltage outputted from the connection ends of the first transistor 32 and the second transistor 33 is consistent with the desired voltage.

[0063] Figure 6 This is a schematic diagram of another source driver buffer output circuit provided by an embodiment of the present disclosure. Figure 6 As shown, the voltage switching unit in the source driver buffer output circuit provided by the present disclosure includes: a fourth switch component SW4 to a thirteenth switch component SW13.

[0064] The two ends of the fourth switch component SW4 are connected to the third power supply V3 and the driving end of the first transistor 32 respectively;

[0065] Two ends of the fifth switch component SW5 are respectively connected to the fourth power supply and the driving end of the second transistor;

[0066] One end of the sixth switch component SW6 is connected to the first power supply, and the other end of the sixth switch component SW6 is connected to one end of the seventh switch component SW7;

[0067] The other end of the seventh switch component SW7 is connected to the driving end of the first transistor 32;

[0068] One end of the eighth switch component SW8 is connected to the second power supply V2, and the other end of the eighth switch component SW8 is connected to one end of the ninth switch component SW9;

[0069] The other end of the ninth switch component SW9 is connected to the driving end of the second transistor 33;

[0070] Two ends of the tenth switch component SW10 are connected to the substrate of the first transistor 32 and the first power supply V1 respectively;

[0071] Two ends of the eleventh switch component SW11 are connected to the substrate of the first transistor 32 and the third power supply V3 respectively;

[0072] Two ends of the twelfth switch component SW12 are respectively connected to the substrate of the second transistor 33 and the second power supply V2;

[0073] Two ends of the thirteenth switch element SW13 are connected to the substrate of the second transistor 33 and the fourth power supply V4 respectively.

[0074] in, Figure 6 In the figure, "A", "AB", "C", and "CB" respectively represent control signals for controlling the corresponding switch components to be turned on or off. "A" and "AB" represent control signals that are opposite to each other. For example, if A=1, then AB=0. In addition, "C" and "CB" represent control signals that are opposite to each other. For example, if C=0, then CB=1, etc.

[0075] The source driver buffer output circuit provided in the embodiment of the present disclosure can control whether the first transistor 32 and the second transistor 33 output a driving current to the display panel by controlling the conduction state of each switch component, and make the driving voltage output by the first transistor 32 and the second transistor 33 consistent with the desired driving voltage.

[0076] It should be noted that the above Figure 6 The provided source driver buffer output circuit can also be used to drive non-liquid crystal display panels. In this case, since there is no need to switch the polarity of the drive voltage corresponding to each column of pixels, the various switch components in the voltage switching unit can be fixed in a specific state. For example, all switch components in the voltage switching unit can be disconnected; or, the switch components used to connect the driving terminals of the first transistor 32 and the second transistor 33 to the power supply can be disconnected, and the substrates of the first transistor 32 and the second transistor 33 are respectively connected to a fixed voltage to ensure that the first transistor 32 and the second transistor 33 can be reliably turned on and off.

[0077] Based on the source driver buffer output circuit provided in the above embodiment, the embodiment of the present disclosure can also provide a source driver buffer output chip, which includes the above Figure 3 、 Figure 4 or Figure 6 Any of the source driver buffer output circuits shown.

[0078] That is to say, the source driver buffer output circuit provided by the embodiment of the present disclosure can be integrated on a substrate or semiconductor chip and packaged in a tube shell. In order to maximize the compatibility and adaptability of the source driver buffer output chip, the source driver buffer output chip provided by the embodiment of the present disclosure can be integrated as follows: Figure 6 The source driver buffer output chip includes three input terminals and four power terminals, wherein the three input terminals are respectively used to connect to the source driver buffer, and the four power terminals can select corresponding power connections according to the type of display panel to be driven.

[0079] Based on the source driver buffer output circuit provided in the above embodiment, the present disclosure may further provide a source driver buffer circuit. The source driver buffer circuit includes n buffers and m source driver buffer output circuits provided in any of the above embodiments, where n and m are integers greater than or equal to 1.

[0080] in, Figure 3 and Figure 4 , exemplarily shows a schematic diagram of a source driver buffer circuit consisting of a buffer and a source driver buffer output circuit. The source driver buffer circuit can be used to drive a column of pixels in a non-liquid crystal display screen.

[0081] Figure 7 A schematic structural diagram of a source driver cache circuit provided by an embodiment of the present disclosure.

[0082] When used to drive a liquid crystal display panel, the source driver buffer circuit needs to include two buffers (such as Figure 7 71, 72) and 4 as shown in Figure 6 The source driver cache output circuit shown (such as Figure 7 73-76 shown in ).

[0083] like Figure 7 As shown, the first input end of one of the buffers is used to receive a positive drive signal INP(+), and the first input end of another buffer is used to receive a negative drive signal INP(-);

[0084] The input terminals of the first source driver buffer output circuit 73 and the third source driver buffer output circuit 75 of the four source driver buffer output circuits are respectively connected to the output terminals of the buffer 71 receiving the positive drive signal, and the input terminals of the second source driver buffer output circuit 74 and the fourth source driver buffer output circuit 76 are respectively connected to the output terminals of the buffer 72 receiving the negative drive signal.

[0085] The output end of the first source driver buffer output circuit 73 is connected to the output end of the second source driver buffer output circuit 74, and is used to provide a driving current for a column of pixels in the liquid crystal display panel;

[0086] The output end of the third source driver buffer output circuit 75 is connected to the output end of the fourth source driver buffer output circuit 76 to provide driving current for another column of pixels in the liquid crystal display panel.

[0087] in, Figure 7 The magnitude relationship among the power supplies VDDA, VSSA and HVDD can be referred to the detailed description of the above embodiment and will not be repeated here.

[0088] It should be noted that Figure 7 It can be seen that the driving terminals of the P-type transistors in the first source driver buffer output circuit 73 and the third source driver buffer output circuit 75 are connected to the same power supply (VDDA) through the switch components. Since the driving terminals of the P-type transistors are not connected to different voltages as different switch components are turned on, the substrate voltage can be kept fixed and reliable control can be achieved. Figure 7 As shown, the substrates of the P-type transistors in the first source driver buffer output circuit 73 and the third source driver buffer output circuit 75 do not need to be connected to different power supplies through switch components.

[0089] Likewise, Figure 7 In the example, the driving terminals of the N-type transistors in the second source driver buffer output circuit 74 and the fourth source driver buffer output circuit 76 are also connected to the same power supply (VSSA) through the switch component. Therefore, the substrate voltages of the two N-type transistors can be kept constant without having to connect them to different power supplies through the switch component.

[0090] In addition, A, B, C, AB, BB, and CB in the figure represent signals for controlling the on / off state of each switch element, wherein A and AB, B and BB, and C and CB have opposite phases. For example, if A=1, then AB=0, and if C=0, then CB=1.

[0091] Depend on Figure 7 It can be seen that the control signals C and CB can control the polarity of the output drive signal. In addition, in order to ensure Figure 7 In the source driver buffer circuit shown in FIG, each driver channel has only one source driver buffer output circuit outputting a driving signal at the same time. Figure 7 The control signal timing of each switch component in the circuit shown is reasonably controlled.

[0092] When the control signal C is 0, the control signal A must also be 0. At this time, if the control signal B is 0, then Figure 7 The driving channels shown in do not output driving signals, and if the control signal B is 1, the driving signal output by the CH1 channel is a negative polarity signal, and the driving signal output by the CH2 channel is a positive polarity signal. When the control signal C is 1, the control signal B must be zero. At this time, if the control signal A is 0, then Figure 7 The driving channels shown in do not output driving signals, and if the control signal A is 1, the driving signal output by the CH1 channel is a positive polarity signal, and the driving signal output by the CH2 channel is a negative polarity signal.

[0093] It should be noted that the above control signal logic is only a schematic illustration, and the control logic of control signal A and control signal B can also be interchanged. That is to say, when control signal C is 0, control signal B is also 0, and at this time control signal A can be 0 or 1, and when control signal C is 1, control signal A is 0, and at this time control signal B can be 0 or 1, and so on. The present disclosure does not limit this. When C=1 and CB=0, the first source driver buffer output circuit 73 and the fourth source driver buffer output circuit 76 are enabled, and the second source driver buffer output circuit 74 and the third source driver buffer output circuit 75 are disabled. At this time, the output of the buffer 71 receiving the positive drive signal is connected to CH1 through the first source driver buffer output circuit 73, and the output of the buffer 72 receiving the negative drive signal is connected to CH2 through the fourth source driver buffer output circuit 76. That is, when C=0 and C=1, the driving signals output by the CH1 channel and the CH2 channel have opposite polarities. Thus, the driving voltage polarities of the CHI driving channel and the CH2 driving channel are switched by adjusting the control signals C and CB.

[0094] The following combination Figure 8 and Figure 9 , for the above Figure 7 The working principle of the source driver buffer circuit shown is described in detail.

[0095] Figure 8 When C=0, A=0 Figure 7 The schematic diagram of the source driver buffer circuit shown in FIG. Figure 9 When C=1 and B=0 Figure 7 The structural diagram of the source driver buffer circuit is shown in FIG.

[0096] like Figure 8As shown, when C = 0 and A = 0, the second source driver buffer output circuit 74 and the third source driver buffer output circuit 75 are enabled, and the first source driver buffer output circuit 73 and the fourth source driver buffer output circuit 76 are disabled. At this time, if B = 1 and BB = 0, the output of the buffer 71 receiving the positive drive signal can be connected to CH2 through the third source driver buffer output circuit 75, and the output of the buffer 72 receiving the negative drive signal can be connected to CH1 through the second source driver buffer output circuit 74. If B = 0 and BB = 1, then neither CH1 nor CH2 outputs a drive signal.

[0097] like Figure 9 As shown, when C=1 and B=0, the first source driver buffer output circuit 73 and the fourth source driver buffer output circuit 76 are enabled, and the second source driver buffer output circuit 74 and the third source driver buffer output circuit 75 are disabled. At this time, if A=1 and AB=0, the output of the buffer 71 receiving the positive drive signal is connected to CH1 through the first source driver buffer output circuit 73, and the output of the buffer 72 receiving the negative drive signal is connected to CH2 through the fourth source driver buffer output circuit 76. If A=0 and AB=1, then neither CH1 nor CH2 outputs a drive signal.

[0098] In other words, by adjusting the control signals C and CB, the driving voltage polarity of the CH1 driving channel and the CH2 driving channel can be switched. Furthermore, when the control signal C = 0 and A = 0, by adjusting the control signal B, it is possible to determine whether the driving signal is output to the CH1 channel and the CH2 channel; and when the control signal C = 1 and B = 0, by adjusting the control signal A, it is possible to determine whether the driving signal is output to the CH1 channel and the CH2 channel. Based on the source driver cache circuit provided in the above embodiment, the present disclosure further provides a source driver cache chip, including the source driver cache circuit provided in the above embodiment.

[0099] In some possible implementation forms, the source driver cache chip provided by the embodiment of the present disclosure may include a cache and a source driver cache output circuit (such as Figure 3 or 4); or, it may further include a buffer and two source driver buffer output circuits ( Figure 7 The circuit shown can be regarded as consisting of two such chips); or, it can also include two buffers and four source driver buffer output circuits (such as Figure 7 shown).

[0100] That is to say, the source driver cache circuit provided by the embodiment of the present disclosure can be integrated on a substrate or semiconductor chip and packaged in a tube shell. In order to maximize the compatibility and adaptability of the source driver cache chip, the source driver cache chip provided by the embodiment of the present disclosure can integrate a cache and two source driver cache output circuits connected thereto, such as Figure 7 The buffer 71, the first source driver buffer output circuit 73 and the third source driver buffer output circuit 75, or, Figure 7 The buffer 72, the second source driver buffer output circuit 74 and the fourth source driver buffer output circuit 76.

[0101] Based on the source driver cache circuit provided in the above embodiment, an embodiment of the present disclosure further provides a source driver circuit, including the source driver cache circuit provided in the above embodiment.

[0102] Based on the source driver circuit provided in the above embodiment, an embodiment of the present disclosure further provides an electronic device, including the source driver circuit and a display panel provided in the above embodiment.

[0103] It should be noted that if the display panel in the electronic device is an LCD panel, the structure of the source driver buffer circuit included in the source driver circuit can be as follows: Figures 7 to 9 If the display panel is a non-liquid crystal panel, the structure of the source driver buffer circuit included in the source driver circuit can be as shown in FIG. Figure 3 Or as shown in 4.

[0104] The source driver cache circuit, source driver circuit, and electronic device provided by the embodiments of the present disclosure can control whether a driving current is output to a display panel by controlling the conduction state of a first transistor and a second transistor using an output control unit. Furthermore, the driving current output to the display panel does not need to pass through a switching component, thereby reducing the equivalent resistance of the driving current passing through a branch and reducing energy loss.

[0105] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this disclosure, the meaning of "plurality" is at least two, for example, two, three, etc., unless otherwise specifically defined.

[0106] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and are not to be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A source driver buffer output circuit, characterized in that: include: An output control unit, a first transistor, a second transistor, and a voltage switching unit; Wherein, the first input end of the output control unit is used to be connected to the first output end of the source driver buffer, the second input end of the output control unit is connected to the second output end of the source driver buffer, the third input end of the output control unit is connected to the third output end of the source driver buffer, the first output end of the output control unit is connected to the driving end of the first transistor, the second output end of the output control unit is connected to the driving end of the second transistor, and the third output end of the output control unit is connected to the connection end of the first transistor and the second transistor. The output control unit is used to control whether the first transistor and the second transistor output a driving current to the display panel; The first connection terminal of the first transistor is connected to a first power supply, and the second connection terminal of the first transistor is connected to the first connection terminal of the second transistor; The second connection terminal of the second transistor is connected to a second power supply; The voltage switching unit is configured to control the driving end and substrate of the first transistor to be connected to the first power supply or the third power supply, and to control the driving end and substrate of the second transistor to be connected to the second power supply or the fourth power supply, respectively; The voltage switching unit includes a fourth switch component to a thirteenth switch component; Wherein, two ends of the fourth switch component are connected to the third power supply and the driving end of the first transistor respectively; Two ends of the fifth switch component are respectively connected to the fourth power supply and the driving end of the second transistor; One end of the sixth switch assembly is connected to the first power source, and the other end of the sixth switch assembly is connected to one end of the seventh switch assembly; The other end of the seventh switch component is connected to the driving end of the first transistor; One end of the eighth switch assembly is connected to the second power supply, and the other end of the eighth switch assembly is connected to one end of the ninth switch assembly; The other end of the ninth switch component is connected to the driving end of the second transistor; Two ends of the tenth switch component are respectively connected to the substrate of the first transistor and the first power supply; Two ends of the eleventh switch component are respectively connected to the substrate of the first transistor and the third power supply; Two ends of the twelfth switch component are respectively connected to the substrate of the second transistor and the second power supply; Two ends of the thirteenth switch component are connected to the substrate of the second transistor and the fourth power source respectively.

2. The circuit according to claim 1, wherein The output control unit includes a first switch component, a second switch component and a third switch component; One end of the first switch component is connected to the first output end of the source driver buffer, and the other end of the first switch component is connected to the driving end of the first transistor; One end of the second switch component is connected to the second output end of the source driver buffer, and the other end of the second switch component is connected to the driving end of the second transistor; One end of the third switch component is connected to the third output end of the source driver buffer, and the other end of the third switch component is connected to the connection end of the first transistor and the second transistor.

3. A source driver buffer output chip, characterized in that: The device comprises a source driver buffer output circuit as described in any one of claims 1-2.

4. A source driver buffer circuit, characterized in that: The method comprises n buffers and m source driver buffer output circuits as claimed in any one of claims 1 to 2, wherein n and m are integers greater than or equal to 1 respectively.

5. The circuit according to claim 4, wherein n=2, m=4, and the four source driver buffer output circuits are as described in claim 1 or 2; Wherein, the first input terminal of one of the buffers is used to receive a positive driving signal, and the first input terminal of the other buffer is used to receive a negative driving signal; The input ends of the first source driver buffer output circuit and the third source driver buffer output circuit of the four source driver buffer output circuits are respectively connected to the output ends of the buffers receiving the positive drive signal, and the input ends of the second source driver buffer output circuit and the fourth source driver buffer output circuit are respectively connected to the output ends of the buffers receiving the negative drive signal; The output end of the first source driver buffer output circuit is connected to the output end of the second source driver buffer output circuit, and is used to provide a driving current for a column of pixels in the liquid crystal display panel; The output end of the third source driver buffer output circuit is connected to the output end of the fourth source driver buffer output circuit, and is used to provide driving current for another column of pixels in the liquid crystal display panel.

6. A source driver buffer chip, characterized in that: It comprises the source driver cache circuit as claimed in claim 4 or 5.

7. A source driver circuit, characterized in that: It comprises the source driver cache circuit as claimed in claim 4 or 5.

8. An electronic device, characterized in that: It comprises the source driving circuit and the display panel as claimed in claim 7.

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