Method of manufacturing an mram memory

Abstract

The application provides a preparation method of MRAM memory, which comprises the following steps: providing a substrate, wherein the substrate comprises an array area and a logic area; depositing a medium on the surface of the substrate to form a first medium layer of the array area and a medium layer of the logic area; then forming a magnetic tunnel junction bottom electrode, a magnetic tunnel junction material layer and a medium hard mask layer in the array area, and exposing the medium layer of the logic area; forming a second medium layer on the medium hard mask layer of the array area, and supplementing the medium layer of the logic area; performing photoetching and etching to form a first perforation for exposing the magnetic tunnel junction material layer in the array area, and forming a second perforation for exposing a bottom metal wire in the logic area; filling metal in the first perforation and the second perforation, and performing a planarization treatment to form a metal hard mask layer of the array area and a metal through hole of the logic area; and etching the magnetic tunnel junction material layer based on the metal hard mask layer to form a magnetic tunnel junction in the array area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication technology, and in particular to a method for fabricating an MRAM memory. Background Technology

[0002] For memory chips, their internal structure can typically be divided into an array region for implementing storage functions and a logic region for implementing logic functions and other functions. For some memory chips, the array region structure is characterized by placing / fabricating storage structures between two metal layers, such as MRAM. The core storage cell of MRAM is a magnetic tunnel junction (MTJ), placed between the bottom electrode and the top electrode.

[0003] Currently, ion beam etching is the most common method used both domestically and internationally for etching MTJs. To ensure sufficient cleaning after the main etching process, the bottom electrode also needs to have sufficient height. The method of interconnecting the bottom electrode of the MTJ with the underlying conductive layer greatly limits the over-etching and sidewall cleaning processes after MTJ etching. If sufficient over-etching and sidewall cleaning are used for MTJ etching, it will come into contact with the underlying metal interconnects, causing metal contamination and etching backsplatter.

[0004] Furthermore, to reduce backsplashing during the MTJ etching process, the bottom electrode should have the following structural features: the top critical dimension should not be larger than the bottom critical dimension of the MTJ, and its height should be greater than the over-etching amount of the memory cell; that is, the bottom electrode should have a high aspect ratio. Due to the memory functional structure and the presence of the aforementioned high aspect ratio bottom electrode, the depth of the logic area metal vias is generally large. Limited by the copper plating process capabilities, forming logic area metal vias is not easily achieved under current processes. Summary of the Invention

[0005] To address the above problems, this invention provides a method for fabricating an MRAM memory that can solve the problem of filling metal vias in the logic area.

[0006] This invention provides a method for fabricating an MRAM memory, comprising:

[0007] A substrate is provided, the substrate including an array region and a logic region;

[0008] A dielectric is deposited on the substrate surface to form a first dielectric layer of the array region and a dielectric layer of the logic region. Then, a magnetic tunnel junction bottom electrode, a magnetic tunnel junction material layer and a dielectric hard mask layer are formed in the array region, and the dielectric layer of the logic region is exposed.

[0009] A second dielectric layer is formed on the array region dielectric hard mask layer, and the logic region dielectric layer is supplemented.

[0010] Photolithography and etching are performed to form a first via in the array region for exposing the magnetic tunnel junction material layer, and a second via in the logic region for exposing the bottom metal line;

[0011] Metal is filled into the first and second through holes and planarized to form a metal hard mask layer for the array region and a metal via for the logic region.

[0012] The magnetic tunnel junction material layer is etched based on the metal hard mask layer to form a magnetic tunnel junction in the array region.

[0013] Optionally, the array region forms a magnetic tunnel junction bottom electrode, a magnetic tunnel junction material layer, and a dielectric hard mask layer, and exposes the logic region dielectric layer, including:

[0014] A magnetic tunnel junction bottom electrode is formed in the first dielectric layer, and then a magnetic tunnel junction material layer and a dielectric hard mask layer are sequentially deposited on the first dielectric layer and the logic region dielectric layer.

[0015] Remove the magnetic tunnel junction material layer and dielectric hard mask layer covering the logic region to expose the logic region dielectric layer.

[0016] Optionally, removing the magnetic tunnel junction material layer and dielectric hard mask layer of the logic region to expose the dielectric layer of the logic region includes:

[0017] The array area and logic area are patterned to ensure that the array area is covered by photoresist while the logic area is exposed.

[0018] The dielectric hard mask layer of the logic region is etched to expose the magnetic tunnel junction material layer of the logic region. After etching, the photoresist covering the array region is removed.

[0019] The entire array region and logic region are etched until the magnetic tunnel junction material layer in the logic region is completely removed.

[0020] Optionally, the metal filled in the first and second perforations is tungsten.

[0021] Alternatively, the filler metal may be processed using tungsten chemical vapor deposition.

[0022] Optionally, etching the magnetic tunnel junction material layer based on the metal hard mask layer to form a magnetic tunnel junction in the array region includes:

[0023] Remove the second dielectric layer and dielectric hard mask layer around the metal hard mask layer to form a metal hard mask pattern, thereby exposing some logic area metal vias;

[0024] The magnetic tunnel junction material layer is etched using the metal hard mask pattern.

[0025] Optionally, after the step of removing the second dielectric layer and the dielectric hard mask layer surrounding the metal hard mask layer to form a metal hard mask pattern and expose the metal vias of a portion of the logic area, the method further includes:

[0026] A layer of anti-splashing medium is deposited on the surface.

[0027] Optionally, the material of the anti-splash dielectric layer is selected from SiN, SiO2 and SiON.

[0028] Optionally, after etching the magnetic tunnel junction material layer based on the metal hard mask layer to form the magnetic tunnel junction in the array region, the method further includes:

[0029] An insulating protective layer is deposited in situ, covering the entire device surface;

[0030] Backfill the medium and perform chemical-mechanical leveling;

[0031] Form the top circuit structure.

[0032] Optionally, during the etching process of the magnetic tunnel junction material layer in the array region, the metal vias in the logic region are etched into an inverted "T" shape.

[0033] The present invention provides a method for fabricating an MRAM memory, which obtains metal vias in the logic region while fabricating an MTJ metal hard mask. This method can reduce backsplashing during the MTJ etching process and solve the problem of filling the metal vias in the logic region caused by the height difference between the logic region and the array region due to the bottom electrode of the high aspect ratio MTJ. Attached Figure Description

[0034] Figures 1-9 This is a schematic diagram of the process flow for a method of fabricating an MRAM memory according to an embodiment of the present invention;

[0035] Figures 10-12 This is a schematic diagram of the process flow for forming the top circuit structure according to an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of this disclosure.

[0037] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged and may have been omitted for clarity. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from actual designs due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0038] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0039] This invention provides a method for fabricating an MRAM memory. Figures 1-12 The entire preparation process is illustrated. Specifically, it includes:

[0040] First, a substrate 100 is provided, which includes an array region 100a and a logic region 100b.

[0041] Semiconductor substrate 100 may be an active layer of silicon (doped or undoped) or a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 100 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer substrates or gradient substrates. Figure 1 M1a and M1b show that bottom metal lines have been formed in array region 100a and logic region 100b respectively.

[0042] Then, a dielectric is deposited on the substrate surface to form the first dielectric layer of the array region and the dielectric layer of the logic region. Subsequently, a magnetic tunnel junction bottom electrode, a magnetic tunnel junction material layer and a dielectric hard mask layer are formed in the array region, and the dielectric layer of the logic region is exposed.

[0043] Specifically, a dielectric is deposited on the surface of the substrate 100 to form a first dielectric layer 102a of the array region and a dielectric layer 102b of the logic region, and a magnetic tunnel junction bottom electrode BE is formed in the first dielectric layer 102a. Then, a magnetic tunnel junction material layer and a dielectric hard mask layer are sequentially deposited on the first dielectric layer 102a and the logic region dielectric layer 102b.

[0044] refer to Figure 1 Before depositing the medium, in this embodiment, an etch barrier layer 101a and 101b is first formed on the substrate.

[0045] The first dielectric layer 102a and the logic region dielectric layer 102b can be formed of any suitable dielectric material, such as nitrides, like silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; or similar materials. The dielectric layers can be formed by any acceptable deposition process (e.g., spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or combinations thereof). Furthermore, in this embodiment, the formed magnetic tunnel junction bottom electrode BE has a high aspect ratio, and its critical dimension is smaller than the critical dimension of the magnetic tunnel junction subsequently formed above it. Such a BE structure facilitates over-etching during subsequent etching of the magnetic tunnel junction material layer.

[0046] A magnetic tunnel junction material layer 103a and a dielectric hard mask layer 104a are deposited in the array region, and a magnetic tunnel junction material layer 103b and a dielectric hard mask layer 104b are deposited in the logic region.

[0047] Then remove the magnetic tunnel junction material layer 103b and the dielectric hard mask layer 104b covering the logic region to expose the logic region dielectric layer 102b.

[0048] For details, please refer to the following: Figures 1 to 3 This can be achieved in the following way:

[0049] like Figure 1 As shown, the patterned array area and logic area are defined, ensuring that the array area is covered by photoresist (PR, also known as photoresist), while the logic area is exposed.

[0050] like Figure 2 As shown, the dielectric hard mask layer 104b of the logic region is etched to expose the magnetic tunnel junction material layer 103b of the logic region. This process can be reactive ion etching (RIE). After etching, the photoresist covering the array region is removed.

[0051] like Figure 3 As shown, the entire array region and logic region are etched until the magnetic tunnel junction material layer in the logic region is completely removed.

[0052] Throughout the etching process, due to the protection of the array region by the dielectric hard mask layer 104a, only the magnetic tunnel junction material layer 103b of the logic region is ultimately etched. This process can be either reactive ion etching (RIE) or ion beam etching (IBE). This step requires ensuring that the magnetic tunnel junction material layer 103b of the logic region is completely removed.

[0053] Then, the dielectric is backfilled, a second dielectric layer 105a is formed on the array region dielectric hard mask layer 104a, and the logic region dielectric layer 102b is added.

[0054] Figure 4 The device structure after backfilling with dielectric is shown. The material of the backfill dielectric can be the same as or different from the material of the first dielectric layer 102a and the logic region dielectric layer 102b formed previously.

[0055] Next, photolithography and etching are performed to form a first via in the array region for exposing the magnetic tunnel junction material layer, and a second via in the logic region for exposing the bottom metal line.

[0056] refer to Figure 5 After backfilling with dielectric, the device surface is uneven, so planarization can be performed first. Then, photoresist is spin-coated onto the surfaces of the second dielectric layer 105a and the logic region dielectric layer 102b to form an etching pattern on the photoresist.

[0057] refer to Figure 6 Through etching, specifically reactive ion etching (RIE), a first via 106a is formed in the array region, and a second via 106b is formed in the logic region. The first via 106a penetrates the second dielectric layer 105a and the dielectric hard mask layer 104a in the array region, exposing the magnetic tunnel junction material layer 103a. The second via 106b penetrates the dielectric layer 102b and the etch barrier layer 101b in the logic region, exposing the bottom metal line M1b of the logic region. This etching step is crucial, as vias are formed in both the array region and the logic region, requiring strict control over the etching endpoint.

[0058] Then, metal is filled into the first and second vias and planarized to form a metal hard mask layer for the array region and metal vias for the logic region.

[0059] Figure 7 A schematic diagram of the structure forming the metal hard mask layer 107a and the logic region metal via 107b is shown. In this embodiment, tungsten chemical vapor deposition (W CVD) is used to fill the vias with tungsten (W). The W hard mask layer can reduce the probability of backsplatting during MTJ etching. The logic region metal vias use W, which has better filling capabilities and no risk of electron migration, increasing product reliability. Moreover, compared with the traditional copper electroplating Cu ECP process, the W CVD process has better filling performance for high aspect ratio second vias.

[0060] Then, the magnetic tunnel junction material layer is etched based on the metal hard mask layer to form a magnetic tunnel junction in the array region.

[0061] Before etching, the second dielectric layer and dielectric hard mask layer around the metal hard mask layer are removed to form a metal hard mask pattern, thus exposing some logic area metal vias. Figure 8A schematic diagram of the structure after removing the second dielectric layer around the metal hard mask layer 107a and the dielectric hard mask layer is shown. The dielectric is backfilled by reverse etching, exposing the metal hard mask 107a and part of the logic region metal vias 107b. The array region dielectric hard mask layer 104a is also etched away using RIE (Round-Etched Electrode).

[0062] Optionally, after removing the second dielectric layer and the dielectric hard mask layer surrounding the metal hard mask layer 107a, a dielectric layer can be deposited on the surface. The purpose of this dielectric layer is to reduce backsplashing caused by the metal hard mask during subsequent MTJ etching; therefore, this dielectric layer can be called an anti-backsplash dielectric layer. The material of the anti-backsplash dielectric layer is selected from SiN, SiO2, and SiON.

[0063] refer to Figure 9 The magnetic tunnel junction material layer 103a is etched using a metal hard mask pattern as a mask. Ion beam etching (IBE) can be used to etch the structure, and partial over-etching (OE) is introduced to ensure complete removal of backsplashing during the process. A magnetic tunnel junction 103a' is formed in the array region, and the logic region dielectric layer surrounding the logic region metal via 107b is simultaneously removed. In this embodiment, the logic region metal via 107b exhibits a distinct inverted "T" shaped structure. When designing the bottom electrode height, it is necessary to consider that the over-etching must not touch 101b. In addition to vertical etching, the critical lateral dimension of the logic region metal via 107b also decreases with etching. Combined with the restriction of not touching 101b, an inverted "T" shaped structure can be formed. Furthermore, Figure 9 Although the structure shown in the figure has the logic area metal vias fully exposed, in reality, MTJ etching introduces over-etching, and it is not necessary for the logic area vias to be fully exposed, and there can be dielectric residue.

[0064] Thus, through the above steps, a magnetic tunnel junction has been formed in the array region, and an inverted "T"-shaped metal via has been formed in the logic region.

[0065] The MRAM memory fabrication method provided in this embodiment obtains logic region metal vias while fabricating the MTJ metal hard mask. This reduces backsplashing during the MTJ etching process and solves the problem of filling logic region metal vias caused by the height difference between the logic region and the array region due to the high aspect ratio MTJ bottom electrode.

[0066] Furthermore, after the array region forms a magnetic tunnel junction and the logic region forms a logic region metal via, the top circuit structure of the array region and the logic region can continue to be formed on top.

[0067] Specifically, Figures 10 to 12 One implementation of the top circuit structure forming the array region and logic region is shown. (Reference) Figure 10An in-situ deposited insulating protective layer 108 covers the entire device surface to prevent oxidation of the memory cells after they leave the cavity. The insulating protective layer for the array region is designated 108a, and the insulating protective layer for the logic region is designated 108b. (Reference) Figure 11 Backfill with the medium and perform chemical-mechanical leveling. (Reference) Figure 12 The subsequent BEOL (back end of line) process forms the top circuit structures 110a and 110b. This step can use existing conventional processes and will not be elaborated further.

[0068] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0069] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating an MRAM memory, characterized in that, include: A substrate is provided, the substrate including an array region and a logic region; A dielectric is deposited on the substrate surface to form a first dielectric layer of the array region and a dielectric layer of the logic region. Then, a magnetic tunnel junction bottom electrode, a magnetic tunnel junction material layer and a dielectric hard mask layer are formed in the array region, and the dielectric layer of the logic region is exposed. A second dielectric layer is formed on the array region dielectric hard mask layer, and the logic region dielectric layer is supplemented. Photolithography and etching are performed to form a first via in the array region for exposing the magnetic tunnel junction material layer, and a second via in the logic region for exposing the bottom metal line; Metal is filled into the first and second through holes and planarized to form a metal hard mask layer for the array region and a metal via for the logic region. The magnetic tunnel junction material layer is etched based on the metal hard mask layer to form a magnetic tunnel junction in the array region.

2. The method according to claim 1, characterized in that, The array region forms a magnetic tunnel junction bottom electrode, a magnetic tunnel junction material layer, and a dielectric hard mask layer, and exposes the logic region dielectric layer, including: A magnetic tunnel junction bottom electrode is formed in the first dielectric layer, and then a magnetic tunnel junction material layer and a dielectric hard mask layer are sequentially deposited on the first dielectric layer and the logic region dielectric layer. Remove the magnetic tunnel junction material layer and dielectric hard mask layer covering the logic region to expose the logic region dielectric layer.

3. The method according to claim 2, characterized in that, Removing the magnetic tunnel junction material layer and dielectric hard mask layer of the logic region to expose the dielectric layer of the logic region includes: The array area and logic area are patterned to ensure that the array area is covered by photoresist while the logic area is exposed. The dielectric hard mask layer of the logic region is etched to expose the magnetic tunnel junction material layer of the logic region. After etching, the photoresist covering the array region is removed. The entire array region and logic region are etched until the magnetic tunnel junction material layer in the logic region is completely removed.

4. The method according to claim 1, characterized in that, The metal filled in the first and second perforations is tungsten.

5. The method according to claim 4, characterized in that, The filler metal was produced using tungsten chemical vapor deposition.

6. The method according to claim 1, characterized in that, Etching the magnetic tunnel junction material layer based on the aforementioned metal hard mask layer to form a magnetic tunnel junction in the array region includes: Remove the second dielectric layer and dielectric hard mask layer around the metal hard mask layer to form a metal hard mask pattern, thereby exposing some logic area metal vias; The magnetic tunnel junction material layer is etched using the metal hard mask pattern.

7. The method according to claim 6, characterized in that, After the steps of removing the second dielectric layer and dielectric hard mask layer surrounding the metal hard mask layer to form a metal hard mask pattern and exposing the metal vias of a portion of the logic area, the method further includes: A layer of anti-splashing medium is deposited on the surface.

8. The method according to claim 7, characterized in that, The material of the anti-splash dielectric layer is selected from one of SiN, SiO2 and SiON.

9. The method according to claim 1, characterized in that, After etching the magnetic tunnel junction material layer based on a metal hard mask layer to form a magnetic tunnel junction in the array region, the process further includes: An insulating protective layer is deposited in situ, covering the entire device surface; Backfill the medium and perform chemical-mechanical leveling; Form the top circuit structure.

10. The method according to claim 1, characterized in that, During the etching process of the magnetic tunnel junction material layer in the array region, the metal vias in the logic region are etched into an inverted "T" shape.

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