A topcon cell and a preparation method thereof

Abstract

The application provides a TOPCon cell, comprising: a single crystal silicon wafer; an inner expansion layer arranged on the back surface of the single crystal silicon wafer; a doped polysilicon layer arranged below the inner expansion layer; the doped polysilicon layer comprises: a first doped polysilicon region and a second doped polysilicon region, the doping concentration of the first doped polysilicon region is higher than that of the second doped polysilicon region; the inner layer comprises: a first inner expansion region and a second inner expansion region, the position of the first inner expansion region corresponds to the position of the first doped polysilicon region, and the junction depth of the first inner expansion region is greater than that of the second inner expansion region. The TOPCon cell provided by the application has a specific structure, which can ensure the thickness and concentration of the doped polysilicon in the metal contact area, avoid the destruction of the tunneling oxide layer in the slurry sintering process, reduce the recombination current and the contact resistance, and at the same time, reduce the light parasitic absorption of the non-metal area, especially the free carrier absorption.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of batteries, and particularly relates to a TOPCon battery and a preparation method thereof. BACKGROUND

[0002] In the prior art, a TOPCon (tunneling oxide passivated contact) battery is generally prepared by preparing a 1-2 nm ultra-thin tunneling oxide layer on the back surface of a silicon wafer, then depositing a doped polysilicon layer with a thickness of 80-200 nm on the surface of the oxide layer, and finally depositing silicon nitride on the doped polysilicon layer; this structure provides good surface passivation and field passivation for the back surface of the silicon wafer, the ultra-thin oxide layer can make electrons tunnel into the polysilicon layer while blocking the transport of holes, thereby reducing the recombination current; meanwhile, the lateral transport characteristics of the doped polysilicon layer reduce the series resistance; these two characteristics together improve the open-circuit voltage, the fill factor and the conversion efficiency of the battery.

[0003] The back surface of the TOPCon battery usually adopts Ag paste to burn through the dielectric film and form an ohmic contact with the doped polysilicon. During the sintering process of the paste, the metal Ag grains may penetrate the doped polysilicon film layer and destroy the passivation effect of the interface oxide layer; in order to reduce the recombination current density of the metal contact area, the thickness of the doped polysilicon cannot be too thin, and is usually 100-150 nm; in order to ensure good field passivation effect and low ohmic contact, the doped polysilicon needs to have a sufficient doping concentration, which is usually >1e20 cm -3 ; however, the polysilicon film layer in the passivation structure is too thick and has too large a doping concentration, which will cause a loss of the short-circuit current of the TOPCon battery due to the free carrier absorption (FCA) of the doped polysilicon to long-wave light; meanwhile, the parasitic absorption of the doped polysilicon to the back surface incident light will reduce the bifaciality of the battery.

[0004] At present, the thickness and the doping concentration of the polysilicon film layer are reduced as much as possible under the premise that the metal electrode paste does not burn through the tunneling oxide layer and a good ohmic contact is formed between the metal electrode and the polysilicon film layer, so as to reduce the current loss; or only the metal electrode area of the battery adopts the passivation structure, which is difficult to balance the light absorption and the passivation effect of the battery. SUMMARY

[0005] Therefore, the application aims to provide a TOPCon battery and a preparation method thereof, which can reduce the light parasitic absorption of a non-metal area while ensuring the thickness and the concentration of the doped polysilicon in the metal contact area.

[0006] The application provides a TOPCon battery, which comprises:

[0007] a single crystal silicon wafer;

[0008] an inner expansion layer arranged on the back surface of the single crystal silicon wafer;

[0009] A doped polycrystalline silicon layer positioned below the inner expansion layer;

[0010] The doped polysilicon layer includes: a first doped polysilicon region and a second doped polysilicon region, wherein the doping concentration of the first doped polysilicon region is higher than the doping concentration of the second doped polysilicon region.

[0011] The inner layer includes a first inner expansion region and a second inner expansion region. The position of the first inner expansion region corresponds to the position of the first doped polysilicon region, and the junction depth of the first inner expansion region is greater than the junction depth of the second inner expansion region.

[0012] In the embodiments of the present invention, other layer structures of the TOPCon cell can be set according to the structure of the TOPCon cell known to those skilled in the art. For example, a diffusion layer, a passivation layer, a front anti-reflection layer and a front metal electrode can be sequentially set on the front side of the monocrystalline silicon; a tunneling layer can be set between the inner diffusion layer and the doped polycrystalline silicon layer, and a back anti-reflection layer and a back metal electrode can be sequentially set below the doped polycrystalline silicon layer. That is, an inner diffusion layer, a tunneling layer, a doped polycrystalline silicon layer, a back anti-reflection layer and a back metal electrode can be sequentially set on the back side of the monocrystalline silicon wafer.

[0013] In embodiments of the present invention, the single-crystal silicon wafer can be a phosphorus-doped N-type single-crystal silicon wafer with a resistivity of 0.1 to 10 Ωcm, such as 0.5 Ωcm, 1 Ωcm, 2 Ωcm, 4 Ωcm, 6 Ωcm, or 8 Ωcm; and a thickness of 100 to 200 micrometers, such as 120 micrometers, 140 micrometers, 160 micrometers, or 180 micrometers.

[0014] In an embodiment of the invention, the diffusion layer can be a P-type doped layer formed by boron doping, and the sheet resistance can be selected from 100 to 300 Ω, such as 150 Ω, 200 Ω, or 250 Ω.

[0015] In embodiments of the present invention, the passivation layer may be selected from an aluminum oxide layer; the thickness of the passivation layer may be selected from 2 to 6 nm, such as 3 nm, 4 nm, or 5 nm.

[0016] In embodiments of the present invention, the front antireflection layer may be selected from one or more stacked films of silicon nitride layer and silicon oxynitride layer; the (total) thickness of the front antireflection layer may be selected from 70 to 120 nm, such as 80 nm, 90 nm, 100 nm, 110 nm; the (comprehensive) refractive index of the front antireflection layer may be selected from 1.9 to 2.1, such as 2.0.

[0017] In embodiments of the present invention, the front metal electrode can be selected from the negative electrode, such as an Ag / Al electrode.

[0018] In embodiments of the present invention, the tunneling layer may be a silicon oxide layer; the thickness of the tunneling layer may be selected from 1 to 3 nm, such as 2 nm.

[0019] In embodiments of the present invention, the doped polysilicon layer can be a phosphorus-doped polysilicon layer. In embodiments of the present invention, the thickness of the doped polysilicon layer can be selected from 100–200 nm, such as 120 nm, 140 nm, 160 nm, or 180 nm. The thickness of the first doped polysilicon region and the second doped polysilicon region are the same as the thickness of the doped polysilicon layer, and they are two regions located at different positions on the doped polysilicon layer. The doping concentration of the first doped polysilicon region (which can be referred to as the first doped polysilicon layer) is higher than the doping concentration of the second doped polysilicon region (which can be referred to as the second doped polysilicon layer) (5–100)E19 cm⁻¹. -3 (i.e. (5~100)×10) 19 cm -3 (e.g., can be higher than 10E19 cm) -3 20E19 cm -3 30E19 cm -3 40E19 cm -3 50E19 cm -3 60E19 cm -3 70E19 cm -3 80E19 cm -3 90E19 cm -3 In embodiments of the present invention, the doping concentration of the first doped polysilicon region can be selected from 2E20 to 1E21 cm⁻¹. -3 (i.e., 2×10) 20 ~1×10 21 cm -3 ), such as 4E20 cm -3 6E20 cm -3 8E20 cm -3 The doping concentration of the second doped polysilicon region can be selected from 5E19 to 2E20 cm⁻¹. -3 (i.e., 5×10) 19 ~2×10 20 cm -3 ), such as 10E19cm -3 15E19 cm -3 .

[0020] In an embodiment of the present invention, the first inner expansion region (which may be referred to as the first inner expansion layer) and the second inner expansion region (which may be referred to as the second inner expansion layer) are located on the upper surface of the tunneling layer, and the first doped polysilicon region and the second doped polysilicon region are located on the lower surface of the tunneling layer. The positions of the first inner expansion region and the first doped polysilicon region correspond; the positions of the second inner expansion region and the second doped polysilicon region also correspond; the first doped polysilicon region and the first inner expansion region are disposed at positions corresponding to the metal electrode, and can be disposed at the position corresponding to the back metal electrode of the single crystal silicon wafer in the tunneling layer.

[0021] In embodiments of the present invention, the back antireflection layer may be selected from one or more stacked films of silicon nitride layer and silicon oxynitride layer; the (total) thickness of the back antireflection layer may be selected from 70 to 120 nm, such as 80 nm, 90 nm, 100 nm, 110 nm; the (comprehensive) refractive index of the back antireflection layer may be selected from 1.9 to 2.1, such as 2.0.

[0022] In embodiments of the present invention, the back metal electrode may be selected from Ag electrodes.

[0023] In embodiments of the present invention, the structure of the TOPCon battery can be as follows: Figure 1 As shown, it includes: an N-type monocrystalline silicon wafer 1; a diffusion layer 2; a passivation layer 3; a front anti-reflection layer 4; a front metal electrode 5; an inner expansion layer 6, a first inner expansion region 6-1, and a second inner expansion region 6-2; a tunneling layer 7; a doped polycrystalline silicon layer 8; a first doped polycrystalline silicon region 8-1, and a second doped polycrystalline silicon region 8-2; a back anti-reflection layer 9; and a back metal electrode 10. The diffusion layer, passivation layer, front anti-reflection layer, and front metal electrode are sequentially disposed on the upper surface of the N-type monocrystalline silicon wafer. The inner expansion layer, tunneling layer, doped polycrystalline silicon layer, back anti-reflection layer, and back metal electrode are sequentially disposed on the lower surface of the N-type monocrystalline silicon wafer. The first inner expansion region is disposed in a portion of the upper surface of the tunneling layer, and the second inner expansion region is disposed in the remaining areas. The junction depth is greater than that of the second inner expansion region, and the first inner expansion region and the second inner expansion region form an integral inner expansion layer; the first doped polysilicon region is disposed in a portion of the lower surface of the tunneling layer, and the second doped polysilicon region is disposed in the remaining other regions, forming an integral doped polysilicon layer; the first doped polysilicon region is located below the corresponding position of the first inner expansion region, and the second doped polysilicon region is located below the corresponding position of the second inner expansion region, and the inner expansion layer and the doped polysilicon layer are separated by the tunneling layer; the positions of the first doped polysilicon region and the first inner expansion region correspond to the positions of the back metal electrode, that is, the first inner expansion region and the first doped polysilicon region are disposed at the positions of the back metal electrode corresponding to the tunneling layer.

[0024] This invention provides a method for preparing a TOPCon battery, comprising:

[0025] After preparing a doped amorphous silicon thin film on the lower surface of the tunneling layer, it is annealed.

[0026] A silicon oxide layer is prepared on the lower surface of the annealed film as a diffusion barrier layer;

[0027] Grooves are cut into the surface of the diffusion barrier layer;

[0028] POCl3 diffusion is performed, and heavy doping is carried out at the groove to form the first doped polycrystalline silicon region;

[0029] No doping is performed in the non-grooved areas, forming a second doped polysilicon region.

[0030] In embodiments of the present invention, the method for preparing a TOPCon battery may further include:

[0031] A diffusion layer, a passivation layer, a front antireflection layer, and a front metal electrode are sequentially fabricated on the upper surface (front) of a single-crystal silicon wafer.

[0032] A tunneling layer, a doped polycrystalline silicon layer, a back antireflection layer, and a back metal electrode are sequentially fabricated on the lower surface (back side) of a single-crystal silicon wafer.

[0033] In embodiments of the present invention, the method for preparing a single-crystal silicon wafer may include:

[0034] Chemicals are used to remove contaminants from the surface of monocrystalline silicon wafers and to form surface textures on the surface of monocrystalline silicon wafers.

[0035] In embodiments of the present invention, the chemical reagent can be an acid or alkali; the contaminant can be an organic stain or a metallic impurity; forming a texture on the surface of a single-crystal silicon wafer can increase the absorption of sunlight and reduce reflection.

[0036] In the embodiments of the present invention, the diffusion layer can be prepared by high-temperature diffusion, such as by high-temperature diffusion of borides, and the borides can be selected from BCl3 or BBr3; the diffusion temperature can be selected from 950 to 1050°C, such as 1000°C; there are no special restrictions on the specific preparation method of the diffusion layer, and the diffusion layer can be prepared by following the high-temperature diffusion method well known in the art.

[0037] In embodiments of the present invention, after obtaining the diffusion layer, the method may further include:

[0038] Single-sided HF etching removes the BSG (borosilicate glass) on the back side;

[0039] Backside etching removes the PN junction formed by parasitic diffusion on the backside, preventing edge leakage.

[0040] In embodiments of the present invention, the passivation layer can be prepared by using ALD (atomic deposition) to prepare an aluminum oxide (AlOx) film on the surface of the diffusion layer; there are no special restrictions on the specific preparation method of the passivation layer, and it can be prepared by using the ALD method for preparing aluminum oxide films well known in the art.

[0041] In embodiments of the present invention, the front antireflection layer can be prepared by depositing one or more stacked films of silicon nitride film and silicon oxynitride film on the surface of the passivation layer using PECVD (plasma-enhanced chemical vapor deposition). There are no special restrictions on the specific preparation method of the front antireflection layer, and it can be prepared by using the PECVD method well known in the art to prepare silicon nitride film or silicon oxynitride film.

[0042] In embodiments of the present invention, the front metal electrode can be co-sintered by printing the negative electrode Ag / Al paste to form a good ohmic contact.

[0043] In embodiments of the present invention, the method for preparing the tunneling layer may include:

[0044] A silicon oxide layer is grown on the back side of a single-crystal silicon wafer using PECVD (plasma-enhanced chemical vapor deposition).

[0045] In the embodiments of the present invention, there are no special restrictions on the specific preparation method of the tunneling layer, and it can be prepared by the PECVD method well known in the art for preparing the silicon oxide layer.

[0046] In embodiments of the present invention, the method for preparing the doped polycrystalline silicon layer is the process described in the above technical solution for obtaining the first doped polycrystalline silicon region and the second doped polycrystalline silicon region, which together constitute the doped polycrystalline silicon layer. In embodiments of the present invention, the doped amorphous silicon thin film in the above technical solution can be a phosphorus-doped amorphous silicon thin film. The phosphorus-doped amorphous silicon thin film can be prepared using the PECVD method, and the specific preparation method can be prepared according to the well-known PECVD method for preparing phosphorus-doped amorphous thin films. In embodiments of the present invention, the thickness of the phosphorus-doped amorphous thin film can be selected from 100–200 nm, such as 120 nm, 140 nm, 160 nm, or 180 nm; the annealing temperature can be selected from 800–900 °C, such as 830 °C, 850 °C, or 870 °C; and the doping concentration in the film formed after annealing can be selected from 8E19–2E20 cm⁻¹. -3 (i.e., 8×10) 19 ~2×10 20 cm -3 ), such as can be selected from 10E19 cm -3 12E19 cm -3 14E19 cm-3 16E19 cm -3 18E19 cm -3 .

[0047] In the embodiments of the present invention, the diffusion barrier layer can be formed by preparing a silicon oxide layer using the PECVD method. There are no special restrictions on the specific preparation method. It can be prepared by the PECVD method well known in the art. The thickness of the diffusion barrier layer can be selected from 50 to 100 nm, such as 60 nm, 70 nm, 80 nm, and 90 nm.

[0048] In an embodiment of the present invention, a groove can be made on the back metal electrode at the position corresponding to the diffusion barrier layer; the groove can be made by laser etching; the laser wavelength for laser etching can be selected from 350-360nm, such as 355nm; the size and area of ​​the groove can be consistent with the size and area of ​​the back metal electrode.

[0049] In embodiments of the present invention, amorphous silicon can be crystallized by POCl3 diffusion, and the phosphorus-doped polycrystalline film at the trench of the silicon oxide diffusion barrier layer can be heavily doped to form a first phosphorus-doped polycrystalline silicon region. The doping concentration of the first phosphorus-doped polycrystalline silicon region can be selected from 2 to 6E20cm. -3 For example, 3E20cm -3 4E20cm -3 5E20cm -3 In the ungrooved region, the phosphorus-doped polycrystalline silicon film is blocked by a relatively thick silicon oxide barrier layer, maintaining its original low doping concentration and forming a second phosphorus-doped polycrystalline silicon region. The doping concentration of this second region can be selected from 8E19 to 2E20 cm⁻¹. -3 (i.e., 8×10) 19 ~2×10 20 cm -3 ), such as 10E19 cm -3 15E19 cm -3 In an embodiment of the present invention, during the POCl3 diffusion process, due to the use of a slotted configuration, a first doped polysilicon region with a higher doping concentration is formed at the slotted location, and a first inner expansion region is formed at the location of the inner expansion layer corresponding to the first doped polysilicon region; a second doped polysilicon region with a lower doping concentration is formed at the un-slotted location, and a second inner expansion region is formed at the location of the inner expansion layer corresponding to the second doped polysilicon region. The junction depth of the first inner expansion region is necessarily greater than the junction depth of the second inner expansion region.

[0050] In embodiments of the present invention, after the POCl3 diffusion is complete, the following may also be included:

[0051] Single-sided hydrofluoric acid (HF) etching is used to remove the PSG (phosphosilicate glass) on the front and edge polycrystalline silicon surfaces after diffusion. Then, alkaline solution etching is used to remove the polycrystalline silicon layers on the front and edge surfaces. Hydrofluoric acid cleaning is used to remove the BSG on the front and the PSG on the back, as well as the silicon oxide diffusion barrier layer used to block phosphorus diffusion.

[0052] In embodiments of the present invention, the back antireflection layer can be prepared by depositing one or more stacked films of silicon nitride film and silicon oxynitride film on the lower surface of polycrystalline silicon doped layer using PECVD. There are no special restrictions on the specific preparation method of the back antireflection layer, and it can be prepared by using the PECVD method well known in the art to prepare silicon nitride film or silicon oxynitride film.

[0053] In an embodiment of the present invention, the back metal electrode can be co-sintered by printing Ag paste to form a good ohmic contact.

[0054] In an embodiment of the present invention, after obtaining the front metal electrode and the back metal electrode, the method further includes:

[0055] Photoinjection repairs defects in the cell body and on its surface.

[0056] In embodiments of the present invention, the method for preparing a TOPCon battery may include the following steps, such as... Figure 2 As shown:

[0057] 1) Texturing: Using acid and alkali chemicals, organic contaminants and metallic impurities on the surface of silicon wafers are removed, forming a surface texture on the surface of N-type monocrystalline silicon wafers, increasing the absorption of sunlight and reducing reflection; the monocrystalline silicon wafers are phosphorus-doped N-type monocrystalline silicon wafers with a resistivity of 0.1 to 10 Ωcm and a thickness of 100 to 200 micrometers;

[0058] 2) Boron diffusion: A front diffusion layer is formed. The diffusion layer is a boron-doped P-type doped layer with a sheet resistance of 100-300Ω. It is formed by high-temperature diffusion using BCl3 or BBr3.

[0059] 3) BSG: Single-sided HF etching to remove BSG on the back side;

[0060] 4) Backside etching: Removes the PN junction formed by parasitic diffusion on the backside to prevent edge leakage;

[0061] 5) PECVD SiOx / a-Si:H / SiOx: First, a tunneling oxide layer with a thickness of 1–3 nm is grown on the back side of the silicon wafer using PECVD technology. Then, after the tunneling oxide layer is grown, a phosphorus-doped amorphous silicon thin film with a thickness of 100–200 nm is deposited on the surface of the tunneling oxide layer using PECVD technology. After annealing, the doping concentration is 8E19–2E20 cm⁻¹. -3Finally, a silicon oxide diffusion barrier layer with a thickness of 50–100 nm is grown on the back side of the silicon wafer using PECVD technology.

[0062] 6) LCO: The silicon oxide diffusion barrier layer under the back metal area is etched and grooved using laser etching.

[0063] 7) Phosphorus diffusion: POCl3 diffusion is used to crystallize amorphous silicon. Simultaneously, the trenches in the silicon oxide diffusion barrier layer are heavily doped with a doping concentration of 2–6E20cm⁻¹. -3 In the ungrooved region, the doping concentration of amorphous silicon is limited by the silicon oxide barrier layer. Due to the thickness of the barrier layer, the doping concentration ranges from 8E19 to 2E20 cm⁻¹. -3 The level remained low.

[0064] 8) PSG: Single-sided HF etching to remove PSG from the front and edge surfaces of the polysilicon after diffusion.

[0065] 9) Front etching: The polysilicon layer on the front and edge is removed by alkaline etching, and the BSG on the front and PSG and diffusion barrier layer on the back are removed by hydrofluoric acid cleaning.

[0066] 10) ALD: A dense AlOx film with a thickness of 2-6 nm is deposited on the front side of the substrate using ALD atomic layer deposition.

[0067] 11) Front-side PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the front side of a substrate using PECVD;

[0068] 12) Backside PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the backside of a substrate using PECVD;

[0069] 13) Printing / Sintering / Photoinjection: The negative electrode Ag / Al paste is printed on the front side, and the electrode Ag paste is printed on the back side; co-sintering is performed to form a good ohmic contact; photoinjection is used to repair defects in the cell body and on the surface.

[0070] This invention employs PECVD deposition of a tunneling oxide layer, a lightly doped amorphous silicon layer, and a silicon oxide diffusion barrier layer. Laser ablation is performed on the silicon oxide diffusion barrier layer in the metal region (back metal electrode), followed by POCL3 diffusion to crystallize the lightly doped amorphous silicon layer. During this process, phosphorus atoms diffuse inward to form an inner expansion layer. Simultaneously, the ablation region is heavily doped, forming a first doped polycrystalline silicon region corresponding to the metal region (back metal electrode) and a second doped polycrystalline silicon region corresponding to the non-metal region on the back side of the N-type single-crystal silicon wafer. The first doped polycrystalline silicon region has a higher doping concentration than the second doped polycrystalline silicon region, resulting in lower contact resistance in the metal region and lower doping concentration in the non-metal region, reducing free carrier absorption and thus achieving a higher short-circuit current density. The inner expansion layer includes a first inner expansion region corresponding to the first doped polycrystalline silicon region and a second inner expansion region corresponding to the second doped polycrystalline silicon region corresponding to the non-metal region on the back side. The junction depth of the first inner expansion region is greater than that of the second inner expansion region, reducing the recombination current densities Jo1 and Jo2 in the metal region and improving the cell's Voc and pFF. In addition, the preparation method provided by the present invention is simple and easy to implement.

[0071] The TOPCon battery provided by this invention has a specific structure that can ensure the thickness and concentration of doped polycrystalline silicon in the metal contact area (back metal electrode), avoid damage to the tunneling oxide layer during the slurry sintering process, and reduce recombination current and contact resistance; at the same time, it can reduce photoparasitic absorption in the non-metallic area, especially reduce free carrier absorption. Attached Figure Description

[0072] Figure 1 This is a schematic diagram of the TOPCon battery structure in an embodiment of the present invention;

[0073] Figure 2 This is a flowchart illustrating the fabrication process of the TOPCon battery structure in an embodiment of the present invention.

[0074] Figure 3 This is a schematic diagram of the TOPCon battery structure in Comparative Example 1 of the present invention. Detailed Implementation

[0075] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0076] Example 1

[0077] according to Figure 2 The flowchart shown illustrates the fabrication of a TOPCon battery, including the following specific steps:

[0078] S1 texturing: Select phosphorus-doped N-type single crystal silicon wafers with resistivity of 0.5-1.0 Ωcm and thickness of 130-160 micrometers; use acid and alkali chemicals to remove organic contaminants and metallic impurities from the silicon wafer surface, forming a surface texture on the silicon wafer surface to increase the absorption of sunlight and reduce reflection;

[0079] S2 boron diffusion: BCl3 low-pressure diffusion is used to form a front PN junction with a diffusion temperature of 950-1050℃ and a sheet resistance of 150-250Ω to form a diffusion layer.

[0080] S3 BSG: Single-sided HF etching to remove backside BSG;

[0081] S4 Backside Etching: Alkaline solution etching is used to remove the PN junction formed by parasitic diffusion on the backside;

[0082] S5 PECVD SiOx / a-Si:H / SiOx: First, a tunneling oxide layer with a thickness of 1–3 nm is grown on the back side of a single-crystal silicon wafer using PECVD technology. Then, after the tunneling oxide layer is grown, a phosphorus-doped amorphous silicon film with a thickness of 120–150 nm is deposited on the surface of the tunneling oxide layer using PECVD technology. After annealing at 850℃, the doping concentration is 8E19–1E20 cm⁻¹. -3 Finally, a silicon oxide diffusion barrier layer with a thickness of 50–100 nm is grown on the back side of the silicon wafer using PECVD technology.

[0083] S6 LCO: The back metal area (back metal electrode) is grooved at the position of the silicon oxide diffusion barrier layer by laser film opening method. The laser wavelength for laser film opening is 355nm.

[0084] S7 phosphorus diffusion: POCl3 diffusion is used to crystallize amorphous silicon, while the trenches in the silicon oxide diffusion barrier layer are heavily doped with a doping concentration of 2E20~3E20cm⁻¹. -3 The amorphous silicon doping concentration in the ungrooved region is blocked by the silicon oxide barrier layer, maintaining a relatively low concentration of 8E19~1E20cm⁻¹. -3 This forms a doped polycrystalline silicon layer;

[0085] S8 PSG: Single-sided HF etching to remove the PSG on the front side of the polysilicon surface after diffusion;

[0086] S9 front etching: Alkaline solution etching is used to remove the polysilicon layer, and hydrofluoric acid cleaning is used to remove the BSG on the front and the PSG and silicon oxide barrier layer on the back.

[0087] S10 ALD: A dense AlOx film with a thickness of 3-5 nm is deposited on the front side of the substrate using ALD atomic layer deposition.

[0088] S11 Front-side PECVD: One or more stacked films of silicon nitride and silicon oxynitride are deposited on the front side of the diffusion layer by PECVD, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.1.

[0089] S12 Backside PECVD: One or more stacked films of silicon nitride and silicon oxynitride are deposited on the backside of the doped polycrystalline silicon layer by PECVD, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.1.

[0090] S13 Printing / Sintering / Photoinjection: Front side is printed with negative electrode Ag / Al paste, and back side is printed with electrode Ag paste; co-sintering forms good ohmic contact; photoinjection repairs defects in the cell body and surface.

[0091] A schematic diagram of the TOPCon battery structure prepared in Example 1 of this invention is shown below. Figure 1 As shown, it includes: a monocrystalline silicon wafer, a diffusion layer, a passivation layer, a front anti-reflection layer, and a front metal electrode sequentially disposed on the front side of the monocrystalline silicon wafer, and an inner expansion layer, a tunneling layer, a doped polycrystalline silicon layer, a back anti-reflection layer, and a back metal electrode sequentially disposed on the back side of the monocrystalline silicon wafer; the doped polycrystalline silicon layer includes a first doped polycrystalline silicon region and a second doped polycrystalline silicon region; the doping concentration of the first doped polycrystalline silicon region is higher than that of the second doped polycrystalline silicon region; the inner expansion layer includes a first inner expansion region and a second inner expansion region; the first inner expansion region corresponds to the position of the first doped polycrystalline silicon layer, and its junction depth is greater than that of the second inner expansion region; the thickness of the doped polycrystalline silicon layer is 120-150 nm, and the doping concentration of the first doped polycrystalline silicon region is 2E20-3E20 cm⁻¹. -3 The doping concentration in the second doped polysilicon region is 8E19~1E20cm⁻¹. -3 .

[0092] Example 2

[0093] The TOPCon battery was prepared according to the method of Example 1, the difference being that the phosphorus diffusion in S7 was as follows:

[0094] Amorphous silicon was crystallized using POCl3 diffusion, while the trenches in the silicon oxide diffusion barrier layer were heavily doped with a doping concentration of 3E20–4E20 cm⁻¹. -3 The amorphous silicon doping concentration in the ungrooved region is blocked by the silicon oxide barrier layer, maintaining a relatively low concentration of 8E19~1E20cm⁻¹. -3 This forms a doped polycrystalline silicon layer.

[0095] Comparative Example 1

[0096] The TOPCon cell was prepared according to the method of Example 1, the difference being that the doping concentration of the polycrystalline silicon layer was the same, and there was no distinction between the first doped polycrystalline silicon region and the second doped polycrystalline silicon region; its structural schematic diagram is shown below. Figure 3 As shown, compared with Example 1, the thickness of the single-concentration doped polycrystalline silicon layer is 120-130 nm, and the doping concentration is 2-3E20 cm⁻¹. -3 . Figure 3 1 is an N-type single-crystal silicon wafer; 2 is a diffusion layer; 3 is a passivation layer; 4 is a front anti-reflection layer; 5 is a front metal electrode; 6 is a tunneling layer; 7 is a doped polycrystalline silicon layer; 8 is an anti-reflection layer; and 9 is a back metal electrode.

[0097] Performance testing

[0098] IV performance tests were performed on the TOPCon batteries prepared in Examples 1, 2, and Comparative Example 1 of this invention. The test results are as follows:

[0099] Conversion efficiency Eta (%) Open circuit voltage Voc (mV) Short circuit current Jsc(mA / cm 2 )]]> Fill factor FF (%) Example 1 25.10 721 41.5 83.9 Example 2 25.16 720.8 41.4 84.3 Comparative Example 1 24.88 719 41.3 83.8

[0100] Comparing the TOPCon cells prepared in the examples and the comparative examples, it can be seen that the examples employed PECVD deposition of a tunneling oxide layer, a lightly doped amorphous silicon layer, and a silicon oxide diffusion barrier layer. Laser ablation was performed on the silicon oxide diffusion barrier layer in the metal region, and the lightly doped amorphous silicon layer was crystallized using POCL3 diffusion. During this process, phosphorus atoms diffused inward to form an inner expansion layer. Simultaneously, the ablation region was heavily doped, forming a first doped polycrystalline silicon region at the corresponding position of the metal region (back metal electrode) and a second doped polycrystalline silicon region at the corresponding position of the non-metal region on the back side of the N-type single-crystal silicon wafer. The doping concentration of the first doped polycrystalline silicon region is higher than that of the second doped polycrystalline silicon region, allowing the metal region to achieve lower contact resistance, while the non-metal region has a lower doping concentration, reducing free carrier absorption and thus achieving a higher short-circuit current density. The inner expansion layer includes a first inner expansion region at the corresponding position of the first doped polycrystalline silicon layer and a second inner expansion region at the corresponding position of the second doped polycrystalline silicon region in the back non-metal region. The junction depth of the first inner expansion region is greater than that of the second inner expansion region, reducing the recombination current density in the metal region and improving the cell's Voc and FF. The preparation method of this invention is simple and easy to implement.

[0101] While the invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not intended to limit the invention. It will be readily understood by those skilled in the art that various changes may be made to suit particular circumstances, materials, compositions, substances, methods, or processes to the objectives, spirit, and scope of this application without departing from the true spirit and scope of the invention as defined by the appended claims. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this application.

Claims

1. A method for preparing a TOPCon battery, comprising: After preparing a doped amorphous silicon thin film on the surface of the tunneling layer, it is annealed. A silicon oxide layer is prepared on the lower surface of the annealed film as a diffusion barrier layer; Grooves are cut into the surface of the diffusion barrier layer; POCl3 diffusion is performed, and heavy doping is carried out at the groove. A first doped polysilicon region with a high doping concentration is formed at the groove location, and then a first inner expansion region is formed at the location of the inner expansion layer corresponding to the first doped polysilicon region. A second doped polysilicon region with a low doping concentration was formed at the ungrouted location, and then a second inner expansion region was formed at the location of the inner expansion layer corresponding to the second doped polysilicon region. The knot depth of the first inner expansion region is greater than the knot depth of the second inner expansion region.

2. The method for preparing a TOPCon battery according to claim 1, characterized in that, The doping concentration of the first doped polysilicon region is selected from 2E20~1E21cm. -3 .

3. The method for preparing a TOPCon battery according to claim 1, characterized in that, The doping concentration of the second doped polysilicon region is selected from 5E19~2E20cm. -3 .

4. The method for preparing a TOPCon battery according to claim 1, characterized in that, The first polycrystalline doped silicon region and the first inner expansion region are located at the positions corresponding to the metal electrodes in the TOPCon cell.

5. The preparation method according to claim 1, characterized in that, The doped amorphous silicon thin film is selected from phosphorus-doped amorphous silicon thin films; The phosphorus-doped amorphous silicon thin film was prepared by PECVD. The thickness of the phosphorus-doped amorphous silicon thin film is selected from 100~200nm.

6. The preparation method according to claim 1, characterized in that, The thickness of the diffusion barrier layer is selected from 50~100nm.

7. The preparation method according to claim 1, characterized in that, The grooving is performed on the back metal electrode of the monocrystalline silicon wafer at the position corresponding to the diffusion barrier layer.

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