A charge-discharge control circuit with adjustable gear

Abstract

A charge-discharge control circuit with adjustable gear, characterized in that: the circuit comprises a charge-discharge unit, a mirror unit and an error comparison unit; wherein the charge-discharge unit is connected with the CO and DO pins of the charge-discharge control chip respectively, and is used for outputting an actual charge-discharge voltage based on the control of the charge-discharge control chip; the mirror unit is connected with the charge-discharge unit and a reference current respectively, and is used for generating a reference charge-discharge voltage based on the reference current and the internal resistance of the mirror unit; the error comparison unit compares the actual charge-discharge voltage with the reference charge-discharge voltage to obtain a detection result. The method is simple, the circuit structure is easy to adjust, the influence of the offset voltage and the direct current working voltage is eliminated, the accurate output of the detection result is realized, and the system error is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a charge / discharge control circuit with adjustable speed settings. Background Technology

[0002] Currently, current sensing circuits are typically used to detect the operating current of integrated circuits. However, traditional current sensing circuits usually first convert the current to be detected into a detection voltage, then sample the detection voltage, convert the sampled voltage back into a sampling current, and finally perform a current-to-voltage conversion on the sampled current to achieve overcurrent comparison and determination. The problem with this method is that during the multiple voltage / current or current / voltage conversions of the detected current, a large amount of conversion error is introduced due to current mismatch, which significantly limits the accuracy of overcurrent determination.

[0003] On the other hand, the main needs for current detection in existing technologies are concentrated in the power supply battery pack and the corresponding circuits containing the charge / discharge control chips for the battery pack. Therefore, the need for detecting charging current and discharging current usually exists simultaneously. However, in traditional current detection circuits, due to the different DC operating points of the circuit during charging and discharging, two comparators are used to separately compare and determine the overcurrent of the charging and discharging currents. Because the comparators contain high-power operational amplifier devices, the power consumption of the current detection circuit is relatively high, and it is difficult to reduce using traditional methods.

[0004] In addition, in the existing technology, the charging voltage and discharging voltage in the charging and discharging control circuit are usually fixed, making it cumbersome to adjust the charging voltage and discharging voltage, and there are very few charging and discharging control circuits with multiple adjustable levels.

[0005] Therefore, there is an urgent need for a new charging and discharging control circuit with adjustable speed settings. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide an adjustable charge / discharge control circuit. This circuit uses a reference current and the impedance of a sampling tube as comparison benchmarks to compare the actual charge / discharge voltage output by the charge / discharge tube. Simultaneously, a dynamic disappearing modulation structure is employed to eliminate comparator offset errors. A polling setting is used to multiplex the comparator employed for charge / discharge current detection, and the deviation between the actual charge / discharge voltage and the reference charge / discharge voltage during the charge / discharge process is output.

[0007] The present invention adopts the following technical solution.

[0008] An adjustable charging and discharging control circuit includes a charging and discharging unit, a mirror unit, and an error comparison unit. The charging and discharging unit is connected to the CO and DO pins of a charging and discharging control chip and outputs an actual charging and discharging voltage based on the control of the charging and discharging control chip. The mirror unit is connected to the charging and discharging unit and a reference current and generates a reference charging and discharging voltage based on the reference current and the internal resistance of the mirror unit. The error comparison unit compares the actual charging and discharging voltage with the reference charging and discharging voltage to obtain a detection result.

[0009] Preferably, the charging / discharging unit includes a charging transistor Mn1, a discharging transistor Mn2, a charging control transistor Mn3, and a discharging control transistor Mn4; wherein, the gate of the charging transistor Mn1 is connected to the CO pin of the charging / discharging control chip, and the source is connected to the negative terminal pckn of the battery pack where the charging / discharging control chip is located; the gate of the discharging transistor Mn2 is connected to the DO pin of the charging / discharging control chip, and the source is connected to the negative terminal batn of the battery pack where the charging / discharging control chip is located; the drains of the charging transistor Mn1 and the discharging transistor Mn2 are interconnected and output a charging voltage V_chg through the charging control transistor Mn3, and output a discharging voltage V_dis through the discharging control transistor Mn4.

[0010] Preferably, the charging control transistor Mn3 receives the charging overcurrent detection control signal Det_oc_d at its gate, and its source is connected to the mirror unit. It is also used as the output terminal of the reference charging voltage V_chg0 and the actual charging voltage V_chg1 to input V_chg into the error comparison unit. The discharging control transistor Mn4 receives the discharging overcurrent detection control signal Det_od_d at its gate, and its source is connected to the mirror unit. It is also used as the output terminal of the reference discharging voltage V_dis0 and the actual discharging voltage V_dis1 to input V_dis into the error comparison unit.

[0011] Preferably, the mirror unit includes a charging mirror unit and a discharging mirror unit; wherein the charging mirror unit and the discharging mirror unit each include a plurality of charging mirror sub-units and a plurality of discharging mirror sub-units.

[0012] Preferably, the charging mirror subunit includes a voltage-bearing transistor Mn5, a sampling transistor Mn6X, a trimming transistor Mn7, and a reference switch transistor Mn8 connected in sequence using a common-source, common-gate configuration. The source of voltage-bearing transistor Mn5 and the drain of reference switch transistor Mn8 serve as the two ends of the charging mirror subunit. The source of Mn5 is connected to the negative terminal pckn of the battery pack, the drain of Mn8 is connected to the reference current I_ref, and the source of Mn8 is connected to the gate of Mn7 and the source of Mn3. The gate of voltage-bearing transistor Mn5 is connected to the CO pin of the charge / discharge control chip. The gate of sampling transistor Mn6X is connected to the high-level drive voltage Drv_on. The gate of trimming transistor Mn7 is connected to the trimming control voltage Trim. The gate of reference switch transistor Mn8 is connected to the reference current detection control signal Drvb_oc.

[0013] Preferably, when the charging overcurrent detection control signal Det_oc is high, the reference current detection control signal Drvb_oc is low, the charging control transistor Mn3 is turned on, the reference switch transistor Mn8 is turned off, and the mirror unit generates the actual charging voltage V_chg1=I_co*R_on_Mn1; where I_co is the charging current of the lithium-ion battery pack, and R_on_Mn1 is the on-resistance of the charging transistor Mn1.

[0014] Preferably, when the charging overcurrent detection control signal Det_oc is low, the reference current detection control signal Drvb_oc is high, the charging detection control transistor Mn3 is turned off, the reference switch transistor Mn8 is turned on, and the mirror unit generates a reference charging voltage of V_chg0 = I_ref * R_on_Mn6X; where R_on_Mn6X is the on-resistance of the sampling transistor Mn6X.

[0015] Preferably, the discharge mirror subunit includes a sampling transistor Mn11, a trimming transistor Mn10, and a reference switch Mn9 connected in a common-source, common-gate configuration. The source of the sampling transistor Mn11 is connected to the negative terminal batn of the battery in the battery pack; the drain of Mn9 is connected to the reference current I_ref; and the source of Mn9 is connected to the gate of Mn10 and the source of Mn4. The gate of the sampling transistor Mn11 is connected to the high-level driving voltage Drv_on; the gate of the trimming transistor Mn10 is connected to the trimming control voltage Trim; and the gate of the reference switch Mn9 is connected to the reference current detection control signal Drvb_od.

[0016] Preferably, when the discharge overcurrent detection control signal Det_od is high, the reference current detection control signal Drvb_oc is low, the discharge detection control transistor Mn4 is turned on, the reference switch transistor Mn9 is turned off, and the mirror unit generates the actual discharge voltage V_dis1 = I_do * R_on_Mn2; where I_do is the discharge current of the lithium-ion battery pack, and R_on_Mn2 is the on-resistance of the discharge transistor Mn2.

[0017] Preferably, when the discharge overcurrent detection control signal Det_od is low, the reference current detection control signal Drvb_oc is high, the discharge detection control transistor Mn4 is turned off, the reference switch transistor Mn9 is turned on, and the mirror unit generates a reference discharge voltage of V_dis0 = I_ref * R_on_Mn11; where R_on_Mn11 is the on-resistance of the sampling transistor Mn11.

[0018] Preferably, the error comparison unit includes a first switch S_det_oc, a second switch S_det_od, a third switch S_phsa, a fourth switch S_phsb, a switched capacitor Coff, an operational amplifier, and a NAND gate; wherein, one end of the first switch S_det_oc is connected to the charging voltage V_chg, and the other end is connected to one end of the third switch S_phsa and the fourth switch S_phsb respectively; one end of the second switch S_det_od is connected to the discharging voltage V_dis, and the other end is connected to one end of the third switch S_phsa, the fourth switch S_phsb respectively. One end of the fourth switch S_phsb is connected; the other ends of the third switch S_phsa and the fourth switch S_phsb are both connected to one end of the switched capacitor Coff, and the other end of the switched capacitor Coff is connected to the negative input terminal of the operational amplifier; the positive input terminal of the operational amplifier is connected to the DC operating voltage V_ref_dc of the operational amplifier, and the fifth switch is connected in the negative feedback branch with an operating voltage of V_phsb. The output terminal is connected to the first input terminal of the NAND gate; the voltage at the second input terminal of the NAND gate is V_phsa, and the output terminal V_out outputs the detection result.

[0019] Preferably, when the charging overcurrent detection control signal Det_oc is high and the discharging overcurrent detection control signal Det_od is low, the detection result of the error comparison unit includes information about the difference between the reference charging voltage V_chg1 and V_chg0; when the charging overcurrent detection control signal Det_oc is low and the discharging overcurrent detection control signal Det_od is high, the detection result of the error comparison unit includes information about the difference between the reference discharging voltage V_dis1 and V_dis0.

[0020] Preferably, the detection result of the error comparison unit is independent of the op-amp's DC operating voltage V_ref_dc and the op-amp's offset voltage Vos.

[0021] Preferably, the control signals for the third switch S_phsa and the fourth switch S_phsb are non-overlapping clock signals phsa and phsb; the gate control signals Det_oc_d and Det_od_d of the charging control transistor Mn3 and the discharging control transistor Mn4 are obtained based on the AND operation of the clock detection signal Ck_det and the charging overcurrent detection control signal Det_oc, and the AND operation of the clock detection signal Ck_det and the discharging overcurrent detection control signal Det_od, respectively; and the high-level state of the charging overcurrent detection control signal Det_oc and the discharging overcurrent detection control signal Det_od continues for the entire cycle of the non-overlapping clock signals phsa and phsb.

[0022] Preferably, the ratio of the width-to-length ratio of the sampling tube Mn6X to the width-to-length ratio of the charging tube Mn1 in the charging mirror subunit is fixed; the ratio of the width-to-length ratio of the sampling tube Mn11 to the width-to-length ratio of the discharging tube Mn2 in the discharging mirror subunit is fixed.

[0023] Preferably, the number of charging mirror sub-units and the number of charging mirror sub-units in the mirror unit are equal, and are related to the number of charging voltage Vchg and discharging voltage Vdis levels in the circuit.

[0024] Preferably, the number of Mn6X in the multiple charging mirror sub-units is equal or in a set ratio, and the value of the charging voltage Vchg in the circuit at each level is determined according to the quantitative relationship of the multiple charging mirror sub-units Mn6X; the number of Mn11 in the multiple discharging mirror sub-units is equal or in a set ratio, and the value of the discharging voltage Vdis in the circuit at each level is determined according to the quantitative relationship of the multiple discharging mirror sub-units Mn11.

[0025] Preferably, the ratio X of the number of sampling tubes Mn6X in the charging mirror subunit to the number of sampling tubes Mn11 in the discharging mirror subunit is determined by the ratio of the reference charging voltage V_chg to the reference discharging voltage V_dis.

[0026] The beneficial effects of this invention are that, compared with the prior art, the adjustable charge / discharge control circuit of this invention can compare the actual charge / discharge voltage output by the charge / discharge tube with the reference current and the impedance of the sampling tube as a comparison benchmark. Simultaneously, it employs a dynamic disappearing modulation structure to eliminate comparator offset error, and uses polling to multiplex the comparator used for charge / discharge current detection, outputting the deviation between the actual charge / discharge voltage and the reference charge / discharge voltage during the charge / discharge process. This invention is simple in method, easy to adjust in circuit structure, eliminates the influence of offset voltage and DC operating voltage, achieves accurate output of detection results, and reduces system errors.

[0027] The beneficial effects of the present invention also include:

[0028] 1. The current detection circuit in this invention does not require multiple current / voltage conversions or voltage / current conversions. The method of this invention directly acquires the charging and discharging current of the control chip through the MOS transistor and compares it with the reference current multiple times. Only one current-to-voltage conversion is needed to obtain the detection result, which reduces the system error caused by multiple conversions and sampling processes and improves the detection accuracy.

[0029] 2. In this invention, the magnitude of the reference current, the mirror ratio between the sampling tube and the charging / discharging tube, and the number of mirror units can be reasonably set according to requirements, resulting in a large range of reasonable parameter values ​​and easy parameter setting. Furthermore, this invention can further adjust the output of the mirror circuit through the adjustment tube, allowing the reference charging voltage and reference discharging voltage to have multiple different levels with significant differences, expanding the circuit's application range without affecting the detection results at different levels. Overall, the circuit's detection accuracy is higher.

[0030] 3. In this invention, by reasonably setting the ratio of the sampling tube in the charging mirror unit to the sampling tube in the discharging mirror unit, a fixed proportional relationship can be achieved between the charging voltage and the discharging voltage. This method makes the circuit's operating state more controllable during the charging and discharging process, and enhances circuit safety. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the circuit structure of the charging / discharging unit, detection and control unit, and mirror unit in an adjustable charging / discharging control circuit of the present invention.

[0032] Figure 2 This is a schematic diagram of the circuit structure of the error comparison unit in an adjustable charging and discharging control circuit of the present invention.

[0033] Figure 3 This is a schematic diagram of the timing curve of the control signal in an adjustable charging and discharging control circuit of the present invention. Detailed Implementation

[0034] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0035] Figure 1 This is a schematic diagram of the circuit structure of the charging / discharging unit, detection and control unit, and mirror unit in an adjustable charging / discharging control circuit of the present invention. Figure 1As shown, an adjustable charging and discharging control circuit includes a charging and discharging unit, a mirror unit, and an error comparison unit. The charging and discharging unit is connected to the CO and DO pins of the charging and discharging control chip, and is used to output the actual charging and discharging voltage based on the control of the charging and discharging control chip. The mirror unit is connected to the charging and discharging unit and a reference current, and is used to generate a reference charging and discharging voltage based on the reference current and the internal resistance of the mirror unit. The error comparison unit compares the actual charging and discharging voltage with the reference charging and discharging voltage to obtain the detection result.

[0036] It is understood that this invention differs from the approach commonly used in traditional current detection circuits. In this invention, a charging / discharging unit is used to obtain the actual charging / discharging voltage of the control chip, while a mirror unit is used to obtain a reference charging / discharging voltage. The circuit can simultaneously compare the actual charging / discharging voltage and the reference charging / discharging voltage through an error comparison unit, thereby obtaining the difference between the actual charging / discharging voltage and the reference charging / discharging voltage, and adjusting the actual charging / discharging voltage accordingly.

[0037] Specifically, the actual charge / discharge voltage in this invention can be calculated based on the charge / discharge current and the on-resistance of the charge / discharge main tube. Once the circuit is determined, the on-resistance of the charge / discharge main tube is also determined accordingly. On the other hand, the reference charge / discharge voltage in this invention is generated based on a pre-set reference current and the on-resistance of the sampling tube in the mirror unit. Therefore, once the circuit is determined, the on-resistance of the sampling tube in the mirror unit remains constant under a certain adjustment state. Thus, after obtaining the difference between the actual charge / discharge voltage and the reference charge / discharge voltage, the circuit can obtain the difference between the actual charge / discharge current and the reference charge / discharge voltage / current.

[0038] It should be noted that, in this invention, the ratio between the on-resistance of the charging / discharging main tube and the on-resistance of the sampling tube in the mirror unit can be preset according to actual needs. For example, this can be achieved by setting parameters such as the size and number of the charging / discharging main tube and the sampling tube.

[0039] Preferably, the charging / discharging unit includes a charging transistor Mn1, a discharging transistor Mn2, a charging control transistor Mn3, and a discharging control transistor Mn4; wherein, the gate of the charging transistor Mn1 is connected to the CO pin of the charging / discharging control chip, and the source is connected to the negative terminal pckn of the battery pack where the charging / discharging control chip is located; the gate of the discharging transistor Mn2 is connected to the DO pin of the charging / discharging control chip, and the drain and source are connected to the negative terminal batn of the battery pack where the charging / discharging control chip is located; the drains of the charging transistor Mn1 and the discharging transistor Mn2 are interconnected and output a charging voltage V_chg through the charging control transistor Mn3, and output a discharging voltage V_dis through the discharging control transistor Mn4.

[0040] It is understood that in this invention, the charging and discharging unit includes a charging tube Mn1 and a discharging tube Mn2. These two tubes can be connected to the corresponding pins of the control chip of the port device of the battery pack in the control circuit. Generally speaking, the pins of the control chip should include a CO pin and a DO pin, where the CO pin is the charging output pin and the DO pin is the discharging output pin.

[0041] When the battery pack is charged via the circuit of this invention, that is, when the charger charges the positive and negative terminals of the internal battery through the positive and negative ports of the battery pack, CO is at a high level, turning on Mn1 and Mn3, thereby connecting the source and drain of Mn3 and the source and drain of Mn1. The charging current flows from the V_chg terminal to the pckn port, giving the circuit a charging voltage V_chg. When the battery discharges into the battery pack, DO is at a high level, turning on Mn2 and Mn4, thereby connecting the source and drain of Mn2 and the source and drain of Mn4. The discharging current flows from V_dis to the batn terminal, generating a discharging voltage V_dis.

[0042] Preferably, the charging control transistor Mn3 receives the charging overcurrent detection control signal Det_oc at its gate, its source is connected to the mirror unit, and serves as the output terminal of the reference charging voltage V_chg0 and the actual charging voltage V_chg1, inputting V_chg into the error comparison unit; the discharging control transistor Mn4 receives the discharging overcurrent detection control signal Det_od at its gate, its source is connected to the mirror unit, and serves as the output terminal of the reference discharging voltage V_dis0 and the actual discharging voltage V_dis1, inputting V_dis into the error comparison unit.

[0043] It is understood that the two MOS transistors Mn3 and Mn4 in this invention can output the actual charge and discharge voltage generated from the charge and discharge unit to the error comparison unit when they are in the on state. If the two transistors are in the off state, they can output the reference charge and discharge voltage to the error comparison unit according to the corresponding parameters of the mirror unit and the value of the reference current.

[0044] Preferably, the mirror unit includes a charging mirror unit and a discharging mirror unit; wherein the charging mirror unit and the discharging mirror unit each include a plurality of charging mirror sub-units and a plurality of discharging mirror sub-units.

[0045] It is understood that in this invention, the number of charging mirror sub-units and discharging mirror sub-units is predetermined. Typically, the reference current Iref is generated by a bias current source, and its magnitude remains constant. With the reference current Iref constant, when different numbers of charging and discharging mirror sub-units are connected to the circuit, the current magnitude in each mirror sub-unit changes, thus changing the value of the reference charging voltage V_chg0 when the pre-designed on-resistance of Mn6X remains constant. Similarly, when the on-resistance of Mn11 remains constant, the value of the reference discharging voltage V_dis0 also changes. When the reference charging and discharging voltages change, according to the logic of this invention, the actual charging and discharging voltages can be adjusted to approach the reference charging and discharging voltages. This achieves adjustment of the actual charging and discharging voltage levels when different numbers of charging and discharging mirror sub-units are connected to the circuit.

[0046] It should be noted that the number of charging mirror sub-units and the number of discharging mirror sub-units connected in this invention are based on the trimming signal Trim. <n:0>This is achieved. In one embodiment of the present invention, the number of adjustment signals can be 1, 2, or 6, that is, the number of mirror sub-units can be 2, 3, or 7, but the technical solution of the present invention does not limit the range of values ​​for n.

[0047] However, it's conceivable that the more mirror sub-units there are, the more charging and discharging voltage levels there will be. When the number of mirror sub-units is n, the number of voltage levels can range from n to 2. n -1.

[0048] Additionally, it should be noted that in this invention, Mn6X and Mn11 do not only include... Figure 1 A MOSFET in one mirror cell represents the corresponding MOSFETs in multiple mirror cells. For example, Mn6X includes not only... Figure 1 MN6X in the text also includes Figure 1 MN6_1X, MN6_2X, etc. And Mn11 includes not only... Figure 1 MN11 in the text also includes Figure 1 MN11_1 and MN11_2 in the example. The actual width-to-length ratio of the MOSFETs in multiple Mn6X transistors can be equal, or they can be increased or decreased sequentially according to a set ratio, so that the adjusted voltage meets the requirements of different voltage levels.

[0049] Preferably, the charging mirror subunit includes a voltage-bearing transistor Mn5, a sampling transistor Mn6X, a trimming transistor Mn7, and a reference switch transistor Mn8 connected in a common-source, common-gate configuration. The source of voltage-bearing transistor Mn5 and the drain of reference switch transistor Mn8 serve as the two ends of the charging mirror subunit. The source of Mn5 is connected to the negative terminal pckn of the battery pack, the drain of Mn8 is connected to the reference current I_ref, and the source of Mn8 is connected to the gate of Mn7 and the source of Mn3. The gate of voltage-bearing transistor Mn5 is connected to the CO pin of the charge / discharge control chip. The gate of sampling transistor Mn6X is connected to the high-level drive voltage Drv_on. The gate of trimming transistor Mn7 is connected to the trimming control voltage Trim. The gate of reference switch transistor Mn8 is connected to the reference current detection control signal Drvb_oc.

[0050] It is understood that the main structure of the mirror unit in this invention is a series of MOSFETs. The gate control signals of different MOSFETs are different, resulting in different functions of different MOSFETs during the conduction of the mirror unit. Specifically, since the control terminal signals of Mn5 and the main charging transistor Mn1 are exactly the same, it can be used to withstand voltage at the moment the charging transistor Mn1 is turned on, to prevent excessive output voltage from damaging the subsequent circuit. Secondly, Mn6X, as a sampling transistor, needs to have its parameters designed in a fixed ratio with the main charging transistor, so that the ratio of their on-resistance values ​​is relatively fixed. Since the on-resistance of Mn6X is relatively large, the on-resistance of other transistors, such as Mn5, Mn7, and Mn8, can be ignored when this mirror branch is turned on. Thirdly, Mn7, as a trimming transistor, has its gate trimming signal generated by the trimming logic of the trimming circuit (not shown in this invention). As mentioned above, after trimming, the circuit can adjust the charging voltage level. Finally, Mn8 acts as a switch for the mirror branch. When it is turned on, it causes a portion of the reference charge / discharge current Iref to flow into the mirror branch. When it is turned off, it causes V_chg to take the value of the actual charge / discharge current.

[0051] Preferably, when the charging overcurrent detection control signal Det_oc is high, the reference current detection control signal Drvb_oc is low, the charging control transistor Mn3 is turned on, the reference switch transistor Mn8 is turned off, and the mirror unit generates the actual charging voltage V_chg1=I_co*R_on_Mn1; where I_co is the charging current of the lithium-ion battery pack, and R_on_Mn1 is the on-resistance of the charging transistor Mn1.

[0052] It is understood that when the charging overcurrent detection control signal turns on the Mn3 transistor in this invention, the reference current detection control signal can be turned off by timing control. At this time, as mentioned above, the actual charging voltage will be output through the V_chg port.

[0053] Preferably, when the charging overcurrent detection control signal Det_oc is low, the reference current detection control signal Drvb_oc is high, the charging detection control transistor Mn3 is turned off, the reference switch transistor Mn8 is turned on, and the mirror unit generates a reference charging voltage of V_chg0 = I_ref * R_on_Mn6X; where R_on_Mn6X is the on-resistance of the sampling transistor Mn6X.

[0054] It is understood that when the charging overcurrent detection control signal in this invention turns off the Mn3 transistor, the reference current detection control signal can be turned on by timing control. At this time, as mentioned above, the reference charging voltage is generated by Iref through the mirror branch, and the voltage divider between Mn7 and Mn8 is output through the V_chg port.

[0055] Preferably, the discharge mirror subunit includes a sampling transistor Mn11, a trimming transistor Mn10, and a reference switch Mn9 connected in a common-source, common-gate configuration. The sampling transistor Mn11 is connected to the negative terminal batn of the battery in the battery pack; the drain of Mn9 is connected to the reference current I_ref; and the source of Mn9 is connected to the gate of Mn10 and the source of Mn4. The gate of the sampling transistor Mn11 is connected to the high-level driving voltage Drv_on; the gate of the trimming transistor Mn10 is connected to the trimming control voltage Trim; and the gate of the reference switch Mn9 is connected to the reference current detection control signal Drvb_od.

[0056] It is understood that the structure of the discharge mirror subunit and the charging mirror subunit in this invention is similar. The only difference between the discharge mirror subunit and the charging mirror subunit is that the discharge mirror subunit receives discharge current. Due to the function of the main circuit, this discharge current will not overshoot at the moment the discharge tube is turned on. Therefore, there is no need to use a pressure-bearing tube in the discharge mirror subunit in this invention.

[0057] In addition, the sampling tube Mn11, trimming tube Mn10, and reference switch tube Mn9 used in the discharge mirror subunit have similar functions and roles to the corresponding tubes in the charging mirror subunit.

[0058] Preferably, when the discharge overcurrent detection control signal Det_od is high, the reference current detection control signal Drvb_oc is low, the discharge detection control transistor Mn4 is turned on, the reference switch transistor Mn9 is turned off, and the mirror unit generates the actual discharge voltage V_dis1 = I_do * R_on_Mn2; where I_do is the discharge current of the lithium-ion battery pack, and R_on_Mn2 is the on-resistance of the discharge transistor Mn2.

[0059] It is understood that when the discharge detection control transistor Mn4 is turned on and the reference switch transistor Mn9 is turned off in this invention, the output of the circuit V_dis port should be the actual discharge voltage generated by the Mn2 transistor.

[0060] Preferably, when the discharge overcurrent detection control signal Det_od is low, the reference current detection control signal Drvb_oc is high, the discharge detection control transistor Mn4 is turned off, the reference switch transistor Mn9 is turned on, and the mirror unit generates a reference discharge voltage of V_dis0 = I_ref * R_on_Mn11; where R_on_Mn11 is the on-resistance of the sampling transistor Mn11.

[0061] It is understood that when the discharge detection control transistor Mn4 is turned off and the reference switch transistor Mn9 is turned on in this invention, the output of the V_dis port of the circuit should be the reference discharge voltage generated by the mirror unit.

[0062] Preferably, the error comparison unit includes a first switch S_det_oc, a second switch S_det_od, a third switch S_phsa, a fourth switch S_phsb, a switched capacitor Coff, an operational amplifier, and a NAND gate; wherein, one end of the first switch S_det_oc is connected to the charging voltage V_chg, and the other end is connected to one end of the third switch S_phsa and the fourth switch S_phsb respectively; one end of the second switch S_det_od is connected to the discharging voltage V_dis, and the other end is connected to one end of the third switch S_phsa and the fourth switch S_phsb respectively. One end of the four switches S_phsb is connected; the other ends of the third switch S_phsa and the fourth switch S_phsb are both connected to one end of the switched capacitor Coff, and the other end of the switched capacitor Coff is connected to the negative input terminal of the operational amplifier; the positive input terminal of the operational amplifier is connected to the DC operating voltage V_ref_dc of the operational amplifier, and the fifth switch is connected in the negative feedback branch with an operating voltage of V_phsb. The output terminal is connected to the first input terminal of the NAND gate; the voltage at the second input terminal of the NAND gate is V_phsa, and the output terminal V_out outputs the detection result.

[0063] Figure 2 This is a schematic diagram of the error comparison unit in the current detection circuit of a charge / discharge control chip according to the present invention. Figure 2 As shown, the error comparison unit in this invention includes a comparator and a NAND gate. Additionally, it includes a corresponding switching structure similar to a switched-capacitor amplifier, enabling the error comparison unit to dynamically eliminate offset and reduce system error. Simultaneously, it can obtain the comparison detection results of charging overcurrent and discharging overcurrent through timing control in a polling manner.

[0064] Specifically Figure 2 The positions of the first to fifth switches are recorded with the control signals for each of them. For example, for the first switch S_det_oc, as its name suggests, when the Det_oc signal is high, the switch is in the closed state, and when the Det_oc signal is low, the switch is in the open state.

[0065] For a comparator, it can be derived from... Figure 2 As shown, when the phsb signal is high and the fifth switch is closed, the op-amp is in a negative feedback connection state. In this state, the op-amp acts as a voltage follower, and its output voltage can be V_ref_dc + Vos, which is the difference between the voltage at the non-inverting input of the op-amp and the offset voltage. At this time, one side of the switched capacitor Coff should receive the actual or reference charging / discharging voltage output from the mirror unit or the detection and control unit, while the other side of the switched capacitor Coff directly receives the output voltage through the negative feedback connection. Therefore, when the phsb signal is high, the switched capacitor Coff is charging.

[0066] When the phsb signal switches to a low level, the fifth switch is turned on, and the op-amp is no longer in the negative feedback connection state. At this time, the op-amp acts as a comparator, taking the DC operating voltage V_ref_dc and the actual or reference charging and discharging voltage output from the mirror unit or detection and control unit as the input voltages of the positive and negative input terminals of the comparator, respectively, to obtain the comparison result.

[0067] It should be noted that since the amount of internal charge in the switched capacitor Coff does not change instantaneously, the voltage drop across the two plates of the capacitor is synchronous. Specifically, when the comparator detects a sudden voltage amplitude shift in the input from one end of the switched capacitor Coff—that is, in V_chg or V_dis from the mirror unit or detection control unit—for example, a sudden change from V_chg0 to V_chg1 or vice versa, it can be predicted that the voltage at the other end of the switched capacitor Coff will also undergo a similar shift, for example, a sudden change from V_chg0 to V_chg1. It is important to note that before the voltage shift, the initial voltage value at the other end of the switched capacitor is V_ref_dc + Vos; therefore, after the shift, the voltage value at the other end of the switched capacitor Coff will shift accordingly to (V_chg1 - V_chg0) + (V_ref_dc + Vos). When the op-amp is in comparator mode, the output voltage of the op-amp is (V_chg1-V_chg0)+(V_ref_dc+Vos)-V_ref_dc-Vos=V_chg1-V_chg0.

[0068] Therefore, in this invention, the detection result output by the error comparator is not affected by the DC operating point voltage V_ref_dc and the offset voltage Vos. Thus, the detection result of the error comparator is independent of the op-amp's DC operating voltage V_ref_dc and offset voltage Vos.

[0069] Figure 3 This is a schematic diagram of the timing curve of the control signal in the current detection circuit of a charge / discharge control chip according to the present invention. Figure 3 As shown, preferably, when the charging overcurrent detection control signal Det_oc is high and the discharging overcurrent detection control signal Det_od is low, the detection result of the error comparison unit includes information about the difference between the reference charging voltage V_chg1 and V_chg0; when the charging overcurrent detection control signal Det_oc is low and the discharging overcurrent detection control signal Det_od is high, the detection result of the error comparison unit includes information about the difference between the reference discharging voltage V_dis1 and V_dis0.

[0070] It is easy to understand that in this invention, when the output of the overcurrent detection control signal for charging or discharging changes accordingly, the comparator will receive V_chg and V_dis accordingly, thereby realizing the detection of the charging or discharging current.

[0071] Preferably, the control signals for the third switch S_phsa and the fourth switch S_phsb are non-overlapping clock signals phsa and phsb; the gate control signals Det_oc_d and Det_od_d of the charging control transistor Mn3 and the discharging control transistor Mn4 are obtained based on the AND operation of the clock detection signal Ck_det and the charging overcurrent detection control signal Det_oc, and the AND operation of the clock detection signal Ck_det and the discharging overcurrent detection control signal Det_od, respectively; and the high-level state of the charging overcurrent detection control signal Det_oc and the discharging overcurrent detection control signal Det_od continues for the entire cycle of the non-overlapping clock signals phsa and phsb.

[0072] It should be noted that the charging overcurrent detection control signal Det_oc and the discharging overcurrent detection control signal Det_od in this invention are used to control the error comparison unit to select one of the two signals V_chg and V_dis. When one of the two signals is output, for example, when V_chg is output, the value of V_chg may have two possibilities. The first is that when Det_oc_d is at a high level, Mn3 is on, and Mn8 is off, the output is V_chg1. The other is that when Det_oc_d is at a low level, Mn3 is off, and Mn8 is on, the output is V_chg1. That is to say, within half a cycle of the charging overcurrent detection control signal Det_oc running at a high level, two high-low level switching of the Det_oc_d signal will occur simultaneously throughout the entire cycle. The control signal Drvb_oc for Mn8 will also undergo a similar switching, but its switching method is completely opposite to that of Det_oc_d.

[0073] Similarly, in order to achieve the cyclic switching of the comparator between two different operating states within one Det_oc signal cycle, the phsa and phsb signals also need to be set to half the period of the Det_oc signal. In addition, to prevent errors during the switching process, the two complementary signals phsa and phsb should be in a non-overlapping state.

[0074] Furthermore, to overcome the op-amp's delay, the Det_oc_d and Det_o_d signals can be obtained by performing AND operations on the clock detection signal Ck_det and the charging overcurrent detection control signal Det_oc, and by performing AND operations on the clock detection signal Ck_det and the square current overcurrent detection control signal Det_od, respectively. Once these two signals are obtained, the Mn3 and Mn4 transistors controlled by them will be essentially synchronized with the op-amp's state switching signals phsa and phsb, thus controlling the output Vout.

[0075] Preferably, the ratio of the width-to-length ratio of the sampling tube Mn6X to the width-to-length ratio of the charging tube Mn1 in the charging mirror subunit is fixed; the ratio of the width-to-length ratio of the sampling tube Mn11 to the width-to-length ratio of the discharging tube Mn2 in the discharging mirror subunit is fixed.

[0076] Assuming a fixed ratio K between the sampling transistor Mn6X and the charging transistor Mn1, then when the actual charging current flows through the sampling transistor, the current flowing through Mn6X is 1 / K of Mn1. This is because the reference charging voltage V_chg0=I_ref*R_on_Mn6X and the actual charging voltage V_chg1=I_co*R_on_Mn1 are equal in magnitude.

[0077] Similarly, the width-to-length ratio of Mn11 and the width-to-length ratio of discharge tube Mn2 also conform to this relationship.

[0078] Preferably, the number of charging mirror sub-units and the number of charging mirror sub-units in the mirror unit are equal, and are related to the number of charging voltage V_chg and discharging voltage V_dis levels in the circuit.

[0079] In this invention, the number of mirror sub-units as described above, and the aspect ratio of Mn6X or Mn11 in each mirror sub-unit, can make Trim...<n:0> When the signal has different values, that is, when the circuit is in different adjustment modes, the reference values ​​of the charging voltage and the discharging voltage are at different levels. Therefore, the number of mirror sub-units can be determined together based on the range of levels and the precision of level adjustment.

[0080] Preferably, the number of Mn6X in the multiple charging mirror sub-units is equal or in a set ratio, and the value of the charging voltage V_chg in the circuit at each level is determined according to the quantitative relationship of the multiple charging mirror sub-units Mn6X; the number of Mn11 in the multiple discharging mirror sub-units is equal or in a set ratio, and the value of the discharging voltage V_dis in the circuit at each level is determined according to the quantitative relationship of the multiple discharging mirror sub-units Mn11.

[0081] According to the common adjustment methods in existing technology, the on-resistance of Mn6X in multiple different mirror sub-units can be proportionally determined based on the number of Mn6X units, or in other words, the aspect ratio. Thus, in different on / off states of a sub-unit, when Mn3 is off and Iref remains constant, the value of V_chg will be different, corresponding to different design settings.

[0082] Preferably, the ratio X of the number of sampling tubes Mn6X in the charging mirror subunit to the number of sampling tubes Mn11 in the discharging mirror subunit is determined by the ratio of the reference charging voltage V_chg to the reference discharging voltage V_dis.

[0083] It is understood that the Iref provided to the charging mirror subunit and the discharging mirror subunit in this invention is equal, while V_chg and V_dis need to be preset according to different actual situations. Therefore, the value of X can be selected according to the design values ​​of both.

[0084] Additionally, after the number of mirror sub-units is determined after the present invention has been adjusted, there may be cases where V_chg and V_dis are at different levels. In this case, the value of X can also be adjusted again to ensure that the values ​​of V_chg and V_dis are consistent or maintain a fixed ratio.

[0085] The beneficial effects of this invention are that, compared with the prior art, the current detection circuit of the charge / discharge control chip in this invention can compare the charge / discharge voltage output by the charge / discharge tube with the reference current and the impedance of the sampling tube as a comparison benchmark. Simultaneously, it employs a dynamic vanishing modulation structure to eliminate comparator offset error, and uses polling to multiplex the comparator used for charge / discharge current detection, while simultaneously outputting the charge / discharge detection result. This invention is simple in method, easy to adjust in circuit structure, eliminates the influence of offset voltage and DC operating voltage, achieves accurate output of detection results, and reduces system error.

[0086] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A charging and discharging control circuit with adjustable speed settings, characterized in that: The circuit includes a charging / discharging unit, a mirror unit, and an error comparison unit; wherein... The charging and discharging unit is connected to the CO and DO pins of the charging and discharging control chip, respectively, and is used to output the actual charging and discharging voltage based on the control of the charging and discharging control chip. The mirror unit is connected to the charging / discharging unit and the reference current respectively, and is used to generate a reference charging / discharging voltage based on the reference current and the internal resistance of the mirror unit. The mirror unit includes a charging mirror unit and a discharging mirror unit; wherein... The charging mirror unit and the discharging mirror unit each include multiple charging mirror subunits and multiple discharging mirror subunits; The charging mirror subunit includes a pressure-bearing tube Mn5, a sampling tube Mn6X, a trimming tube Mn7, and a reference switching tube Mn8 connected sequentially in a common-source, common-gate configuration; wherein... The source of the pressure-bearing tube Mn5 and the drain of the reference switch tube Mn8 serve as the two ends of the charging mirror sub-unit. The source of Mn5 is connected to the negative terminal pckn of the battery pack, the drain of Mn8 is connected to the reference current I_ref, and the source of Mn8 is connected to the gate of Mn7 and the source of the charging control tube Mn3. The gate of the pressure-bearing tube Mn5 is connected to the CO pin of the charge / discharge control chip. The gate of the sampling tube Mn6X is connected to the high-level driving voltage Drv_on; The gate of the trimming transistor Mn7 is connected to the trimming control voltage Trim. The gate of the reference switch Mn8 is connected to the reference current detection control signal Drvb_oc; The number of Mn6X in the multiple charging mirror sub-units is equal or in a set ratio, and the value of the charging voltage Vchg in the circuit at each level is determined according to the quantitative relationship of the multiple charging mirror sub-units Mn6X. The error comparison unit compares the actual charge / discharge voltage with the reference charge / discharge voltage to obtain the detection result.

2. The adjustable charging / discharging control circuit according to claim 1, characterized in that: The charging and discharging unit includes a charging transistor Mn1, a discharging transistor Mn2, a charging control transistor Mn3, and a discharging control transistor Mn4; wherein... The gate of the charging tube Mn1 is connected to the CO pin of the charge / discharge control chip, and the source is connected to the negative terminal pckn of the battery pack where the charge / discharge control chip is located. The gate of the discharge tube Mn2 is connected to the DO pin of the charge / discharge control chip, and the source is connected to the negative terminal batn of the battery pack where the charge / discharge control chip is located. The drain of the charging tube Mn1 and the drain of the discharging tube Mn2 are connected to each other and the charging voltage V_chg is output through the charging control tube Mn3, and the discharging voltage V_dis is output through the discharging control tube Mn4.

3. The adjustable charging / discharging control circuit according to claim 2, characterized in that: The charging control transistor Mn3 receives the charging overcurrent detection control signal Det_oc_d at its gate, and its source is connected to the mirror unit. It serves as the output terminal for the reference charging voltage V_chg0 and the actual charging voltage V_chg1, and inputs V_chg into the error comparison unit. The discharge control transistor Mn4 receives the discharge overcurrent detection control signal Det_od_d at its gate, and its source is connected to the mirror unit. It serves as the output terminal for the reference discharge voltage V_dis0 and the actual discharge voltage V_dis1, inputting V_dis into the error comparison unit.

4. The adjustable charging / discharging control circuit according to claim 3, characterized in that: When the charging overcurrent detection control signal Det_oc_d is high, the reference current detection control signal Drvb_oc is low, the charging control transistor Mn3 is turned on, the reference switch transistor Mn8 is turned off, and the mirror unit generates the actual charging voltage V_chg1=I_co*R_on_Mn1. Where I_co is the charging current of the lithium-ion battery pack. R_on_Mn1 is the on-resistance of the charging tube Mn1.

5. The adjustable charging / discharging control circuit according to claim 3, characterized in that: When the charging overcurrent detection control signal Det_oc_d is low, the reference current detection control signal Drvb_oc is high, the charging control transistor Mn3 is turned off, the reference switch transistor Mn8 is turned on, and the mirror unit generates a reference charging voltage of V_chg0=I_ref*R_on_Mn6X; Wherein, R_on_Mn6X is the on-resistance of the sampling tube Mn6X.

6. The adjustable charging / discharging control circuit according to claim 3, characterized in that: The discharge mirror subunit includes a sampling transistor Mn11X, a trimming transistor Mn10, and a reference switch transistor Mn9 connected in a common-source, common-gate configuration; wherein... The source of the sampling tube Mn11X is connected to the negative terminal batn of the battery in the battery pack, the drain of Mn9 is connected to the reference current I_ref, and the source of Mn9 is connected to the drain of Mn10 and the source of Mn4. The gate of the sampling tube Mn11X is connected to the high-level driving voltage Drv_on; The gate of the trimming transistor Mn10 is connected to the trimming control voltage Trim. The gate of the reference switch Mn9 is connected to the reference current detection control signal Drvb_od.

7. The adjustable charging / discharging control circuit according to claim 6, characterized in that: When the discharge overcurrent detection control signal Det_od_d is high, the reference current detection control signal Drvb_od is low, the discharge control transistor Mn4 is turned on, the reference switch transistor Mn9 is turned off, and the mirror unit generates the actual discharge voltage V_dis1=I_do*R_on_Mn2. Where I_do is the discharge current of the lithium-ion battery pack. R_on_Mn2 is the on-resistance of the discharge tube Mn2.

8. The adjustable charging / discharging control circuit according to claim 6, characterized in that: When the discharge overcurrent detection control signal Det_od_d is low, the reference current detection control signal Drvb_od is high, the discharge control transistor Mn4 is turned off, the reference switch transistor Mn9 is turned on, and the mirror unit generates a reference discharge voltage of V_dis0 = I_ref * R_on_Mn11X; Wherein, R_on_Mn11X is the on-resistance of the sampling tube Mn11X.

9. A charge / discharge control circuit with adjustable gears according to any one of claims 3-8, characterized in that: The error comparison unit includes a first switch S_det_oc, a second switch S_det_od, a third switch S_phsa, a fourth switch S_phsb, a switched capacitor Coff, an operational amplifier, and a NAND gate; wherein, One end of the first switch S_det_oc is connected to the charging voltage V_chg, and the other end is connected to one end of the third switch S_phsa and the fourth switch S_phsb respectively. One end of the second switch S_det_od is connected to the discharging voltage V_dis, and the other end is connected to one end of the third switch S_phsa and the fourth switch S_phsb respectively. The other ends of the third switch S_phsa and the fourth switch S_phsb are both connected to one end of the switching capacitor Coff, and the other end of the switching capacitor Coff is connected to the negative input terminal of the operational amplifier. The non-inverting input terminal of the operational amplifier is connected to the DC operating voltage V_ref_dc, the fifth switch is connected in the negative feedback branch of the operational amplifier, the operating voltage is V_phsb, and the output terminal of the operational amplifier is connected to the first input terminal of the NAND gate. The voltage at the second input terminal of the NAND gate is V_phsa, and the output terminal V_out outputs the detection result.

10. The adjustable charging / discharging control circuit according to claim 9, characterized in that: When the charging overcurrent detection control signal Det_oc_d is high and the discharging overcurrent detection control signal Det_od_d is low, the detection result of the error comparison unit includes information about the difference between the actual charging voltage V_chg1 and the reference charging voltage V_chg0. When the charging overcurrent detection control signal Det_oc_d is low and the discharging overcurrent detection control signal Det_od_d is high, the detection result of the error comparison unit includes information about the difference between the actual discharge voltage V_dis1 and the reference discharge voltage V_dis0.

11. The adjustable charging / discharging control circuit according to claim 10, characterized in that: The detection result of the error comparison unit is independent of the DC operating voltage V_ref_dc and the offset voltage Vos of the operational amplifier.

12. The adjustable charging / discharging control circuit according to claim 9, characterized in that: The control signals for the third switch S_phsa and the fourth switch S_phsb are non-overlapping clock signals phsa and phsb; The gate control signals Det_oc_d and Det_od_d of the charging control transistor Mn3 and the discharging control transistor Mn4 are obtained based on the AND operation of the clock detection signal Ck_det and the charging overcurrent detection control signal Det_oc_d, and the AND operation of the clock detection signal Ck_det and the discharging overcurrent detection control signal Det_od_d, respectively; and... The high-level state of the charging overcurrent detection control signal Det_oc_d and the discharging overcurrent detection control signal Det_od_d continues for the entire cycle of the non-overlapping clock signals phsa and phsb.

13. The adjustable charging / discharging control circuit according to claim 6, characterized in that: The aspect ratio of the sampling tube Mn6X to the aspect ratio of the charging tube Mn1 in the charging mirror subunit is fixed. The aspect ratio of the sampling tube Mn11X to the aspect ratio of the discharge tube Mn2 in the discharge mirror subunit is fixed.

14. The adjustable charging / discharging control circuit according to claim 13, characterized in that: The number of charging mirror subunits and discharging mirror subunits in the mirror unit is related to the number of charging voltage Vchg and discharging voltage Vdis levels in the circuit; The number of Mn11X in the plurality of discharge mirror sub-units is equal or in a set ratio, and the discharge voltage Vdis in the circuit is determined at each level based on the quantitative relationship of Mn11X in the plurality of discharge mirror sub-units.

15. The adjustable charging / discharging control circuit according to claim 13, characterized in that: The ratio of the number of sampling tubes Mn6X in the charging mirror subunit to the number of sampling tubes Mn11X in the discharging mirror subunit is determined by the ratio of the charging voltage V_chg to the discharging voltage V_dis.

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