operational amplifier

Abstract

Embodiments of the present disclosure provide an operational amplifier including an input stage circuit, an output stage control circuit, first and second slew rate enhancement circuits, and first and second transistors. The input stage circuit generates a differential output voltage according to a voltage difference between a first input voltage and a second input voltage. The output stage control circuit generates first and second control voltages according to the differential output voltage. The first slew rate enhancement circuit increases a turn-off speed of the first transistor when the voltage difference occurs a downward jump. The second slew rate enhancement circuit increases a turn-off speed of the second transistor when the voltage difference occurs an upward jump. The first slew rate enhancement circuit includes a first negative feedback circuit for slowing down the turn-off speed of the first transistor to suppress an output voltage overshoot of the operational amplifier. The second slew rate enhancement circuit includes a second negative feedback circuit for slowing down the turn-off speed of the second transistor to suppress the output voltage overshoot of the operational amplifier.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to operational amplifiers. Background Technology

[0002] Operational amplifiers (OAs) are common integrated circuits widely used in various circuits to perform different functions, such as signal amplification, output stabilization, and signal driving. Slew rate is a parameter characterizing the OA's ability to process large signals. Some applications require OAs to have a relatively high slew rate. Summary of the Invention

[0003] The embodiments described herein provide an operational amplifier.

[0004] According to a first aspect of this disclosure, an operational amplifier is provided. The operational amplifier includes: an input stage circuit, an output stage control circuit, a first slew rate enhancement circuit, a second slew rate enhancement circuit, a first transistor, and a second transistor. The input stage circuit is configured to amplify the voltage difference between a first input voltage from a first input terminal and a second input voltage from a second input terminal to generate a differential output voltage. The output stage control circuit is configured to generate a first control voltage and a second control voltage based on the differential output voltage and output the first control voltage and the second control voltage from a first output terminal and a second output terminal, respectively. The first control voltage and the second control voltage are negatively correlated with the differential output voltage. The control electrode of the first transistor is coupled to a first output terminal of the output stage control circuit and an output terminal of the first slew rate enhancement circuit. The first electrode of the first transistor is coupled to a first voltage terminal. The second electrode of the first transistor is coupled to an output terminal of the operational amplifier and a second electrode of the second transistor. The control electrode of the second transistor is coupled to a second output terminal of the output stage control circuit and an output terminal of the second slew rate enhancement circuit. The first electrode of the second transistor is coupled to a second voltage terminal. The first slew rate enhancement circuit is configured to adjust the voltage of the control electrode of the first transistor to increase the cutoff speed of the first transistor when a downward transition occurs in the voltage difference. The second slew rate enhancement circuit is configured to adjust the voltage at the control electrode of the second transistor to increase the turn-off speed of the second transistor when the voltage difference jumps upward. The first slew rate enhancement circuit includes a first negative feedback circuit. The first negative feedback circuit is used to reduce the adjustment magnitude of the voltage at the control electrode of the first transistor to suppress output voltage overshoot of the operational amplifier. The second slew rate enhancement circuit includes a second negative feedback circuit. The second negative feedback circuit is used to reduce the adjustment magnitude of the voltage at the control electrode of the second transistor to suppress output voltage overshoot of the operational amplifier.

[0005] In some embodiments of this disclosure, the first conversion rate enhancement circuit further includes: a first input circuit, a first internal load circuit, a second internal load circuit, a pull-up circuit, a first current source, a second current source, a third current source, a third transistor, and a fourth transistor. The first input circuit is configured to generate a first shunt and a second shunt based on a first input voltage, a second input voltage, and a first current from the first current source; output the first shunt via a first node; and output the second shunt via a second node. The sum of the first shunt and the second shunt is equal to the first current. The ratio of the first shunt to the second shunt is inversely proportional to the voltage difference between the first input voltage and the second input voltage. The control electrode of the third transistor is coupled via the first node to the second electrode of the third transistor, the control electrode of the fourth transistor, the first input circuit, and the second current source. The first electrode of the third transistor is coupled to the first internal load circuit and the first negative feedback circuit. The first electrode of the fourth transistor is coupled to the second internal load circuit. The second electrode of the fourth transistor is coupled to the first negative feedback circuit and the pull-up circuit. The first negative feedback circuit is coupled via the second node to the first input circuit and the third current source. The first internal load circuit is configured to control the voltage at the first terminal of the third transistor based on the current flowing through it. The second internal load circuit is configured to control the voltage at the first terminal of the fourth transistor based on the current flowing through it. The pull-up circuit is configured to control the magnitude of the pull-up on the control terminal voltage of the first transistor based on the voltage at the second terminal of the fourth transistor. The first negative feedback circuit is configured to shunt the third current from the third current source to the first internal load circuit.

[0006] In some embodiments of this disclosure, the first input circuit includes a fifth transistor and a sixth transistor. The control electrode of the fifth transistor is coupled to the first input terminal. The first electrode of the fifth transistor is coupled to a first current source and the first electrode of the sixth transistor. The second electrode of the fifth transistor is coupled to a first node. The control electrode of the sixth transistor is coupled to a second input terminal. The second electrode of the sixth transistor is coupled to a second node.

[0007] In some embodiments of this disclosure, the pull-up circuit includes a seventh transistor. The control electrode of the seventh transistor is coupled to the second electrode of the fourth transistor. The first electrode of the seventh transistor is coupled to a first voltage terminal. The second electrode of the seventh transistor is coupled to the control electrode of the first transistor.

[0008] In some embodiments of this disclosure, the first negative feedback circuit includes an eighth transistor and a ninth transistor. The control electrode of the eighth transistor is coupled to the second electrodes of the fourth and ninth transistors. The first electrode of the eighth transistor is coupled to the first electrode of the third transistor. The second electrode of the eighth transistor is coupled to a second node. The control electrode of the ninth transistor is coupled to a first bias voltage terminal. The first electrode of the ninth transistor is coupled to the second node.

[0009] In some embodiments of this disclosure, the first internal load circuit includes a first resistor. A first terminal of the first resistor is coupled to a first terminal of the third transistor. A second terminal of the first resistor is coupled to a first voltage terminal.

[0010] In some embodiments of this disclosure, the second internal load circuit includes a second resistor. A first terminal of the second resistor is coupled to a first terminal of the fourth transistor. A second terminal of the second resistor is coupled to a first voltage terminal.

[0011] In some embodiments of this disclosure, the second conversion rate enhancement circuit further includes: a second input circuit, a third internal load circuit, a fourth internal load circuit, a pull-down circuit, a fourth current source, a fifth current source, a sixth current source, a tenth transistor, and an eleventh transistor. The second input circuit is configured to generate a third shunt and a fourth shunt based on a first input voltage, a second input voltage, and a fourth current from the fourth current source; output the third shunt via a third node; and output the fourth shunt via a fourth node. The sum of the third and fourth shunts equals the fourth current. The ratio of the third and fourth shunts is inversely proportional to the voltage difference between the first and second input voltages. The control electrode of the tenth transistor is coupled to the second electrode of the tenth transistor, the control electrode of the eleventh transistor, and the fifth current source. The first electrode of the tenth transistor is coupled to the second input circuit, the third internal load circuit, and the second negative feedback circuit via the third node. The first electrode of the eleventh transistor is coupled to the fourth internal load circuit via the fourth node. The second electrode of the eleventh transistor is coupled to the second negative feedback circuit and the pull-down circuit. The second negative feedback circuit is coupled to the sixth current source. The third internal load circuit is configured to control the voltage at the first terminal of the tenth transistor based on the current flowing through it. The fourth internal load circuit is configured to control the voltage at the first terminal of the eleventh transistor based on the current flowing through it. The pull-down circuit is configured to control the magnitude of the pull-down of the control terminal voltage of the second transistor based on the voltage at the second terminal of the eleventh transistor. The second negative feedback circuit is configured to shunt the sixth current from the sixth current source to the third internal load circuit.

[0012] In some embodiments of this disclosure, the second input circuit includes a twelfth transistor and a thirteenth transistor. The control electrode of the twelfth transistor is coupled to the first input terminal. The first electrode of the twelfth transistor is coupled to a fourth current source and the first electrode of the thirteenth transistor. The second electrode of the twelfth transistor is coupled to a third node. The control electrode of the thirteenth transistor is coupled to the second input terminal. The second electrode of the thirteenth transistor is coupled to the fourth node.

[0013] In some embodiments of this disclosure, the pull-down circuit includes a fourteenth transistor. The control electrode of the fourteenth transistor is coupled to the second electrode of the eleventh transistor. The first electrode of the fourteenth transistor is coupled to a second voltage terminal. The second electrode of the fourteenth transistor is coupled to the control electrode of the second transistor.

[0014] In some embodiments of this disclosure, the second negative feedback circuit includes a fifteenth transistor and a sixteenth transistor. The control electrode of the fifteenth transistor is coupled to the second electrodes of the eleventh and sixteenth transistors. The first electrode of the fifteenth transistor is coupled to a third node. The second electrode of the fifteenth transistor is coupled to the first electrode of the sixteenth transistor and a sixth current source. The control electrode of the sixteenth transistor is coupled to a second bias voltage terminal.

[0015] In some embodiments of this disclosure, the third internal load circuit includes a third resistor. A first terminal of the third resistor is coupled to a first terminal of the tenth transistor. A second terminal of the third resistor is coupled to a second voltage terminal.

[0016] In some embodiments of this disclosure, the fourth internal load circuit includes a fourth resistor. A first terminal of the fourth resistor is coupled to the first terminal of the eleventh transistor. A second terminal of the fourth resistor is coupled to a second voltage terminal.

[0017] According to a second aspect of this disclosure, an operational amplifier is provided. The operational amplifier includes: an input stage circuit, an output stage control circuit, a first transistor to a sixteenth transistor, a first resistor to a fourth resistor, and a first current source to a sixth current source. The input stage circuit is configured to amplify the voltage difference between a first input voltage from a first input terminal and a second input voltage from a second input terminal to generate a differential output voltage. The output stage control circuit is configured to generate a first control voltage and a second control voltage based on the differential output voltage and output the first control voltage from a first output terminal and the second control voltage from a second output terminal, respectively. The first control voltage and the second control voltage are negatively correlated with the differential output voltage. The control electrode of the first transistor is coupled to a first output terminal of the output stage control circuit and the second electrode of a seventh transistor. The first electrode of the first transistor is coupled to a first voltage terminal. The second electrode of the first transistor is coupled to the output terminal of the operational amplifier and the second electrode of a second transistor. The control electrode of the second transistor is coupled to a second output terminal of the output stage control circuit and the second electrode of a fourteenth transistor. The first electrode of the second transistor is coupled to a second voltage terminal. The control electrode of the third transistor is coupled to the second electrode of the third transistor, the control electrode of the fourth transistor, the second electrode of the fifth transistor, and the second current source. The first terminal of the third transistor is coupled to the first terminal of the first resistor and the first terminal of the eighth transistor. The first terminal of the fourth transistor is coupled to the first terminal of the second resistor. The second terminal of the fourth transistor is coupled to the control terminals of the seventh and eighth transistors and the second terminal of the ninth transistor. The second terminal of the first resistor is coupled to the second terminal of the second resistor and the first voltage terminal. The control terminal of the fifth transistor is coupled to the first input terminal. The first terminal of the fifth transistor is coupled to the first current source and the first terminal of the sixth transistor. The control terminal of the sixth transistor is coupled to the second input terminal. The second terminal of the sixth transistor is coupled to the second terminal of the eighth transistor, the first terminal of the ninth transistor, and the third current source. The first terminal of the seventh transistor is coupled to the first voltage terminal. The control terminal of the ninth transistor is coupled to the first bias voltage terminal. The control terminal of the tenth transistor is coupled to the second terminal of the tenth transistor, the control terminal of the eleventh transistor, and the fifth current source. The first terminal of the tenth transistor is coupled to the second terminal of the twelfth transistor, the first terminal of the fifteenth transistor, and the first terminal of the third resistor. The first terminal of the eleventh transistor is coupled to the second terminal of the thirteenth transistor and the first terminal of the fourth resistor. The second terminal of the eleventh transistor is coupled to the control terminals of the fourteenth, fifteenth, and sixteenth transistors. The second terminal of the third resistor is coupled to the second terminal of the fourth resistor and the second voltage terminal. The control terminal of the twelfth transistor is coupled to the first input terminal. The first terminal of the twelfth transistor is coupled to the fourth current source and the first terminal of the thirteenth transistor. The control terminal of the thirteenth transistor is coupled to the second input terminal. The first terminal of the fourteenth transistor is coupled to the second voltage terminal. The second terminal of the fifteenth transistor is coupled to the first terminal of the sixteenth transistor and the sixth current source. The control terminal of the sixteenth transistor is coupled to the second bias voltage terminal. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0019] Figure 1 This is a schematic block diagram of an operational amplifier;

[0020] Figure 2 This is a schematic block diagram of an operational amplifier according to an embodiment of the present disclosure;

[0021] Figure 3 yes Figure 2 A schematic block diagram of the first slew rate enhancement circuit in the operational amplifier shown;

[0022] Figure 4 yes Figure 3 An exemplary circuit diagram of the first conversion rate enhancement circuit is shown;

[0023] Figure 5 yes Figure 2 A schematic block diagram of the second slew rate enhancement circuit in the operational amplifier shown; and

[0024] Figure 6 yes Figure 5 An exemplary circuit diagram of the second conversion rate enhancement circuit is shown.

[0025] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0028] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0029] Figure 1 A schematic block diagram of an operational amplifier 100 is shown. The operational amplifier 100 includes an input stage circuit 110, an output stage control circuit 120, a first transistor M1, and a second transistor M2. The input stage circuit 110 is configured to amplify the voltage difference between a first input voltage from a first input terminal IN+ and a second input voltage from a second input terminal IN- to generate a differential output voltage. The output stage control circuit 120 is configured to generate a first control voltage and a second control voltage based on the differential output voltage and output the first control voltage from a first output terminal A and a second output terminal B, respectively. The first control voltage and the second control voltage are negatively correlated with the differential output voltage. When the differential output voltage is positive, the first control voltage and the second control voltage decrease as the differential output voltage increases. When the differential output voltage is negative, the first control voltage and the second control voltage increase as the absolute value of the differential output voltage increases.

[0030] The control electrode of the first transistor M1 is coupled to the first output terminal A of the output stage control circuit 120. The first electrode of the first transistor M1 is coupled to the first voltage terminal V1. The second electrode of the first transistor M1 is coupled to the output terminal Out of the operational amplifier 100 and the second electrode of the second transistor M2. The control electrode of the second transistor M2 is coupled to the second output terminal B of the output stage control circuit 120. The first electrode of the second transistor M2 is coupled to the second voltage terminal V2.

[0031] When a positive step signal is applied to the first input terminal IN+ (or a negative step signal is applied to the second input terminal IN-), the output voltage from the output terminal Out of operational amplifier 100 flips to a high level. When a negative step signal is applied to the first input terminal IN+ (or a positive step signal is applied to the second input terminal IN-), the output voltage from the output terminal Out of operational amplifier 100 flips to a low level. In some applications, a high slew rate of operational amplifier 100 is desirable, meaning that the output voltage level should flip as quickly as possible when a step signal is applied to either the first input terminal IN+ or the second input terminal IN-.

[0032] Therefore, embodiments of this disclosure provide an operational amplifier with an enhanced slew rate. Figure 2 A schematic block diagram of an operational amplifier 200 according to an embodiment of the present disclosure is shown. The operational amplifier 200 includes: an input stage circuit 110, an output stage control circuit 120, a first slew rate enhancement circuit 230, a second slew rate enhancement circuit 240, a first transistor M1, and a second transistor M2. Figure 2 In the example, the first transistor M1 is a PMOS transistor, and the second transistor M2 is an NMOS transistor. A high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded.

[0033] Input stage circuit 110 is coupled to a first input terminal IN+ and a second input terminal IN-. The output terminal of input stage circuit 110 is coupled to an input terminal of output stage control circuit 120. Input stage circuit 110 is configured to amplify the voltage difference between a first input voltage from the first input terminal IN+ and a second input voltage from the second input terminal IN- to generate a differential output voltage. Output stage control circuit 120 is configured to generate a first control voltage and a second control voltage based on the differential output voltage, output the first control voltage from a first output terminal A, and output the second control voltage from a second output terminal B. The first and second control voltages are negatively correlated with the differential output voltage. When the differential output voltage is positive, the first and second control voltages decrease as the differential output voltage increases. When the differential output voltage is negative, the first and second control voltages increase as the absolute value of the differential output voltage increases. In some embodiments of this disclosure, the voltage values ​​of the first and second control voltages may not be equal.

[0034] The control electrode of the first transistor M1 is coupled to the first output terminal A of the output stage control circuit 120 and the output terminal of the first slew rate enhancement circuit 230. The first electrode of the first transistor M1 is coupled to the first voltage terminal V1. The second electrode of the first transistor M1 is coupled to the output terminal Out of the operational amplifier 200 and the second electrode of the second transistor M2. The control electrode of the second transistor M2 is coupled to the second output terminal B of the output stage control circuit 120 and the output terminal of the second slew rate enhancement circuit 240. The first electrode of the second transistor M2 is coupled to the second voltage terminal V2.

[0035] A first slew rate enhancement circuit 230 is coupled to the control electrode of a first transistor M1. The first slew rate enhancement circuit 230 is configured to adjust the voltage of the control electrode of the first transistor M1 to increase the cutoff speed of the first transistor M1 when the voltage difference between the first input voltage and the second input voltage undergoes a downward transition (when a negative step signal is applied to the first input terminal IN+, or a positive step signal is applied to the second input terminal IN-). When the first transistor M1 is a PMOS transistor, the first slew rate enhancement circuit 230 is configured to raise the voltage of the control electrode of the first transistor M1 to increase the cutoff speed of the first transistor M1 when the voltage difference between the first input voltage and the second input voltage undergoes a downward transition. Increasing the cutoff speed of the first transistor M1 allows for a faster cessation of power transfer from the first voltage terminal V1 to the output terminal Out via the first transistor M1, thereby enhancing the slew rate of the operational amplifier.

[0036] In some embodiments of this disclosure, the first slew rate enhancement circuit 230 is further configured to not operate when the voltage difference between the first input voltage and the second input voltage does not experience a downward jump. Thus, under normal fluctuations in the first and second input voltages, the first slew rate enhancement circuit 230 will not affect the magnitude of the output voltage.

[0037] The second slew rate enhancement circuit 240 is coupled to the control electrode of the second transistor M2. The second slew rate enhancement circuit 240 is configured to adjust the voltage of the control electrode of the second transistor M2 to increase the cutoff speed of the second transistor M2 when the voltage difference between the first input voltage and the second input voltage jumps upward. When the second transistor M2 is an NMOS transistor, the second slew rate enhancement circuit 240 is configured to decrease the voltage of the control electrode of the second transistor M2 to increase the cutoff speed of the second transistor M2 when the voltage difference between the first input voltage and the second input voltage jumps upward. Increasing the cutoff speed of the second transistor M2 allows for a faster stop of power transfer from the output terminal Out to the second voltage terminal V2 via the second transistor M2, thereby enhancing the slew rate of the operational amplifier.

[0038] In some embodiments of this disclosure, the second slew rate enhancement circuit 240 is further configured to not operate when the voltage difference between the first input voltage and the second input voltage does not jump upwards. Thus, under normal fluctuations in the first and second input voltages, the second slew rate enhancement circuit 240 will not affect the magnitude of the output voltage.

[0039] According to embodiments of the present disclosure, the operational amplifier 200 improves the slew rate by providing a first slew rate enhancement circuit 230 and a second slew rate enhancement circuit 240 to increase the cutoff speed of the first transistor M1 and the second transistor M2, respectively.

[0040] However, if the cutoff speed of the first transistor M1 and the second transistor M2 is too fast, it will cause output voltage overshoot. Therefore, embodiments of this disclosure include a first negative feedback circuit in the first slew rate enhancement circuit 230 (in Figure 3 (As shown in the diagram). The first negative feedback circuit is used to mitigate the adjustment amplitude of the voltage to the control electrode of the first transistor M1 to suppress the output voltage overshoot of the operational amplifier 200. A second negative feedback circuit is provided in the second slew rate enhancement circuit 240 (in... Figure 5 (As shown in the diagram). The second negative feedback circuit is used to reduce the adjustment amplitude of the voltage at the control electrode of the second transistor M2 to suppress the output voltage overshoot of the operational amplifier 200.

[0041] Thus, the operational amplifier 200 according to the embodiments of this disclosure can improve the slew rate of the operational amplifier 200 more stably and reliably.

[0042] Figure 3 Show Figure 2 A schematic block diagram of the first slew rate enhancement circuit in the operational amplifier 200 is shown. Figure 3 In the example, the first conversion rate enhancement circuit 330 includes: a first negative feedback circuit 335, a first input circuit 331, a first internal load circuit 332, a second internal load circuit 333, a pull-up circuit 334, a first current source I1, a second current source I2, a third current source I3, a third transistor M3, and a fourth transistor M4. Figure 3 In this example, the third transistor M3 and the fourth transistor M4 are PMOS transistors. A high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded.

[0043] The first current source I1 outputs the first current I1. The second current source I2 outputs the second current I2. The third current source I3 outputs the third current I3.

[0044] The first input circuit 331 is coupled to a first current source I1, a first input terminal IN+, and a second input terminal IN-. The first input circuit 331 is configured to generate a first shunt current Is1 and a second shunt current Is2 based on a first input voltage, a second input voltage, and a first current I1 from the first current source I1. The first shunt current Is1 is output via a first node N1, and the second shunt current Is2 is output via a second node N2. The sum of the first shunt current Is1 and the second shunt current Is2 is equal to the first current I1. The ratio of the first shunt current Is1 to the second shunt current Is2 is inversely proportional to the voltage difference between the first input voltage IN+ and the second input voltage IN-. When the voltage difference between the first input voltage IN+ and the second input voltage IN- increases, the ratio of the first shunt current Is1 to the second shunt current Is2 decreases; therefore, the first shunt current Is1 decreases while the second shunt current Is2 increases. When the voltage difference between the first input voltage IN+ and the second input voltage IN- decreases, the ratio of the first shunt Is1 to the second shunt Is2 increases, thus the first shunt Is1 increases while the second shunt Is2 decreases.

[0045] The control electrode of the third transistor M3 is coupled to the second electrode of the third transistor M3, the control electrode of the fourth transistor M4, the first input circuit 331, and the second current source I2 via the first node N1. The first electrode of the third transistor M3 is coupled to the first internal load circuit 332 and the first negative feedback circuit 335.

[0046] The first terminal of the fourth transistor M4 is coupled to the second internal load circuit 333. The second terminal of the fourth transistor M4 is coupled to the first negative feedback circuit 335 and the pull-up circuit 334.

[0047] The first internal load circuit 332 is coupled to the first terminal of the third transistor M3 and the first negative feedback circuit 335. The first internal load circuit 332 is configured to: based on the current I flowing through the first internal load circuit 332... R1 This is used to control the voltage at the first terminal of the third transistor M3.

[0048] The second internal load circuit 333 is coupled to the first terminal of the fourth transistor M4. The second internal load circuit 333 is configured to: based on the current I flowing through the second internal load circuit 333... R2 This is used to control the voltage at the first terminal of the fourth transistor M4.

[0049] The pull-up circuit 334 is configured to control the magnitude of the pull-up of the voltage at the control terminal (i.e., the first output terminal A) of the first transistor M1 based on the voltage at the second terminal of the fourth transistor M4. In some embodiments of this disclosure, the magnitude of the pull-up of the voltage at the control terminal of the first transistor M1 may increase as the voltage at the second terminal of the fourth transistor M4 decreases.

[0050] The first negative feedback circuit 335 is coupled to the first input circuit 331 and the third current source I3 via the second node N2. The first negative feedback circuit 335 is also coupled to the second terminal of the fourth transistor and the pull-up circuit 334. The first negative feedback circuit 335 is further coupled to the first terminal of the third transistor M3 and the first internal load circuit 332. The first negative feedback circuit 335 is configured to shunt the third current I3 from the third current source I3 to the first internal load circuit 332.

[0051] According to an embodiment of this disclosure, the first conversion rate enhancement circuit 330 reduces the voltage at the first terminal of the third transistor M3 by shunting the third current I3 to the first internal load circuit 332, thereby reducing the voltage at the control terminal of the fourth transistor M4. This causes the voltage at the second terminal of the fourth transistor M4 to tend to increase. The voltage at the second terminal of the fourth transistor M4 is limited by the first negative feedback circuit 335, which prevents the voltage at the control terminal of the first transistor M1 from being pulled up too much, thereby preventing output voltage overshoot.

[0052] Figure 4 An exemplary circuit diagram of the first conversion rate enhancement circuit 430 is shown. Figure 4 In the example, the first input circuit 431 includes a fifth transistor M5 and a sixth transistor M6. The control electrode of the fifth transistor M5 is coupled to the first input terminal IN+. The first electrode of the fifth transistor M5 is coupled to the first current source I1 and the first electrode of the sixth transistor M6. The second electrode of the fifth transistor M5 is coupled to the first node N1. The control electrode of the sixth transistor M6 is coupled to the second input terminal IN-. The second electrode of the sixth transistor M6 is coupled to the second node N2. Figure 4 In the example, transistors M3 through M8 are PMOS transistors. Transistor M9 is an NMOS transistor. A high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded.

[0053] The pull-up circuit 434 includes a seventh transistor M7. The control electrode of the seventh transistor M7 is coupled to the second electrode of the fourth transistor M4. The first electrode of the seventh transistor M7 is coupled to the first voltage terminal V1. The second electrode of the seventh transistor M7 is coupled to the control electrode (i.e., the first output terminal A) of the first transistor M1.

[0054] The first negative feedback circuit 435 includes an eighth transistor M8 and a ninth transistor M9. The control electrode of the eighth transistor M8 is coupled to the second electrode of the fourth transistor M4 and the second electrode of the ninth transistor M9. The first electrode of the eighth transistor M8 is coupled to the first electrode of the third transistor M3. The second electrode of the eighth transistor M8 is coupled to the second node N2. The control electrode of the ninth transistor M9 is coupled to a first bias voltage terminal Vb1. The first electrode of the ninth transistor M9 is coupled to the second node N2. The magnitude of the first bias voltage Vb1 from the first bias voltage terminal Vb1 is set such that the ninth transistor M9 is fully turned on.

[0055] The first internal load circuit 432 includes a first resistor R1. The first terminal of the first resistor R1 is coupled to the first terminal of the third transistor M3. The second terminal of the first resistor R1 is coupled to a first voltage terminal V1. The current flowing through the first resistor R1 is expressed as I. R1 .

[0056] The second internal load circuit 433 includes a second resistor R2. The first terminal of the second resistor R2 is coupled to the first terminal of the fourth transistor M4. The second terminal of the second resistor R2 is coupled to the first voltage terminal V1. The current flowing through the second resistor R2 is expressed as I. R2 In some embodiments of this disclosure, the resistance value of the second resistor R2 is equal to the resistance value of the first resistor R1.

[0057] When the voltage difference between the first input voltage and the second input voltage undergoes a downward jump (e.g., when a negative step signal is applied to the first input terminal IN+), the first shunt current Is1 increases while the second shunt current Is2 decreases. Since I2 = Is1 + I... R1 Therefore, the current I flowing through the first resistor R1 R1 The voltage decreases, thereby increasing the voltage at the first electrode of the third transistor M3, which in turn increases the voltage at the control electrode of the fourth transistor M4. In this situation, the voltage at the control electrode of the seventh transistor M7 decreases, and the seventh transistor M7 is turned on more fully, thereby increasing the voltage at the control electrode of the first transistor M1.

[0058] When the seventh transistor M7 is turned on, the eighth transistor M8 also turns on, thus shunting a portion of the third current I3 to the first resistor R1. This reduces the voltage at the first terminal of the third transistor M3, thereby reducing the voltage at the control terminal of the fourth transistor M4. This tends to increase the voltage at the second terminal of the fourth transistor M4. The voltage at the second terminal of the fourth transistor M4 is limited by the eighth transistor M8, preventing the voltage at the control terminal of the seventh transistor M7 from dropping too much. This prevents the voltage at the control terminal of the first transistor M1 from being pulled up too much, thus avoiding output voltage overshoot.

[0059] In some embodiments of this disclosure, the aspect ratio of the fifth transistor M5 is greater than that of the sixth transistor M6. When the voltage difference between the first and second input voltages does not exceed a rated value (i.e., when a downward transition does not occur, for example, when the first and second input voltages fluctuate normally), the seventh transistor M7 is turned off, and the first conversion rate enhancement circuit 430 does not affect the voltage at the control electrode of the first transistor M1.

[0060] Figure 5 Show Figure 2 A schematic block diagram of the second slew rate enhancement circuit in the operational amplifier 200 is shown. Figure 5 In the example, the second conversion rate enhancement circuit 540 includes: a second negative feedback circuit 545, a second input circuit 541, a third internal load circuit 542, a fourth internal load circuit 543, a pull-down circuit 544, a fourth current source I4, a fifth current source I5, a sixth current source I6, a tenth transistor M10, and an eleventh transistor M11. Figure 5 In the example, the tenth transistor M10 and the eleventh transistor M11 are NMOS transistors. A high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded.

[0061] The fourth current source I4 outputs the fourth current I4. The fifth current source I5 outputs the fifth current I5. The sixth current source I6 outputs the sixth current I6.

[0062] The second input circuit 541 is coupled to a fourth current source I4, a first input terminal IN+, and a second input terminal IN-. The second input circuit 541 is configured to generate a third shunt current Is3 and a fourth shunt current Is4 based on the first input voltage IN+, the second input voltage IN-, and a fourth current from the fourth current source I4. The third shunt current Is3 is output via a third node N3, and the fourth shunt current Is4 is output via a fourth node N4. The sum of the third shunt current Is3 and the fourth shunt current Is4 equals the fourth current I4. The ratio of the third shunt current Is3 to the fourth shunt current Is4 is inversely proportional to the voltage difference between the first input voltage IN+ and the second input voltage IN-. When the voltage difference between the first input voltage IN+ and the second input voltage IN- increases, the ratio of the third shunt current Is3 to the fourth shunt current Is4 decreases; therefore, the third shunt current Is3 decreases while the fourth shunt current Is4 increases. When the voltage difference between the first input voltage IN+ and the second input voltage IN- decreases, the ratio of the third shunt Is3 and the fourth shunt Is4 increases, thus the third shunt Is3 increases while the fourth shunt Is4 decreases.

[0063] The control electrode of the tenth transistor M10 is coupled to the second electrode of the tenth transistor M10, the control electrode of the eleventh transistor M11, and the fifth current source I5. The first electrode of the tenth transistor M10 is coupled to the second input circuit 541, the third internal load circuit 542, and the second negative feedback circuit 545 via the third node N3.

[0064] The first terminal of the eleventh transistor M11 is coupled to the fourth internal load circuit 543 via the fourth node N4. The second terminal of the eleventh transistor M11 is coupled to the second negative feedback circuit 545 and the pull-down circuit 544. The second negative feedback circuit 545 is coupled to the sixth current source I6.

[0065] The third internal load circuit 542 is coupled to the second input circuit 541, the second negative feedback circuit 545, and the first terminal of the tenth transistor M10 via the third node N3. The third internal load circuit 542 is configured to: based on the current I flowing through the third internal load circuit 542... R3 This is used to control the voltage at the first terminal of the tenth transistor M10.

[0066] The fourth internal load circuit 543 is coupled to the second input circuit 541 and the first terminal of the eleventh transistor M11 via the fourth node N4. The fourth internal load circuit 543 is configured to control the voltage of the first terminal of the eleventh transistor M11 based on the current flowing through the fourth internal load circuit 543.

[0067] The pull-down circuit 544 is configured to control the magnitude by which the voltage of the control electrode (i.e., the second output terminal B) of the second transistor M2 is pulled down based on the voltage of the second electrode of the eleventh transistor M11. In some embodiments of this disclosure, the magnitude by which the voltage of the control electrode of the second transistor M2 is pulled down may decrease as the voltage of the second electrode of the eleventh transistor M1 increases.

[0068] The second negative feedback circuit 545 is coupled to the sixth current source I6. The second negative feedback circuit 545 is coupled to the second input circuit 541, the third internal load circuit 542, and the first terminal of the tenth transistor M10. The second negative feedback circuit 545 is also coupled to the pull-down circuit 544 and the second terminal of the eleventh transistor M11. The second negative feedback circuit 545 is configured to shunt the sixth current I6 from the sixth current source I6 to the third internal load circuit 542.

[0069] According to an embodiment of this disclosure, the second conversion rate enhancement circuit 540 can raise the voltage of the first electrode of the tenth transistor M10 by shunting the sixth current I6 to the third internal load circuit 542, thereby raising the voltage of the control electrode of the eleventh transistor M11. This causes the voltage of the second electrode of the eleventh transistor M11 to tend to decrease. The voltage of the second electrode of the eleventh transistor M11 is limited by the second negative feedback circuit 545, which can prevent the voltage of the control electrode of the second transistor M2 from being pulled down by too much, thereby avoiding output voltage overshoot.

[0070] Figure 6 An exemplary circuit diagram of the second conversion rate enhancement circuit 640 is shown. Figure 6 In the example, the second input circuit 641 includes a twelfth transistor M12 and a thirteenth transistor M13. The control electrode of the twelfth transistor M12 is coupled to the first input terminal IN+. The first electrode of the twelfth transistor M12 is coupled to the fourth current source I4 and the first electrode of the thirteenth transistor M13. The second electrode of the twelfth transistor M12 is coupled to the third node N3. The control electrode of the thirteenth transistor M13 is coupled to the second input terminal IN-. The second electrode of the thirteenth transistor M13 is coupled to the fourth node N4. Figure 6 In the example, transistors M10 (10th), M11 (11th), M14 (14th), and M15 (15th) are NMOS transistors. Transistors M12 (12th), M13 (13th), and M16 (16th) are PMOS transistors. A high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded.

[0071] The pull-down circuit 644 includes: a fourteenth transistor M14. The control electrode of the fourteenth transistor M14 is coupled to the second electrode of the eleventh transistor M11. The first electrode of the fourteenth transistor M14 is coupled to the second voltage terminal V2. The second electrode of the fourteenth transistor M14 is coupled to the control electrode (i.e., the second output terminal B) of the second transistor M2.

[0072] The second negative feedback circuit 645 includes a fifteenth transistor M15 and a sixteenth transistor M16. The control electrode of the fifteenth transistor M15 is coupled to the second electrode of the eleventh transistor M11 and the second electrode of the sixteenth transistor M16. The first electrode of the fifteenth transistor M15 is coupled to the third node N3. The second electrode of the fifteenth transistor M15 is coupled to the first electrode of the sixteenth transistor M16 and the sixth current source I6. The control electrode of the sixteenth transistor M16 is coupled to the second bias voltage terminal Vb2. The magnitude of the second bias voltage Vb2 is set such that the sixteenth transistor M16 is fully turned on.

[0073] The third internal load circuit 642 includes a third resistor R3. The first terminal of the third resistor R3 is coupled to the first terminal of the tenth transistor M10. The second terminal of the third resistor R3 is coupled to the second voltage terminal V2. The current flowing through the third resistor R3 is expressed as I. R3 .

[0074] The fourth internal load circuit 643 includes a fourth resistor R4. The first terminal of the fourth resistor R4 is coupled to the first terminal of the eleventh transistor M11. The second terminal of the fourth resistor R4 is coupled to the second voltage terminal V2. The current flowing through the fourth resistor R4 is expressed as I. R4 In some embodiments of this disclosure, the resistance value of the fourth resistor R4 is equal to the resistance value of the third resistor R3.

[0075] When the voltage difference between the first and second input voltages jumps upwards (e.g., when a positive step signal is applied to the first input terminal IN+), the third shunt current Is3 decreases while the fourth shunt current Is4 increases. The current I flowing through the third resistor R3... R3 This reduces the voltage at the first electrode of the tenth transistor M10, which in turn reduces the voltage at the control electrode of the eleventh transistor M11. In this situation, the voltage at the control electrode of the fourteenth transistor M14 increases, and the fourteenth transistor M14 is turned on more fully, thereby pulling down the voltage at the control electrode of the second transistor M2.

[0076] When the fourteenth transistor M14 is turned on, the fifteenth transistor M15 also turns on, thus shunting a portion of the sixth current I6 to the third resistor R3. This raises the voltage at the first terminal of the tenth transistor M10, thereby raising the voltage at the control terminal of the eleventh transistor M11. This causes the voltage at the second terminal of the eleventh transistor M11 to tend to decrease. The voltage at the second terminal of the eleventh transistor M11 is limited by the fifteenth transistor M15, preventing the voltage at the control terminal of the fourteenth transistor M14 from rising too much. This also prevents the voltage at the control terminal of the second transistor M2 from being pulled down too much, thus avoiding output voltage overshoot.

[0077] In some embodiments of this disclosure, the aspect ratio of the twelfth transistor M12 is greater than that of the thirteenth transistor M13. When the increase in the voltage difference between the first input voltage and the second input voltage does not exceed a rated value (i.e., when there is no upward jump, for example, when the first input voltage and the second input voltage fluctuate normally), the fourteenth transistor M14 is turned off, and the second conversion rate enhancement circuit 640 does not affect the voltage at the control electrode of the second transistor M2.

[0078] Those skilled in the art should understand that Figures 3 to 6Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figures 3 to 6 The examples shown have different settings.

[0079] Embodiments of this disclosure also provide a chip. The chip includes an operational amplifier according to embodiments of this disclosure. This chip is, for example, a chip for processing large signals.

[0080] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. Examples of this electronic device include portable devices, MP3 players, cellular phones, personal digital assistants, laptops, tablets, etc.

[0081] In summary, the operational amplifier according to the embodiments of this disclosure can achieve a high slew rate and avoid output voltage overshoot.

[0082] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0083] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0084] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. An operational amplifier, comprising: The circuit includes an input stage, an output stage control circuit, a first slew rate enhancement circuit, a second slew rate enhancement circuit, a first transistor, and a second transistor. The input stage circuit is configured to amplify the voltage difference between a first input voltage from a first input terminal and a second input voltage from a second input terminal to generate a differential output voltage. The output stage control circuit is configured to generate a first control voltage and a second control voltage based on the differential output voltage, and output the first control voltage and the second control voltage from the first output terminal and the second output terminal respectively, wherein the first control voltage and the second control voltage are negatively correlated with the differential output voltage. The control electrode of the first transistor is coupled to the first output terminal of the output stage control circuit and the output terminal of the first conversion rate enhancement circuit; the first electrode of the first transistor is coupled to the first voltage terminal; and the second electrode of the first transistor is coupled to the output terminal of the operational amplifier and the second electrode of the second transistor. The control electrode of the second transistor is coupled to the second output terminal of the output stage control circuit and the output terminal of the second conversion rate enhancement circuit, and the first electrode of the second transistor is coupled to the second voltage terminal; The first conversion rate enhancement circuit is configured to: when the voltage difference jumps downward, adjust the voltage of the control electrode of the first transistor to increase the cutoff speed of the first transistor; The second conversion rate enhancement circuit is configured to adjust the voltage of the control electrode of the second transistor to increase the cutoff speed of the second transistor when the voltage difference jumps upward. The first slew rate enhancement circuit includes a first negative feedback circuit, which is used to reduce the adjustment range of the voltage at the control electrode of the first transistor to suppress the output voltage overshoot of the operational amplifier. The second slew rate enhancement circuit includes a second negative feedback circuit, which is used to reduce the adjustment range of the voltage at the control electrode of the second transistor to suppress the output voltage overshoot of the operational amplifier.

2. The operational amplifier according to claim 1, wherein, The first conversion rate enhancement circuit further includes: a first input circuit, a first internal load circuit, a second internal load circuit, a pull-up circuit, a first current source, a second current source, a third current source, a third transistor, and a fourth transistor. The first input circuit is configured to generate a first shunt and a second shunt based on the first input voltage, the second input voltage, and a first current from a first current source; output the first shunt via a first node and output the second shunt via a second node; wherein the sum of the first shunt and the second shunt is equal to the first current; and the ratio of the first shunt to the second shunt is inversely proportional to the voltage difference between the first input voltage and the second input voltage. The control electrode of the third transistor is coupled to the second electrode of the third transistor, the control electrode of the fourth transistor, the first input circuit, and the second current source via the first node; the first electrode of the third transistor is coupled to the first internal load circuit and the first negative feedback circuit. The first terminal of the fourth transistor is coupled to the second internal load circuit, and the second terminal of the fourth transistor is coupled to the first negative feedback circuit and the pull-up circuit. The first negative feedback circuit is coupled to the first input circuit and the third current source via the second node; The first internal load circuit is configured to control the voltage of the first terminal of the third transistor based on the current flowing through the first internal load circuit. The second internal load circuit is configured to control the voltage of the first terminal of the fourth transistor based on the current flowing through the second internal load circuit; The pull-up circuit is configured to control the pull-up amplitude of the control electrode voltage of the first transistor based on the voltage of the second electrode of the fourth transistor. The first negative feedback circuit is configured to shunt the third current from the third current source to the first internal load circuit.

3. The operational amplifier according to claim 2, wherein, The first input circuit includes: a fifth transistor and a sixth transistor. Wherein, the control electrode of the fifth transistor is coupled to the first input terminal, the first electrode of the fifth transistor is coupled to the first current source and the first electrode of the sixth transistor, and the second electrode of the fifth transistor is coupled to the first node; The control electrode of the sixth transistor is coupled to the second input terminal, and the second electrode of the sixth transistor is coupled to the second node.

4. The operational amplifier according to claim 2, wherein, The pull-up circuit includes: a seventh transistor, The control electrode of the seventh transistor is coupled to the second electrode of the fourth transistor, the first electrode of the seventh transistor is coupled to the first voltage terminal, and the second electrode of the seventh transistor is coupled to the control electrode of the first transistor.

5. The operational amplifier according to any one of claims 2 to 4, wherein, The first negative feedback circuit includes: an eighth transistor and a ninth transistor. Wherein, the control electrode of the eighth transistor is coupled to the second electrode of the fourth transistor and the second electrode of the ninth transistor, the first electrode of the eighth transistor is coupled to the first electrode of the third transistor, and the second electrode of the eighth transistor is coupled to the second node; The control electrode of the ninth transistor is coupled to the first bias voltage terminal, and the first electrode of the ninth transistor is coupled to the second node.

6. The operational amplifier according to claim 1, wherein, The second slew rate enhancement circuit further includes: a second input circuit, a third internal load circuit, a fourth internal load circuit, a pull-down circuit, a fourth current source, a fifth current source, a sixth current source, a tenth transistor, and an eleventh transistor. The second input circuit is configured to generate a third shunt and a fourth shunt based on the first input voltage, the second input voltage, and a fourth current from a fourth current source; output the third shunt via a third node and the fourth shunt via a fourth node; wherein the sum of the third shunt and the fourth shunt is equal to the fourth current; and the ratio of the third shunt to the fourth shunt is inversely proportional to the voltage difference between the first input voltage and the second input voltage. The control electrode of the tenth transistor is coupled to the second electrode of the tenth transistor, the control electrode of the eleventh transistor and the fifth current source, and the first electrode of the tenth transistor is coupled to the second input circuit, the third internal load circuit and the second negative feedback circuit via the third node; The first terminal of the eleventh transistor is coupled to the fourth internal load circuit via the fourth node, and the second terminal of the eleventh transistor is coupled to the second negative feedback circuit and the pull-down circuit; The second negative feedback circuit is coupled to the sixth current source; The third internal load circuit is configured to control the voltage of the first terminal of the tenth transistor based on the current flowing through the third internal load circuit. The fourth internal load circuit is configured to control the voltage of the first terminal of the eleventh transistor based on the current flowing through the fourth internal load circuit. The pull-down circuit is configured to control the magnitude by which the voltage of the control electrode of the second transistor is pulled down based on the voltage of the second electrode of the eleventh transistor. The second negative feedback circuit is configured to shunt the sixth current from the sixth current source to the third internal load circuit.

7. The operational amplifier according to claim 6, wherein, The second input circuit includes: a twelfth transistor and a thirteenth transistor. The control electrode of the twelfth transistor is coupled to the first input terminal, the first electrode of the twelfth transistor is coupled to the fourth current source and the first electrode of the thirteenth transistor, and the second electrode of the twelfth transistor is coupled to the third node. The control terminal of the thirteenth transistor is coupled to the second input terminal, and the second terminal of the thirteenth transistor is coupled to the fourth node.

8. The operational amplifier according to claim 6, wherein, The pull-down circuit includes: a fourteenth transistor, The control electrode of the fourteenth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the fourteenth transistor is coupled to the second voltage terminal, and the second electrode of the fourteenth transistor is coupled to the control electrode of the second transistor.

9. The operational amplifier according to any one of claims 6 to 8, wherein, The second negative feedback circuit includes: a fifteenth transistor and a sixteenth transistor. The control electrode of the fifteenth transistor is coupled to the second electrode of the eleventh transistor and the second electrode of the sixteenth transistor; the first electrode of the fifteenth transistor is coupled to the third node; and the second electrode of the fifteenth transistor is coupled to the first electrode of the sixteenth transistor and the sixth current source. The control electrode of the sixteenth transistor is coupled to the second bias voltage terminal.

10. An operational amplifier, comprising: Input stage circuit, output stage control circuit, first to sixteenth transistors, first to fourth resistors, first to sixth current sources, The input stage circuit is configured to amplify the voltage difference between a first input voltage from a first input terminal and a second input voltage from a second input terminal to generate a differential output voltage. The output stage control circuit is configured to generate a first control voltage and a second control voltage based on the differential output voltage, and output the first control voltage and the second control voltage from the first output terminal and the second output terminal respectively, wherein the first control voltage and the second control voltage are negatively correlated with the differential output voltage. The control electrode of the first transistor is coupled to the first output terminal of the output stage control circuit and the second electrode of the seventh transistor. The first electrode of the first transistor is coupled to the first voltage terminal, and the second electrode of the first transistor is coupled to the output terminal of the operational amplifier and the second electrode of the second transistor. The control electrode of the second transistor is coupled to the second output terminal of the output stage control circuit and the second electrode of the fourteenth transistor, and the first electrode of the second transistor is coupled to the second voltage terminal; The control electrode of the third transistor is coupled to the second electrode of the third transistor, the control electrode of the fourth transistor, the second electrode of the fifth transistor, and the second current source; the first electrode of the third transistor is coupled to the first terminal of the first resistor and the first electrode of the eighth transistor. The first terminal of the fourth transistor is coupled to the first terminal of the second resistor, and the second terminal of the fourth transistor is coupled to the control terminal of the seventh transistor, the control terminal of the eighth transistor, and the second terminal of the ninth transistor; The second end of the first resistor is coupled to the second end of the second resistor and the first voltage terminal; The control electrode of the fifth transistor is coupled to the first input terminal, and the first electrode of the fifth transistor is coupled to the first current source and the first electrode of the sixth transistor; The control terminal of the sixth transistor is coupled to the second input terminal, and the second terminal of the sixth transistor is coupled to the second terminal of the eighth transistor, the first terminal of the ninth transistor, and the third current source; The first terminal of the seventh transistor is coupled to the first voltage terminal; The control electrode of the ninth transistor is coupled to the first bias voltage terminal; The control electrode of the tenth transistor is coupled to the second electrode of the tenth transistor, the control electrode of the eleventh transistor, and the fifth current source; the first electrode of the tenth transistor is coupled to the second electrode of the twelfth transistor, the first electrode of the fifteenth transistor, and the first terminal of the third resistor. The first terminal of the eleventh transistor is coupled to the second terminal of the thirteenth transistor and the first terminal of the fourth resistor; the second terminal of the eleventh transistor is coupled to the control terminal of the fourteenth transistor, the control terminal of the fifteenth transistor, and the second terminal of the sixteenth transistor. The second end of the third resistor is coupled to the second end of the fourth resistor and the second voltage terminal; The control terminal of the twelfth transistor is coupled to the first input terminal, and the first terminal of the twelfth transistor is coupled to the fourth current source and the first terminal of the thirteenth transistor; The control electrode of the thirteenth transistor is coupled to the second input terminal; The first terminal of the fourteenth transistor is coupled to the second voltage terminal; The second terminal of the fifteenth transistor is coupled to the first terminal of the sixteenth transistor and the sixth current source; The control electrode of the sixteenth transistor is coupled to the second bias voltage terminal.

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