Method of producing independent and stress-free epitaxial layers starting from a disposable substrate patterned with an etched pillar array

Abstract

The method provides growing an epitaxial layer (200) made of a first semiconductor material on a substrate (100) made of a second semiconductor material; the materials are different and have different CTEs; the method comprises the following steps: A) patterning the substrate (100) by an etching process to form an array of pillars (110) laterally spaced apart from each other and having a top portion (112) greater than a bottom portion (114) and / or an intermediate portion (116), B) depositing the second semiconductor material on top of the pillars (110) at a growth temperature to form the epitaxial layer (200) resulting from vertical growth and lateral growth, and C) inducing a fracture of the pillars (110) by cooling the substrate (100) and the epitaxial layer (200) to below the growth temperature.

Description

[0001] Invention Field This invention relates to a method for generating independent epitaxial layers from a single substrate; structures formed by such a method are also disclosed herein, particularly independent epitaxial layers intended for use as substrates for manufacturing electrical or electronic or optoelectronic components. Background Technology

[0002] Creating substrates for manufacturing electrical, electronic, or optoelectronic components is a crucial step in microelectronics because the quality of the functional films deposited on the substrate (i.e., the core of the component) largely depends on the properties of the substrate.

[0003] Epitaxial growth of materials with different coefficients of thermal expansion relative to the substrate (thermal misfit) leads to detrimental bending or propagation cracking of the wafer during cooling due to accumulated thermal stress in the film, which in turn is caused by the different shrinkage of the film relative to the substrate. Heteroepitaxy remains very popular because inexpensive substrates such as silicon provide seed crystals for the epitaxial phase of functional materials, not only for economic reasons but also because it is the best way to induce special crystalline phases (e.g., cubic 3C-SiC on Si). Appropriate orientation of the wafer surface is required to match the crystalline phase of the epitaxial film, or to orient the growth front of the film in a way that reduces the density of propagation defects: for example, Si(111) may be suitable for reducing antiphase domains and staking faults in cubic 3C-SiC. However, such orientation results in significant thermal stress, even at moderate film thicknesses, due to a combination of the elastic constants in the mechanical properties of such materials and the lower density of moving propagation defects. Cubic 3C-SiC cannot be deposited on planar Si(111) substrates with a film thickness exceeding 1 micrometer without the formation of propagating cracks. Such a small thickness is unsuitable for the fabrication of any power device, not only for purely geometric reasons, but also because the quality of the functional portions at the top of the film, particularly for the portions of interest to electrical, electronic, and optoelectronic components, is generally known to improve with increasing film thickness due to mutual defect elimination.

[0004] In the inventors’ previous patent application (WO2017186810A1, now published in the United States under US 10,734,226 B2) and subsequent scientific papers, it was proposed how the patterning of a substrate with a defined region of micron-sized pillar arrays can adapt to different shrinkages of the film relative to the substrate by utilizing the lateral curvature of the pillars. Such an compliant mechanism is effective if the aspect ratio of the pillars is quantitatively tailored relative to the lateral dimensions of the array, resulting in continuous film patches deposited on the pillars in a manner with reduced curvature and no cracks. Thus, a substrate wafer can be patterned into several separate arrays with suitable geometry, pillar spacing, and array separation, such that the entire wafer surface is covered with film patches of 10-20 microns in a manner with reduced curvature and no cracks. For example, in the case of cubic 3C-SiC on Si(111), the thickness of the film patches (up to 500 microns) can even be as low as 20 microns, with significantly reduced curvature and no cracks. This is particularly useful when the film is still integrated on the substrate, and is suitable for any application that requires both SiC and Si, such as power devices in 3C-SiC connected and driven by logic transistors on the Si side.

[0005] However, the inventors have considered that if any standalone application requires a separate wafer of deposited film, or if a separate layer of deposited film with a lateral dimension of several centimeters is required, the film thickness should be several hundred micrometers, and a substrate can be provided.

[0006] In a recently assigned patent to STMicroelectronics (US 10,153,207), this is achieved by epitaxially growing a film, such as a SiC film, on a planar substrate, such as Si, at a sufficiently high temperature, such that the substrate melts before growth is complete. This process works when the substrate's melting temperature is significantly lower than the film's melting temperature, and the growth kinetics of the deposited film at such high temperatures are suitable. This appears to be the case with SiC on Si. However, in addition to the aforementioned limitations of substrate and film properties, the melting of the substrate in the growth chamber requires a specially designed susceptor and other systems to capture the molten silicon.

[0007] In recent scientific literature, methods for peeling ultrathin films from a substrate (particularly for the production of multijunction solar cells) can be divided into two main categories: one is to deposit a sacrificial layer between the film and the substrate, which is eventually removed by wet etching, possibly in combination with other process conditions (see, for example, Journal of Electronic Materials, Vol. 24, No. 6, (1995) 757-760, and Applied Physics Letters, Vol. 111, (2017) 233509); the other is to generate a porous silicon layer on top of the substrate, possibly in combination with thermal treatment, and finally remove the film deposited thereon by mechanical action such as rolling (see, for example, Solar Energy Materials and Solar Cells, Vol. 135, (2015) 113-123, and Solar Energy Materials and Solar Cells, Vol. 203, (2019) 110108, or Joule, Vol. 3, (2019) 1782-1793).

[0008] However, aside from the complexity of the methods and the different purposes (including the reuse of the substrate), the inventors believe that none of them rely solely on the spontaneous action of thermal stress in the unavoidable cooling step without chemical action or (or almost no) mechanical action (which would be very advantageous, as explained below) to carry out the stripping process.

[0009] Overview Therefore, there is a need to improve existing technical methods for producing substrates used in the manufacture of electrical, electronic, or optoelectronic components.

[0010] The general objective of this invention is to satisfy the following requirement.

[0011] This general purpose and more specific purposes are achieved by means of the contents set forth in the appended claims that form an integral part of this specification.

[0012] The first basic idea of ​​this invention is to generate independent epitaxial layers starting from the substrate to be set.

[0013] The second basic idea of ​​this invention is to use different semiconductor materials for the substrate and epitaxial layer.

[0014] The third fundamental idea of ​​this invention is to separate the epitaxial layer from the substrate without (or substantially without) mechanical and / or chemical post-processing steps. According to the invention, the separation originates (only or primarily) from the cooling of the resulting structure; in particular, such cooling induces cracking due to the different contractions of different portions of the resulting structure.

[0015] The fourth basic idea of ​​the present invention is to grow an epitaxial layer on an array of pillars (especially pillars obtained by patterning a substrate).

[0016] Advantageously, the pillars are shaped and sized such that they break at the same (or approximately the same) location, particularly at the same (or approximately the same) depth from the top surface of the substrate in which the pillars are etched.

[0017] Advantageously, this method of generation results in the deposited epitaxial layers being non-laterally bonded (or substantially non-laterally bonded), such that the layers detach from the substrate when the column fractures. In particular, this can be achieved in two ways: the deposited layers are surrounded by free space, or the deposited layers are surrounded by one or more elements of different materials that do not adhere to the material of the epitaxial layers.

[0018] List of Attached Figures The invention will become clearer from the following detailed description, which is considered in conjunction with the accompanying drawings, in which: Figure 1A-1B The diagram schematically illustrates the vertical cross-sections of an embodiment of the structure according to the invention before and after cooling. Figure 2A-2H The sequence of steps in an embodiment of the method according to the invention is illustrated schematically. Figure 3 The column of an embodiment of the structure produced according to the present invention is illustrated schematically. Figure 4 A cross-section schematically illustrating a first exemplary detail of an embodiment of a structure produced according to the present invention is shown. Figure 5 A cross-section schematically illustrating a second exemplary detail of an embodiment of the structure produced according to the present invention is shown. Figure 6 A top view schematically illustrates a first exemplary seed crystal of an embodiment of the structure produced according to the present invention. Figure 7 A top view schematically illustrates a first exemplary patch of an embodiment of the structure produced according to the present invention. Figure 8 A top view schematically illustrating a second exemplary seed crystal of an embodiment of the structure produced according to the present invention, and Figure 9 A top view of a second exemplary patch representing an embodiment of the structure produced according to the present invention is shown schematically.

[0019] As will be readily understood, there are various ways in which the invention can be actually carried out. The invention is defined in its main advantageous aspects by the appended claims and is not limited to the following detailed description or the accompanying drawings.

[0020] Detailed Explanation The structure produced according to the present invention essentially comprises a manufactured semiconductor substrate (e.g., the substrate marked 100 in Figures 1 and 2) and a semiconductor epitaxial layer (e.g., the layer marked 200 in Figures 1 and 2) formed on top of the substrate by a high-temperature epitaxial growth process carried out in the reaction chamber of an epitaxial reactor.

[0021] The growth temperature depends on a variety of factors, particularly the semiconductor material, precursor material, growth pressure, and type of epitaxial reactor. For example, and without limiting the purpose of the invention, single-crystal silicon can be epitaxially grown on single-crystal silicon at 1150°C and 100 kPa, single-crystal hexagonal silicon carbide can be epitaxially grown on single-crystal hexagonal silicon carbide at 1650°C and 10 kPa, and single-crystal cubic silicon carbide can be epitaxially grown on single-crystal silicon at 1370°C and 13 kPa.

[0022] Once the high-temperature epitaxial growth process is complete, the structure is extracted from the reaction chamber and cooled to, for example, room temperature (e.g., 20°C-30°C).

[0023] In addition to the high-temperature epitaxial growth process, the structures produced according to the present invention typically undergo many other processing steps.

[0024] Figure 1A An embodiment of the structure according to the invention is schematically shown before cooling inside the reaction chamber, and Figure 1B The same structure is shown after cooling outside the reaction chamber.

[0025] In Figure 1, a substrate 100 made of, for example, silicon is patterned and a plurality of pillars 110 are formed, and an epitaxial layer 200 of, for example, silicon carbide is located on the substrate 100, particularly on the pillars 110; it should be noted that both the substrate and the layer continue, for example, on the right side, and this is indicated by the shape of the pointed tip.

[0026] According to the embodiment of Figure 1, the column 110 is appropriately shaped; there is a large top portion 112 (adjacent layer 200) and a small bottom portion 114; the cross-sectional area of ​​the column 110 gradually decreases from the bottom portion 114 to the middle portion 116, and then gradually increases from the middle portion 116 to the top portion 112; therefore, there is a necking 118 in the middle portion of the column 110.

[0027] During the cooling phase, due to the different CTE (coefficient of thermal expansion) of the two materials, the silicon carbide epitaxial layer 200 shrinks more than the silicon substrate 100. Figure 1BThe white arrows in the diagram represent thermal stress within the epitaxial layer 100. Due to this thermal stress within layer 200, shear stress develops within the pillars 110. If the pillars 110 are (sufficiently) thin, such thermal stress may cause them to fracture; Figure 1B In the middle, all columns 110 have broken; it should be noted that column 110 has broken at its neck 118, that is, at the point where its cross-sectional area is smallest. Figure 1B As shown, after fracture, a portion of the columns 110 (i.e., their upper portions) can remain connected to the layer 200, and a portion of the columns 110 (i.e., their lower portions) can remain integral with the substrate 100.

[0028] If all the posts 110 break, then the layer 200 is completely detached from the substrate 100. If a few posts 110 do not break and / or if any mechanical connection is maintained between the substrate 100 and the layer 200, a (small) force or (small) torque may be applied to the substrate 100 and / or the layer 200 to detach the layer 200 from the substrate 100.

[0029] At this stage, settings can be configured. Figure 1B The base 100 (including any part of the pillar 110), and Figure 1B Layer 200 (including any part of pillar 110) is an independent epitaxial layer (if the thickness of the layer is sufficiently high, for example, 50 micrometers to 500 micrometers, preferably 150 micrometers to 300 micrometers), and can be used as a substrate for manufacturing electrical or electronic or optoelectronic components, or as a substrate for further epitaxial growth.

[0030] It should be noted that after layer 200 separates from substrate 100, especially if the top of pillar 110 remains connected to layer 200, it may be advantageous to grind the back side of layer 200 so that the independent epitaxial layer is flat on both sides.

[0031] It should be noted that, according to the embodiment of Figure 1, the epitaxial layer shrinks more than the substrate due to cooling. However, alternatively, according to the invention, it is likely that the substrate shrinks more than the epitaxial layer. What happens depends on the CTE of the substrate material and the CTE of the layer material.

[0032] The following description, aided by Figure 2, illustrates the process. Figure 1A Possible processes for the structure.

[0033] The starting point of this process is a substrate 100 made of monocrystalline silicon, such as... Figure 2A As shown in the image.

[0034] The substrate 100 is properly masked for etching; Figure 2B A substrate 100 is shown, wherein a plurality of mask elements 150 are placed on top of a flat upper surface of the substrate 100.

[0035] Then, the first etching step is performed, creating multiple deep and narrow vertical grooves 122, such as... Figure 2C As shown in the diagram; this can be referred to as a “vertical” etching step. In this way, an array of vertical columns is formed on the upper portion of the substrate 100. Such a first etching step can be performed using a dry etching process, such as the Bosch process or the Cryo process (well-known to experts).

[0036] Then, a second etching step is performed, and the groove 122 is enlarged to create a number of deep and well-defined vertical grooves 124, such as... Figure 2D As shown in the diagram. In this way, the array of columns is transformed into... Figure 1A The array of pillars 110, which are laterally spaced from each other, is shown in the figure. Such a second etching step can be performed by an isotropic dry etching process or a wet etching process (well known to experts).

[0037] Then, for example, the mask element 150 is removed from the top portion of the pillar 110 by a third etching step, such as... Figure 2E As shown, a flat and smooth "epi-ready" surface 119 is left on the top of pillar 110; as is known, "epi-ready" means ready for subsequent epitaxy to form a single crystal material. Such a third etching step can be performed by a dry etching process or a wet etching process (well known to experts), and can include surface oxidation and wet oxide stripping.

[0038] In this stage, a silicon carbide epitaxial deposition process is performed at a high temperature. For this purpose, for example, [the following is an example:] Figure 2E The structure shown is introduced into the reaction chamber of the epitaxial reactor.

[0039] In the following text, for the sake of simple illustrative explanation, the epitaxial deposition process is divided into three consecutive deposition sub-steps; however, this should not be construed as a limitation of the invention; in fact, as is known to the experts, the actual deposition steps (corresponding to step B described above) are quite complex and are carried out through many sub-steps. Figure 2F , Figure 2G and Figure 2H This can correspond to different moments in a single deposition step B.

[0040] Following the first deposition sub-step, single-crystal seed crystals 210 of silicon carbide are formed on each surface 119 of pillar 110, such as... Figure 2F As shown in the diagram, the seed crystals 210 are spaced laterally apart from each other. During this first deposition, it can be assumed that growth occurs primarily in the vertical direction.

[0041] Following the second deposition sub-step, the seed crystals 210 grow both vertically and laterally, forming an array of adjacent seed crystals 220 of silicon carbide, as shown below. Figure 2G The image shows the beginning of merging multiple seed crystals into a single patch.

[0042] Following the third deposition sub-step, a silicon carbide layer 200 of appropriate thickness is formed on pillar 110, as follows: Figure 2H As shown in the image.

[0043] At this stage, the structure can be extracted from the reaction chamber of the epitaxial reactor; typically, the structure may still be relatively hot at the time of extraction.

[0044] Typically, the method for producing the independent epitaxial layer according to the invention is based on using two different semiconductor materials with different CTEs.

[0045] According to embodiments of the present invention, the substrate may belong to, for example, a first family including Si, Ge or SiGe (which allows for easy patterning), or a second family including GaAs, GaP, ZnSe, ZnS, SiC, GaN, or a third family (i.e. oxides) such as ZnO, Al2O3, MgAlO4.

[0046] According to embodiments of the invention, the epitaxial layer may include, for example, Si, Ge, GaN (hexagonal and cubic) and SiC (hexagonal and cubic), which are attractive as semiconductor materials for, for example, power electronics and / or optoelectronics.

[0047] Typically, a method for generating a separate epitaxial layer according to the invention includes the following steps (refer to Figures 1 and 2 for non-limiting purposes): (A) (See Figure 2 in particular) The substrate (100) of the first semiconductor material is patterned by an etching process to form an array of pillars (110), the pillars (110) being appropriately spaced laterally from each other and having a top portion (112) that is larger than the bottom portion (114) and / or the middle portion (116). B) (See Figure 2 for details) A second semiconductor material is deposited on top of the pillar (110) at the growth temperature to form an epitaxial layer (200) generated by the vertical and lateral growth of the second semiconductor material, and C) (see Figure 1 in particular) fracture of the pillar (110) is induced by cooling the substrate (100) and epitaxial layer (200) to below the growth temperature.

[0048] The top portion of the pillar is preferably quite large to provide a good starting point for subsequent deposition; moreover, the top portion should allow for the subsequent growth of single-crystal material (especially being flat and smooth). The bottom and / or middle portions are preferably quite narrow to facilitate relatively easy breakage. More details regarding the shape and size of the pillars will be provided later; generally, the pillars are identical or very similar.

[0049] How to control the ratio between vertical and horizontal growth in step B is known to those skilled in the art; typically, this is achieved by controlling the deposition conditions.

[0050] Step B may include one, two or more consecutive deposition steps.

[0051] Although the structure can typically be cooled to room temperature in step C, this is not absolutely necessary. Further processing steps after step C may allow the temperature to be reduced, for example, to only 10%-40% of the growth temperature, provided that the columns (preferably all or most of the columns, e.g., greater than 80%-90%) break.

[0052] As is evident from the description of the embodiments in Figures 1 and 2, it is advantageous to generate pillars through a multi-step etching process of the substrate.

[0053] Such a multi-step etching process may include at least two dry etching steps to properly shape the pillar, particularly to form a necking (118 in FIG. 1) in the middle portion of the pillar; the necking is arranged to fracture under thermal stress according to step C. Preferably, the necking is formed at the same (or approximately the same) depth from the top surface of the substrate, such that the pillar fractures at the same (or approximately the same) location.

[0054] Such a multi-step etching process may include a wet etching step to form a prepared epitaxial surface (119 in Figure 2) at the top portion of the pillar (112 in Figure 1).

[0055] The steps of the method according to the invention are designed such that the epitaxial layer deposited in step B extends only in the region corresponding to the array of pillars. It should be noted that, due to, for example, lateral growth, the region of the epitaxial layer may not precisely correspond to the region occupied by the array of pillars.

[0056] Now refer to Figure 3 There are three columns 300, which correspond to columns 110 in Figures 1 and 2. The shape of the column cross-section will be considered later; for simplicity, we will assume it is circular for now.

[0057] Column 300 can be considered to have a "T-shaped" geometry, in which the wide top 302 is supported by a narrow rod 304; the middle section ( Figure 1A116) is located between the top 302 and the rod 304, and there is a necking in the column at this intermediate part; in fact, in the top part ( Figure 1A 112 in the middle) and the bottom part ( Figure 1A There are multiple intermediate portions 306 between 114). In particular, the cross-sectional area of ​​the rod 304 gradually decreases from the bottom to the intermediate portion, and the cross-sectional area of ​​the top 302 gradually increases from the intermediate portion to the top.

[0058] The size 312 of the top portion can be, for example, in the range of 3 micrometers to 20 micrometers, preferably in the range of 5 micrometers to 10 micrometers.

[0059] The dimension 314 of the distance between the top portions of two consecutive columns can be, for example, in the range of 1 micrometer to 5 micrometers, preferably in the range of 1.5 micrometers to 3 micrometers.

[0060] The size 322 of the middle portion at the neck can be, for example, in the range of 0.2 micrometers to 2 micrometers, preferably in the range of 0.7 micrometers to 1.5 micrometers.

[0061] The size 332 of the bottom portion can be, for example, in the range of 1.5 micrometers to 5 micrometers, preferably in the range of 2 micrometers to 3.5 micrometers.

[0062] The dimension 342 of the height of the top 302 can be, for example, in the range of 1 micrometer to 10 micrometers, preferably in the range of 1.2 micrometers to 5 micrometers.

[0063] The height dimension 344 of rod 304 can be, for example, in the range of 7 micrometers to 30 micrometers, preferably in the range of 9 micrometers to 15 micrometers.

[0064] Therefore, the height of the column can be, for example, in the range of 8 micrometers to 40 micrometers, preferably in the range of 10 micrometers to 20 micrometers.

[0065] Therefore, the distance 334 between the vertical axes of the two consecutive columns can be, for example, in the range of 2.5 micrometers to 15 micrometers, preferably in the range of 4 micrometers to 8 micrometers.

[0066] The cross-sectional shape of the column can be, for example, a square (see example). Figure 8 ), rectangle, pentagon, hexagon (see example) Figure 6 ), circular or elliptical. Typically, the column maintains the same or approximately the same shape along its length, but preferably varies its cross-sectional area.

[0067] In the above description, it has been assumed that the epitaxial layers are not laterally bonded (or largely not laterally bonded), such that when the column fractures, the layers detach from the substrate.

[0068] According to the reference Figure 4 The first possibility that can be better understood is the trench ( Figure 4 (400) is formed in the base as a surrounding column ( Figure 4 The array of 110 in the middle makes the epitaxial layer ( Figure 4 (200 in the text) is laterally unbonded. Typically, trenches surround an array of pillars. For example, during step B, semiconductor material is deposited not only on the pillars but also around them (see...). Figure 4 Mark 230 in the middle) and inside the trench (see mark 230) and inside the trench (see mark 23 Figure 4 (marked 240 in the text); however, due to the depth of the trench, voids remain in the epitaxial layer ( Figure 4 Around 200 in the middle.

[0069] According to the reference Figure 5 A better understanding of the second possibility, the framework of the third material ( Figure 5 500 in the base ( Figure 5 The 100 in the middle is formed around the column ( Figure 5 The array of 110 in the middle makes the epitaxial layer ( Figure 5 The 200 in the middle is loosely and laterally bonded to the frame ( Figure 5 (500 in the text). Typically, the framework surrounds an array of pillars. If the layer material is monocrystalline silicon carbide, the framework material (different from the layer material) can be, for example, amorphous or polycrystalline silicon carbide. For example, during step B, semiconductor material is deposited not only on the pillars but also around them (see 500 in the text). Figure 5 (Mark 500 in the text). According to Figure 5 In one implementation, the deposited material (e.g., silicon carbide) is the same, but the grown material is different; this is due to, for example, a layer 450 of silicon nitride or silicon oxide formed before the frame surrounding the array of pillars.

[0070] Figure 6 An embodiment is shown in which the cross-sectional shape of the pillar is hexagonal; in particular, the designation 600 corresponds to a very thin (e.g., less than 1 micrometer) seed crystal on the pillar that has not yet been fused together to form a patch or layer (see example...). Figure 2F The distance 602 between consecutive seed crystals can be in the range of 1 micrometer to 5 micrometers, preferably in the range of 1.5 micrometers to 3 micrometers.

[0071] Figure 8 An embodiment is shown in which the cross-sectional shape of the pillar is square; in particular, the designation 800 corresponds to a very thin (e.g., less than 1 micrometer) seed crystal on the pillar that has not yet been joined together to form a patch or layer (see example...). Figure 2FThe distance 802 between consecutive seed crystals can be in the range of 1 micrometer to 5 micrometers, preferably in the range of 1.5 micrometers to 3 micrometers.

[0072] Figure 6 and Figure 8 The conceptual similarities between them are obvious.

[0073] Figure 6 and Figure 8 An embodiment is shown, wherein in step A, a set of different and separate arrays of pillars are formed in the substrate so as to form a corresponding set of epitaxial layer patches in step B (see respective embodiments). Figure 7 and Figure 9 , Figure 7 Each patch is labeled 700. Figure 9 Each patch is labeled 900. Figure 6 Three sets of pillars 610, 620 and 630 are shown; their lateral spacing is greater than that of the seed crystal; such a distance 604 can be in the range of 3 micrometers to 10 micrometers, preferably in the range of 5 micrometers to 8 micrometers. Figure 8 Four sets of pillars 810, 820, 830, and 840 are shown; their lateral spacing is greater than that of the seed crystals; such a distance 804 can range from 3 micrometers to 10 micrometers, preferably from 5 micrometers to 8 micrometers. Much longer distances should not be excluded, especially if these patches are considered as separate, independent epitaxial layers.

[0074] Each of these patches (e.g.) Figure 7 700 and Figure 9 The 900 in the image can be an independent epitaxial layer and can be used as a substrate for manufacturing electrical, electronic, or optoelectronic components; in this case, their dimensions should be relatively large, for example, the dimensions 702 of patch 700 and 902 of patch 900 can be in the range of 100 micrometers to 1000 micrometers (e.g., corresponding to the size of a single electrical, electronic, or optoelectronic component). However, processing small patches can be difficult; therefore, for processing purposes, the dimensions mentioned above can be increased.

[0075] Figure 7 and Figure 9 The conceptual similarities between them are obvious.

[0076] patch (e.g.) Figure 7 Patch 700 and Figure 9 Patch 900 can be used as a starting building block or starting component for forming a larger epitaxial layer; in this case, their size should be relatively small, for example, the size 702 of patch 700 and the size 902 of patch 900 can be less than a few hundred micrometers.

[0077] In this case, a set of continuous thin patches is formed through the first step B, such as Figure 7 and Figure 9 As shown in the diagram (such patches can have relatively small thicknesses, for example, in the range of 5-50 micrometers, since they do not need to be "independent"); then, step C can be used to break most of the pillars of each patch. Afterwards, step B is performed to merge the patches and grow thick (e.g., in the range of 50-500 micrometers, preferably in the range of 150-300 micrometers) and wide (e.g., in the range of 1,000-10,000 micrometers, but reaching approximately the size of the entire wafer, or for example, approximately 1 / 2, 1 / 3, 1 / 4, or 1 / 5 of the entire wafer) independent epitaxial layers. Finally, step C can be used to break any remaining pillars.

[0078] As already described, independent epitaxial layers can be formed by the methods of the present invention and arranged to serve as a substrate for manufacturing electrical, electronic, or optoelectronic components, or as a substrate for further epitaxial growth. Such a layer can be considered the final product of the methods of the present invention.

[0079] Typically, independent epitaxial layers can have any size (which must be slightly smaller) and any shape (especially circular or square) that is almost the same size as the initial epoch substrate.

[0080] It should be noted that, for example, if the method of the present invention is stopped immediately after step A, or immediately after step B, or immediately after step C (especially if the epitaxial layer is not completely separated from the disposable substrate), the method of the present invention forms an intermediate product.

Claims

1. A method for generating independent epitaxial layers (200) starting from a deployable substrate (100), The epitaxial layer (200) is made of a first semiconductor material. The substrate (100) is made of a second semiconductor material. The first semiconductor material is different from the second semiconductor material. The CTE of the first semiconductor material is different from the CTE of the second semiconductor material. The method includes the following steps: A) The substrate (100) is patterned by a multi-step etching process to form an array of pillars (110) that are laterally spaced apart from each other and have a top portion (112) that is larger than the bottom portion (114) and / or the middle portion (116). B) Deposit the second semiconductor material on the top of the pillar (110) at the growth temperature to form an epitaxial layer (200) generated by vertical and lateral growth of the second semiconductor material, and C) Inducing fracture of the pillar (110) by cooling the substrate (100) and the epitaxial layer (200) to below the growth temperature; The multi-step etching process includes at least two dry etching steps to form a neck (118) at the middle portion of the pillar (110).

2. The method according to claim 1, The neck (118) is formed at the same depth as the top surface of the substrate (100), and the neck (118) is arranged to fracture under thermal stress according to step C.

3. The method according to claim 1, The multi-step etching process includes a wet etching step to form a prepared epitaxial surface at the top portion (112).

4. The method according to claim 2, The multi-step etching process includes a wet etching step to form a prepared epitaxial surface at the top portion (112).

5. The method according to any of the preceding claims, wherein the epitaxial layer (200) extends only in the region corresponding to the array of pillars (110).

6. The method according to any one of claims 1 to 4, The array surrounding the pillar (110) forms trenches (400) in the substrate (100), such that the epitaxial layer (200) is laterally unbonded.

7. The method according to claim 5, The array surrounding the pillar (110) forms trenches (400) in the substrate (100), such that the epitaxial layer (200) is laterally unbonded.

8. The method according to any one of claims 1 to 4, The array surrounding the pillar (110) forms a framework (500) of a third material on the substrate (100), such that the epitaxial layer (200) is loosely and laterally bonded to the framework (500).

9. The method according to claim 5, The array surrounding the pillar (110) forms a framework (500) of a third material on the substrate (100), such that the epitaxial layer (200) is loosely and laterally bonded to the framework (500).

10. The method according to any one of claims 1-4, 7 and 9, Step B includes two or more consecutive deposition steps.

11. The method according to claim 5, Step B includes two or more consecutive deposition steps.

12. The method according to claim 6, Step B includes two or more consecutive deposition steps.

13. The method according to claim 8, Step B includes two or more consecutive deposition steps.

14. The method according to any one of claims 1-4, 7, 9 and 11-13, In step A, an array of different and separate pillars is formed in the substrate so that an epitaxial layer patch can be formed in step B.

15. The method according to claim 5, In step A, an array of different and separate pillars is formed in the substrate so that an epitaxial layer patch can be formed in step B.

16. The method according to claim 6, In step A, an array of different and separate pillars is formed in the substrate so that an epitaxial layer patch can be formed in step B.

17. The method according to claim 8, In step A, an array of different and separate pillars is formed in the substrate so that an epitaxial layer patch can be formed in step B.

18. The method according to claim 10, In step A, an array of different and separate pillars is formed in the substrate so that an epitaxial layer patch can be formed in step B.

19. The method according to claim 14, Steps B and C are repeated to merge the set of epitaxial layer patches and form a single independent epitaxial layer.

20. The method according to any one of claims 15-18, Steps B and C are repeated to merge the set of epitaxial layer patches and form a single independent epitaxial layer.

21. The method according to any one of claims 1-4, 7, 9, 11-13, and 15-19, It also includes the following steps: D) After step C, apply force or torque to detach the epitaxial layer (200) from the substrate (100).

22. The method according to claim 5, It also includes the following steps: D) After step C, apply force or torque to detach the epitaxial layer (200) from the substrate (100).

23. The method according to claim 6, It also includes the following steps: D) After step C, apply force or torque to detach the epitaxial layer (200) from the substrate (100).

24. The method according to claim 8, It also includes the following steps: D) After step C, apply force or torque to detach the epitaxial layer (200) from the substrate (100).

25. The method according to claim 10, It also includes the following steps: D) After step C, apply force or torque to detach the epitaxial layer (200) from the substrate (100).

26. The method according to claim 14, It also includes the following steps: D) After step C, apply force or torque to detach the epitaxial layer (200) from the substrate (100).

27. The method according to claim 20, It also includes the following steps: D) After step C, apply force or torque to detach the epitaxial layer (200) from the substrate (100).

28. The method according to any one of claims 1-4, 7, 9, 11-13, 15-19, and 22-27, It also includes the following steps: E) After step C or step D, grind the back side of the epitaxial layer (200).

29. The method according to claim 5, It also includes the following steps: E) After step C or step D, grind the back side of the epitaxial layer (200).

30. The method according to claim 6, It also includes the following steps: E) After step C or step D, grind the back side of the epitaxial layer (200).

31. The method according to claim 8, It also includes the following steps: E) After step C or step D, grind the back side of the epitaxial layer (200).

32. The method according to claim 10, It also includes the following steps: E) After step C or step D, grind the back side of the epitaxial layer (200).

33. The method according to claim 14, It also includes the following steps: E) After step C or step D, grind the back side of the epitaxial layer (200).

34. The method according to claim 20, It also includes the following steps: E) After step C or step D, grind the back side of the epitaxial layer (200).

35. The method according to claim 21, It also includes the following steps: E) After step C or step D, grind the back side of the epitaxial layer (200).

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