Multi-chip packaging structure, manufacturing method and electronic device

Abstract

A multi-chip packaging structure (300, 400, 500, 600), a manufacturing method, and an electronic device can improve the flexibility of the multi-chip packaging to further achieve miniaturization of electronic device packaging. The packaging structure (300, 400) comprises, from top to bottom, a first bare chip layer (301), a second bare chip layer (302), and a third bare chip layer (303); a plurality of hybrid bonding structures (305) are provided between the first bare chip layer (301) and the second bare chip layer (302); a plurality of TSVs (307) penetrating the second bare chip layer (302) are provided in the second bare chip layer (302); and a plurality of solder bumps (306) are provided between the third bare chip layer (303) and the second bare chip layer (302).

Description

Technical Field

[0001] The present application relates to the field of electronic packaging, and in particular to a multi-chip packaging structure, a manufacturing method, and an electronic device. Background Art

[0002] In recent years, with the trend of miniaturization and portability of devices, chip packaging technology has gradually been moving towards 3D stacking. Traditional 2D chips set the modules on a planar layer, while 3D chips allow multi-layer stacking, providing vertical signal connections for multiple bare chips (dies) through silicon vias (TSV). 3D packaging technology can be used for microsystem integration, usually in the form of a system-in-package (SIP). As an example, the application areas of 3D packaging technology can include image sensors, memory, etc.

[0003] Although 3D packaging technology is currently a hot development direction in the industry, it also faces the problem of balancing area, cost, and performance. For example, in order to ensure smooth electrical connection between the various chips in the 3D package, the process and size of the chips in each layer of the 3D package must be consistent, and a wafer-to-wafer (W2W) connection method must be adopted. This connection method requires a higher yield, and a higher yield usually requires the use of a more traditional process node. Because the more traditional the process node, the fewer functions the chip provides in the same area and the greater the power consumption, resulting in lower flexibility and higher cost of 3D packaging. In addition, due to the limited functions that can be implemented by the traditional 3D packaging structure, some functions need to rely on the system on chip (SOC). A large number of signals will be transmitted to the SOC through the motherboard for processing. This signal processing method is limited by the motherboard bandwidth and the SOC processing power, thereby reducing the efficiency of data processing and increasing the load on the SOC. Summary of the Invention

[0004] The present application provides a multi-chip packaging structure, a manufacturing method and an electronic device, which can solve at least one of the above-mentioned shortcomings.

[0005] In a first aspect, a multi-chip packaging structure is provided, which includes, from top to bottom, a first bare chip layer, a second bare chip layer and a third bare chip layer, wherein the first bare chip layer includes at least one first bare chip, the second bare chip layer includes at least one second bare chip, and the third bare chip layer includes at least one third bare chip; wherein a plurality of hybrid bonding structures are arranged between the first bare chip layer and the second bare chip layer, so that the first bare chip layer and the second bare chip layer are electrically connected through at least one hybrid bonding structure; a plurality of through silicon vias (TSVs) penetrating the second bare chip layer are arranged in the second bare chip layer, a plurality of solder bumps are arranged between the third bare chip layer and the second bare chip layer, and the first bare chip layer and the third bare chip layer are electrically connected through at least one hybrid bonding structure, at least one TSV electrically connected to the at least one hybrid bonding structure, and at least one solder bump electrically connected to the at least one TSV.

[0006] The first bare chip layer and the second bare chip layer are connected using hybrid bonding. The third bare chip layer is connected to the second bare chip layer via solder bumps. The first bare chip layer and the third bare chip layer are electrically connected via a hybrid bonding structure, multiple TSVs, and multiple solder bumps. The combination of hybrid bonding, solder bumps, and TSVs enables stacked packaging of different processes and different chips. The use of solder bumps can support the packaging of bare chips of different sizes and processes in the second and third bare chip layers, thereby increasing the flexibility of multi-chip packaging and further achieving miniaturization of electronic device packaging.

[0007] Optionally, the third bare chip layer utilizes a process with smaller feature sizes than the first and second bare chip layers. Optionally, the third bare chip layer includes circuits for edge computing. Further, optionally, the package structure is applied to an image sensor, the first bare chip layer includes a chip with an optical device, and the second bare chip layer includes a logic chip.

[0008] In a multi-chip package structure, the third die layer utilizes a process with smaller feature sizes than the first and second die layers, resulting in a smaller area and the ability to integrate more functions. Because the third die layer's area and process differ from those of the other die layers, the third and second die layers are connected using solder bumps. In this package structure, the third die layer can include circuitry that provides edge computing capabilities. Edge computing refers to information processing at the signal acquisition end. Therefore, the package structure can process at least some signals locally, reducing the amount of data transmitted to and from the SOC. Furthermore, since it is no longer constrained by transmission bandwidth, the efficiency of local data processing within the multi-chip package structure can be improved, while also reducing power consumption. In existing technologies, edge computing functions rely on the SOC, with signals transmitted via the motherboard to the main SOC for processing. This signal processing approach is limited by the motherboard's bandwidth and the SOC's processing capabilities. Furthermore, all signals must be transmitted to the SOC, increasing the signal transmission volume and the SOC's load. On the contrary, in the technical solution of the present application, the third bare chip layer may include circuits that provide edge computing functions, and a large amount of data is processed quickly locally, reducing the load of the SOC and the amount of signal transmission; more importantly, a large amount of data is processed locally, which is not limited by the SOC transmission bandwidth and is more efficient.

[0009] Optionally, the multi-chip package structure may also include more than three layers of bare chips.

[0010] In combination with the first aspect, in a possible implementation, it further includes a metal layer arranged in the second bare chip layer, the multiple TSVs are electrically connected to the metal layer, and the first bare chip layer and the third bare chip layer are electrically connected through at least one hybrid bonding structure, the metal layer electrically connected to the at least one hybrid bonding structure, at least one TSV electrically connected to the metal layer, and at least one solder bump electrically connected to the at least one TSV.

[0011] In combination with the first aspect, in a possible implementation, the second bare chip layer and the third bare chip layer are electrically connected through the metal layer, at least one TSV electrically connected to the metal layer, and at least one solder bump electrically connected to the at least one TSV.

[0012] The third bare chip layer is connected to the second bare chip layer via solder bumps, metal layers, and TSVs. This hybrid bonding structure, combined with solder bumps, metal layers, and TSVs, enables stacked packaging of chips using different process technologies. This allows for packaging bare chips of varying sizes and process technologies, enhancing the flexibility of multi-chip packaging.

[0013] In combination with the first aspect, in one possible implementation, the third bare chip layer includes two third bare chips, and the two third bare chips are electrically connected in sequence through at least one solder bump, at least one TSV electrically connected to the at least one solder bump, the metal layer electrically connected to the at least one TSV, at least one other TSV electrically connected to the metal layer, and at least one other solder bump electrically connected to the at least one other TSV.

[0014] The at least one solder bump and the at least one other solder bump respectively correspond to different third bare chips.

[0015] Optionally, the third bare chip layer may include a plurality of third bare chips, and the two third bare chips may be any two third bare chips among the plurality of third bare chips.

[0016] In combination with the first aspect, in a possible implementation, a redistribution layer RDL is provided in the second bare chip layer, and the first bare chip layer and the third bare chip layer are electrically connected through at least one hybrid bonding structure, at least one TSV electrically connected to the at least one hybrid bonding structure, the RDL electrically connected to the at least one TSV, and at least one solder bump electrically connected to the RDL.

[0017] By setting RDL in the second bare chip layer, signal transmission can be achieved between the second bare chip layer and the third bare chip layer, or between multiple third bare chips in the third bare chip layer through RDL, thereby reducing the need to set TSV in the second bare chip layer, saving TSV process steps and area overhead, improving signal bandwidth and signal quality, and improving chip heat dissipation.

[0018] Optionally, RDL can be implemented using polyimide, or copper interconnection can be implemented using a Damascus process, or aluminum interconnection can be used. The above materials can reduce product costs and have strong power supply capabilities.

[0019] Optionally, when the multi-chip package structure is used in scenarios with higher signal frequency requirements, an RDL can be provided in the second bare chip layer. When the multi-chip package structure is used in scenarios with lower signal frequency requirements, an RDL may not be required to reduce process costs and design complexity.

[0020] In combination with the first aspect, in a possible implementation manner, the second bare chip layer and the third bare chip layer are electrically connected via the RDL and at least one solder bump electrically connected to the RDL.

[0021] In combination with the first aspect, in one possible implementation, the third bare chip layer includes two third bare chips, and the two third bare chips are electrically connected to each other through at least one solder bump, the RDL electrically connected to the at least one solder bump, and at least one other solder bump electrically connected to the RDL.

[0022] In combination with the first aspect, in one possible implementation, the multiple TSVs are electrically connected to the metal layer provided in the second bare chip layer, and the first bare chip layer and the third bare chip layer are electrically connected through at least one hybrid bonding structure, the metal layer electrically connected to the at least one hybrid bonding structure, at least one TSV electrically connected to the metal layer, the RDL electrically connected to the at least one TSV, and at least one solder bump electrically connected to the at least one TSV.

[0023] In combination with the first aspect, in one possible implementation, the first bare chip layer includes any one of the following types of chips: a chip provided with an optical device; a chip provided with a static random access memory SRAM; a chip provided with a dynamic random access memory DRAM; a chip provided with an application-specific integrated circuit ASIC; a logic chip, wherein the logic chip is provided with an algorithm processing circuit.

[0024] In combination with the first aspect, in a possible implementation, the second bare chip layer includes any one of the following types of chips: a chip provided with SRAM; a chip provided with DRAM; a chip provided with ASIC; a logic chip, wherein the logic chip is provided with an algorithm logic circuit.

[0025] In combination with the first aspect, in a possible implementation, the third bare chip layer includes any one of the following types of chips: a chip provided with ASIC; a chip provided with DRAM; a chip provided with SRAM; a logic chip, wherein the logic chip is provided with an algorithm logic circuit.

[0026] In a second aspect, a method for manufacturing a multi-chip packaging structure is provided, wherein the packaging structure comprises, from top to bottom, a first bare chip layer, a second bare chip layer and a third bare chip layer, wherein the first bare chip layer includes at least one first bare chip, the second bare chip layer includes at least one second bare chip, and the third bare chip layer includes at least one third bare chip, and the method comprises: obtaining the first bare chip layer and the second bare chip layer; adding the hybrid bonding structure on the metal layer of the first bare chip layer and the metal layer of the second bare chip layer, respectively; docking the first bare chip layer and the second bare chip layer so that the first bare chip layer and the second bare chip layer are electrically connected through the hybrid bonding structure; obtaining the third bare chip layer; preparing solder bumps on the surface of the third bare chip layer and the surface of the second bare chip layer, respectively; docking the solder bumps of the third bare chip layer and the solder bumps of the second bare chip layer to achieve electrical connection between the second bare chip layer and the third bare chip layer through the solder bumps.

[0027] The first bare chip layer and the second bare chip layer are connected using hybrid bonding. The third bare chip layer is connected to the second bare chip layer via solder bumps. The first bare chip layer and the third bare chip layer are electrically connected via a hybrid bonding structure, multiple TSVs, and multiple solder bumps. The combination of hybrid bonding, solder bumps, and TSVs enables stacked packaging of different processes and different chips. The use of solder bumps can support the packaging of bare chips of different sizes and processes in the second and third bare chip layers, thereby increasing the flexibility of multi-chip packaging and further achieving miniaturization of electronic device packaging.

[0028] Optionally, the third bare chip layer uses a process with smaller feature sizes than the first and second bare chip layers, and the third bare chip layer includes circuits for edge computing. Further optionally, the package structure is applied to an image sensor, the first bare chip layer includes a chip with an optical device, and the second bare chip layer includes a logic chip.

[0029] In the manufacturing method of the multi-chip packaging structure, the characteristic size of the process used by the third bare chip layer is smaller than that of the first bare chip layer and the second bare chip layer, its area is smaller, and more functions can be integrated. Therefore, since the area and process of the third bare chip layer are different from those of the other bare chip layers, the third bare chip layer and the second bare chip layer are connected using solder bumps. Under this packaging form, the third bare chip layer can include a circuit that provides edge computing functions. Edge computing refers to a way of processing information at the signal acquisition end. Therefore, the packaging structure can process at least part of the signal locally, which can reduce the amount of data transmission between the SOC and the SOC. And because it is no longer affected by the transmission bandwidth, it can improve the efficiency of the multi-chip packaging structure in processing data locally.

[0030] In combination with the second aspect, in a possible implementation, the method further includes: fabricating a plurality of TSVs penetrating the second bare chip layer in the second bare chip layer.

[0031] In combination with the second aspect, in one possible implementation, multiple TSVs running through the second bare chip layer are produced in the second bare chip layer, including preparing the multiple TSVs using any one of the following processes: a first TSV process, an intermediate TSV process, or a last TSV process.

[0032] In combination with the second aspect, in a possible implementation, a redistribution layer (RDL) is fabricated on the surface of the second bare chip layer, and the RDL is connected to the metal layer of the second bare chip layer through at least one TSV in the second bare chip layer.

[0033] In combination with the second aspect, in a possible implementation, the preparing solder bumps on the surface of the third bare chip layer and the surface of the second bare chip layer respectively includes: making the solder bumps on the surface of the third bare chip layer and the RDL layer of the second bare chip layer respectively, so as to achieve electrical connection between the third bare chip layer and the second bare chip layer through the solder bumps and the RDL.

[0034] In combination with the second aspect, in a possible implementation, it also includes: after docking the first bare chip layer and the second bare chip layer, thinning the substrate of the first bare chip layer; and preparing an optical functional structure on the substrate of the first bare chip layer.

[0035] In a third aspect, an electronic device is provided, wherein the electronic device is provided with the multi-chip packaging structure as described in the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1FIG. 1 is a schematic structural diagram of a bare chip connected by fusion bonding (FB) according to an embodiment of the present application.

[0037] Figure 2 FIG. 1 is a schematic structural diagram of bare chips connected by hybrid bonding (HB) according to an embodiment of the present application.

[0038] Figure 3 FIG. 3 is a schematic diagram of a multi-chip package structure 300 according to an embodiment of the present application.

[0039] Figure 4 FIG. 4 is a schematic diagram of a multi-chip package structure 400 according to an embodiment of the present application.

[0040] Figure 5 yes Figure 3 FIG. 3 is a schematic diagram of a specific application of a multi-chip package structure 300 .

[0041] Figure 6 yes Figure 4 FIG. 4 is a schematic diagram of a specific application of a multi-chip package structure 400 .

[0042] Figure 7 yes Figure 3 Schematic diagram of signal transmission paths of a multi-chip package structure 300.

[0043] Figure 8 yes Figure 4 Schematic diagram of signal transmission paths of a multi-chip package structure 400.

[0044] Figure 9 FIG. 1 is a cross-sectional schematic diagram of a manufacturing process of a multi-chip package structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in this application will be described below in conjunction with the accompanying drawings. First, several terms involved in the embodiments of this application will be introduced.

[0046] An image sensor is an electronic device that uses the photoelectric conversion function of a photoelectric device to convert the light image on a photosensitive surface into an electrical signal proportional to the light image. In other words, it is a device that converts optical images into electronic signals and is widely used in digital cameras and other electro-optical devices. Image sensor products include charge-coupled devices (CCDs) and complementary metal oxide semiconductor image sensors (CMOS image sensors, CISs).

[0047] Static random-access memory (SRAM): A type of random-access memory that retains stored data permanently as long as the SRAM remains powered.

[0048] Dynamic random-access memory (DRAM): A type of random-access memory that stores data that needs to be updated periodically.

[0049] CIS: refers to an image sensor implemented using CMOS technology.

[0050] Application specific integrated circuit (ASIC): An application specific integrated circuit is an integrated circuit designed to meet specific user requirements and the needs of a specific electronic system. In the embodiments of this application, an ASIC chip may also be referred to as a custom logic chip.

[0051] Wafer: refers to the silicon chip used to make silicon semiconductor integrated circuits.

[0052] Bare chip (die): A chip before packaging can be called a bare chip. A bare chip can refer to an entire wafer or a single chip obtained by dicing a wafer. In the embodiments of this application, the front side of a bare chip is also called the active side or active surface, which refers to the side of the bare chip used to grow active devices. The back side of a bare chip refers to the side facing the substrate.

[0053] Chip: can refer to a chip before packaging or a chip after packaging. In the embodiments of the present application, the definition of chip includes bare chips (die).

[0054] Fusion bonding (FB) refers to bonding two bare chips (dies) that need to be packaged together and have a signal connection relationship through a dielectric layer. For example, the dielectric layer can be silicon dioxide (SiO2).

[0055] Figure 1 FIG. 1 is a schematic structural diagram of a bare chip connected by fusion bonding (FB) in one embodiment of the present application. Figure 1 As shown in the figure, the upper bare die (Die 1) and the lower bare die (Die 2) can be physically connected through the dielectric layer through fusion bonding. It should be noted that fusion bonding (FB) is only used to achieve physical connection, and TSV is usually required to pass through the bonding interface to achieve electrical connection.

[0056] Front end of the line (FEOL): also known as integrated circuit front-end process, is the first part of the process steps of integrated circuits, covering all processes until the deposition of metal interconnection layers.

[0057] Back-end of the line (BEOL): Also known as integrated circuit back-end process, it refers to the metal interconnects that form the components of an integrated circuit (IC) process. BEOL typically includes one or more metal layers.

[0058] Hybrid bonding (HB) involves connecting two bare chips with signal connections through chemical bonding. Hybrid bonding involves placing both metal and insulator at the die's bonding interface. During the bonding process, the metal and insulator at the two die's bonding interfaces are aligned, and bonding is performed under specific temperature conditions.

[0059] Figure 2 FIG. 1 is a schematic diagram of the structure of a bare chip connected by hybrid bonding (HB) in one embodiment of the present application. Figure 2 As shown, the BEOL of the upper bare chip (die 1) and the BEOL of the lower bare chip (die 2) are chemically bonded via a dielectric layer comprising copper (Cu) and an insulating material.

[0060] Face to back (F2B): refers to connecting the back side of the first die to the front side of the second die.

[0061] Face to face (F2F): refers to connecting the front side of the first bare chip to the front side of the second bare chip.

[0062] Back to back (B2B): refers to connecting the back side of the first bare chip to the back side of the second bare chip.

[0063] Substrate: Also known as packaging substrate, it is used to mechanically protect and support the chip and realize the electrical connection between the chip and the outside world. The substrate can include a metal substrate, a ceramic substrate or an organic substrate.

[0064] A carrier wafer: A carrier wafer provides support for subsequent steps in the semiconductor manufacturing process and is typically removed after use. For example, thin wafers can be supported using a carrier wafer. Carrier wafers can be made of glass or silicon-based materials.

[0065] Solder bumps are spheres that connect bare chips to bare chips, or to bare chips and substrates. They can be made of conductive materials such as copper or tin. It should be noted that these solder bumps can include micro-bumps (Ubumps).

[0066] Redistribution layer: This layer can refer to the connecting wires between the die pads and solder bumps. This layer is typically fabricated using a damascene process, or it can be made from a polymer. The damascene process is a copper patterning process used in integrated circuit manufacturing. The polymer can be, for example, polyimide.

[0067] In multi-chip packaging solutions implemented through fusion bonding (FB) and through-silicon via (TSV) technology, signal transmission between multiple dies must be fully utilized using TSVs. This solution requires that the die sizes within multiple chip layers be identical, and cannot accommodate dies of different sizes or produced using different processes, thus limiting the flexibility of multi-chip packaging.

[0068] In this context, embodiments of the present application propose a multi-chip packaging structure and electronic device. This packaging structure provides a packaging method for a three-dimensional chip stack product. Through a combination of hybrid bonding, solder bumps, and TSVs, it enables multi-layer stacking of chips using different processes. This solution supports packaging bare chips of varying sizes and process sizes, improves the flexibility of multi-chip packaging, and facilitates the miniaturization of multi-chip packaged devices.

[0069] The multi-chip packaging structure of the embodiment of the present application can be applied to the fields of image sensors, memory, etc. The multi-chip packaging structure can be applied to electronic devices that are equipped with image sensors, memory, or chips with other functions.

[0070] Figure 3 FIG. 3 is a schematic diagram of a multi-chip package structure 300 according to an embodiment of the present application. The multi-chip package structure 300 is a multi-chip vertical stacking package structure. Figure 3 As shown, the multi-chip package structure 300 includes three bare chip layers, which are a first bare chip layer 301 , a second bare chip layer 302 and a third bare chip layer 303 from top to bottom.

[0071] Optionally, the first die layer 301 may include one or more first die 301-1, the second die layer 302 may include one or more second die 302-1. The third die layer 303 may include one or more third die. As an example, Figure 3In the description, the third bare chip layer 303 including two third bare chips (303-1, 303-2) is taken as an example. It should be understood that the third bare chip layer 303 may include more or fewer bare chips.

[0072] The third die layer 303 may have a smaller feature size than the first die layer 301 and the second die layer 302. The third die layer 303 may include circuits for performing edge computing, which is a method of processing information at the signal acquisition end.

[0073] The above-mentioned feature size refers to the minimum size used in semiconductor processes. For example, the feature size used in the first bare chip layer 301 and the second bare chip layer 302 may be 18 nanometers (nm), while the feature size used in the process of the third bare chip layer may be 7 nm.

[0074] It should be understood that the smaller the feature size of a semiconductor process, the more functions it can provide within the same area.

[0075] A plurality of hybrid bonding structures 305 are disposed between the first bare chip layer 301 and the second bare chip layer 302 to support electrical connection between the first bare chip layer 301 and the second bare chip layer 302 using the hybrid bonding (HB) structure 305 .

[0076] The hybrid bonding structure 305 connects the first bare chip layer 301 and the second bare chip layer 302, which have a signal connection relationship, by chemical bonding. The specific structure of the hybrid bonding structure 305 can be found in the description of hybrid bonding (HB) and Figure 2 The content will not be repeated here.

[0077] Optionally, the first bare chip layer 301 and the second bare chip layer 302 may be hybrid bonded in a face-to-face (F2F), face-to-back (F2B) or back-to-back (B2B) manner.

[0078] It should be understood that the first bare chip layer 301 and the second bare chip layer 302 can be manufactured using the same process. Therefore, the first bare chip layer 301 and the second bare chip layer 302 are connected using a wafer-to-wafer (W2W) method. Wafer-to-wafer connection refers to a process flow in which two chips are electrically connected in the wafer state, and then cut into multiple units in a subsequent process.

[0079] The second bare chip layer 302 is provided with a plurality of through-silicon vias (TSVs) 307 penetrating the second bare chip layer 302, and a plurality of solder bumps 306 are provided between the third bare chip layer 303 and the second bare chip layer 302. The first bare chip layer 301 and the third bare chip layer 303 are electrically connected via at least one hybrid bonding structure 305, at least one TSV 307 electrically connected to the at least one hybrid bonding structure 305, and at least one solder bump 306 electrically connected to the at least one TSV 307.

[0080] The second bare chip layer 302 and the third bare chip layer 303 may be electrically connected via at least one solder bump 306 .

[0081] In an embodiment of the present application, the characteristic size of the process used by the third bare chip layer 303 is smaller than that of the first bare chip layer 301 and the second bare chip layer 302, and its area is smaller and can integrate more functions. In view of the situation where the area and process of the third bare chip layer 303 are different from those of other bare chip layers, the third bare chip layer 303 and the second bare chip layer 302 are connected using solder bumps. In this packaging form, the third bare chip layer 303 can include a circuit that provides edge computing functions. Edge computing refers to a calculation that processes information at the signal acquisition end. Therefore, the packaging structure can process at least part of the signal locally, which can reduce the amount of data transmission between the SOC and the SOC. And because it is no longer affected by the transmission bandwidth, it can improve the efficiency of the multi-chip packaging structure in processing data locally.

[0082] Since the third bare chip layer 303 adopts a more advanced process, the third bare chip layer 303 can provide more functions than the other two bare chip layers, such as raw signal clipping, compression, artificial intelligence (AI), etc., and has lower power consumption and faster processing speed. In the prior art, these functions need to rely on SOC to complete, and the signal needs to be transmitted to the main chip SOC through the motherboard and then processed. This signal processing method is limited by the motherboard bandwidth and SOC processing power. And since the signals need to be transmitted to the SOC, the signal transmission volume and the load of the SOC are increased. In an embodiment of the present application, the third bare chip layer 303 is integrated into the multi-chip packaging structure, and a large amount of data can be quickly processed locally through edge computing, reducing the load of the SOC and the signal transmission volume. In addition, the data is processed locally, is not limited by the transmission bandwidth, and is more efficient.

[0083] Furthermore, the third bare chip layer 303 can also be used to support functions that are not possible with traditional 3D packaging technology. For example, for image sensor chips, edge computing can pre-merge and compress multiple frames of images before transmitting them to the SOC via the motherboard, thereby reducing the amount of data transmitted by the motherboard. This means that the image acquisition frequency or resolution is increased under the same motherboard bandwidth, enabling high-definition slow-motion photography.

[0084] In an embodiment of the present application, the first bare chip layer 301 and the second bare chip layer 302 are connected by hybrid bonding (HB). The third bare chip layer 303 and the second bare chip layer 302 are connected by solder bumps 306. The first bare chip layer 301 and the third bare chip layer 303 are electrically connected by a hybrid bonding structure 305, at least one TSV 307 and at least one solder bump 306. Through the combination of the hybrid bonding structure, solder bumps and TSVs, stacking packaging between different processes and different chips is achieved. Among them, the use of solder bumps 306 can support the second bare chip layer 302 and the third bare chip layer 303 to encapsulate bare chips of different sizes and processes, which can improve the flexibility of multi-chip packaging.

[0085] In addition, placing a large number of TSVs in a bare chip will limit signal bandwidth and increase area consumption, as well as affect signal integrity and poor heat dissipation. In the embodiment of the present application, signal transmission is achieved between the first bare chip layer 301 and the second bare chip layer 302 through hybrid bonding, thereby reducing the number of TSVs in the first bare chip layer 301. This can save TSV process steps and area overhead, improve signal bandwidth and signal quality, and enhance chip heat dissipation.

[0086] Optionally, a metal layer 309 is further provided in the second bare chip layer 302, and the metal layer 309 is interconnected, or electrically connected, to the plurality of TSVs 307. The metal layer 309 may belong to the BEOL, ie, the metal interconnection portion in the back-end process of the integrated circuit.

[0087] In some examples, the second die layer 302 and the third die layer 303 are electrically connected via a metal layer 309 , at least one TSV 307 electrically connected to the metal layer 309 , and at least one solder bump 306 electrically connected to the at least one TSV.

[0088] In some examples, if the third bare chip layer 303 includes multiple third bare chips ( 303 - 1 , 303 - 2 ), the multiple third bare chips ( 303 - 1 , 303 - 2 ) are electrically connected via multiple solder bumps 306 , multiple TSVs 307 , and a metal layer 309 .

[0089] For example, the two third bare chips (303-1, 303-2) are electrically connected in sequence through at least one solder bump 306, at least one TSV307 electrically connected to the at least one solder bump 306, the metal layer 309 electrically connected to the at least one TSV307, at least one other TSV307 electrically connected to the metal layer 309, and at least one other solder bump 306 electrically connected to the at least one other TSV307.

[0090] The at least one solder bump 306 and the at least one other solder bump 306 correspond to different third bare chips ( 303 - 1 , 303 - 2 ), respectively.

[0091] Optionally, the third bare chip layer 303 may include a plurality of third bare chips ( 303 - 1 , 303 - 2 ), and the two third bare chips ( 303 - 1 , 303 - 2 ) may be any two third bare chips among the plurality of third bare chips ( 303 - 1 , 303 - 2 ).

[0092] In the embodiment of the present application, the third bare chip layer 303 is connected to the second bare chip layer 302 via solder bumps 306, metal layer 309, and TSVs 307. The combination of hybrid bonding structure 305, solder bumps 306, metal layer 309, and TSVs 307 enables stacked packaging of chips using different processes. This allows for packaging of bare chips of varying sizes and process sizes, improves the flexibility of multi-chip packaging, and facilitates the miniaturization of electronic devices.

[0093] In some examples, the hybrid bonding method is suitable for scenarios where the electrical connections between bare chips are relatively dense, and the solder bump connection method is suitable for scenarios where the electrical connections between bare chips are relatively few.

[0094] Optionally, the multi-chip package structure 300 in the embodiment of the present application may also include more than three bare chip layers, which is not limited in the embodiment of the present application.

[0095] As an example, the first bare chip layer 301 may include any of the following types of chips: a chip with an optical device; a chip with an SRAM; a chip with a DRAM; a chip with an ASIC; or a logic chip. The logic chip may include a general logic chip or a chip with an algorithm processing circuit.

[0096] As an example, the second bare chip layer 302 includes any one of the following types of chips: a chip provided with SRAM; a chip provided with DRAM; a chip provided with ASIC; or a logic chip.

[0097] As an example, the third bare chip layer 303 includes any of the following types of chips: a logic chip, an ASIC chip, or a memory chip. The logic chip may include a general-purpose logic chip or other types of logic chips. The ASIC chip may include, for example, an image processing chip. The memory chip may include a DRAM chip, an SRAM chip, or other types of memory chips.

[0098] In some examples, if the multi-chip package structure 300 is applied to an image sensor, the first bare chip layer 301 may be a chip provided with an optical device. The above-mentioned optical device may include a micro lens or other types of photosensitive circuits. The second bare chip layer 302 may be a logic chip, which may include an algorithm logic unit for processing images. The third bare chip layer 303 may include an ASIC chip. The ASIC chip may, for example, include an image processing chip. Alternatively, the third bare chip layer 303 may include a circuit that provides edge computing functions. As previously described, a large amount of data can be processed quickly locally, which can reduce the amount of data transmission between the SOC and the prior art, and because it is no longer affected by the transmission bandwidth, the efficiency of the multi-chip package structure in processing data locally can be improved.

[0099] In some examples, if the multi-chip package structure 300 is applied to a memory device, the first bare chip layer 301 may be an SRAM chip, a DRAM chip, or another type of memory chip. The second bare chip layer 302 may be a logic chip. The third bare chip layer 303 may include one or more ASIC chips. Optionally, the positions of the first bare chip layer 301 and the second bare chip layer 302 may be interchanged. For example, the first bare chip layer 301 may include a logic chip, and the second bare chip layer 302 may include an SRAM chip, a DRAM chip, or another type of memory chip.

[0100] Optionally, the chip types in the first bare chip layer 301 to the third bare chip layer 303 are only examples, and other types of chips may also be provided in the three layers of bare chips.

[0101] Figure 4 FIG. 4 is a schematic diagram of a multi-chip package structure 400 according to another embodiment of the present invention. Figure 3 , Figure 4 The back side of the second bare chip layer 302 in the multi-chip package structure 400 is provided with a redistribution layer RDL 308. RDL 308 can be interconnected with TSV 307, or electrically connected. RDL 308 can also be electrically connected to solder bumps 306 provided between the second bare chip layer 302 and the third bare chip layer 303. For simplicity, Figure 4 and Figure 3 The same or similar parts will not be described again.

[0102] like Figure 4 As shown, the first bare chip layer 301 and the third bare chip layer 303 are electrically connected through at least one hybrid bonding structure 305 , at least one TSV 307 electrically connected to the 305 , an RDL 308 electrically connected to the at least one TSV 307 , and a plurality of solder bumps 306 .

[0103] The second bare chip layer 302 and the third bare chip layer 303 are electrically connected via the RDL 308 and a plurality of solder bumps 306 .

[0104] In some examples, if the third bare chip layer 303 includes multiple bare chips ( 303 - 1 , 303 - 2 ), the multiple bare chips ( 303 - 1 , 303 - 2 ) are electrically connected to each other via multiple solder bumps 306 , RDL 308 , and multiple solder bumps 306 in sequence.

[0105] For example, the third bare chip layer 303 includes two third bare chips (303-1, 303-2), and the two third bare chips (303-1, 303-2) are electrically connected to each other through at least one solder bump 306, the RDL308 electrically connected to the at least one solder bump 306, and at least one other solder bump 306 electrically connected to the RDL308.

[0106] The at least one solder bump 306 and the at least one other solder bump 306 correspond to different third bare chips ( 303 - 1 , 303 - 2 ), respectively.

[0107] Optionally, a metal layer 309 is provided in the second bare chip layer 302 , and the metal layer 309 is interconnected with, or electrically connected to, the plurality of TSVs 307 .

[0108] In some examples, the first bare chip layer 301 and the third bare chip layer 303 are electrically connected via a hybrid bonding structure 305 , a metal layer 309 , a plurality of TSVs 307 , an RDL 308 , and a plurality of solder bumps 306 .

[0109] Optionally, RDL can be implemented using polyimide, or copper interconnection can be implemented using a Damascus process, or aluminum interconnection can be used. The above materials can reduce product costs and have strong power supply capabilities.

[0110] Optionally, when the multi-chip package structure is used in scenarios with higher signal frequency requirements, RDL 308 can be fabricated in the second bare chip layer 302. When the multi-chip package structure is used in scenarios with lower signal frequency requirements, RDL 308 may not be fabricated to reduce process cost and design complexity.

[0111] In an embodiment of the present application, signal transmission is achieved between the first bare chip layer 301 and the second bare chip layer 302 by hybrid bonding, thereby reducing the need to set TSV 307 in the first bare chip layer 301. In addition, by setting RDL 308 in the second bare chip layer 302, signal transmission can be achieved between the second bare chip layer 302 and the third bare chip layer 303, or between multiple third bare chips (303-1, 303-2) in the third bare chip layer 303 through RDL 308, making the multi-chip packaging structure suitable for scenarios with high signal frequency requirements. It can also reduce the need to set TSV in the second bare chip layer 302, save TSV process steps and area overhead, improve signal bandwidth and signal quality, and improve chip heat dissipation.

[0112] Figure 5 yes Figure 3 FIG. 3 is a schematic diagram of a specific application of a multi-chip package structure 300 . Figure 5 The multi-chip package structure 500 shown can be applied to image sensors. Figure 3 The structure of the multi-chip package structure 300 is the same as that of the multi-chip package structure 300 in FIG

[0113] Specifically, if Figure 5 As shown, the first bare chip layer 301 may be a chip provided with an optical device. As an example, the optical device may include a micro lens. A chip provided with an optical device may also be called a pixel chip.

[0114] The second die layer 302 may be a logic chip, and the third die layer 303 may include one or more ASIC chips. Figure 5 The third bare chip layer 303 including the first ASIC chip 303 - 1 and the second ASIC chip 303 - 2 is taken as an example for description.

[0115] Figure 6 yes Figure 4 FIG. 4 is a schematic diagram of a specific application of a multi-chip package structure 400 . Figure 6 The multi-chip package structure 600 shown can be applied to an image sensor and has the same structure as the multi-chip package structure 400 .

[0116] Specifically, if Figure 6 As shown, the first bare chip layer 301 may be a chip provided with an optical device. As an example, the optical device may include a micro lens. A chip provided with an optical device may also be called a pixel chip.

[0117] The second die layer 302 may be a logic chip. The third die layer 303 may include one or more custom logic chips. Figure 6The third bare chip layer 303 including the first ASIC chip 303 - 1 and the second ASIC chip 303 - 2 is taken as an example for description.

[0118] Figure 7 yes Figure 3 Schematic diagram of signal transmission path of multi-chip package structure 300. Figure 7 As shown, a first path 501 represents a signal transmission path between the first die layer 301 and the third die 303-1 in the third die layer 303. The first path 501 reaches the die 303-1 from the first die layer 301 via the at least one hybrid bonding structure 305, the at least one TSV 307 electrically connected to the at least one hybrid bonding structure 305, and the at least one solder bump 306 electrically connected to the at least one TSV 307.

[0119] Optionally, when the at least one TSV307 and the at least one hybrid bonding structure 305 are electrically connected through the metal layer 309, the first path 501 reaches the third bare chip 303-1 through the at least one hybrid bonding structure 305, the metal layer 309 electrically connected to the at least one hybrid bonding structure 305, the at least one TSV307 electrically connected to the metal layer 309, and the at least one solder bump 306 electrically connected to the at least one TSV307.

[0120] The second path 502 represents a signal transmission path between the second die layer 302 and the third die 303-1 in the third die layer 303. The second path 502 extends from the second die layer 302 to the third die 303-1 via the metal layer 309, the at least one TSV 307 electrically connected to the metal layer 309, and the at least one solder bump 306 electrically connected to the at least one TSV 307.

[0121] The third path 503 represents a signal transmission path between the plurality of third dies (303-1, 303-2) in the third die layer. The third path 503 runs from the third die 303-1 through at least one solder bump 306, at least one TSV 307 electrically connected to the at least one solder bump 306, a metal layer 309 electrically connected to the at least one TSV 307, at least one other TSV 307 electrically connected to the metal layer 309, and at least one other solder bump 306 electrically connected to the at least one other TSV 307, to the third die 303-2.

[0122] The fourth path 504 represents a signal transmission path between the second die layer 302 and the die 303-2 in the third die layer 303. The fourth path 504 is similar to the second path 502 and will not be described again herein.

[0123] Figure 8 yes Figure 4 Schematic diagram of signal transmission path of multi-chip package structure 400. Figure 8 As shown, a first path 601 represents a signal transmission path between the first die layer 301 and the third die 303-1 in the third die layer 303. The first path 601 reaches the third die 303-1 from the chip 301 via the at least one hybrid bonding structure 305, the at least one TSV 307 electrically connected to the at least one hybrid bonding structure 305, the RDL 308 electrically connected to the at least one TSV 307, and the at least one solder bump 306 electrically connected to the RDL 308.

[0124] Optionally, in the case where the multiple TSVs 307 need to be electrically connected to the hybrid bonding structure 305 through the metal layer 309, the first path 601 reaches the third bare chip 303-1 through at least one hybrid bonding structure 305, a metal layer 309 electrically connected to the at least one hybrid bonding structure 305, at least one TSV 307 electrically connected to the metal layer 309, an RDL 308 electrically connected to the at least one TSV 307, and at least one solder bump 306 electrically connected to the RDL 308.

[0125] The second path 602 represents a signal transmission path between the second die layer 302 and the third die 303-1 in the third die layer 303. The second path 602 extends from the second die layer 302 through the RDL 308 and at least one solder bump 306 electrically connected to the RDL 308 to the third die 303-1.

[0126] The third path 603 represents a signal transmission path between the plurality of die (303-1, 303-2) in the third die layer. The third path 603 runs from the third die 303-1 to the die 303-2 via at least one solder bump 306 on the third die 303-1, an RDL 308 electrically connected to the at least one solder bump 306, and at least one other solder bump 306 on the third die 303-2.

[0127] The fourth path 604 represents a signal transmission path between the second die layer 302 and the third die 303-2 in the third die layer 303. The fourth path is similar to the second path and will not be described again.

[0128] Next, the manufacturing process of the multi-chip packaging structure according to the embodiment of the present application will be described in conjunction with the accompanying drawings.

[0129] Figure 9 FIG. 1 is a cross-sectional schematic diagram of a manufacturing process of a multi-chip package structure according to an embodiment of the present application. Figure 9 China-Israel Figure 4The manufacturing process of the multi-chip packaging structure 400 in the embodiment is used as an example to illustrate. It should be understood that after limited changes, such as adding steps, reducing steps or replacing some steps, the manufacturing process can also be applied to the manufacturing process of other multi-chip packaging structures in the embodiments of the present application.

[0130] Figure 9 (1)-(13) in the figure show the manufacturing process of the multi-chip package structure 400 in sequence. Figure 9 , the manufacturing process of the multi-chip package structure 400 is introduced through steps S1 to S13.

[0131] It should be noted that in steps S1-S12, the first bare chip layer 301 and the second bare chip layer 302 are in wafer form. In step S13, the first bare chip layer 301 and the second bare chip layer 302 are cut into individual chips. In steps S7-S13, the third bare chip layer (303-1, 303-2) is cut into individual chips.

[0132] S1: If Figure 9 As shown in (1), first obtain the first bare chip layer 301 and the second bare chip layer 302.

[0133] Alternatively, in step S1, the second bare chip layer 302 may be a bare chip layer that has already been pre-fabricated with TSVs 307. Alternatively, in steps S1-S5, the second bare chip layer 302 without TSVs 307 may be used, and TSVs 307 may be fabricated in the second bare chip layer 302 after S5.

[0134] S2, such as Figure 9 As shown in (2), a hybrid bonding structure 305 is added to the metal layer 309 of the first bare chip layer 301 and the metal layer 309 of the second bare chip layer 302, respectively. The hybrid bonding structure 305 includes a metal and an insulating material for wrapping the metal. For example, the above-mentioned metal may include Cu, and the above-mentioned insulating material may include SiO2, silicon nitride (SiN), etc. Then the first bare chip layer 301 is flipped 180 degrees so that the metal layer 309 between the first bare chip layer 301 and the second bare chip layer 302 is connected. That is, the first bare chip layer 301 and the second bare chip layer 302 are connected in a face-to-face (F2F) manner. It should be noted that the first bare chip layer 301 and the second bare chip layer 302 can also be connected in a face-to-back (F2B) or back-to-back (B2B) manner. Through the hybrid bonding method, the first bare chip layer 301 and the second bare chip layer 302 are electrically connected.

[0135] S3, such as Figure 9As shown in (3), the substrate in the first bare chip layer 301 is thinned to achieve a preset thickness of the first bare chip layer 301. The thickness can be determined according to actual needs and is not specifically limited in the embodiment of the present application.

[0136] S4, such as Figure 9 As shown in (4), optionally, a structure can be further prepared on the substrate of the first bare chip layer 301, such as preparing a metal layer and other functional layers (such as an optical functional structure), and exposing the metal in the first bare chip layer 301 as a metal pad by etching.

[0137] In other scenarios, after the metal in the first bare chip layer 301 is exposed by etching, a metal pad may be further prepared, and the metal pad may be connected to the exposed metal in the first bare chip layer 301. The metal pad may be further interconnected in subsequent processes, such as by connecting the metal pad to a substrate using wire bonding or flip chip (FC).

[0138] S5, such as Figure 9 As shown in (5), a carrier (labeled as carrier 1) is bonded to the substrate surface of the first bare chip layer 301. The carrier 1 is used to protect the surface of the first bare chip layer 301 and play a supporting role in subsequent processes.

[0139] S6, such as Figure 9 As shown in (6), the second bare chip layer 302 is thinned and a redistribution layer RDL308 is prepared on the back side thereof, and the RDL308 is connected to the metal layer 309 of the second bare chip layer 302 through at least one TSV307.

[0140] In some examples, TSVs 307 can be prepared in the second bare chip layer 302 in S1. The TSV preparation process can use a through silicon via first (TSV) or a through silicon via mid (TSV) process. Then, in this step, the second bare chip layer 302 is thinned and a standard through silicon back side via reveal (BVR) process is used to expose the TSVs 307. RDLs 308 are then prepared.

[0141] In some other examples, TSVs may not be formed in S1 . Then in step S6 , the second bare chip layer 302 is thinned first, and then TSVs 307 are formed using a through silicon via last (TSV) process, and then RDLs 308 are formed.

[0142] The "TSV-first" process involves fabricating the TSV holes first, followed by the circuitry. The "TSV-intermediate" process involves fabricating the circuitry and some metal layers first, then the TSVs, and finally the remaining TSVs. The "TSV-last" process involves fabricating the circuitry and metal layers first, followed by the TSVs.

[0143] S7, such as Figure 9 As shown in (7), the prepared third layer of bare chips (303-1, 303-2) are tested, and chips with normal function are selected as the third bare chip layer (303-1, 303-2). The bare chips that test normally are called knowgood dies (KGD). Solder bumps 306 are added to the surfaces of the third bare chip layer (303-1, 303-2) and the RDL 308 of the second bare chip layer 302.

[0144] S8, such as Figure 9 As shown in (8), the solder bumps 306 of the third bare chip layer (303-1, 303-2) are connected to the solder bumps 306 of the second bare chip layer 302. The electrical connection between the third bare chip layer (303-1, 303-2) and the second bare chip layer 302 is achieved through the solder bumps 306 and the RDL 308 of the second bare chip layer 302. In addition, signal transmission between the third bare chip layer (303-1, 303-2) and the first bare chip layer 301 can be achieved through the TSV 307 penetrating the second bare chip layer 302.

[0145] S9, such as Figure 9 As shown in (9), the third bare chip layer (303-1, 303-2) is encapsulated and protected, such as by using under filler, non-conductive film (NCF) or epoxy molding compound (EMC) and other materials.

[0146] S10, such as Figure 9 As shown in (10), a carrier (labeled as carrier 2) is added to the bottom layer of the third bare chip layer (303-1, 303-2) to serve as a protective layer.

[0147] S11, such as Figure 9 As shown in (11), the carrier (ie, carrier 1) on the first bare chip layer 301 is removed.

[0148] S12, such as Figure 9As shown in (12), depending on the function of the chip, further processing can be performed on the back side of the first bare chip layer 301, such as adding optical devices, such as color filters, micro lenses, and anti-reflection films.

[0149] S13, such as Figure 9 As shown in (13), the bottom carrier (labeled as carrier 2) of the third bare chip layer (303-1, 303-2) is removed to obtain a multi-chip packaging structure, which is a chip packaged in a three-layer stacked structure.

[0150] Optionally, after step S13, the obtained multi-chip package structure may be further integrated, for example, by integrating it into other packages through wire bonding or flip chip bonding (FC). The embodiment of the present application does not limit the subsequent packaging process.

[0151] Optionally, if implemented Figure 3 The multi-chip package structure 300 process flow can be Figure 9 Based on the process flow of FIG, the step of preparing the redistribution layer RDL is omitted, that is, the RDL308 in the second bare chip layer 302 is not prepared, so that the TSV307 is directly connected to the solder bump 306 and the metal layer 309 of the bare chip 301. In other words, in Figure 9 In the manufacturing process, the rewiring step is removed, and TSV307 and solder bumps 306 are used to realize signal transmission between the third bare chip layer (303-1, 303-2) and the second bare chip layer 302, thereby reducing the process steps of RDL308.

[0152] In the embodiment of the present application, signals are transmitted between the first bare chip layer 301 and the second bare chip layer 302 by hybrid bonding, and solder bumps are used to connect the second bare chip layer 302 and the third bare chip layer (303-1, 303-2). Therefore, the sizes and processes of the second bare chip layer 302 and the third bare chip layer (303-1, 303-2) do not have to be completely consistent, so that the process nodes and sizes of the second bare chip layer 302 and the third bare chip layer (303-1, 303-2) can be flexibly selected, which can improve the flexibility of the multi-chip packaging structure and is conducive to the miniaturization of electronic devices.

[0153] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A multi-chip package structure, characterized in that: The package structure includes, from top to bottom, a first bare chip layer, a second bare chip layer, and a third bare chip layer, wherein the first bare chip layer includes at least one first bare chip, the second bare chip layer includes at least one second bare chip, and the third bare chip layer includes at least one third bare chip; Wherein, a plurality of hybrid bonding structures are provided between the first bare chip layer and the second bare chip layer, so that the first bare chip layer and the second bare chip layer are electrically connected via at least one hybrid bonding structure; The second bare chip layer is provided with a plurality of through silicon vias (TSVs) penetrating the second bare chip layer, a plurality of solder bumps are provided between the third bare chip layer and the second bare chip layer, and the first bare chip layer and the third bare chip layer are electrically connected via at least one hybrid bonding structure, at least one TSV electrically connected to the at least one hybrid bonding structure, and at least one solder bump electrically connected to the at least one TSV; The feature size of the process used by the third bare chip layer is smaller than that of the first bare chip layer and the second bare chip layer.

2. The packaging structure according to claim 1, wherein: It further includes a metal layer arranged in the second bare chip layer, the TSV is electrically connected to the metal layer, and the first bare chip layer and the third bare chip layer are electrically connected through at least one hybrid bonding structure, the metal layer electrically connected to the at least one hybrid bonding structure, at least one TSV electrically connected to the metal layer, and at least one solder bump electrically connected to the at least one TSV.

3. The packaging structure according to claim 2, wherein: The second bare chip layer and the third bare chip layer are electrically connected via the metal layer, at least one TSV electrically connected to the metal layer, and at least one solder bump electrically connected to the at least one TSV.

4. The packaging structure according to claim 2 or 3, wherein: The third bare chip layer includes two third bare chips, and the two third bare chips are electrically connected in sequence through at least one solder bump, at least one TSV electrically connected to the at least one solder bump, the metal layer electrically connected to the at least one TSV, at least one other TSV electrically connected to the metal layer, and at least one other solder bump electrically connected to the at least one other TSV.

5. The packaging structure according to claim 1, wherein: A redistribution layer RDL is provided in the second bare chip layer, and the first bare chip layer and the third bare chip layer are electrically connected through at least one hybrid bonding structure, at least one TSV electrically connected to the at least one hybrid bonding structure, the RDL electrically connected to the at least one TSV, and at least one solder bump electrically connected to the RDL.

6. The packaging structure according to claim 5, wherein: The second bare chip layer and the third bare chip layer are electrically connected via the RDL and at least one solder bump electrically connected to the RDL.

7. The packaging structure according to claim 5 or 6, wherein: The third bare chip layer includes two third bare chips, and the two third bare chips are electrically connected to each other through at least one solder bump, the RDL electrically connected to the at least one solder bump, and at least one other solder bump electrically connected to the RDL.

8. The packaging structure according to claim 5 or 6, wherein: The TSV is electrically connected to the metal layer arranged in the second bare chip layer, and the first bare chip layer and the third bare chip layer are electrically connected through at least one hybrid bonding structure, the metal layer electrically connected to the at least one hybrid bonding structure, at least one TSV electrically connected to the metal layer, the RDL electrically connected to the at least one TSV, and at least one solder bump electrically connected to the at least one TSV.

9. The packaging structure according to any one of claims 1 to 3, wherein: The third bare chip layer includes circuits for providing edge computing functions.

10. The packaging structure according to any one of claims 1 to 3, wherein: The packaging structure is applied to an image sensor, the first bare chip layer includes a chip provided with an optical device, and the second bare chip layer includes a logic chip.

11. A method for manufacturing a multi-chip package structure, characterized in that: The package structure includes, from top to bottom, a first bare chip layer, a second bare chip layer, and a third bare chip layer, wherein the first bare chip layer includes at least one first bare chip, the second bare chip layer includes at least one second bare chip, and the third bare chip layer includes at least one third bare chip. The feature size of the process used in the third bare chip layer is smaller than that of the first bare chip layer and the second bare chip layer. The method includes: Obtaining the first bare chip layer and the second bare chip layer; adding a hybrid bonding structure on the metal layer of the first bare chip layer and the metal layer of the second bare chip layer respectively; docking the first bare chip layer and the second bare chip layer so that the first bare chip layer and the second bare chip layer are electrically connected via the hybrid bonding structure; Acquire the third bare chip layer; preparing solder bumps on the surface of the third bare chip layer and the surface of the second bare chip layer respectively; The solder bumps of the third bare chip layer are butted against the solder bumps of the second bare chip layer to achieve electrical connection between the second bare chip layer and the third bare chip layer through the solder bumps.

12. The method according to claim 11, wherein The method further includes: forming a plurality of through silicon vias (TSVs) in the second bare chip layer and penetrating the second bare chip layer.

13. The method according to claim 12, wherein: A plurality of TSVs penetrating the second bare chip layer are fabricated in the second bare chip layer, including fabricating the plurality of TSVs by adopting any one of the following processes: a first TSV process, an intermediate TSV process, or a last TSV process.

14. The method according to claim 12 or 13, wherein: The method further comprises: A redistribution layer (RDL) is fabricated on the surface of the second bare chip layer, and the RDL is connected to the metal layer of the second bare chip layer through at least one TSV in the second bare chip layer.

15. The method according to claim 14, wherein The step of preparing solder bumps on the surface of the third bare chip layer and the surface of the second bare chip layer respectively comprises: The solder bumps are respectively fabricated on the surface of the third bare chip layer and the RDL of the second bare chip layer, so as to achieve electrical connection between the third bare chip layer and the second bare chip layer through the solder bumps and the RDL.

16. The method according to any one of claims 11 to 13, characterized in that The method further comprises: After the first bare chip layer and the second bare chip layer are joined together, thinning the substrate of the first bare chip layer; An optical functional structure is prepared on the substrate of the first bare chip layer.

17. The method according to any one of claims 11 to 13, characterized in that The third bare chip layer includes circuits for providing edge computing functions.

18. The method according to any one of claims 11 to 13, characterized in that The packaging structure is applied to an image sensor, the first bare chip layer includes a chip provided with an optical device, and the second bare chip layer includes a logic chip.

19. An electronic device, characterized in that: The electronic device is provided with the multi-chip packaging structure according to any one of claims 1 to 10.

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