Miv test circuit and test method based on voltage divider

Abstract

The application belongs to the field of test circuit, and particularly relates to an MIV test circuit and test method based on a voltage divider. The common test unit is used for switching different test modes to detect whether there is an open-circuit fault, a short-circuit fault or an electric leakage fault in the MIV. The voltage dividing unit is used for establishing a test model of the MIV group. The voltage comparison unit is used for judging whether the voltage at the test point is within a normal voltage range. The application provides an MIV test circuit and test method based on a voltage divider to solve the problem of limited detectable fault range in the prior art.

Description

Technical Field

[0001] This invention belongs to the field of test circuits, specifically relating to a MIV test circuit and test method based on a voltage divider. Background Technology

[0002] 3D integration technology is a promising solution for extending Moore's Law. Currently, 3D integrated circuits are primarily implemented using through-silicon vias (TSVs), offering higher integration density and lower power consumption compared to traditional 2D integrated circuits. However, the size and high manufacturing requirements of TSVs limit further improvements in device integration. To overcome these limitations, monolithic 3D integration technology has emerged. In monolithic 3D integrated circuits (M3D ICs), transistors are fabricated layer by layer on the same wafer, eliminating the need for any mold alignment and significantly reducing the size of monolithic inter-tier vias (MIVs).

[0003] While monolithic 3D integration technology can significantly reduce chip area and improve circuit performance, the high integration density and significant reduction in interlayer dielectric thickness make MIVs highly susceptible to defects. Related research shows that the yield of MIVs is far lower than that of traditional through-hole (via) circuits. As the hub for electrical transmission between adjacent layers, MIV failures can compromise the signal integrity of the entire chip. Therefore, MIV testing is crucial for the large-scale application of M3D ICs. However, existing MIV test circuits can only perform open-circuit and short-circuit tests, limiting the range of detectable faults and failing to meet practical application requirements. Summary of the Invention

[0004] This invention provides a MIV test circuit and test method based on a voltage divider to solve the problem of limited fault detection range in existing technologies.

[0005] This invention is achieved through the following technical solution:

[0006] A voltage divider-based MIV test circuit, the MIV test circuit including a common test unit, a voltage divider unit and a voltage comparison unit;

[0007] The common test unit is used to switch between different test modes to detect whether there is an open circuit fault, short circuit fault or leakage fault in the MIV.

[0008] The voltage divider unit is used to establish a test model for the MIV group;

[0009] The voltage comparison unit shown is used to determine whether the voltage at the test point is within the normal voltage range.

[0010] The common test unit is connected to the voltage comparison unit through a voltage divider unit.

[0011] A MIV test circuit based on a voltage divider, wherein the common test unit is connected to the voltage divider unit, and the voltage divider unit is connected to the voltage comparison unit;

[0012] The common test unit 1 includes a test controller, a first test-dedicated MIV, a second test-dedicated MIV, and a third test-dedicated MIV; the first test-dedicated MIV, the second test-dedicated MIV, and the third test-dedicated MIV are all located in the middle layer chip, and the test controller is located in the upper layer chip;

[0013] The voltage divider unit 2 includes an upper-layer chip voltage divider unit 2 and a lower-layer chip voltage divider unit 2;

[0014] One output of the test controller is connected to the address input of the multiplexer of the voltage divider unit 2 in the upper layer chip, and the address input of the multiplexer of the voltage divider unit 2 in the lower layer chip is connected to the other output of the test controller through a test-dedicated MIV.

[0015] After the first test-dedicated MIV, the second test-dedicated MIV and the third test-dedicated MIV are connected in parallel, the end connected to the upper-layer chip is the MIV head end, and the end connected to the lower-layer chip is the MIV tail end.

[0016] The first, second, and third test-dedicated MIVs are all connected to the two output terminals of the test controller, and their ends are all connected to the address input terminal of the multiplexer in the lower-level chip.

[0017] A MIV test circuit based on a voltage divider, wherein the voltage divider unit 2 includes a 2-to-1 multiplexer, an i-th 4-to-1 multiplexer, and an i-th input resistor R. I1_i The i-th input resistance R I2_i Voltage divider resistor R D1 and voltage divider resistor R D2 ;

[0018] The input terminal 0 of the two-to-one multiplexer 22 and the voltage divider resistor R D1 One end is connected to the input terminal 1 of the 2-to-1 multiplexer and the voltage divider resistor R. D2 One end of the connector is connected, and the output of the two-to-one multiplexer shown is connected to ground.

[0019] A MIV test circuit based on a voltage divider, wherein the voltage divider unit 2 includes a 4-to-1 multiplexer, the input terminal 0 of the first 4-to-1 multiplexer is connected to the power supply, and the input terminal 1 of the first 4-to-1 multiplexer is connected to the input resistor R. I1_1 One end is connected to input terminal 2 of the first 4-to-1 multiplexer and input resistor R. I2_1 One end of the first 4-to-1 multiplexer is connected to the input terminal 3 of the first 4-to-1 multiplexer, which is connected to one end of the function input FI; the address input terminals A0 and A1 of the first 4-to-1 multiplexer are both connected to one end of the test controller; the output terminal of the first 4-to-1 multiplexer is connected to the beginning of the first MIV under test.

[0020] Input terminal 0 of the i-th 4-to-1 multiplexer is connected to the end of the (i-1)-th MIV being measured, and input terminal 1 of the i-th 4-to-1 multiplexer is connected to the input resistor R. I1_i One end is connected to the input terminal 2 of the i-th 4-to-1 multiplexer and the input resistor R. I2_i One end of the i-th 4-to-1 multiplexer is connected to the input terminal 3, which is connected to one end of the function input FI. The address input terminals A0 and A1 of the i-th 4-to-1 multiplexer are both connected to the end of the test-dedicated MIV. The output terminal of the i-th 4-to-1 multiplexer is connected to the end of the i-th MIV under test. Input terminal 0 of the i-th 4-to-1 multiplexer (i=3,5,…,n-1) is connected to the beginning of the (i-1)-th MIV under test. Input terminal 1 of the i-th 4-to-1 multiplexer is connected to the input resistor R. I1_i One end is connected to the input terminal 2 of the i-th 4-to-1 multiplexer and the input resistor R. I2_i One end of the i-th 4-to-1 multiplexer is connected to the input terminal 3 of the i-th 4-to-1 multiplexer, which is connected to one end of the function input FI; the address input terminals A0 and A1 of the i-th 4-to-1 multiplexer are both connected to one end of the test controller; the output terminal of the i-th 4-to-1 multiplexer is connected to the beginning of the i-th MIV under test.

[0021] A MIV test circuit based on a voltage divider, wherein the input resistor R I1_1 One end is connected to the power supply, and the input resistance is R. I1_1 The other end is connected to input terminal 1 of the first 4-to-1 multiplexer. The i-th input resistor R... I1_i One end of (i=2,4,…,n) is connected to the end of the (i-1)th measured MIV, and the i-th input resistance R I1_i The other end of (i=2,4,…,n) is connected to input terminal 1 of the i-th 4-to-1 multiplexer. The i-th input resistor R I1_i One end of (i=3,5,…,n-1) is connected to the beginning of the (i-1)th MIV being measured, and the i-th input resistor R I1_i The other end of (i=3,5,…,n) is connected to input terminal 1 of the i-th 4-to-1 multiplexer;

[0022] Input resistance R I2_1 One end is connected to the power supply, and the input resistor R I2_1 The other end is connected to input terminal 2 of the first 4-to-1 multiplexer. The i-th input resistor R... I2_i One end of (i=2,4,…,n) is connected to the end of the (i-1)th measured MIV, and the i-th input resistance R I2_i The other end of (i=2,4,…,n) is connected to input terminal 2 of the i-th 4-to-1 multiplexer. The i-th input resistor R I2_i One end of (i=3,5,…,n-1) is connected to the beginning of the (i-1)th MIV being measured, and the i-th input resistor R I2_i The other end of (i=3,5,…,n) is connected to input terminal 2 of the i-th 4-to-1 multiplexer;

[0023] Voltage divider resistor R D1 Voltage divider resistor R D1 One end is connected to the beginning of the nth MIV being measured, and the voltage divider resistor R D1 The other end is connected to input terminal 0 of the 2-to-1 multiplexer;

[0024] Voltage divider resistor R D2 Voltage divider resistor R D2 One end is connected to the beginning of the nth MIV being measured, and the voltage divider resistor R D2 The other end is connected to input 1 of the 2-to-1 multiplexer.

[0025] Furthermore, the voltage comparison unit 3 includes a first voltage comparator 31 and a second voltage comparator 32;

[0026] The first voltage comparator and the second voltage comparator constitute a dual-limit voltage comparator;

[0027] The positive input terminal of the first voltage comparator is connected to the beginning of the nth measured MIV, and the negative input terminal of the first voltage comparator is connected to resistor R. VC_1 With resistance R VC_2 Between them, the output terminal of the first voltage comparator is connected to the output terminal of the second voltage comparator;

[0028] The positive input terminal of the first voltage comparator is connected to the beginning of the nth measured MIV, and the negative input terminal of the first voltage comparator is connected to resistor R. VC_1 With resistance R VC_2 Between them, the output terminals of the first voltage comparator and the second voltage comparator are connected to form the output terminal V of the entire test circuit. out .

[0029] The resistor R VC_1One end of the resistor is connected to the power supply, and the resistor R shown is... VC_1 The other end is connected to the negative input of the first voltage comparator.

[0030] The resistor R VC_2 One end of the resistor R is connected to the negative input of the first voltage comparator. VC_2 The other end is connected to the ground;

[0031] The resistor R VC_3 One end of the resistor R is connected to the power supply. VC_3 The other end is connected to the negative input of the second voltage comparator.

[0032] The resistor R VC_4 One end of the resistor R is connected to the negative input terminal of the second voltage comparator. VC_4 The other end is connected to the ground;

[0033] The resistor R VC_5 One end of the resistor R is connected to the power supply. VC_5 The other end is connected to the output terminal V of the entire test circuit. out connect.

[0034] A test method for a voltage divider-based MIV test circuit, utilizing the voltage divider-based MIV test circuit as described above, includes the following steps:

[0035] Step 1: Perform open-circuit fault detection on the entire MIV group. The test controller outputs a "10" command to the i-th 4-to-1 multiplexer and a "1" command to the 2-to-1 multiplexer. The test circuit will output the test output signal V. out_1 ;

[0036] Step 2: Simultaneously perform leakage fault detection for the entire MIV group and short-circuit fault detection for the first half of the MIV group. The test controller outputs a "01" command to the i-th 4-to-1 multiplexer, a "00" command to the i-th 4-to-1 multiplexer, and a "0" command to the 2-to-1 multiplexer. The test circuit will output the test output signal V. out_2 ;

[0037] Step 3: Perform short-circuit fault detection on the second half of the MIV group. The test controller outputs a "00" command to the i-th 4-to-1 multiplexer, a "01" command to the i-th 4-to-1 multiplexer, and a "0" command to the 2-to-1 multiplexer. The test circuit will output the test output signal V. out_3 ;

[0038] Step 4: Based on the output signal V obtained in steps 1-3 out_1 Output signal V out_2 and output signal Vout_3 Determine if there is a fault in the MIV group. If the test output signal V out_1 V out_2 and V out_3 If all signals are high, the tested MIV group is fault-free; if the test output signal V... out_1 V out_2 and V out_3 If any one of the test output signals is low, then the tested MIV group has a fault.

[0039] In step 1, n is an even number among the n MIVs;

[0040] In the i-th 4-to-1 multiplexer of step 1, i = 1, 2, ..., n.

[0041] In step 2, the i-th 4-to-1 multiplexer that receives the "01" instruction has i=1,2,…,n / 2;

[0042] In step 2, the i-th 4-to-1 multiplexer that receives the “00” instruction has i = n / 2+1, n / 2+2, ...,n.

[0043] In step 3, the i-th 4-to-1 multiplexer that receives the “00” instruction has i=1,2,…,n / 2;

[0044] In step 3, the i-th 4-to-1 multiplexer that receives the "01" instruction has i = n / 2+1, n / 2+2, ...,n.

[0045] A test method for a MIV test circuit based on a voltage divider, and an electrical model of the MIV group under fault-free conditions, wherein each MIV can be equivalently represented by a resistor R. MIV and capacitor C MIV The RC circuit model consists of resistor R. MIV It is the on-resistance of the MIV, and the capacitance C. MIV It is the capacitance caused by the MIV insulating wall, R I and R D These are the input resistor and voltage divider resistor set in the test circuit, respectively.

[0046] Assuming the relative change in resistance is η, for a fault-free MIV group, the minimum voltage V at the test point is... MIV_normal_min and maximum voltage V MIV_normal_max They are respectively:

[0047] (1)

[0048] (2).

[0049] A test method for a MIV test circuit based on a voltage divider is proposed. Considering the manufacturing process variations in actual resistors, the voltage range corresponding to the fault-free MIV group is V. MIV_normal_min ~V MIV_normal_max ;

[0050] A dual-threshold voltage comparator is used to determine whether the voltage at the test point is within the normal voltage range. The threshold voltage setting requirement is: V TH1 ≤V MIV_normal_min V TH2 ≥V MIV_normal_max ;

[0051] If V TH1 ≤V MIV ≤V TH2 Output signal V out It is a high level; if V MIV <V TH1 or V MIV >V TH2 Output signal V out It is at a low level; therefore, the output signal V out It can be used directly to determine whether the MIV is faulty.

[0052] A test method for a MIV test circuit based on a voltage divider can detect single-type MIV faults that meet the following conditions: For an open-circuit MIV fault, the maximum value V of the test point voltage in the open-circuit state. MIV_open_max Less than the minimum voltage at the test point under fault-free conditions, V MIV_normal_min For MIV short-circuit faults, the minimum value V of the test point voltage under short-circuit conditions. MIV_short_min Greater than the maximum value V of the test point voltage under fault-free conditions MIV_normal_max ;

[0053] For MIV leakage faults, the maximum value V of the voltage at the test point under leakage conditions is... MIV_leak_max Less than the minimum voltage at the test point under fault-free conditions, V MIV_normal_min ,

[0054] (3)

[0055] (4)

[0056] (5)

[0057] Where R parallel1 R parallel2 and R parallel3 They are represented as follows:

[0058] (6)

[0059] (7)

[0060] (8).

[0061] The beneficial effects of this invention are:

[0062] This invention employs a voltage divider-based MIV test circuit to test on-chip MIVs. This test structure is simple and effective, and has high test accuracy. The test circuit takes into account the influence of process deviations and is highly feasible. The test circuit can be used to detect open circuit faults, short circuit faults, and leakage faults in MIVs, and has a wide range of fault detection capabilities. Attached Figure Description

[0063] Figure 1 This is a schematic diagram of the structure of the present invention.

[0064] Figure 2 This is a flowchart of the testing method of the present invention.

[0065] Figure 3 This is a schematic diagram of the electrical model of the MIV group under fault-free conditions according to the present invention.

[0066] Figure 4 This is a schematic diagram of the electrical model of the MIV group under open-circuit fault conditions according to the present invention.

[0067] Figure 5 This is a schematic diagram of the electrical model of the MIV group under short-circuit fault conditions of the present invention.

[0068] Figure 6 This is a schematic diagram of the electrical model of the MIV group under leakage fault conditions according to the present invention.

[0069] Figure 7 The following are the test results of MIV under different states of the present invention: (a) Schematic diagram of no fault state, (b) Schematic diagram of open circuit fault state, (c) Schematic diagram of short circuit fault state, (d) Schematic diagram of leakage fault state. Detailed Implementation

[0070] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0071] A voltage divider-based MIV test circuit, the MIV test circuit including a common test unit, a voltage divider unit and a voltage comparison unit;

[0072] The common test unit is used to switch between different test modes to detect whether there is an open circuit fault, short circuit fault or leakage fault in the MIV.

[0073] The voltage divider unit is used to establish a test model for the MIV group;

[0074] The voltage comparison unit shown is used to determine whether the voltage at the test point is within the normal voltage range.

[0075] The common test unit is connected to the voltage comparison unit through a voltage divider unit.

[0076] A MIV test circuit based on a voltage divider, wherein the common test unit is connected to the voltage divider unit, and the voltage divider unit is connected to the voltage comparison unit;

[0077] The common test unit 1 includes a test controller, a first test-dedicated MIV, a second test-dedicated MIV, and a third test-dedicated MIV. Since the test-dedicated MIV cannot be tested, three redundant test-dedicated MIVs are set to ensure the reliability of the test circuit. The first test-dedicated MIV, the second test-dedicated MIV, and the third test-dedicated MIV are all in the middle layer chip, and the test controller is in the upper layer chip.

[0078] The voltage divider unit 2 includes an upper-layer chip voltage divider unit 2 and a lower-layer chip voltage divider unit 2;

[0079] One output of the test controller is connected to the address input of the multiplexer of the voltage divider unit 2 in the upper layer chip, and the address input of the multiplexer of the voltage divider unit 2 in the lower layer chip is connected to the other output of the test controller through a test-dedicated MIV.

[0080] After the first test-dedicated MIV, the second test-dedicated MIV and the third test-dedicated MIV are connected in parallel, the end connected to the upper-layer chip is the MIV head end, and the end connected to the lower-layer chip is the MIV tail end.

[0081] The first, second, and third test-dedicated MIVs are all connected to the two output terminals of the test controller, and their ends are all connected to the address input terminal of the multiplexer in the lower-level chip.

[0082] A MIV test circuit based on a voltage divider, wherein the voltage divider unit 2 includes a 2-to-1 multiplexer (MUX), an i-th 4-to-1 multiplexer (i=1,2,…,n and n is an even number), and an i-th input resistor R. I1_i The i-th input resistance R I2_i Voltage divider resistor R D1 and voltage divider resistor RD2 ;

[0083] The input terminal 0 of the two-to-one multiplexer 22 and the voltage divider resistor R D1 One end is connected to the input terminal 1 of the 2-to-1 multiplexer and the voltage divider resistor R. D2 One end of the connector is connected, and the output of the two-to-one multiplexer shown is connected to ground.

[0084] A MIV test circuit based on a voltage divider, wherein the voltage divider unit 2 includes a 4-to-1 multiplexer, the input terminal 0 of the first 4-to-1 multiplexer is connected to the power supply, and the input terminal 1 of the first 4-to-1 multiplexer is connected to the input resistor R. I1_1 One end is connected to input terminal 2 of the first 4-to-1 multiplexer and input resistor R. I2_1 One end of the first 4-to-1 multiplexer is connected to the input terminal 3 of the first 4-to-1 multiplexer, which is connected to one end of the function input FI; the address input terminals A0 and A1 of the first 4-to-1 multiplexer are both connected to one end of the test controller; the output terminal of the first 4-to-1 multiplexer is connected to the beginning of the first MIV under test.

[0085] The input terminal 0 of the i-th 4-to-1 multiplexer (i=2,4,…,n) is connected to the end of the (i-1)-th MIV being measured, and the input terminal 1 of the i-th 4-to-1 multiplexer is connected to the input resistor R. I1_i One end is connected to the input terminal 2 of the i-th 4-to-1 multiplexer and the input resistor R. I2_i One end of the i-th 4-to-1 multiplexer is connected to the input terminal 3, which is connected to one end of the function input FI. The address input terminals A0 and A1 of the i-th 4-to-1 multiplexer are both connected to the end of the test-dedicated MIV. The output terminal of the i-th 4-to-1 multiplexer is connected to the end of the i-th MIV under test. Input terminal 0 of the i-th 4-to-1 multiplexer (i=3,5,…,n-1) is connected to the beginning of the (i-1)-th MIV under test. Input terminal 1 of the i-th 4-to-1 multiplexer is connected to the input resistor R. I1_i One end is connected to the input terminal 2 of the i-th 4-to-1 multiplexer and the input resistor R. I2_i One end of the i-th 4-to-1 multiplexer is connected to the input terminal 3 of the i-th 4-to-1 multiplexer, which is connected to one end of the function input FI; the address input terminals A0 and A1 of the i-th 4-to-1 multiplexer are both connected to one end of the test controller; the output terminal of the i-th 4-to-1 multiplexer is connected to the beginning of the i-th MIV under test.

[0086] A MIV test circuit based on a voltage divider, wherein the first input resistor R I1_1 One end is connected to the power supply, and the first input resistor R I1_1 The other end is connected to input terminal 1 of the first 4-to-1 multiplexer. The i-th input resistor R... I1_iOne end of (i=2,4,…,n) is connected to the end of the (i-1)th measured MIV, and the i-th input resistance R I1_i The other end of (i=2,4,…,n) is connected to input terminal 1 of the i-th 4-to-1 multiplexer. The i-th input resistor R I1_i One end of (i=3,5,…,n-1) is connected to the beginning of the (i-1)th MIV being measured, and the i-th input resistor R I1_i The other end of (i=3,5,…,n) is connected to input terminal 1 of the i-th 4-to-1 multiplexer;

[0087] First input resistance R I2_1 One end is connected to the power supply, and the first input resistor R I2_1 The other end is connected to input terminal 2 of the first 4-to-1 multiplexer. The i-th input resistor R... I2_i One end of (i=2,4,…,n) is connected to the end of the (i-1)th measured MIV, and the i-th input resistance R I2_i The other end of (i=2,4,…,n) is connected to input terminal 2 of the i-th 4-to-1 multiplexer. The i-th input resistor R I2_i One end of (i=3,5,…,n-1) is connected to the beginning of the (i-1)th MIV being measured, and the i-th input resistor R I2_i The other end of (i=3,5,…,n) is connected to input terminal 2 of the i-th 4-to-1 multiplexer;

[0088] Voltage divider resistor R D1 Voltage divider resistor R D1 One end is connected to the beginning of the nth MIV being measured, and the voltage divider resistor R D1 The other end is connected to input terminal 0 of the 2-to-1 multiplexer;

[0089] Voltage divider resistor R D2 Voltage divider resistor R D2 One end is connected to the beginning of the nth MIV being measured, and the voltage divider resistor R D2 The other end is connected to input 1 of the 2-to-1 multiplexer.

[0090] A MIV test circuit based on a voltage divider, wherein the voltage comparison unit 3 includes a first voltage comparator 31 and a second voltage comparator 32; and also includes an external resistor R. VC_k (k=1,…,5);

[0091] The first voltage comparator and the second voltage comparator constitute a dual-limit voltage comparator;

[0092] The positive input terminal of the first voltage comparator is connected to the beginning of the nth measured MIV, and the negative input terminal of the first voltage comparator is connected to resistor R. VC_1 With resistance R VC_2Between them, the output terminal of the first voltage comparator is connected to the output terminal of the second voltage comparator;

[0093] The positive input terminal of the first voltage comparator is connected to the beginning of the nth measured MIV, and the negative input terminal of the first voltage comparator is connected to resistor R. VC_1 With resistance R VC_2 Between them, the output terminals of the first voltage comparator and the second voltage comparator are connected to form the output terminal V of the entire test circuit. out .

[0094] The resistor R VC_1 One end of the resistor is connected to the power supply, and the resistor R shown is... VC_1 The other end is connected to the negative input of the first voltage comparator.

[0095] The resistor R VC_2 One end of the resistor R is connected to the negative input of the first voltage comparator. VC_2 The other end is connected to the ground;

[0096] The resistor R VC_3 One end of the resistor R is connected to the power supply. VC_3 The other end is connected to the negative input of the second voltage comparator.

[0097] The resistor R VC_4 One end of the resistor R is connected to the negative input terminal of the second voltage comparator. VC_4 The other end is connected to the ground;

[0098] The resistor R VC_5 One end of the resistor R is connected to the power supply. VC_5 The other end is connected to the output terminal V of the entire test circuit. out connect.

[0099] On-chip MIVs are tested using a voltage divider-based MIV test circuit. This test structure is simple and effective, and has high test accuracy. The test circuit takes into account the influence of process deviations and is highly feasible. The test circuit can be used to detect open circuit faults, short circuit faults, and leakage faults in MIVs, and has a wide range of fault detection capabilities.

[0100] A test method for a voltage divider-based MIV test circuit, used to perform group testing on-chip MIVs, utilizing the voltage divider-based MIV test circuit as described above, the test method includes the following steps:

[0101] Step 1: Perform open-circuit fault detection on the entire MIV group (a group of n MIVs, where n is an even number). The test controller outputs a "10" command to the i-th 4-to-1 multiplexer (i=1,2,…,n) and a "1" command to the 2-to-1 multiplexer. The test circuit will output the test output signal V. out_1 ;

[0102] Step 2: Simultaneously perform leakage fault detection for the entire MIV group and short-circuit fault detection for the first half of the MIV group. The test controller outputs a "01" instruction to the i-th 4-to-1 multiplexer (i=1,2,…,n / 2), a "00" instruction to the i-th 4-to-1 multiplexer (i= n / 2+1, n / 2+2,…,n), and a "0" instruction to the 2-to-1 multiplexer. The test circuit will output the test output signal V. out_2 ;

[0103] Step 3: Perform short-circuit fault detection on the second half of the MIV group. The test controller outputs a "00" instruction to the i-th 4-to-1 multiplexer (i=1,2,…,n / 2), a "01" instruction to the i-th 4-to-1 multiplexer (i= n / 2+1, n / 2+2,…,n), and a "0" instruction to the 2-to-1 multiplexer. The test circuit will output the test output signal V. out_3 ;

[0104] Step 4: Based on the output signal V obtained in steps 1-3 out_1 Output signal V out_2 and output signal V out_3 Determine if there is a fault in the MIV group. If the test output signal V out_1 V out_2 and V out_3 If all signals are high, the tested MIV group is fault-free; if the test output signal V... out_1 V out_2 and V out_3 If any one of the test output signals is low, then the tested MIV group has a fault.

[0105] A test method for a MIV test circuit based on a voltage divider, wherein n is an even number in the n MIVs of step 1;

[0106] In the i-th 4-to-1 multiplexer of step 1, i = 1, 2, ..., n.

[0107] A test method for a MIV test circuit based on a voltage divider, wherein in step 2, the i-th 4-to-1 multiplexer that receives the “01” instruction has i=1,2,…,n / 2;

[0108] In step 2, the i-th 4-to-1 multiplexer that receives the “00” instruction has i = n / 2+1, n / 2+2, ...,n.

[0109] A test method for a MIV test circuit based on a voltage divider, wherein in step 3, the i-th 4-to-1 multiplexer that receives the “00” instruction has i=1,2,…,n / 2;

[0110] In step 3, the i-th 4-to-1 multiplexer that receives the "01" instruction has i = n / 2+1, n / 2+2, ...,n.

[0111] In this embodiment, a common test unit 1 is responsible for controlling all the MIV groups under test in the entire chip. This embodiment takes one MIV group under test as an example, such as... Figure 1 As shown, a common test unit 1 consists of a test controller and three dedicated test MIVs. The test controller generates test commands and provides address input signals to the multiplexers in the voltage divider unit 2. In the upper-level chip, the address input signals A1 and A0 of the 4-to-1 multiplexer and the address input signal A of the 2-to-1 multiplexer are directly provided by the test controller; in the lower-level chip, the address input signals A1 and A0 of the 4-to-1 multiplexer are provided by the test controller through the dedicated test MIVs.

[0112] In this embodiment, the first voltage comparator 31 and the second voltage comparator 32 together constitute a dual-threshold voltage comparator. The first threshold voltage V of the dual-threshold voltage comparator... TH1 From resistor R VC_1 and resistance R VC_2 The second threshold voltage V of the dual-threshold voltage comparator is determined. TH2 From resistor R VC_3 and resistance R VC_4 Decision. The test clock signal for this test circuit is CLK, the clock signal for the dual-limit voltage comparator is CLK_VC, and the voltage signal at the test point is V. MIV The test output signal is V out .

[0113] Figure 3 For the electrical model of the MIV group under fault-free conditions, each MIV can be equivalent to a resistor R. MIV and capacitor C MIV The RC circuit model consists of resistor R. MIV It is the on-resistance of the MIV, and the capacitance C. MIV It is the capacitance caused by the MIV insulating wall, R I and R D These are the input resistor and voltage divider resistor set in the test circuit, respectively. Assuming the relative change in resistance is η, for a fault-free MIV group, the minimum voltage V at the test point is...MIV_normal_min and maximum voltage V MIV_normal_max They are respectively:

[0114] (1)

[0115] (2)

[0116] Figures 4-6 The electrical models of the MIV group under open-circuit, short-circuit, and leakage fault conditions are shown respectively. According to the voltage divider principle, the voltage at the test point is lower under open-circuit and leakage fault conditions than the voltage at the test point under fault-free conditions, while the voltage at the test point is higher under short-circuit fault conditions than the voltage at the test point under fault-free conditions. Considering the manufacturing process variations in actual resistors, the voltage range corresponding to the fault-free MIV group is V. MIV_normal_min ~V MIV_normal_max This test circuit primarily uses a dual-threshold voltage comparator to determine whether the voltage at the test point is within the normal voltage range. The threshold voltage setting requirement is: V TH1 ≤V MIV_normal_min V TH2 ≥V MIV_normal_max If V TH1 ≤V MIV ≤V TH2 Output signal V out It is a high level; if V MIV <V TH1 or V MIV >V TH2 Output signal V out It is at a low level. Therefore, the output signal V out This test method can be directly used to determine whether a MIV is faulty. The single type of MIV fault that this test method can detect meets the following condition: For an open-circuit fault in the MIV, the maximum value V of the test point voltage in the open-circuit state. MIV_open_max Less than the minimum voltage at the test point under fault-free conditions, V MIV_normal_min For MIV short-circuit faults, the minimum value V of the test point voltage under short-circuit conditions. MIV_short_min Greater than the maximum value V of the test point voltage under fault-free conditions MIV_normal_max For MIV leakage faults, the maximum value V of the test point voltage under leakage conditions is... MIV_leak_max Less than the minimum voltage at the test point under fault-free conditions, V MIV_normal_min .

[0117] (3)

[0118] (4)

[0119] (5)

[0120] Where Rparallel1 R parallel2 and R parallel3 They are represented as follows:

[0121] (6)

[0122] (7)

[0123] (8).

[0124] For a set of numbers n (n is an even number and The method for testing the MIV group includes the following steps:

[0125] Step 1: Perform open-circuit fault detection on the entire MIV group (n MIVs). The test controller outputs a "10" command to the i-th 4-to-1 multiplexer (i=1,2,…,n) and a "1" command to the 2-to-1 multiplexer.

[0126] Step two: Simultaneously perform leakage fault detection for the entire MIV group and short-circuit fault detection for the first half of the MIV group. The test controller outputs a "01" instruction to the i-th 4-to-1 multiplexer (i=1,2,…,n / 2), a "00" instruction to the i-th 4-to-1 multiplexer (i= n / 2+1, n / 2+2,…,n), and a "0" instruction to the 2-to-1 multiplexer.

[0127] Step 3: Perform short-circuit fault detection on the second half of the MIV group. The test controller outputs a "00" instruction to the i-th 4-to-1 multiplexer (i=1,2,…,n / 2), a "01" instruction to the i-th 4-to-1 multiplexer (i= n / 2+1, n / 2+2,…,n), and a "0" instruction to the 2-to-1 multiplexer.

[0128] In this embodiment, it is assumed that a tested MIV group contains 10 MIVs, and the relative change in MIV resistance is 5%. After establishing the test circuit model in HSPICE simulation software, the MIV group is tested under four states. State 1: All 10 MIVs are fault-free; State 2: MIV1 has an open circuit fault (R... open =0.5kΩ), the other MIVs are fault-free; State 3: There is a short circuit fault between MIV1 and MIV2 (R short =0.15kΩ), the other MIVs are fault-free; State 4: MIV1 has a leakage fault (R leak =20kΩ), the remaining MIVs were fault-free. The parameter settings during the test were as follows:

[0129] Fault-free MIV parameters:

[0130] Test clock frequency: R MIV =2.66Ω, C MIV =0.4658fF;

[0131] On-chip power supply voltage: 1.8V;

[0132] Threshold voltage of the dual-limit voltage comparator: V TH1 =1.145V, V TH2 =1.240V;

[0133] Input resistance: R I1_i (i=1,2,…,10) =2kΩ, R I2_i (i=1,2,…,10) =0.1kΩ;

[0134] Voltage divider resistor: R D1 =20kΩ, R D2 =2kΩ.

[0135] Figure 7 The graph shows the test results of the MIV group under different conditions. It can be seen that if the tested MIV group is fault-free, the test output signal V out The output signal is high; if there is a fault in the tested MIV group, the test output signal V will be high. out It is a low level.

Claims

1. A MIV test circuit based on a voltage divider, characterized in that, The MIV test circuit includes a common test unit, a voltage divider unit, and a voltage comparison unit. The common test unit is used to switch between different test modes to detect whether there is an open circuit fault, short circuit fault or leakage fault in the MIV. The voltage divider unit is used to establish a test model for the MIV group; The voltage comparison unit shown is used to determine whether the voltage at the test point is within the normal voltage range. The common test unit is connected to the voltage comparison unit through a voltage divider unit; The common test unit is connected to the voltage divider unit, and the voltage divider unit is connected to the voltage comparison unit; The common test unit (1) includes a test controller, a first test-dedicated MIV, a second test-dedicated MIV, and a third test-dedicated MIV; the first test-dedicated MIV, the second test-dedicated MIV, and the third test-dedicated MIV are all in the middle layer chip, and the test controller is in the upper layer chip; The voltage divider unit (2) includes an upper-layer chip voltage divider unit and a lower-layer chip voltage divider unit; The voltage comparison unit (3) includes a first voltage comparator (31) and a second voltage comparator (32); The first voltage comparator and the second voltage comparator constitute a dual-limit voltage comparator.

2. The MIV test circuit based on a voltage divider according to claim 1, characterized in that, One output of the test controller is connected to the address input of the multiplexer of the voltage divider unit in the upper-layer chip, and the address input of the multiplexer of the voltage divider unit in the lower-layer chip is connected to the other output of the test controller through a test-dedicated MIV. After the first test-dedicated MIV, the second test-dedicated MIV and the third test-dedicated MIV are connected in parallel, the end connected to the upper-layer chip is the MIV head end, and the end connected to the lower-layer chip is the MIV tail end. The first, second, and third test-dedicated MIVs are all connected to the two output terminals of the test controller, and their ends are all connected to the address input terminal of the multiplexer in the lower-level chip.

3. The MIV test circuit based on a voltage divider according to claim 2, characterized in that, The voltage divider unit (2) includes a 2-to-1 multiplexer (22), an i-th 4-to-1 multiplexer, and an i-th input resistor R. I1_i The i-th input resistance R I2_i Voltage divider resistor R D1 and voltage divider resistor R D2 ; The input terminal 0 of the two-to-one multiplexer (22) is connected to the voltage divider resistor R. D1 One end is connected to the input terminal 1 of the 2-to-1 multiplexer and the voltage divider resistor R. D2 One end of the connector is connected, and the output of the two-to-one multiplexer shown is connected to ground.

4. The MIV test circuit based on a voltage divider according to claim 2, characterized in that, The voltage divider unit (2) includes a 4-to-1 multiplexer. The input terminal 0 of the first 4-to-1 multiplexer is connected to the power supply, and the input terminal 1 of the first 4-to-1 multiplexer is connected to the input resistor R. I1_1 One end is connected to input terminal 2 of the first 4-to-1 multiplexer and input resistor R. I2_1 One end of the first 4-to-1 multiplexer is connected to the input terminal 3 of the first 4-to-1 multiplexer, which is connected to one end of the function input FI; the address input terminals A0 and A1 of the first 4-to-1 multiplexer are both connected to one end of the test controller; the output terminal of the first 4-to-1 multiplexer is connected to the beginning of the first MIV under test. Input terminal 0 of the i-th 4-to-1 multiplexer is connected to the end of the (i-1)-th MIV being measured, and input terminal 1 of the i-th 4-to-1 multiplexer is connected to the input resistor R. I1_i One end is connected to the input terminal 2 of the i-th 4-to-1 multiplexer and the input resistor R. I2_i One end of the i-th 4-to-1 multiplexer is connected to the input terminal 3 of the i-th 4-to-1 multiplexer and one end of the function input FI; the address input terminals A0 and A1 of the i-th 4-to-1 multiplexer are both connected to the end of the test-dedicated MIV; the output terminal of the i-th 4-to-1 multiplexer is connected to the end of the i-th MIV under test. Input terminal 0 of the i-th 4-to-1 multiplexer is connected to the beginning of the (i-1)-th MIV being measured, and input terminal 1 of the i-th 4-to-1 multiplexer is connected to the input resistor R. I1_i One end is connected to the input terminal 2 of the i-th 4-to-1 multiplexer and the input resistor R. I2_i One end of the i-th 4-to-1 multiplexer is connected to the input terminal 3 of the i-th 4-to-1 multiplexer, which is connected to one end of the function input FI; the address input terminals A0 and A1 of the i-th 4-to-1 multiplexer are both connected to one end of the test controller; the output terminal of the i-th 4-to-1 multiplexer is connected to the beginning of the i-th MIV under test.

5. The MIV test circuit based on a voltage divider according to claim 4, characterized in that, The input resistance R I1_1 One end is connected to the power supply, and the input resistance is R. I1_1 The other end is connected to input terminal 1 of the first 4-to-1 multiplexer; the i-th input resistor R I1_i One end is connected to the end of the (i-1)th measured MIV, and the i-th input resistance R I1_i The other end is connected to input terminal 1 of the i-th 4-to-1 multiplexer; the i-th input resistor R I1_i One end is connected to the beginning of the (i-1)th MIV being measured, and the i-th input resistance R I1_i The other end is connected to input terminal 1 of the i-th 4-to-1 multiplexer; Input resistance R I2_1 One end is connected to the power supply, and the input resistance is R. I2_1 The other end is connected to input terminal 2 of the first 4-to-1 multiplexer; the i-th input resistor R I2_i One end is connected to the end of the (i-1)th measured MIV, and the i-th input resistance R I2_i The other end is connected to input terminal 2 of the i-th 4-to-1 multiplexer; the i-th input resistor R I2_i One end is connected to the beginning of the (i-1)th MIV being measured, and the i-th input resistance R I2_i The other end is connected to input terminal 2 of the i-th 4-to-1 multiplexer; Voltage divider resistor R D1 Voltage divider resistor R D1 One end is connected to the beginning of the nth MIV being measured, and the voltage divider resistor R D1 The other end is connected to input terminal 0 of the 2-to-1 multiplexer; Voltage divider resistor R D2 Voltage divider resistor R D2 One end is connected to the beginning of the nth MIV being measured, and the voltage divider resistor R D2 The other end is connected to input 1 of the 2-to-1 multiplexer.

6. The MIV test circuit based on a voltage divider according to claim 1, characterized in that, The positive input terminal of the first voltage comparator is connected to the beginning of the nth measured MIV, and the negative input terminal of the first voltage comparator is connected to resistor R. VC_1 With resistance R VC_2 Between them, the output terminal of the first voltage comparator is connected to the output terminal of the second voltage comparator; The positive input terminal of the first voltage comparator is connected to the beginning of the nth measured MIV, and the negative input terminal of the first voltage comparator is connected to resistor R. VC_1 With resistance R VC_2 Between them, the output terminals of the first voltage comparator and the second voltage comparator are connected to form the output terminal V of the entire test circuit. out ; The resistor R VC_1 One end of the resistor is connected to the power supply, and the resistor R shown is... VC_1 The other end is connected to the negative input of the first voltage comparator. The resistor R VC_2 One end of the resistor R is connected to the negative input of the first voltage comparator. VC_2 The other end is connected to the ground; The resistor R VC_3 One end of the resistor R is connected to the power supply. VC_3 The other end is connected to the negative input of the second voltage comparator. The resistor R VC_4 One end of the resistor R is connected to the negative input terminal of the second voltage comparator. VC_4 The other end is connected to the ground; The resistor R VC_5 One end of the resistor R is connected to the power supply. VC_5 The other end is connected to the output terminal V of the entire test circuit. out connect.

7. A test method for a MIV test circuit based on a voltage divider, characterized in that, Using the voltage divider-based MIV test circuit described in any one of claims 1-6, the test method includes the following steps: Step 1: Perform open-circuit fault detection on the entire MIV group. The test controller outputs a "10" command to the i-th 4-to-1 multiplexer and a "1" command to the 2-to-1 multiplexer. The test circuit will output the test output signal V. out_1 ; Step 2: Simultaneously perform leakage fault detection for the entire MIV group and short-circuit fault detection for the first half of the MIV group. The test controller outputs a "01" command to the i-th 4-to-1 multiplexer, a "00" command to the i-th 4-to-1 multiplexer, and a "0" command to the 2-to-1 multiplexer. The test circuit will output the test output signal V. out_2 ; Step 3: Perform short-circuit fault detection on the second half of the MIV group. The test controller outputs a "00" command to the i-th 4-to-1 multiplexer, a "01" command to the i-th 4-to-1 multiplexer, and a "0" command to the 2-to-1 multiplexer. The test circuit will output the test output signal V. out_3 ; Step 4: Based on the output signal V obtained in steps 1-3 out_1 Output signal V out_2 and output signal V out_3 Determine if there is a fault in the MIV group; if the test output signal V out_1 V out_2 and V out_3 If all signals are high, the tested MIV group is fault-free; if the test output signal V... out_1 V out_2 and V out_3 If any one of the test output signals is low, then the tested MIV group has a fault.

8. The test method for a MIV test circuit based on a voltage divider according to claim 7, characterized in that, The electrical model of the MIV group under fault-free conditions, where each MIV is equivalent to a resistor R MIV and capacitor C MIV The RC circuit model consists of resistor R. MIV It is the on-resistance of the MIV, and the capacitance C. MIV It is the capacitance caused by the MIV insulating wall, R I and R D These are the input resistor and voltage divider resistor set in the test circuit, respectively. Assuming the relative change in resistance is η, for a fault-free MIV group, the minimum voltage V at the test point is... MIV_normal_min and maximum voltage V MIV_normal_max They are respectively: （1） （2）。 9. The test method for a MIV test circuit based on a voltage divider according to claim 8, characterized in that, Considering the actual resistance may have manufacturing variations, the voltage range corresponding to the fault-free MIV group is V. MIV_normal_min ~V MIV_normal_max ; A dual-threshold voltage comparator is used to determine whether the voltage at the test point is within the normal voltage range. The threshold voltage setting requirement is: V TH1 ≤V MIV_normal_min V TH2 ≥V MIV_normal_max ; If V TH1 ≤V MIV ≤V TH2 Output signal V out It is a high level; if V MIV <V TH1 or V MIV >V TH2 Output signal V out It is at a low level; therefore, the output signal V out It is used directly to determine whether the MIV is faulty.

10. The test method for a MIV test circuit based on a voltage divider according to claim 9, characterized in that, The single-type MIV fault that the test method can detect meets the following condition: For an open-circuit MIV fault, the maximum value V of the test point voltage in the open-circuit state. MIV_open_max Less than the minimum voltage at the test point under fault-free conditions, V MIV_normal_min For MIV short-circuit faults, the minimum value V of the test point voltage under short-circuit conditions. MIV_short_min Greater than the maximum value V of the test point voltage under fault-free conditions MIV_normal_max ; For MIV leakage faults, the maximum value V of the voltage at the test point under leakage conditions is... MIV_leak_max Less than the minimum voltage at the test point under fault-free conditions, V MIV_normal_min , (3) (4) (5) Where R parallel1 R parallel2 and R parallel3 They are represented as follows: (6) (7) (8)。

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