Power supply detection device and power supply detection method

Abstract

A power detection device and a power detection method are disclosed. The power detection device includes a voltage generation circuit, a reference circuit, a level holding circuit and a comparison circuit. The voltage generation circuit generates a bias voltage and a detection voltage according to a power voltage. The reference circuit generates a first reference voltage according to the power voltage. The level holding circuit selectively transmits the first reference voltage to a node according to the bias voltage, outputs a second reference voltage via the node, and holds a level of the second reference voltage after stopping transmitting the first reference voltage to the node. The comparison circuit compares the second reference voltage and the detection voltage to generate a power detection signal.

Description

Technical Field

[0001] This application relates to the field of power supply detection technology, and in particular to a power supply detection device and method that can avoid low-voltage detection errors. Background Technology

[0002] In existing electronic devices, if the power supply voltage or its internal voltage experiences a momentary voltage drop due to sudden power-on or power-off events, the circuitry within the device may malfunction or malfunction. In existing technologies, power supply detection devices can determine if an excessive voltage drop has occurred by comparing a reference voltage with the power supply voltage (or a specific voltage generated based on the power supply voltage). However, in these technologies, since the reference voltage is generated based on the power supply voltage, when the power supply voltage begins to decrease, the reference voltage also decreases or deviates, causing the reference voltage to remain below the specified voltage during the power supply voltage drop. Consequently, the power supply detection device will be unable to accurately determine if an excessive voltage drop has occurred in a low-voltage environment, leading to circuit malfunctions or malfunctions in the system. Summary of the Invention

[0003] In some embodiments, one of the objectives of this invention is to provide a power supply detection device and a power supply detection method that can avoid low-voltage detection errors, thereby improving upon the shortcomings of the prior art.

[0004] In some embodiments, the power supply detection device includes a voltage generation circuit, a reference circuit, a level holding circuit, and a comparator circuit. The voltage generation circuit generates a bias voltage and a detection voltage based on a power supply voltage. The reference circuit generates a first reference voltage based on the power supply voltage. The level holding circuit selectively transmits the first reference voltage to a node based on the bias voltage, outputs a second reference voltage via the node, and maintains the level of the second reference voltage after stopping the transmission of the first reference voltage to the node. The comparator circuit compares the second reference voltage and the detection voltage to generate a power supply detection signal.

[0005] In some embodiments, the power detection method includes the following operations: generating a bias voltage and a detection voltage based on a power supply voltage; generating a first reference voltage based on the power supply voltage; selectively transmitting the first reference voltage to a node based on the bias voltage, and outputting a second reference voltage via the node, and maintaining the level of the second reference voltage after stopping the transmission of the first reference voltage to the node; and comparing the second reference voltage and the detection voltage to generate a power detection signal.

[0006] The features, implementation, and effects of this case are described in detail below with reference to the accompanying drawings, providing a preferred embodiment. Attached Figure Description

[0007] Figure 1 A schematic diagram of a power detection device is provided based on some embodiments of this case; Figure 2 Drawing based on some embodiments of this case Figure 1 A schematic diagram of the reference circuit and the level holding circuit in the diagram; Figure 3 Drawing based on some embodiments of this case Figure 1 and Figure 2 A waveform diagram of some of the signals in the diagram; Figure 4 A flowchart of a power supply detection method is provided based on some embodiments of this case.

[0008] Figure label: 100: Power supply detection device; 110: Voltage generation circuit; 120: Reference circuit; 130: Level holding circuit; 131: Switch; 140: Comparator circuit; 150: Delay circuit; 400: Power supply testing method; C: Capacitor; CLK: Clock signal; EN: Enable signal; M0~M6: Transistors; N1: Node; P1: Period; PGD: Power supply detection signal; R1, R2: Resistors; S410, S420, S430, S440: Operation; VBIAS: Bias voltage; VDD: Power supply voltage; VDET: Detection Voltage; VREF1, VREF2: Reference voltages; t0, t1: time. Detailed Implementation

[0009] All terms used herein have their common meanings. The definitions of the terms mentioned above in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this document. Similarly, this document is not limited to the various embodiments shown in this specification.

[0010] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can refer to a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.

[0011] Figure 1 A schematic diagram of a power detection device 100 is provided according to some embodiments of this invention. In some embodiments, the power detection device 100 can be used to detect whether an abnormal voltage drop occurs in the power supply voltage VDD, and accordingly generate a power detection signal PGD to notify other circuits (not shown) in the system to reset. This prevents other circuits in the system from malfunctioning due to an abnormal voltage drop in the power supply voltage VDD. In some embodiments, the power supply voltage VDD may be supplied via, but is not limited to, a battery.

[0012] In some embodiments, the power supply detection device 100 includes a voltage generation circuit 110, a reference circuit 120, a level holding circuit 130, a comparator circuit 140, and a delay circuit 150. The voltage generation circuit 110 generates a bias voltage VBIAS and a detection voltage VDET based on the power supply voltage VDD. In some embodiments, the voltage generation circuit 110 may divide the power supply voltage VDD to generate the bias voltage VBIAS and the detection voltage VDET. For example, the power supply detection device 100 may be a voltage divider circuit including several resistors connected in series, but this is not a limitation thereof. It should be understood that since the bias voltage VBIAS and the detection voltage VDET are derived from the power supply voltage VDD through a voltage divider, the level of each of the bias voltage VBIAS and the detection voltage VDET is proportional to the level of the power supply voltage VDD. Specifically, when the level of the power supply voltage VDD increases, the level of the bias voltage VBIAS and / or the level of the detection voltage VDET also increases. Alternatively, when the supply voltage VDD level goes low, the bias voltage VBIAS level and / or the detection voltage VDET level will also go low.

[0013] Reference circuit 120 generates a reference voltage VREF1 based on the power supply voltage VDD. In some embodiments, reference circuit 120 may be a simple current mirror circuit (e.g., but not limited to, [example circuit]). Figure 2 The circuit shown is implemented to reduce circuit cost. The level holding circuit 130 selectively transmits the reference voltage VREF1 to node N1 and outputs the reference voltage VREF2 via node N1 based on the bias voltage VBIAS, and maintains the level of the reference voltage VREF2 for a period of time after stopping the transmission of the reference voltage VREF1 to node N1. The comparator circuit 140 compares the reference voltage VREF2 with the detection voltage VDET to generate a power supply detection signal PGD.

[0014] When the power supply voltage VDD begins to decrease, the detection voltage VDET and the bias voltage VBIAS also begin to decrease, while the level of the reference voltage VREF2 can be maintained for a period of time by the level holding circuit 130. When the level of the detection voltage VDET is lower than the level of the reference voltage VREF2, the comparator circuit 140 can generate a power supply detection signal PGD with a specific logic value (e.g., but not limited to, logic value 0) to indicate that the level of the power supply voltage VDD is too low. Since the reference circuit 120 generates the reference voltage VREF1 based on the power supply voltage VDD and the reference circuit 120 is implemented by a simple current mirror circuit, the level of the reference voltage VREF1 may also be affected and become inaccurate when the power supply voltage VDD begins to decrease. By setting the level holding circuit 130, the level of the reference voltage VREF2 can be maintained for a period of time when the power supply voltage VDD begins to decrease, thereby ensuring that the comparator circuit 140 can still correctly detect the detection voltage VDET to generate a suitable power supply detection signal PGD. In this way, errors in low-voltage detection by the comparator circuit 140 can be avoided. Further details on this operation will be provided later. Figure 3 The waveform diagram further illustrates this. In some embodiments, the comparator circuit 140 may be implemented by a voltage comparator, but this invention is not limited thereto.

[0015] In some embodiments, the comparator circuit 140 is further activated according to the enable signal EN to begin comparing the reference voltage VREF2 and the detection voltage VDET, thereby generating a power detection signal PGD. The delay circuit 150 can generate the enable signal EN according to the clock signal CLK when the power supply voltage VDD is powered on, wherein the clock signal CLK is generated when the power supply voltage VDD is powered on. When the power supply voltage VDD is just powered on, the reference voltage VREF1, reference voltage VREF2, bias voltage VBIAS, and / or detection voltage VDET may not have reached a preset target level. The delay circuit 150 introduces a delay time when the power supply voltage VDD is just powered on, preventing the comparator circuit 140 from activating according to the enable signal EN, thus not comparing the reference voltage VREF2 and the detection voltage VDET during this delay time to avoid generating an incorrect power detection signal PGD. After this delay time, the reference voltage VREF1, reference voltage VREF2, bias voltage VBIAS, and / or detection voltage VDET can rise to their respective preset target levels. Therefore, after this delay, the comparator circuit 140 can be activated by the enable signal EN to begin comparing the reference voltage VREF2 with the detection voltage VDET.

[0016] Figure 2 Drawing based on some embodiments of this case Figure 1A schematic diagram of reference circuit 120 and level holding circuit 130 is shown. Reference circuit 120 includes multiple transistors M0 to M5 and multiple resistors R1 to R2. The first terminal (e.g., drain) of transistor M0 is coupled to the first terminal of resistor R1, the second terminal (e.g., source) of transistor M0 is coupled to ground, and the control terminal (e.g., gate) of transistor M0 is coupled to the second terminal of resistor R1. The first terminal of transistor M1 is coupled to the second terminal of transistor M2, the second terminal of transistor M1 is coupled to ground, and the control terminal of transistor M1 is coupled to the first terminal of transistor M0. The first terminal of transistor M2 receives the power supply voltage VDD, and the second terminal of transistor M2 is coupled to the control terminal of transistor M2. The first terminal of transistor M3 receives the power supply voltage VDD, the second terminal of transistor M3 is coupled to the second terminal of resistor R1, and the control terminal of transistor M3 is coupled to the second terminal and control terminal of transistor M2. The first terminal of transistor M4 receives the power supply voltage VDD. The second terminal of transistor M4 is coupled to the first terminal of resistor R2 and outputs a reference voltage VREF1. The control terminal of transistor M4 is coupled to the control terminal of transistor M2. The first terminal of transistor M5 is coupled to the control terminal of transistor M5 and the second terminal of resistor R2. The second terminal of transistor M5 is coupled to ground.

[0017] With the above arrangement, multiple transistors M0 to M3 and resistor R1 can form the circuit portion of the current mirror circuit that generates the main current, and multiple transistors M4 and M5 and resistor R2 form the circuit portion of the current mirror circuit used to mirror the main current to generate the reference voltage VREF1. The above arrangement of the reference circuit 120 is only for example and is not limited thereto.

[0018] The level-holding circuit 130 includes a switch 131 and a capacitor C. In this example, the switch 131 may be implemented by transistor M6, but this is not a limitation of the present invention. The first terminal of the switch 131 (e.g., the source of transistor M6) is coupled to the reference circuit 120 to receive the reference voltage VREF1, the second terminal of the switch 131 (e.g., the drain of transistor M6) is coupled to node N1, and the control terminal of the switch 131 (e.g., the gate of transistor M6) is coupled to... Figure 1A voltage generation circuit 110 receives a bias voltage VBIAS. A switch 131 can be selectively turned on according to the bias voltage VBIAS to transmit a reference voltage VREF1 to node N1. A capacitor C is coupled between node N1 and ground. In this example, transistor M6 can be an N-type transistor. Thus, when the power supply voltage VDD is powered on, causing the bias voltage VBIAS to have a preset target level, switch 131 can be turned on to begin transmitting the reference voltage VREF1 to node N1. Under this condition, capacitor C can be charged via the reference voltage VREF1 to generate a reference voltage VREF2. As the level of the power supply voltage VDD begins to decrease, the level of the bias voltage VBIAS also begins to decrease, causing switch 131 to gradually switch off. When the level of the power supply voltage VDD is too low, the level of the bias voltage VBIAS will be insufficient to turn on switch 131, causing switch 131 to stop transmitting the reference voltage VREF1 to node N1. Under these conditions, since capacitor C still stores the corresponding amount of charge corresponding to the level of reference voltage VREF2, and there is no active discharge path for capacitor C, capacitor C can still maintain the level of reference voltage VREF2 for a period of time.

[0019] Figure 3 Drawing based on some embodiments of this case Figure 1 and Figure 2 A waveform diagram of some of the signals in the diagram. Figure 3 This diagram illustrates the level changes of the power supply voltage VDD, the detection voltage VDET, the reference voltage VREF2, and the power supply detection signal PGD during the power-down process. During period P1, the power supply voltage VDD is at a preset target level, causing the reference voltage VREF1 and the bias voltage VBIAS (not shown) to... Figure 3 The detection voltage VDET and the level holding circuit 130 are both at preset target levels, allowing the level holding circuit 130 to transmit the reference voltage VREF1 to node N1 to generate a reference voltage VREF2 with the target level. Under this condition, the detection voltage VDET is higher than the reference voltage VREF2, so the comparator circuit 140 outputs a high-level power detection signal PGD to indicate that the power supply voltage VDD currently has the preset target level.

[0020] At time t0, the supply voltage VDD begins to decrease (e.g., the battery supplying VDD begins to deplete), causing the detection voltage VDET to also decrease. Under this condition, the reference voltage VREF2 remains constant via the level holding circuit 130. That is, at time t0, the supply voltage VDD and the bias voltage VBIAS (not shown) decrease. Figure 3The levels of both the detection voltage VDET and the reference voltage VREF1 begin to decrease. Conversely, the level holding circuit 130 maintains the level of the reference voltage VREF2 at time t0, preventing it from decreasing as the power supply voltage VDD begins to drop. As the power supply voltage VDD decreases, at time t1, the level of the detection voltage VDET falls below the level of the reference voltage VREF2. Under this condition, the comparator circuit 140 outputs a low-level power supply detection signal PGD to indicate that the power supply voltage VDD is too low, and accordingly resets other circuits in the system. After time t1, based on the low power supply voltage VDD in the system, the level of the reference voltage VREF2 also decreases. In this way, if the user externally charges the system, causing the power supply voltage VDD to return to the preset target level in the following period, other circuits in the system and the power detection device 100 can continue to operate as before, without using potentially abnormal signal values ​​and / or circuit states, thereby improving the overall reliability of system operation.

[0021] Figure 4 The following flowchart illustrates a power supply detection method 400 according to some embodiments of this invention. In operation S410, a bias voltage and a detection voltage are generated based on a power supply voltage. In operation S420, a first reference voltage is generated based on the power supply voltage. In operation S430, the first reference voltage is selectively transmitted to a node based on the bias voltage, and a second reference voltage is output via the node, maintaining the level of the second reference voltage after transmission of the first reference voltage to the node stops. In operation S440, the second reference voltage and the detection voltage are compared to generate a power supply detection signal.

[0022] The various operations of the power detection method 400 described above can be referred to the description of the foregoing embodiments, and therefore will not be repeated here. The various operations of the power detection method 400 described above are merely examples and are not limited to being executed in the order shown in this example. Without departing from the operation mode and scope of the various embodiments of this application, the various operations in the power detection method 400 may be appropriately added, replaced, omitted, or executed in a different order (for example, they may be executed simultaneously or partially simultaneously).

[0023] In summary, the power detection device and power detection method in some embodiments of this case can prevent the reference voltage used to detect the power supply voltage from decreasing along with the power supply voltage, thereby avoiding errors in low-voltage detection.

[0024] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make variations to the technical features of this case based on the express or implied content of this case. All such variations may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

Claims

1. A power supply detection device, characterized in that, include: A voltage generation circuit divides a power supply voltage to generate a bias voltage and a detection voltage. A reference circuit includes a current mirror circuit that generates a main current based on the power supply voltage and mirrors the main current to generate a first reference voltage. A level-holding circuit selectively transmits a first reference voltage to a node based on the bias voltage, outputs a second reference voltage via the node, and maintains the level of the second reference voltage after stopping the transmission of the first reference voltage to the node; as well as, A comparator circuit compares the second reference voltage and the detected voltage to generate a power supply detection signal; Specifically, when the power supply voltage level begins to decrease, the bias voltage level and the detection voltage level also begin to decrease, and the level holding circuit maintains the second reference voltage level for a period of time.

2. The power supply detection device as described in claim 1, characterized in that, The level holding circuit includes: A switch, selectively turned on according to the bias voltage, to transmit the first reference voltage to the node; and, A capacitor is coupled between the node and ground and charged via the first reference voltage to generate the second reference voltage.

3. The power supply detection device as described in claim 1, characterized in that, Also includes: A delay circuit generates an enable signal based on a clock signal when the power supply voltage is applied. The comparison circuit is further configured to be activated according to the enable signal to begin comparing the second reference voltage and the detection voltage.

4. A power supply detection method, characterized in that, include: A power supply voltage is divided to generate a bias voltage and a detection voltage; A first reference voltage is generated by using a current mirror circuit to generate a main current based on the power supply voltage and mirroring the main current. The first reference voltage is selectively transmitted to a node according to the bias voltage, and a second reference voltage is output through the node, and the level of the second reference voltage is maintained after the transmission of the first reference voltage to the node is stopped; as well as, The second reference voltage and the detected voltage are compared to generate a power supply detection signal; Specifically, when the power supply voltage level begins to decrease, the level of the second reference voltage is maintained for a period of time, and the levels of the bias voltage and the detection voltage begin to decrease when the power supply voltage level begins to decrease.

5. The power supply detection method as described in claim 4, characterized in that, The step of selectively transmitting the first reference voltage to the node according to the bias voltage, outputting the second reference voltage via the node, and maintaining the level of the second reference voltage after stopping the transmission of the first reference voltage to the node includes: A switch is selectively turned on according to the bias voltage to transmit the first reference voltage to the node via the switch; and, A capacitor is charged via the first reference voltage to generate the second reference voltage, wherein the capacitor is coupled between the node and ground.

6. The power supply detection method as described in claim 4, characterized in that, The step of comparing the second reference voltage and the detected voltage to selectively output the power supply detection signal includes: The comparison between the second reference voltage and the detected voltage begins based on an enable signal. The enable signal is generated by a delay circuit based on a clock signal when the power supply voltage is applied.

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