An inductive amplifier circuit, method, and semiconductor memory

Abstract

An embodiment of the present application provides a sense amplifier circuit, a method, and a semiconductor memory. The sense amplifier circuit includes: a transmission circuit configured to receive a signal to be processed, perform transmission processing on the signal to be processed, and obtain an initial transmission signal; and an amplifier circuit configured to receive a first control signal and the signal to be processed, and perform amplification processing on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal. In this way, signal amplification processing is performed during the signal transmission process of the sense amplifier circuit, thereby improving the signal transmission speed and reducing the signal transmission delay.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor memories, and in particular, to a sense amplifier circuit, method, and semiconductor memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers and consists of many repeated memory cells. During the data reading process, the data signals of each memory cell are sequentially read out via local data lines, global data lines, and data buses.

[0003] During the read operation of DRAM, the signal output by the local data line needs to be transmitted to the global data line. However, the path between the local data line and the global data line is relatively long, and the transmission rate of the data signal is affected by the load effect, increasing the transmission delay and affecting the performance of DRAM. Summary of the Invention

[0004] This application provides a sense amplifier circuit, method, and semiconductor memory, which can improve the signal transmission speed and reduce the signal transmission delay.

[0005] The technical solution of this application is implemented as follows:

[0006] In a first aspect, an embodiment of this application provides a sense amplifier circuit, including:

[0007] A transmission circuit, configured to receive a signal to be processed, and perform transmission processing on the signal to be processed to obtain an initial transmission signal;

[0008] An amplifier circuit, configured to receive a first control signal and the signal to be processed, and perform amplification processing on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal.

[0009] In some embodiments, the signal to be processed includes a first signal to be processed and a second signal to be processed, and the initial transmission signal includes a first initial transmission signal and a second initial transmission signal; the transmission circuit includes a first transistor and a second transistor, and is configured to receive a second control signal; and when the second control signal is in a first level state, perform transmission processing on the first signal to be processed through the first transistor to obtain the first initial transmission signal; and perform transmission processing on the second signal to be processed through the second transistor to obtain the second initial transmission signal.

[0010] In some embodiments, a first end of the first transistor is connected to a first end of the second transistor and is configured to receive the second control signal; a second end of the first transistor is configured to receive the first signal to be processed, and a third end of the first transistor is configured to output the first initial transmission signal; a second end of the second transistor is configured to receive the second signal to be processed, and a third end of the second transistor is configured to output the second initial transmission signal.

[0011] In some embodiments, the transmission circuit is further configured to control the first transistor and the second transistor to be in an on state when the second control signal is in a first level state; or control the first transistor and the second transistor to be in an off state when the second control signal is in a second level state.

[0012] In some embodiments, the amplification circuit is configured to receive a first power supply signal, a second power supply signal, and a ground signal; and amplify the initial transmission signal based on the first power supply signal and the ground signal to obtain the target transmission signal when the first control signal is in a first level state, the first signal to be processed is in a first level state, and the second signal to be processed is in a second level state; or amplify the initial transmission signal based on the second power supply signal and the ground signal to obtain the target transmission signal when the first control signal is in a first level state, the first signal to be processed is in a second level state, and the second signal to be processed is in a first level state.

[0013] In some embodiments, the target transmission signal includes a first target transmission signal and a second target transmission signal; the amplification circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, and the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are first-type transistors, and the sixth transistor and the ninth transistor are second-type transistors, and the operating voltage of the first-type transistor is less than the operating voltage of the second-type transistor; wherein, the first ends of the third transistor, the fourth transistor, and the seventh transistor are all connected to the first control signal; the second end of the fifth transistor is connected to the first power signal, the second end of the eighth transistor is connected to the second power signal, and the third end of the seventh transistor is connected to the ground signal; the first ends of the eighth transistor and the sixth transistor are both connected to the first signal to be processed; the first ends of the fifth transistor and the ninth transistor are both connected to the second signal to be processed; the third ends of the sixth transistor, the second end of the seventh transistor, and the third end of the ninth transistor are connected, the second end of the sixth transistor is connected to the third end of the third transistor, and the second end of the ninth transistor is connected to the third end of the fourth transistor; the second end of the fourth transistor is connected to the third end of the fifth transistor for outputting the first target transmission signal; the second end of the third transistor is connected to the third end of the eighth transistor for outputting the second target transmission signal.

[0014] In some embodiments, the amplification circuit is further configured to, when the first control signal is in a first level state, the first signal to be processed is in a first level state, and the second signal to be processed is in a second level state, based on the second power signal, charge the first initial transmission signal through the fifth transistor to obtain the first target transmission signal; and based on the ground signal, discharge the second initial transmission signal through the third transistor, the sixth transistor, and the seventh transistor to obtain the second target transmission signal.

[0015] In some embodiments, the amplification circuit is further configured to, when the first control signal is in a first level state, the first signal to be processed is in a first level state, and the second signal to be processed is in a second level state, determine that the fifth transistor, the sixth transistor, and the seventh transistor are in an on state, and determine that the eighth transistor and the ninth transistor are in an off state.

[0016] In some embodiments, the amplifier circuit is further configured to, when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, charge the second initial transmission signal based on the first power supply signal through the eighth transistor to obtain the second target transmission signal; and discharge the first initial transmission signal based on the ground signal through the fourth transistor, the seventh transistor, and the ninth transistor to obtain the first target transmission signal.

[0017] In some embodiments, the amplifier circuit is further configured to, when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, determine that the seventh transistor, the eighth transistor, and the ninth transistor are in the on state, and determine that the fifth transistor and the sixth transistor are in the off state.

[0018] In some embodiments, the sense amplifier circuit is further configured to generate the signal to be processed when in the selected state; or generate a reference signal when in the non-selected state; wherein the level state of the reference signal is between the operating voltages of the first type of transistor and the second type of transistor; the amplifier circuit is further configured to control the sense amplifier circuit to be in the operating state through the second type of transistor according to the signal to be processed; or control the sense amplifier circuit to be in the blocking state through the second type of transistor according to the reference signal.

[0019] In some embodiments, the amplifier circuit is further configured to control the sixth transistor to be in the on state and the ninth transistor to be in the off state, or control the sixth transistor to be in the off state and the ninth transistor to be in the on state according to the signal to be processed, so that the sense amplifier circuit is in the operating state; or control both the sixth transistor and the ninth transistor to be in the off state according to the reference signal, so that the sense amplifier circuit is in the blocking state.

[0020] In some embodiments, the first level state is higher than the second level state; the third transistor, the fourth transistor, and the seventh transistor are N-type tunneling field effect transistors, the fifth transistor and the eighth transistor are P-type tunneling field effect transistors, and the first transistor, the second transistor, the sixth transistor, and the ninth transistor are all N-type metal-oxide semiconductor field effect transistors; wherein, the first end of the P-type tunneling field effect transistor is the gate pin, the second end of the P-type tunneling field effect transistor is the source pin, and the third end of the P-type tunneling field effect transistor is the drain pin; the first end of the N-type tunneling field effect transistor is the gate pin, the second end of the N-type tunneling field effect transistor is the drain pin, and the third end of the N-type tunneling field effect transistor is the source pin; the first end of the N-type metal-oxide semiconductor field effect transistor is the gate pin, the second end of the N-type metal-oxide semiconductor field effect transistor is the drain pin, and the third end of the N-type metal-oxide semiconductor field effect transistor is the source pin.

[0021] In a second aspect, an embodiment of the present application provides a sense amplification method, which is applied to a sense amplification circuit. The method includes:

[0022] Determine a signal to be processed and a first control signal;

[0023] Perform transmission processing on the signal to be processed to obtain an initial transmission signal;

[0024] Based on the first control signal and the signal to be processed, perform amplification processing on the initial transmission signal to obtain a target transmission signal.

[0025] In some embodiments, the signal to be processed includes a first signal to be processed and a second signal to be processed, and the initial transmission signal includes a first initial transmission signal and a second initial transmission signal; the performing transmission processing on the signal to be processed to obtain an initial transmission signal includes:

[0026] Receive a second control signal; when the second control signal is in a first level state, perform transmission processing on the first signal to be processed to obtain the first initial transmission signal; and perform transmission processing on the second signal to be processed to obtain the second initial transmission signal.

[0027] In some embodiments, the sense amplification circuit includes a first transistor and a second transistor; when the second control signal is in a first level state, the method further includes:

[0028] Control the first transistor to be in an on state, and perform transmission processing on the first signal to be processed through the first transistor to obtain the first initial transmission signal; and

[0029] Control the second transistor to be in the conducting state, and transmit and process the second signal to be processed through the second transistor to obtain the second initial transmission signal.

[0030] In some embodiments, the step of amplifying the initial transmission signal based on the first control signal and the signal to be processed to obtain the target transmission signal includes:

[0031] Apply a first power signal, a second power signal, and a ground signal; when the first control signal is in the first level state, the first signal to be processed is in the first level state, and the second signal to be processed is in the second level state, amplify the initial transmission signal based on the first power signal and the ground signal to obtain the target transmission signal; or when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, amplify the initial transmission signal based on the second power signal and the ground signal to obtain the target transmission signal.

[0032] In some embodiments, the target transmission signal includes a first target transmission signal and a second target transmission signal, and the amplifying circuit further includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, the method further includes:

[0033] Based on the second power signal, charge the first initial transmission signal through the fifth transistor to obtain the first target transmission signal; based on the ground signal, discharge the second initial transmission signal through the third transistor, the sixth transistor, and the seventh transistor to obtain the second target transmission signal; wherein, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are first-type transistors, the sixth transistor and the ninth transistor are second-type transistors, and the operating voltage of the first-type transistor is less than the operating voltage of the second-type transistor.

[0034] In some embodiments, the amplifying circuit further includes an eighth transistor and a ninth transistor; when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, the method further includes:

[0035] Based on the first power signal, charge the second initial transmission signal through the eighth transistor to obtain the second target transmission signal; based on the ground signal, discharge the first initial transmission signal through the fourth transistor, the seventh transistor, and the ninth transistor to obtain the first target transmission signal.

[0036] In some embodiments, the method further includes: when the sense amplifier circuit is in a selected state, generate the signal to be processed, and control the sense amplifier circuit to be in an operating state through the second type of transistor according to the signal to be processed; when the sense amplifier circuit is in a selected state, generate a reference signal, and control the sense amplifier circuit to be in a blocking state through the second type of transistor according to the reference signal; wherein, the level state of the reference signal is between the operating voltage of the first type of transistor and the operating voltage of the second type of transistor.

[0037] In a third aspect, an embodiment of the present application provides a semiconductor memory, including the sense amplifier circuit according to any one of the first aspect.

[0038] An embodiment of the present application provides a sense amplifier circuit, a method, and a semiconductor memory. The sense amplifier circuit includes: a transmission circuit, configured to receive a signal to be processed and perform a transmission process on the signal to be processed to obtain an initial transmission signal; an amplifier circuit, configured to receive a first control signal and the signal to be processed, and perform an amplification process on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal. In this way, the signal is amplified during the signal transmission process of the sense amplifier circuit, thereby improving the signal transmission speed and reducing the signal transmission delay. Description of the Drawings

[0039] Figure 1 A schematic diagram of a signal transmission process provided for the related art;

[0040] Figure 2 Another schematic diagram of a signal transmission process provided for the related art;

[0041] Figure 3 A schematic diagram of the structure of a sense amplifier circuit provided for an embodiment of the present application;

[0042] Figure 4 Another schematic diagram of the structure of a sense amplifier circuit provided for an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the working process of a sense amplifier circuit provided for an embodiment of the present application;

[0044] Figure 6Schematic diagram of the working process of another sense amplifier circuit provided by an embodiment of the present application;

[0045] Figure 7 Schematic diagram of the structure of yet another sense amplifier circuit provided by an embodiment of the present application;

[0046] Figure 8 Schematic diagram of the current variation of different types of transistors provided by an embodiment of the present application;

[0047] Figure 9 Schematic diagram of the structure of a TFET provided by an embodiment of the present application;

[0048] Figure 10A Schematic symbol diagram of an NTFET provided by an embodiment of the present application;

[0049] Figure 10B Schematic symbol diagram of a PTFET provided by an embodiment of the present application;

[0050] Figure 11 Schematic diagram of the structure of another TFET provided by an embodiment of the present application;

[0051] Figure 12A Energy band diagram of a TFET in the off state provided by an embodiment of the present application;

[0052] Figure 12B Energy band diagram of a TFET in the on state provided by an embodiment of the present application;

[0053] Figure 13 Flow chart of a sense amplification method provided by an embodiment of the present application;

[0054] Figure 14 Schematic diagram of the structure of a semiconductor memory provided by an embodiment of the present application. Detailed implementation manners

[0055] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. In addition, it should be noted that for the convenience of description, only the parts related to the related application are shown in the drawings.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0057] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0058] It should be noted that the terms "first / second / third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0059] BL (Bit Line): Bit Line;

[0060] BLSA (Bit Line Sense Amplifier): Bit Line Sense Amplifier;

[0061] LSA (Local Sense Amplifier): Local Sense Amplifier;

[0062] LIO and / LIO: Local Data Bus;

[0063] GIO and / GIO: Global Data Bus;

[0064] I / O (Input / Output): Input / Output

[0065] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as MOS.

[0066] NMOS: N-type MOSFET, that is, electron-type MOSFET;

[0067] PMOS: P-type MOSFET, that is, hole-type MOSFET;

[0068] TFET (Tunnel Field-Effect Transistor): Tunnel Field-Effect Transistor;

[0069] NTFET: N-type TFET;

[0070] PTFET: P-type TFET;

[0071] mV / dec (mV / decade): When the current density increases or decreases by a factor of ten, the voltage changes by 1 mV.

[0072] It should be understood that with the continuous high-speed development of the semiconductor industry, the demand for wireless devices and mobile devices is also growing rapidly. Therefore, the size of dynamic random access memory (DRAM) is gradually reduced, the external power supply voltage is decreased, and the market's demand for high-speed DRAM is becoming increasingly strong.

[0073] During the data interaction process of DRAM memory, it is necessary to involve the bit line sense amplifier (BLSA), local sense amplifier (LSA), bit lines (BL and / BL), local data bus (LIO and / LIO), and global data bus (GIO and / GIO). Refer to Figure 1 , which shows a schematic diagram of a signal transmission process provided by the related art. As Figure 1 shown, when DRAM performs a read operation, the data of the selected memory cell is first transmitted to BL and / BL, then amplified by the bit line sense amplifier and transmitted to LIO and / LIO, then respectively transmitted from LIO and / LIO to GIO and / GIO, and finally transmitted backward via the input / output amplifier. Refer to Figure 2 , which shows another schematic diagram of a signal transmission process provided by the related art. As Figure 2 shown, during the process of data transmission from the LIO end to the GIO end, it is necessary to control transistors 101 and 102 through a control signal (YS) to transmit the data from LIO to GIO and from / LIO to / GIO.

[0074] As Figure 1 and Figure 2 shown, since the path of the local I / O data line is very long, driving the amplified data to the input / output amplifier (equivalent to the GIO and / GIO ends) at this time will cause the signal transmission to take a long time due to excessive load effect, thus slowing down the transmission speed. In order to improve the driving ability and increase the signal transmission speed, it is necessary to design a local sense amplifier (LSA) circuit between the bit line sense amplifier and the input / output amplifier to improve the read speed of the DRAM memory. However, the current LSA circuit still cannot meet the performance requirements of DRAM. Note that in Figure 2 , the part shown in the dashed box is not the LSA circuit but the circuit for realizing the pre-charge function.

[0075] An embodiment of the present application provides a sense amplifier circuit. The sense amplifier circuit includes: a transmission circuit for receiving a signal to be processed and performing transmission processing on the signal to be processed to obtain an initial transmission signal; an amplification circuit for receiving a first control signal and the signal to be processed, and performing amplification processing on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal. In this way, signal amplification processing is performed during the signal transmission process of the sense amplifier circuit, thereby improving the signal transmission speed and reducing signal transmission delay.

[0076] The following will describe each embodiment of the present application in detail with reference to the accompanying drawings.

[0077] In an embodiment of the present application, refer to Figure 3 , which shows a schematic structural diagram of a sense amplifier circuit 20 provided by an embodiment of the present application. As Figure 3 shown, the sense amplifier circuit 20 may include:

[0078] A transmission circuit 201 for receiving a signal to be processed and performing transmission processing on the signal to be processed to obtain an initial transmission signal;

[0079] An amplification circuit 202 for receiving a first control signal and the signal to be processed, and performing amplification processing on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal.

[0080] It should be noted that the sense amplifier circuit 20 in the embodiment of the present application is applied to various signal transmission scenarios, and those skilled in the art can apply it flexibly.

[0081] For convenience of description, the signal terminal before the input end of the sense amplifier circuit 20 is referred to as the data sending end (such as LIO and / LIO), and the signal terminal after the output end of the sense amplifier circuit 20 is referred to as the data receiving end (such as GIO and / GIO). In other words, the transmission circuit 201 obtains the signal to be processed from the data sending end, and the amplification circuit 202 sends the target transmission signal to the data receiving end.

[0082] Specifically, the transmission circuit 201 is used to control the signal transmission process, that is, whether the signal can be transmitted from the data sending end to the data receiving end. When the sense amplifier circuit 20 is working, the transmission circuit 201 receives the signal to be processed and outputs an initial transmission signal. The amplification circuit 202 is used to control the signal amplification process. When the sense amplifier circuit 20 is working, the amplification circuit 202 receives the first control signal and the signal to be processed, and amplifies the initial transmission signal so that the amplified target transmission signal can be better transmitted to the data receiving end, reducing signal delay and improving the transmission rate.

[0083] It should be noted that in the embodiments of the present application, the meaning of signal amplification at least includes: pulling up or pulling down the voltage value of the signal. Exemplarily, when the signal is in a high-level state, the signal is amplified by pulling up the voltage; when the signal is in a low-level state, the signal is amplified by pulling down the voltage.

[0084] Therefore, the amplification circuit 202 needs to receive two control signals. The first control signal is used to indicate whether the amplification circuit 202 operates, and the signal to be processed is used to indicate the object for voltage pulling up and the object for voltage pulling down of the amplification circuit.

[0085] In this way, due to the existence of the sense amplification circuit 20, not only can it control whether the signal is transmitted, but also it can amplify the signal during the transmission process (i.e., the initial transmission signal), improve the driving ability of the signal, reduce the signal transmission delay, and improve the performance of the semiconductor.

[0086] In some embodiments, the signal to be processed may include a first signal to be processed and a second signal to be processed, and the level states of the first signal to be processed and the second signal to be processed are opposite; the initial transmission signal may include a first initial transmission signal and a second initial transmission signal, and the level states of the first initial transmission signal and the second initial transmission signal are opposite.

[0087] Correspondingly, referring to Figure 4 , which shows a schematic structural diagram of another sense amplification circuit 20 provided by the embodiments of the present application. As Figure 4 shown, the transmission circuit 201 may include a first transistor 301 and a second transistor 302, and is used to receive a second control signal; and,

[0088] When the second control signal is in the first level state, the first signal to be processed is transmitted through the first transistor 301 to obtain a first initial transmission signal; and the second signal to be processed is transmitted through the second transistor 302 to obtain a second initial transmission signal.

[0089] It should be noted that the transmission circuit 201 may be arranged on the transmission link between the data sending end and the data receiving end. The working state of the transmission circuit 201 can be controlled by using the second control signal, so as to control whether the transmission link between the data sending end and the data receiving end is effective.

[0090] In some embodiments, as Figure 4As shown, the first end of the first transistor 301 is connected to the first end of the second transistor 302 for receiving a second control signal; the second end of the first transistor 301 is for receiving a first signal to be processed, and the third end of the first transistor 301 is for outputting a first initial transmission signal; the second end of the second transistor 302 is for receiving a second signal to be processed, and the third end of the second transistor 302 is for outputting a second initial transmission signal.

[0091] In some embodiments, the transmission circuit 201 is further configured to control the first transistor 301 and the second transistor 302 to be in an on state when the second control signal is in a first level state; or, control the first transistor 301 and the second transistor 302 to be in an off state when the second control signal is in a second level state.

[0092] That is to say, when the second control signal is in the first level state, both the first transistor 301 and the second transistor 302 are in an on state, so that the data sending end and the data receiving end are in a conducting state. In this way, the first signal to be processed passes through the first transistor 301 to obtain a first initial transmission signal; the second signal to be processed passes through the second transistor 302 to obtain a second initial transmission signal. Conversely, when the second control signal is in the second level state, both the first transistor 301 and the second transistor 302 are in an off state, so that the data sending end and the data receiving end are in an open state.

[0093] In the embodiments of the present application, the first level state is higher than the second level state, but the specific definition of the level state can be adjusted according to the control logic in the actual application environment, so it does not constitute a relevant limitation.

[0094] In some embodiments, the initial transmission signal may include a first initial transmission signal and a second initial transmission signal, and the level states of the first initial transmission signal and the second initial transmission signal are opposite.

[0095] Correspondingly, the amplification circuit 202 is configured to receive a first power supply signal V DD1 、a second power supply signal V DD2 and a ground signal V ss . Here, the voltage values of the first power supply signal V DD1 and the second power supply signal V DD2 are the same or close, and can be collectively referred to as the power supply signal V DD .

[0096] Correspondingly, the amplification circuit 202 is further configured to, when the first control signal is in the first level state, the first signal to be processed is in the first level state, and the second signal to be processed is in the second level state, based on the first power supply signal V DD1 and the ground signal V ssAmplify the initial transmission signal to obtain a target transmission signal; or, when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, based on the second power supply signal V DD2 and the ground signal V ss Amplify the initial transmission signal to obtain a target transmission signal.

[0097] It should be noted that the signal amplification process can be understood as: using the power supply signal V DD to pull up the high-level signal in the initial transmission signal, and using the ground signal to pull down the low-level signal in the initial transmission signal. It can be understood that the "high-level signal" and "low-level signal" mentioned in the embodiments of the present application are two level signals with relative high and low levels with respect to the reference voltage. For example, when the voltage of the power supply signal V DD is 1.8V, the reference voltage can be half of the power supply signal voltage, 1 / 2V DD , that is, 0.9V. Then, a level signal higher than 0.9V can be understood as a high-level signal, and a level signal lower than 0.9V can be understood as a low-level signal.

[0098] The following takes the local data line in the DRAM as the data sending end and the global data line in the DRAM as the data receiving end as an application scenario to specifically illustrate the embodiments of the present application, but this does not constitute a relevant limitation.

[0099] It should be understood that in the DRAM, the local data line includes LIO and / LIO, and the global data line includes GIO and / GIO. For the convenience of description, the signals corresponding to LIO and GIO are respectively called the first signal to be processed, the first initial transmission signal, and the first target transmission signal; the signals corresponding to / LIO and / GIO are respectively called the second signal to be processed, the second initial transmission signal, and the second target transmission signal. Here, the first target transmission signal and the second target transmission signal are used to form the target transmission signal, and the level states of the first target transmission signal and the second target transmission signal are opposite.

[0100] In the first example case, when the DRAM reads a logic "1" during a read operation, the first signal to be processed is a high-level signal, and the second signal to be processed is a low-level signal. At this time, use the second power supply signal V DD2 to perform a voltage pull-up process on the first initial transmission signal to obtain the first target transmission signal; at the same time, use the ground signal to perform a voltage pull-down process on the second initial transmission signal to obtain the second target transmission signal.

[0101] In the second exemplary scenario, when the DRAM reads a logic "0" during a read operation, the first signal to be processed is a low-level signal, and the second signal to be processed is a high-level signal. At this time, the ground signal is used to pull down the voltage of the first initial transmission signal to obtain the first target transmission signal; at the same time, the first power supply signal V DD1 is used to pull up the voltage of the second initial transmission signal to obtain the second target transmission signal.

[0102] In this way, by amplifying the initial transmission signal, the transmission performance of the signal can be improved, the transmission rate of the signal can be increased, and the signal transmission delay can be reduced.

[0103] In some embodiments, the amplifier circuit 202 includes a third transistor 303, a fourth transistor 304, a fifth transistor 305, a sixth transistor 306, a seventh transistor 307, an eighth transistor 308, and a ninth transistor 309. The third transistor 303, the fourth transistor 304, the fifth transistor 305, the seventh transistor 307, and the eighth transistor 308 are first-type transistors, and the sixth transistor 306 and the ninth transistor 309 are second-type transistors. The operating voltage of the first-type transistor is less than the operating voltage of the second-type transistor.

[0104] It should be noted that in the embodiments of the present application, different types of field effect transistors are used to construct the amplifier circuit, that is, on the basis of the second-type transistor, a first-type transistor with a smaller operating voltage is introduced, hoping that the amplifier circuit can better adapt to the low-voltage environment, thereby reducing the power consumption of the amplifier circuit itself and improving the performance of the DRAM.

[0105] In a specific example, as Figure 4 shown, the first ends of the third transistor 303, the fourth transistor 304, and the seventh transistor 307 are all connected to the first control signal; the second end of the fifth transistor 305 is connected to the first power supply signal V DD1 is connected, the second end of the eighth transistor 308 is connected to the second power supply signal V DD2 is connected, and the third end of the seventh transistor 307 is connected to the ground signal V ss is connected; the first ends of the eighth transistor 308 and the sixth transistor 306 are both connected to the first signal to be processed; the first ends of the fifth transistor 305 and the ninth transistor 309 are both connected to the second signal to be processed; the third ends of the sixth transistor 306, the second end of the seventh transistor 307, and the third end of the ninth transistor 309 are connected, the second end of the sixth transistor 306 and the third end of the third transistor 303 are connected, and the second end of the ninth transistor 309 and the third end of the fourth transistor 304 are connected;

[0106] The second terminal of the fourth transistor 304 is connected to the third terminal of the fifth transistor 305 for outputting a first target transmission signal; the second terminal of the third transistor 303 is connected to the third terminal of the eighth transistor 308 for outputting a second target transmission signal.

[0107] Based on the specific circuit composition of the foregoing amplifier circuit, the signal amplification process of the amplifier circuit will be further described below.

[0108] In the foregoing first example case, refer to Figure 5 , which shows a schematic diagram of the working process of an inductive amplifier circuit 20 provided in an embodiment of the present application. As Figure 5 shown, the amplifier circuit 202 is further configured to, when the first control signal is in the first level state, the first signal to be processed is in the first level state, and the second signal to be processed is in the second level state, based on the second power supply signal V DD2 , charge the first initial transmission signal through the fifth transistor 305 to obtain a first target transmission signal; and based on the ground signal, discharge the second initial transmission signal through the third transistor 303, the sixth transistor 306, and the seventh transistor 307 to obtain a second target transmission signal.

[0109] Specifically, as shown in Figure 5 , the amplifier circuit 202 is further configured to, when the first control signal is in the first level state, the first signal to be processed is in the first level state, and the second signal to be processed is in the second level state, determine that the fifth transistor 305, the sixth transistor 306, and the seventh transistor 307 are in the conducting state, and determine that the eighth transistor 308 and the ninth transistor 309 are in the off state. It should be understood that in Figure 5 , the transistor at a is in the off state, and other transistors are in the conducting state.

[0110] In the foregoing second example case, refer to Figure 6 , which shows a schematic diagram of the working process of another inductive amplifier circuit 20 provided in an embodiment of the present application. As Figure 6 shown, the amplifier circuit 202 is further configured to, when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, based on the first power supply signal V DD1 , charge the second initial transmission signal through the eighth transistor 308 to obtain a second target transmission signal; and based on the ground signal, discharge the first initial transmission signal through the fourth transistor 304, the seventh transistor 307, and the ninth transistor 309 to obtain a first target transmission signal.

[0111] Specifically, as Figure 6As shown, the amplifier circuit 202 is further configured to determine that the seventh transistor 307, the eighth transistor 308, and the ninth transistor 309 are in the on state, and determine that the fifth transistor 305 and the sixth transistor 306 are in the off state when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state. It should be understood that in Figure 6 the transistor at position b is in the off state, and the other transistors are in the on state.

[0112] It should be noted that the data read out by the DRAM in the first example case and the second example case is different. Assuming that in the first case, the DRAM needs to read a logic "1", and in the second case, the DRAM needs to read a logic "0", the working process of the amplifier circuit includes:

[0113] (1) When the DRAM reads a logic "1" during a read operation, the first control signal is in the high level state, the first signal to be processed is a high level signal, and the second signal to be processed is a low level signal. At this time, the fifth transistor 305 is turned on, and the second power supply signal V DD2 is used to charge the first initial transmission signal, thereby completing the voltage pull-up process of the first initial transmission signal; the third transistor 303, the sixth transistor 306, and the seventh transistor 307 are turned on, and the ground signal is used to discharge the second initial transmission signal, thereby completing the voltage pull-down process of the second initial transmission signal.

[0114] (2) When the DRAM needs to read a logic "0", the first control signal is in the high level state, the first signal to be processed is a low level signal, and the second signal to be processed is a high level signal. At this time, the eighth transistor 308 is turned on, and the first power supply signal V DD1 is used to charge the second initial transmission signal, thereby completing the voltage pull-up process of the second initial transmission signal; the fourth transistor 304, the seventh transistor 307, and the ninth transistor 309 are turned on, and the ground signal is used to discharge the first initial transmission signal, thereby completing the voltage pull-down process of the first initial transmission signal.

[0115] In this way, through the first control signal and the signal to be processed, the working states of the fifth transistor 305 to the ninth transistor 309 can be controlled, so as to realize the amplification process of the initial transmission signal, thereby improving the signal transmission rate and improving the signal delay. At the same time, the amplifier circuit is implemented by two types of transistors, and can work in a low voltage environment, with a wider range of application scenarios.

[0116] In some embodiments, the first type of field effect transistor is a metal-oxide-semiconductor field effect transistor (MOSFET), and the second type of field effect transistor is a tunneling field effect transistor (TFET).

[0117] Accordingly, the third transistor 303, the fourth transistor 304, and the seventh transistor 307 are N-type tunneling field effect transistors (NTFETs), the fifth transistor 305 and the eighth transistor 308 are P-type tunneling field effect transistors (PTFETs), and the first transistor 301, the second transistor 302, the sixth transistor 306, and the ninth transistor 309 are all N-type metal-oxide semiconductor field effect transistors (NMOSs).

[0118] It should be noted that, in the foregoing description, the first end of the PTFET is the gate pin, the second end of the PTFET is the source pin, and the third end of the PTFET is the drain pin; the first end of the NTFET is the gate pin, the second end of the NTFET is the drain pin, and the third end of the NTFET is the source pin; the first end of the NMOS is the gate pin, the second end of the NMOS is the drain pin, and the third end of the NMOS is the source pin.

[0119] It should be noted that, compared with MOS transistors, TFETs have a lower operating voltage and can operate at a low operating voltage. For a detailed description of TFETs, please refer to the subsequent embodiments.

[0120] In the embodiments of the present application, the voltage values of the first power signal V DD1 and the second power signal V DD2 are the same or close, and can be collectively referred to as V DD . For the NTFET, it can be turned on when the gate voltage is greater than 1 / 2V DD ; for the PTFET, it is turned on when the gate voltage is less than 1 / 2V DD . In this way, the amplifier circuit 202 can be controlled in a lower voltage environment, thereby reducing power consumption and improving control efficiency.

[0121] In addition, the necessity of the sixth transistor 306 and the ninth transistor 309 is explained.

[0122] It should be understood that in a DRAM, there are a large number of memory cells, and the memory cells in different regions need to be transferred to the global data line through different local data lines. Before the DRAM performs a read operation, all local data lines are charged to a reference value (generally 1 / 2V DD ), and then the selected memory cell is read, and a signal to be processed is generated on the local data line corresponding to the selected memory cell. However, the local data lines corresponding to those unselected memory cells do not generate valid signals.

[0123] Assume that the sixth transistor 306 and the ninth transistor 309 do not exist in the sense amplifier circuit 202. For the local data lines corresponding to those unselected memory cells, LIO and / LIO are at 1 / 2VDD state. If the fifth transistor 305 and the eighth transistor 308 are ordinary MOSFETs, their operating voltage is greater than 1 / 2V DD , at this time, the fifth transistor 305 and the eighth transistor 308 are not conducting, so no effective signal to be processed is generated on LIO and / LIO.

[0124] However, in the embodiment of the present application, since the fifth transistor 305 and the eighth transistor 308 employ TFETs, the operating voltage of the TFETs is relatively low, such that the fifth transistor 305 and the eighth transistor 308 are conducting at 1 / 2V DD state, which will cause a direct current (DC) to be generated between LIO and GIO and between / LIO and / GIO, thus giving an error signal. To solve this problem, as Figures 4 - 6 shown, a sixth transistor 306 and a ninth transistor 309 are added to the sense amplifier circuit 20. The sixth transistor 306 and the ninth transistor 309 are in an off state at 1 / 2V DD , thereby blocking the invalid current on the unselected LIO and / LIO data lines.

[0125] Therefore, in some embodiments, the sense amplifier circuit 20 is further configured to generate the signal to be processed when in a selected state; or generate a reference signal when in a non - selected state; wherein, the level state of the reference signal is between the operating voltage of the first type of transistor and the operating voltage of the second type of transistor;

[0126] The amplifier circuit 20 is further configured to control the sense amplifier circuit 20 to be in an operating state through the second type of transistor according to the signal to be processed; or control the sense amplifier circuit 20 to be in a blocking state through the second type of transistor according to the reference signal.

[0127] Here, the selected state of the sense amplifier circuit 20 means that the memory cell selected during the read operation of the DRAM is connected to the sense amplifier circuit 20; the non - selected state of the sense amplifier circuit 20 means that the memory cell selected during the read operation of the DRAM is not connected to the sense amplifier circuit 20.

[0128] Specifically, the amplifier circuit 20 is further configured to control the sixth transistor 306 to be in a conducting state and the ninth transistor 309 to be in a closed state according to the signal to be processed, or control the sixth transistor 306 to be in a closed state and the ninth transistor 309 to be in a conducting state, so that the sense amplifier circuit 20 is in an operating state; or control the sixth transistor 306 and the ninth transistor 309 to be in an off state according to the reference signal, so that the sense amplifier circuit 20 is in a blocking state.

[0129] In this way, through the sixth transistor 306 and the ninth transistor 309 of the second type, it is possible to prevent the sense amplifier circuit 20 from generating extra current in the unselected state and prevent signal errors.

[0130] In summary, the embodiment of the present application provides a local sense amplifier circuit with a hybrid process composed of MOSFET and TFET. In the circuit, TFET is used to replace some MOSFET transistors, and the source terminal of the NTFET transistor is connected to V SS , and the source terminal of the PTFET transistor is connected to V DD power supply, overcoming the unidirectional conductivity problem of the TFET transistor. At the same time, transistors of two different processes are used to form a differential circuit structure to amplify the signals transmitted from the LIO and / LIO data lines to a certain extent. Thereby improving the read speed of the DRAM memory.

[0131] The embodiment of the present application provides a sense amplifier circuit. The sense amplifier circuit includes: a transmission circuit for receiving a signal to be processed and performing transmission processing on the signal to be processed to obtain an initial transmission signal; an amplification circuit for receiving a first control signal and the signal to be processed, and amplifying the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal. In this way, the signal is amplified during the signal transmission process of the sense amplifier circuit, thereby improving the signal transmission speed and reducing the signal transmission delay.

[0132] In another embodiment of the present application, refer to Figure 7 , which shows a schematic structural diagram of another sense amplifier circuit 20 provided by the embodiment of the present application. As Figure 7 shown, the sense amplifier circuit 20 may include:

[0133] A transmission circuit 201 for receiving a signal to be processed and performing transmission processing on the signal to be processed to obtain an initial transmission signal;

[0134] An amplification circuit 202 for receiving a first control signal and the signal to be processed, and amplifying the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal.

[0135] It should be noted that in the embodiment of the present application, the sense amplifier circuit 20 is taken as an example to be arranged between the local data lines (LIO and / LIO) and the global data lines (GIO and / GIO) of the DRAM for explanation, but this does not constitute a relevant limitation.

[0136] That is, in some embodiments, the sensing amplifier circuit 20 is located between the local data line and the global data line, and is used to receive the signal to be processed from the local data line through the transmission circuit 201, and transmit the target transmission signal to the global data line through the amplifier circuit 202.

[0137] In some embodiments, Figure 7 As shown, the amplifier circuit 202 includes a first type transistor 2021 and a second type transistor 2022, which is used to control the working state of the first type transistor using a first control signal and a signal to be processed, and to control the working state of the second type transistor using the signal to be processed to obtain a target transmission signal.

[0138] The operating voltage of the first type transistor 2021 is lower than the operating voltage of the second type transistor 2022 .

[0139] It should be noted that the amplifier circuit 202 has two types of field effect transistors, and the operating voltage of the first type transistor 2021 is lower than the operating voltage of the second type transistor 2022. In other words, a field effect transistor with a low operating voltage is introduced into the amplifier circuit 202, so that the amplifier circuit 202 can work in a low voltage environment and better play a role in signal amplification.

[0140] Exemplarily, the first type transistor 2021 may be a tunneling field effect transistor TFET, and the second type transistor 2022 may be a metal-oxide semiconductor field effect transistor MOSFET.

[0141] It should be noted that in order to achieve the goal of increasing the DRAM reading speed, the industry has proposed many circuit structures of inductive amplifier circuits, but while achieving high speed, it also increases dynamic power consumption. Therefore, the embodiment of the present application hopes to provide an inductive amplifier circuit that not only improves the signal transmission speed, but also reduces the circuit power consumption as much as possible. Therefore, the embodiment of the present application focuses on a tunneling field effect transistor TFET with a low operating voltage and a very high switching current ratio. The working principle of TFET is band-to-band tunneling, which is itself a source and drain doped asymmetric structure. Its working characteristic is unidirectional conductivity. Its advantages are low operating voltage, small subthreshold swing, low off-state current, and high switching current ratio.

[0142] See also Figure 8 , which shows a schematic diagram of current changes of different types of transistors provided in the embodiment of the present application. Wherein, the X-axis (i.e., the horizontal axis) represents V g , which is the gate voltage, and the Y-axis (i.e., vertical axis) represents Log I d , which is the logarithm of the drain current, curve b is used to indicate TFET, and curve a is used to indicate MOSFET.Figure 8 As shown, the subthreshold swing S of the MOSFET is 60 mV / dec. The subthreshold swing S of the MOSFET can break through the limit of 60 mV / decade, and the I off (off-state current) of the TFET is very low, so the operating voltage of the TFET can be further reduced. As Figure 8 shown by the dashed line in, under the condition of a relatively small gate voltage Vg, the I on (on-state current) and I on / I off of the TFET are both greater than the I on and I on / I off of the traditional MOSFET. Therefore, the TFET is a very promising logic device with low operating voltage and low power consumption.

[0143] The TFET can specifically be a double-gate indium arsenide (InAs) heterojunction tunneling field-effect transistor structure. Refer to Figure 9 , which shows a schematic structural diagram of a TFET provided by an embodiment of the present application. As Figure 9 shown, the TFET includes an InAs source region, a drain region, and a double gate (Gate). The TFET device structure is similar to that of the MOSFET. In the MOSFET, the source and drain dopings are of the same type, and the doping type is opposite to that of the substrate. While in the TFET, the source and drain are of opposite doping types. And the drain region has the same high-concentration doping type as the substrate, that is Figure 9 is an example of the NTFET. According to the structural configuration, the TFET is essentially equivalent to a combination of several devices: (1) a reverse P-I-N diode is in the off state; (2) a tunneling diode is in the on state; (3) a MOS diode forms an inversion layer or a barrier layer under the action of the gate voltage.

[0144] In addition, the TFET includes the NTFET and the PTFET. The symbol of the NTFET is as Figure 10A shown, and the symbol of the PTFET is as Figure 10B shown. In the NTFET, the substrate is lightly doped N-type, and the source region and the drain region are heavily doped P-type and N-type respectively. For the P-type TFET, the substrate is lightly doped P-type, and the source region and the drain region are heavily doped N-type and P-type respectively.

[0145] Refer to Figure 11 , which shows another schematic structural diagram of a TFET provided by an embodiment of the present application. As Figure 11 shown, the TFET sequentially includes a P-type heavily doped region (i.e., the P + region, hereinafter referred to as P for short), a lightly doped region (i.e., the I region, hereinafter referred to as I for short), and an N-type heavily doped region (i.e., the N +Region, hereinafter referred to as N). When the TFET transistor is in equilibrium, the built-in potential of the P-I and I-N junctions will generate a stepped energy band profile. See Figure 12A , which shows the energy band diagram of a TFET transistor provided by an embodiment of the present application in the off state. See Figure 12B , which shows the energy band diagram of a TFET transistor provided by an embodiment of the present application in the on state. In FIGS. 12A and 12B, Ec and Ev represent different valence bands. As Figure 12A shown, when the TFET transistor is in the off state, the P-I-N diode is reverse biased, resulting in a thick tunneling barrier between different energy bands in the working region. The thick tunneling barrier reduces the tunneling probability, thus generating a very small off-state current. As Figure 12B shown, when the TFET transistor is in the on state, as the gate voltage increases, the width of the tunneling barrier gradually decreases, and charge carriers tunnel from the valence band of the source region to the conduction band of the channel region, and then reach the conduction band of the drain region. This process of band-to-band tunneling is the main reason for the injection of carriers from the source region. Due to the existence of the band-to-band tunneling (BTBT) barrier, the off-state current of the TFET transistor is always lower than that of the traditional MOSFET transistor.

[0146] Let V gs represent the voltage between the gate and the source, and let V th represent the operating voltage of the TEFT. When V gs >V th , the NTFET transistor is turned on. When V gs <V th , the PTFET transistor is turned on. In the off state, the P-I-N diode is always reverse biased, thus generating an ultra-low leakage current. Taking the NTFET as an example, the substrate is lightly doped N-type. As the gate (G) voltage increases, it causes the accumulation in the N region. In the NTFET, when an appropriate bias voltage is applied to the gate, electrons tunnel from the P-type doped region into the channel and then flow into the N-type doped region.

[0147] That is to say, as Figure 11 shown, t ox represents the thickness of the gate dielectric, t siRepresents the thickness of the bulk silicon. The TFET is a P+-I-N+ structure, with a gate dielectric and a gate electrode above the I region. It controls the current of the device by modulating the energy band of the I region through the change of the gate voltage. In the NTFET, the substrate is lightly doped N-type, the P-doped region is called the source (electron source), and the N-doped region is called the drain. When Vgs > Vth, the NTFET conducts. For the PTFET, its substrate is lightly doped P-type, and a negative gate voltage can form accumulated holes. Electrons tunnel from the P-channel region into the N-doped region, and holes are generated in the channel and flow to the P-doped region. Therefore, in the PTFET, the P-doped region is named the drain (D), and the N-doped region is called the source (S).

[0148] Thus, by introducing the TFET into the amplifier circuit, it is expected that the amplifier circuit can better adapt to the low-voltage environment, thereby reducing the power consumption of the amplifier circuit itself and improving the performance of the DRAM.

[0149] Here, the amplifier circuit 202 cannot be entirely composed of the first type of transistor 2021 for the following reasons:

[0150] Since the operating voltage of the first type of transistor 2021 is relatively low and it can be in the on state at 1 / 2V DD invalid currents will be generated in the amplifier circuits 202 corresponding to those unselected memory cells. Specifically, even if the sense amplifier circuit 20 does not receive the signal to be processed, the circuit nodes in the sense amplifier circuit 20 will be charged to the voltage of 1 / 2V DD during the pre-charge process. In this case, the first type of transistor 2021 will conduct, thereby generating invalid currents.

[0151] Therefore, in some embodiments, the sense amplifier circuit 20 is further configured to generate a signal to be processed when in the selected state, and control the sense amplifier circuit 20 to be in the operating state through the second type of transistor 2022 according to the signal to be processed; or

[0152] generate a reference signal when in the unselected state, and control the sense amplifier circuit 20 to be in the blocking state through the second type of transistor 2022 according to the reference signal;

[0153] wherein, the level state of the reference signal is between the operating voltage of the first type of transistor 2021 and the operating voltage of the second type of transistor 2022.

[0154] It should be noted that the second type of transistor 2022 also needs to be introduced into the amplifier circuit 202 to block the invalid current in the unselected state. For specific details, please refer to the foregoing embodiments.

[0155] In some embodiments, such as Figure 4As shown, the sense amplifier circuit 20 includes three NTFET transistors, two PTFET transistors, and four MOSFET transistors. Among them, the three NTFETs are respectively denoted as the third transistor 303, the fourth transistor 304, and the seventh transistor 307, the two PTFET transistors are respectively denoted as the fifth transistor 305 and the eighth transistor 308, and the four MOSFET transistors are respectively denoted as the first transistor 301, the second transistor, the sixth transistor 306, and the ninth transistor 309. Their specific connection relationship is as Figure 4 shown.

[0156] The first control signal for controlling the DRAM memory to perform a read operation is electrically connected to the gate of the seventh transistor 307, and the source of the seventh transistor 307 is electrically connected to V SS electrically connected; the second control signal is electrically connected to the gates of the first transistor 301 and the second transistor 302; the source terminals of the eighth transistor 308 and the fifth transistor 305 are electrically connected to V DD electrically connected; LIO is electrically connected to the gate of the sixth transistor 306, and / LIO is electrically connected to the gate of the ninth transistor 309; the drain of the fourth transistor 304 is electrically connected to GIO, and the drain of the eighth transistor 308 is electrically connected to / GIO; the source of the sixth transistor 306 is electrically connected to the source of the third transistor 303; the source of the ninth transistor 309 is electrically connected to the source of the fourth transistor 304;

[0157] In the hold state, both the first control signal and the second control signal are at a low level of "0". When the DRAM memory performs a read "1" operation, the first control signal and the second control signal are set to a high level of "1". At this time, LIO is at a high level of "1", / LIO is at a low level of "0", the seventh transistor 307 - the fourth transistor 304 and the fifth transistor 305, the sixth transistor 306 are turned on, and the eighth transistor 308 and the ninth transistor 309 are turned off. The / GIO signal is discharged to VSS through the seventh transistor 307, the third transistor 303, and the sixth transistor 306. At the same time, V DD charges GIO to V DD through the sixth transistor 306. The read "1" operation is completed. When the DRAM memory performs a read "0" operation, the first control signal and the second control signal are set to a high level of "1". At this time, LIO is at a high level of "0", / LIO is at a low level of "1", the seventh transistor 307 ~ the fourth transistor 304 and the eighth transistor 308, the ninth transistor 309 are turned on, and the fifth transistor 305 and the sixth transistor 306 are turned off. The GIO signal is discharged to V SS through the seventh transistor 307, the fourth transistor 304, and the ninth transistor 309. At the same time, V DD charges / GIO to V DD。The "read 0" operation is completed. In this way, using this circuit structure improves the DRAM read speed, reduces the LIO data line load effect, and has low power consumption and high control efficiency.

[0158] During the precharge phase, there are unselected LIO data lines (LIO data lines corresponding to unselected memory cells). At this time, both the LIO data line and the / LIO data line are at 1 / 2V DD , there is a DC current after the fifth transistor 305 and the eighth transistor 308 are turned on. Therefore, the sixth transistor 306 and the ninth transistor 309 are used to block the DC current path between the LIO and GIO data lines. In this way, there will be no additional impact on the unselected LIO data lines.

[0159] That is to say, when the DRAM memory executes a read operation, since the unselected LIO data lines have been charged to 1 / 2V DD , at this time, the fifth transistor 305 / the eighth transistor 308 is turned on, causing a DC current to pass between the LIO and GIO. Therefore, the sixth transistor 306 and the ninth transistor 309 are added to block the signal transmission on the unselected LIO data lines.

[0160] In summary, the embodiment of the present application provides a sense amplifier circuit. In order to enable the transistor to conduct normally at a low operating voltage, TFET is partially used in the circuit to replace the traditional MOSFET, and the first control signal is used to separately control the conduction and cutoff of the TFET transistor. In order to improve the DRAM read speed, a differential structure and a pull-up structure are adopted to amplify the 0 / 1 signals transmitted to a certain extent to compensate for the level loss that occurs during the signal transmission process. In addition, since the TFET transistor can conduct and work below 1 / 2V DD , traditional MOSFET transistors are used as switches on the main data lines of the LIO and GIO to control the on and off. In particular, when the DRAM memory executes a read operation, since the unselected LIO data lines have been charged to 1 / 2V DD , at this time, the fifth transistor 305 and the eighth transistor 308 are turned on, causing a DC current to pass between the LIO and GIO. Therefore, the sixth transistor 306 and the ninth transistor 309 are added to block the signal transmission on the unselected LIO data lines.

[0161] The embodiment of the present application provides a sense amplifier circuit. Through this embodiment, the foregoing embodiments are further explained. By using TFET to replace some MOSFET transistors in the circuit, the source terminal of the NTFET transistor is connected to V SS , and the source terminal of the PTFET transistor is connected to V DDThe power supply overcomes the unidirectional conductivity problem of the TFET transistor, and at the same time uses transistors of two different processes to form a differential circuit structure to amplify the signals transmitted from the LIO and / LIO data lines to a certain extent, thereby improving the read speed of the DRAM memory.

[0162] In another embodiment of the present application, refer to Figure 13 , which shows a schematic flowchart of a sense amplification method provided by an embodiment of the present application. As Figure 13 shown, the method may include:

[0163] S401: Determine the signal to be processed and the first control signal.

[0164] It should be noted that the sense amplification method in the embodiment of the present application is applied to the sense amplification circuit 20, and the sense amplification circuit 20 can be set in a variety of signal transmission scenarios, and those skilled in the art can apply it flexibly. The structure of the sense amplification circuit 20 can be as described above Figures 3 - 7 shown.

[0165] Here, the signal to be processed refers to the signal that needs to be transmitted in the signal transmission scenario, and the first control signal is used to control whether the sense amplification circuit 20 performs signal amplification operations.

[0166] In the embodiment of the present application, the sense amplification circuit 20 is set between the local data line and the global data line as an application scenario for specific explanation. In other words, the sense amplification circuit 20 receives the signal to be processed from the local data line (LIO and / LIO), and transmits the target transmission signal to the global data line (GIO and / GIO).

[0167] S402: Perform transmission processing on the signal to be processed to obtain an initial transmission signal.

[0168] S403: Amplify the initial transmission signal based on the first control signal and the signal to be processed to obtain a target transmission signal.

[0169] It should be noted that in a specific application scenario, the signal to be processed will lose a certain level state during transmission due to the load effect, and at the same time the transmission rate is slow. Therefore, in the embodiment of the present application, during the signal transmission process, the initial transmission signal is amplified to obtain a target transmission signal, thereby improving the signal transmission rate and reducing the signal transmission delay.

[0170] Here, the amplification process of the initial transmission signal is carried out via the first control signal and the signal to be processed.

[0171] In some embodiments, such as Figure 7As shown, the sense amplifier circuit 20 includes a first type of transistor 2021 and a second type of transistor 2022. The amplifying the initial transmission signal based on the first control signal and the signal to be processed to obtain the target transmission signal may include:

[0172] Controlling the operating state of the first type of transistor using the first control signal and the signal to be processed, and controlling the operating state of the second type of transistor using the signal to be processed, so that the first type of transistor and the second type of transistor jointly amplify the initial transmission signal to obtain the target transmission signal.

[0173] In some embodiments, the signal to be processed includes a first signal to be processed and a second signal to be processed, and the initial transmission signal includes a first initial transmission signal and a second initial transmission signal; the transmitting and processing the signal to be processed to obtain the initial transmission signal may include:

[0174] Receiving a second control signal;

[0175] When the second control signal is in the first level state, transmitting and processing the first signal to be processed to obtain the first initial transmission signal; and transmitting and processing the second signal to be processed to obtain the second initial transmission signal.

[0176] It should be noted that the sense amplifier circuit 20 also needs to receive the second control signal and control the main signal transmission process according to the second control signal.

[0177] As Figure 4 shown, the sense amplifier circuit 20 includes a transmission circuit 201 and an amplifier circuit 202. Among them, the second control signal is used to control the operating state of the transmission circuit 201, thereby controlling the signal transmission process; the first control signal and the signal to be processed are used to control the operating state of the amplifier circuit 202, thereby controlling the signal amplification process.

[0178] In some embodiments, the sense amplifier circuit 20 includes a first transistor 301 and a second transistor 302; when the second control signal is in the first level state, the method may further include:

[0179] Controlling the first transistor 301 to be in the conducting state, and transmitting and processing the first signal to be processed through the first transistor 301 to obtain the first initial transmission signal; and

[0180] Controlling the second transistor 302 to be in the conducting state, and transmitting and processing the second signal to be processed through the second transistor 302 to obtain the second initial transmission signal.

[0181] It should be noted that the first transistor 301 is disposed between LIO and GIO, and the second transistor 302 is disposed between / LIO and / GIO. Thus, when the first transistor 301 and the second transistor 302 are turned on, the first signal to be processed outputs a first initial transmission signal through the first transistor 301, and the second signal to be processed outputs a second initial transmission signal through the second transistor 302. Here, the first initial transmission signal and the second initial transmission signal together form the initial transmission signal.

[0182] In some embodiments, the amplifying the initial transmission signal based on the signal to be processed to obtain a target transmission signal may include:

[0183] Applying a first power signal V DD1 and a second power signal V DD2 and a ground signal V SS ;

[0184] When the first control signal is in the first level state, the first signal to be processed is in the first level state, and the second signal to be processed is in the second level state, amplifying the initial transmission signal based on the first power signal V DD1 and the ground signal V SS to obtain a target transmission signal; or

[0185] When the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, amplifying the initial transmission signal based on the second power signal V DD2 and the ground signal V SS to obtain a target transmission signal.

[0186] It should be noted that the signal amplification process can be understood as: using the power signal to pull up the high-level signal in the initial transmission signal, and using the ground signal to pull down the low-level signal in the initial transmission signal.

[0187] It should be understood that the local data lines include LIO and / LIO, and the global data lines include GIO and / GIO. For convenience of description, the signals located at LIO and GIO are respectively referred to as the first signal to be processed, the first initial transmission signal, and the first target transmission signal; the signals located at / LIO and / GIO are respectively referred to as the second signal to be processed, the second initial transmission signal, and the second target transmission signal. Here, the first target transmission signal and the second target transmission signal are used to form the target transmission signal, and the level states of the first target transmission signal and the second target transmission signal are opposite.

[0188] In one case, when the DRAM needs to read a logic "1", the first signal to be processed is a high-level signal, and the second signal to be processed is a low-level signal. At this time, using the second power signal VDD2 Responsible for performing voltage pull-up processing on the first initial transmission signal to obtain a first target transmission signal; at the same time, using the ground signal to perform voltage pull-down processing on the second initial transmission signal to obtain a second target transmission signal.

[0189] In another case, when the DRAM needs to read a logic "0", the first signal to be processed is a low-level signal, and the second signal to be processed is a high-level signal. At this time, using the low signal to perform voltage pull-down processing on the first initial transmission signal to obtain a first target transmission signal; at the same time, using the first power supply signal V DD1 Perform voltage pull-up processing on the second initial transmission signal to obtain a second target transmission signal.

[0190] In some embodiments, such as Figure 5 As shown, the amplifier circuit further includes a third transistor 303, a fourth transistor 304, a fifth transistor 305, a sixth transistor 306, and a seventh transistor 307; when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, the method may further include:

[0191] Based on the second power supply signal V DD2 , charge the first initial transmission signal through the fifth transistor 305 to obtain a first target transmission signal;

[0192] Based on the ground signal, discharge the second initial transmission signal through the third transistor 303, the sixth transistor 306, and the seventh transistor 307 to obtain a second target transmission signal.

[0193] In some embodiments, such as Figure 6 As shown, the sense amplifier circuit 20 further includes an eighth transistor 308 and a ninth transistor 309; when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, the method may further include:

[0194] Based on the first power supply signal V DD1 , charge the second initial transmission signal through the eighth transistor 308 to obtain a second target transmission signal;

[0195] Based on the ground signal, discharge the first initial transmission signal through the fourth transistor 304, the seventh transistor 307, and the ninth transistor 309 to obtain a first target transmission signal.

[0196] Exemplarily, (1) when the DRAM needs to read a logic '1', the first control signal is in a high level state, the first signal to be processed is a high level signal, and the second signal to be processed is a low level signal. At this time, the fifth transistor 305 is turned on, and the first initial transmission signal is charged using the second power signal, thereby completing the voltage pull-up process of the first initial transmission signal; the third transistor 303, the sixth transistor 306, and the seventh transistor 307 are turned on, and the second initial transmission signal is discharged using the ground signal, thereby completing the voltage pull-down process of the second initial transmission signal.

[0197] (2) When the DRAM needs to read a logic '0', the first control signal is in a high level state, the first signal to be processed is a low level signal, and the second signal to be processed is a high level signal. At this time, the eighth transistor 308 is turned on, and the second initial transmission signal is charged using the first power signal V DD1 thereby completing the voltage pull-up process of the second initial transmission signal; the fourth transistor 304, the seventh transistor 307, and the ninth transistor 309 are turned on, and the first initial transmission signal is discharged using the ground signal, thereby completing the voltage pull-down process of the first initial transmission signal.

[0198] In the embodiments of the present application, for the NTFET, it can be turned on when the gate voltage is greater than or equal to 1 / 2V DD ; for the PTFET, it is turned on when the gate voltage is less than or equal to 1 / 2V DD . In this way, the amplifier circuit 202 can be controlled in a lower voltage environment, thereby reducing power consumption and improving control efficiency. However, if only TFETs are used in the amplifier circuit, it will cause an invalid current to be generated on the unselected LIO data line, as described above. Therefore, conventional MOSFET transistors also need to be introduced into the amplifier circuit to block the invalid current when unselected

[0199] Therefore, in some embodiments, the method may further include:

[0200] When the sense amplifier circuit is in a selected state, generating the signal to be processed and controlling the sense amplifier circuit to be in an operating state according to the signal to be processed;

[0201] When the sense amplifier circuit is in a selected state, generating a reference signal and controlling the sense amplifier circuit to be in a blocking state according to the reference signal;

[0202] wherein, the level state of the reference signal is between the operating voltage of the first type of transistor and the operating voltage of the second type of transistor.

[0203] In this way, through the first control signal, the second control signal, and the signal to be processed, the working state of the sense amplifier circuit can be controlled, thereby realizing the amplification processing of the initial transmission signal, improving the signal transmission rate, and reducing signal delay. Meanwhile, the amplifier circuit is implemented by two types of transistors and can operate in a low-voltage environment, with a wider range of application scenarios.

[0204] An embodiment of the present application provides a sense amplification method, which may include: determining a signal to be processed and a first control signal; performing transmission processing on the signal to be processed to obtain an initial transmission signal; and performing amplification processing on the initial transmission signal based on the first control signal and the signal to be processed to obtain a target transmission signal. In this way, signal amplification processing is performed during the signal transmission process of the sense amplifier circuit, thereby improving the signal transmission speed and reducing signal transmission delay.

[0205] In another embodiment of the present application, refer to Figure 14 , which shows a schematic structural diagram of a semiconductor memory 50 provided by an embodiment of the present application. As Figure 14 shown, the semiconductor memory 40 includes the sense amplifier circuit 20 of any one of the foregoing embodiments.

[0206] In some embodiments, the semiconductor memory 50 at least includes a dynamic random access memory DRAM.

[0207] An embodiment of the present application provides a semiconductor memory, which includes the foregoing sense amplifier circuit, and performs signal amplification processing during signal transmission, thereby improving the signal transmission speed and reducing signal transmission delay.

[0208] The above are only the preferred embodiments of the present application and are not intended to limit the protection scope of the present application.

[0209] It should be noted that in the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including one..." does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0210] The serial numbers of the above embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0211] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0212] The features disclosed in several product embodiments provided by this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0213] The features disclosed in several method or device embodiments provided by this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0214] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and all should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. An induction amplification circuit, characterized in that, Comprising: A transmission circuit, configured to receive a signal to be processed and perform transmission processing on the signal to be processed to obtain an initial transmission signal; An amplification circuit, configured to receive a first control signal and the signal to be processed, and perform amplification processing on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal; wherein, The signal to be processed includes a first signal to be processed and a second signal to be processed, and the initial transmission signal includes a first initial transmission signal and a second initial transmission signal; The transmission circuit includes a first transistor and a second transistor, and is configured to receive a second control signal; and when the second control signal is in a first level state, perform transmission processing on the first signal to be processed through the first transistor to obtain the first initial transmission signal; and perform transmission processing on the second signal to be processed through the second transistor to obtain the second initial transmission signal The amplification circuit is configured to receive a first power supply signal, a second power supply signal, and a ground signal; and When the first control signal is in a first level state, the first signal to be processed is in a first level state, and the second signal to be processed is in a second level state, perform amplification processing on the initial transmission signal based on the first power supply signal and the ground signal to obtain the target transmission signal; or, When the first control signal is in a first level state, the first signal to be processed is in a second level state, and the second signal to be processed is in a first level state, perform amplification processing on the initial transmission signal based on the second power supply signal and the ground signal to obtain the target transmission signal; The target transmission signal includes a first target transmission signal and a second target transmission signal; the amplification circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, and the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are first-type transistors, the sixth transistor and the ninth transistor are second-type transistors, and the operating voltage of the first-type transistor is less than the operating voltage of the second-type transistor; wherein, The first ends of the third transistor, the fourth transistor, and the seventh transistor are all connected to the first control signal; the second end of the fifth transistor is connected to the first power supply signal, the second end of the eighth transistor is connected to the second power supply signal, and the third end of the seventh transistor is connected to the ground signal; the first ends of the eighth transistor and the sixth transistor are both connected to the first signal to be processed; the first ends of the fifth transistor and the ninth transistor are both connected to the second signal to be processed; the third ends of the sixth transistor, the second end of the seventh transistor, and the third end of the ninth transistor are connected, the second end of the sixth transistor and the third end of the third transistor are connected, and the second end of the ninth transistor and the third end of the fourth transistor are connected; The second terminal of the fourth transistor is connected to the third terminal of the fifth transistor and is used to output the first target transmission signal; the second terminal of the third transistor is connected to the third terminal of the eighth transistor and is used to output the second target transmission signal.

2. The sense amplifier circuit according to claim 1, wherein The first terminal of the first transistor is connected to the first terminal of the second transistor and is used to receive the second control signal; The second terminal of the first transistor is used to receive the first signal to be processed, and the third terminal of the first transistor is used to output the first initial transmission signal; The second terminal of the second transistor is used to receive the second signal to be processed, and the third terminal of the second transistor is used to output the second initial transmission signal.

3. The sense amplifier circuit according to claim 2, wherein The transmission circuit is further configured to control the first transistor and the second transistor to be in an on state when the second control signal is in a first level state; or control the first transistor and the second transistor to be in an off state when the second control signal is in a second level state.

4. The sense amplifier circuit according to claim 1, wherein The amplifier circuit is further configured to, when the first control signal is in a first level state, the first signal to be processed is in a first level state, and the second signal to be processed is in a second level state, based on the second power supply signal, charge the first initial transmission signal through the fifth transistor to obtain the first target transmission signal; and based on the ground signal, discharge the second initial transmission signal through the third transistor, the sixth transistor, and the seventh transistor to obtain the second target transmission signal.

5. The sense amplifier circuit according to claim 4, wherein The amplifier circuit is further configured to, when the first control signal is in a first level state, the first signal to be processed is in a first level state, and the second signal to be processed is in a second level state, determine that the fifth transistor, the sixth transistor, and the seventh transistor are in an on state, and determine that the eighth transistor and the ninth transistor are in an off state.

6. The sense amplifier circuit according to claim 1, wherein The amplifier circuit is further configured to, when the first control signal is in a first level state, the first signal to be processed is in a second level state, and the second signal to be processed is in a first level state, based on the first power supply signal, charge the second initial transmission signal through the eighth transistor to obtain the second target transmission signal; and based on the ground signal, discharge the first initial transmission signal through the fourth transistor, the seventh transistor, and the ninth transistor to obtain the first target transmission signal.

7. The sense amplifier circuit according to claim 6, wherein The amplification circuit is further configured to determine that the seventh transistor, the eighth transistor, and the ninth transistor are in an on state, and determine that the fifth transistor and the sixth transistor are in an off state when the first control signal is in a first level state, the first signal to be processed is in a second level state, and the second signal to be processed is in a first level state.

8. The sense amplifier circuit according to claim 1, wherein the sense amplifier circuit is further configured to generate the signal to be processed when in a selected state; or generate a reference signal when in a non-selected state; wherein the level state of the reference signal is between the operating voltage of the first type of transistor and the operating voltage of the second type of transistor; the amplification circuit is further configured to control the sense amplifier circuit to be in an operating state through the second type of transistor according to the signal to be processed; or control the sense amplifier circuit to be in a blocking state through the second type of transistor according to the reference signal.

9. The sense amplifier circuit according to claim 8, wherein the amplification circuit is further configured to control the sixth transistor to be in an on state and the ninth transistor to be in an off state according to the signal to be processed, or control the sixth transistor to be in an off state and the ninth transistor to be in an on state, so that the sense amplifier circuit is in an operating state; or control the sixth transistor and the ninth transistor to be in an off state according to the reference signal, so that the sense amplifier circuit is in a blocking state.

10. The inductive amplifier circuit according to claim 5, wherein The first level state is higher than the second level state; the third transistor, the fourth transistor, and the seventh transistor are N-type tunneling field effect transistors, the fifth transistor and the eighth transistor are P-type tunneling field effect transistors, and the first transistor, the second transistor, the sixth transistor, and the ninth transistor are all N-type metal-oxide semiconductor field effect transistors; wherein the first end of the P-type tunneling field effect transistor is a gate pin, the second end of the P-type tunneling field effect transistor is a source pin, and the third end of the P-type tunneling field effect transistor is a drain pin; the first end of the N-type tunneling field effect transistor is a gate pin, the second end of the N-type tunneling field effect transistor is a drain pin, and the third end of the N-type tunneling field effect transistor is a source pin; the first end of the N-type metal-oxide semiconductor field effect transistor is a gate pin, the second end of the N-type metal-oxide semiconductor field effect transistor is a drain pin, and the third end of the N-type metal-oxide semiconductor field effect transistor is a source pin.

11. An induction amplification method, characterized in that, Applied to a sense amplifier circuit, the method includes: determining a signal to be processed and a first control signal; performing transmission processing on the signal to be processed to obtain an initial transmission signal; performing amplification processing on the initial transmission signal based on the first control signal and the signal to be processed to obtain a target transmission signal; The signal to be processed includes a first signal to be processed and a second signal to be processed, and the initial transmission signal includes a first initial transmission signal and a second initial transmission signal; performing transmission processing on the signal to be processed to obtain an initial transmission signal includes: Receiving a second control signal; When the second control signal is in a first level state, performing transmission processing on the first signal to be processed to obtain the first initial transmission signal; and performing transmission processing on the second signal to be processed to obtain the second initial transmission signal; The induction amplification circuit includes a first transistor and a second transistor; when the second control signal is in a first level state, the method further includes: Controlling the first transistor to be in an on state, and performing transmission processing on the first signal to be processed through the first transistor to obtain the first initial transmission signal; and Controlling the second transistor to be in an on state, and performing transmission processing on the second signal to be processed through the second transistor to obtain the second initial transmission signal; Amplifying the initial transmission signal based on the first control signal and the signal to be processed to obtain a target transmission signal includes: Applying a first power signal, a second power signal, and a ground signal; When the first control signal is in a first level state, the first signal to be processed is in a first level state, and the second signal to be processed is in a second level state, amplifying the initial transmission signal based on the first power signal and the ground signal to obtain the target transmission signal; or When the first control signal is in a first level state, the first signal to be processed is in a second level state, and the second signal to be processed is in a first level state, amplifying the initial transmission signal based on the second power signal and the ground signal to obtain the target transmission signal; The target transmission signal includes a first target transmission signal and a second target transmission signal, and the amplification circuit further includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; when the first control signal is in a first level state, the first signal to be processed is in a second level state, and the second signal to be processed is in a first level state, the method further includes: Based on the second power signal, charging the first initial transmission signal through the fifth transistor to obtain the first target transmission signal; Based on the ground signal, discharging the second initial transmission signal through the third transistor, the sixth transistor, and the seventh transistor to obtain the second target transmission signal; Wherein, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are first-type transistors, the sixth transistor and the ninth transistor are second-type transistors, and the operating voltage of the first-type transistors is less than the operating voltage of the second-type transistors.

12. The induction amplification method according to claim 11, wherein The amplifier circuit further includes an eighth transistor and a ninth transistor; when the first control signal is in the first level state, the first signal to be processed is in the second level state, and the second signal to be processed is in the first level state, the method further includes: Based on the first power supply signal, charge the second initial transmission signal through the eighth transistor to obtain the second target transmission signal; Based on the ground signal, discharge the first initial transmission signal through the fourth transistor, the seventh transistor, and the ninth transistor to obtain the first target transmission signal.

13. The induction amplification method according to claim 12, characterized in that, The method further includes: When the sense amplifier circuit is in the selected state, generate the signal to be processed, and according to the signal to be processed, control the sense amplifier circuit to be in the working state through the second type of transistor; When the sense amplifier circuit is in the selected state, generate a reference signal, and according to the reference signal, control the sense amplifier circuit to be in the blocking state through the second type of transistor; Wherein, the level state of the reference signal is between the operating voltage of the first type of transistor and the operating voltage of the second type of transistor.

14. A semiconductor memory, characterized in that, Comprising the sense amplifier circuit according to any one of claims 1 to 10.

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