A data read / write circuit

Abstract

The application provides a data read-write circuit, which comprises a control circuit, a port selection circuit and a single-port RAM; the control circuit is used for processing a first clock signal generated by a clock source, and the clock period of an output port selection signal is n times that of the first clock signal; the port selection circuit is used for receiving the port selection signal, and in the i th clock period of the first clock signal, an i th input signal group received by an i th first input terminal group is selected and output based on the port selection signal; and the single-port RAM is used for receiving and processing an i th output signal group output by the port selection circuit. By selecting one port for data processing in each clock period of the first clock signal, the data processing of multiple ports is simultaneously realized in one clock period of the port selection signal, so that the single-port RAM is used to realize the function of a multi-port RAM, the implementation is simple, the circuit can be applied to different scenes, and the flexibility of chip use is improved.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a data read / write circuit. Background Technology

[0002] With the continuous expansion of computer applications and the increasing amount of information processed, the demands on memory speed and capacity are also rising. To improve memory access speed, dual-port random access memory (RAM) capable of simultaneous read / write operations on two ports has been designed. However, in actual development, it has been found that certain manufacturing processes cannot provide dual-port RAM, and dual-port RAM can only perform read / write operations on two ports simultaneously, not on more ports. Therefore, how to implement multi-port RAM functionality using single-port RAM has become one of the urgent technical problems to be solved. Summary of the Invention

[0003] This application provides a data read / write circuit that enables the use of a single-port RAM to perform the functions of a multi-port RAM, allowing simultaneous read / write operations on multiple ports.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] A first aspect of this application provides a data read / write circuit, comprising: a control circuit, a port selection circuit, and a single-port RAM; the control circuit is used to process a first clock signal generated by a clock source and output a port selection signal; wherein the clock period of the port selection signal is n times the clock period of the first clock signal, and n is an integer greater than or equal to 2; the port selection circuit includes a first selection terminal, n first input terminal groups, and a first output terminal group, the first selection terminal being coupled to the output terminal of the control circuit; each first input terminal group is used to receive an input signal group; the port selection circuit is used to receive the port selection signal and, in the i-th clock period of the first clock signal, select and output the input signal group received by the i-th first input terminal group based on the port selection signal, where i is an integer greater than or equal to 1 and less than or equal to n; the single-port RAM includes a second input terminal group, the second input terminal group being coupled to the first output terminal group; the single-port RAM is used to receive the i-th output signal group output by the first output terminal group in the i-th clock period of the first clock signal and process the i-th output signal group.

[0006] In conjunction with the first aspect, in one possible implementation, the aforementioned data read / write circuit further includes: a data output circuit, comprising a second selection terminal, a third input terminal, and n third output terminals; the second selection terminal is coupled to the output terminal of the control circuit, and the third input terminal is coupled to the second output terminal of the single-port RAM; the third input terminal is used to receive n data input signals output from the second output terminal of the single-port RAM; the data output circuit is used to process the received n data input signals to generate n data output signals, and outputs n data output signals in the (n+2)th clock cycle of the first clock signal.

[0007] In combination with the first aspect and the above possible implementations, in another possible implementation, the control circuit includes:

[0008] The first logic sub-circuit includes n fourth input terminals and a fourth output terminal; each fourth input terminal is used to receive an enable input signal; the first logic sub-circuit is used to generate and output an enable output signal based on the received n enable input signals.

[0009] The gated clock sub-circuit includes a fifth input terminal, a first clock terminal, and a second clock terminal; the fifth input terminal is coupled to a fourth output terminal; the fifth input terminal is used to receive an enable output signal; the first clock terminal is used to receive a first clock signal generated by a clock source, and the second clock terminal is used to receive a second clock signal, the clock period of the second clock signal being n times the clock period of the first clock signal; the gated clock sub-circuit is used to process the first clock signal based on the enable output signal and the second clock signal, generate and output a gated clock signal, the clock period of the gated clock signal being consistent with the clock period of the first clock signal;

[0010] The port conversion sub-circuit includes a third clock terminal and a fifth output terminal. The third clock terminal is coupled to the clock output terminal of the gated clock sub-circuit, and the fifth output terminal is the output terminal of the control circuit. The port conversion sub-circuit is used to process the gated clock signal output from the clock output terminal to generate and output a port selection signal.

[0011] In combination with the first aspect and the above possible implementations, in another possible implementation, the gated clock sub-circuit includes:

[0012] The first delay unit includes a sixth input terminal, a fourth clock terminal, and (n-1) sixth output terminals; the sixth input terminal is the fifth input terminal of the gated clock sub-circuit, and the fourth clock terminal is the second clock terminal of the gated clock sub-circuit; the first delay unit is used to perform (n-1) delay processing on the enable output signal based on the second clock signal, generating and outputting (n-1) delayed signals; wherein, the j-th delayed signal is j clock cycles slower than the enable output signal, and j is an integer greater than or equal to 1 and less than or equal to (n-1);

[0013] The first logic unit includes n seventh input terminals, one seventh input terminal is coupled to the fourth output terminal, and the remaining (n-1) seventh input terminals are respectively coupled to the (n-1) sixth output terminals of the first delay unit; the first logic unit is used to generate and output a gating enable signal based on the enable output signal and (n-1) delay signals;

[0014] The gating unit includes an eighth input terminal and a fifth clock terminal. The eighth input terminal is coupled to the output terminal of the first logic unit, and the fifth clock terminal is the first clock terminal of the gating clock sub-circuit. The gating unit is used to generate and output a gating clock signal based on the first clock signal and the gating enable signal.

[0015] In combination with the first aspect and the above possible implementations, in another possible implementation, the fourth output terminal of the first logic sub-circuit is coupled to the enable terminal of the single-port RAM, and the enable terminal of the single-port RAM is used to receive the enable output signal.

[0016] The clock output of the gated clock sub-circuit is coupled to the clock output of the single-port RAM.

[0017] In combination with the first aspect and the above possible implementations, in another possible implementation, the port selection circuit includes: a first selection sub-circuit and n input sub-circuits;

[0018] The first selection sub-circuit includes a first selection input terminal, which is the first selection terminal of the port selection circuit; the first selection input terminal is used to receive a port selection signal; the first selection sub-circuit is used to generate and output a first selection signal to enable the i-th input sub-circuit based on the port selection signal in the i-th clock cycle of the first clock signal.

[0019] Each input sub-circuit includes a first input enable terminal, a ninth input terminal group, and a seventh output terminal group; all n first input enable terminals are coupled to the output terminal of the first selection sub-circuit, the n ninth input terminal groups are coupled to the n first input terminal groups respectively, and the n seventh output terminal groups are coupled to the first output terminal groups; the first input enable terminal is used to receive the first selection signal; the i-th input sub-circuit is used to receive the i-th input signal group, and when the i-th first selection signal is received, it generates and outputs the i-th output signal group.

[0020] In combination with the first aspect and the above possible implementations, in another possible implementation, the ninth input terminal group includes a write enable input terminal, an address input terminal and a write data input terminal, and the input signal group includes a write enable input signal, an address input signal and a write data input signal;

[0021] The seventh output terminal group includes a write enable output terminal, an address output terminal, and a write data output terminal. The output signal group includes a write enable output signal, an address output signal, and a write data output signal.

[0022] In combination with the first aspect and the above possible implementations, in another possible implementation, the data output circuit includes: a second selection sub-circuit and n data output sub-circuits;

[0023] The second selection sub-circuit includes a second selection input terminal, which is the second selection terminal of the data output circuit; the second selection input terminal is used to receive a port selection signal; the second selection sub-circuit is used to generate and output a second selection signal to enable the i-th data output sub-circuit based on the port selection signal in the (i+1)-th clock cycle of the first clock signal.

[0024] Each data output sub-circuit includes a second input enable terminal, a tenth input terminal, and an eighth output terminal; n second input enable terminals are all coupled to the output terminal of the second selection sub-circuit, and n tenth input terminals are all coupled to the third input terminal; n eighth output terminals are respectively coupled to n third output terminals; the second input enable terminal is used to receive the second selection signal; the i-th data output sub-circuit is used to receive the data input signal input from the tenth input terminal, and when the i-th second selection signal is received, it processes the received i-th data input signal to generate the i-th data output signal, and outputs the i-th data output signal in the (n+2)-th clock cycle of the first clock signal.

[0025] In combination with the first aspect and the above possible implementations, in another possible implementation, the clock output of the gated clock sub-circuit is coupled to the clock output of each data output sub-circuit.

[0026] In combination with the first aspect and the above possible implementations, in another possible implementation, the i-th data output sub-circuit includes a second delay unit;

[0027] The second delay unit includes an enable terminal, a data input terminal, and a clock terminal; the enable terminal is the second input enable terminal, the data input terminal is the tenth input terminal, and the clock terminal is coupled to the clock output terminal of the gated clock sub-circuit; the enable terminal is used to receive the second selection signal, the data input terminal is used to receive the i-th data input signal, and the clock terminal is used to receive the gated clock signal; the second delay unit is used to perform (n-i+1) delay processing on the i-th data input signal based on the gated clock signal, and generate and output the i-th data output signal.

[0028] A second aspect of this application provides a storage device, which includes a controller and a data read / write circuit as described in the first aspect above.

[0029] A third aspect of the embodiments of this application provides a terminal device, which includes a processor and a memory, the memory including the data read / write circuit as described in the first aspect above.

[0030] The data read / write circuit provided in this application embodiment has one clock cycle of the port selection signal corresponding to multiple clock cycles of the first clock signal. In each clock cycle of the first clock signal, a port is selected from multiple ports and data processing is performed on that port. This allows data processing of multiple ports to be performed simultaneously in one clock cycle of the port selection signal, thereby using a single-port RAM to implement the function of a multi-port RAM. The implementation method is simple, applicable to different application scenarios, and improves the flexibility of chip use. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a data read / write circuit provided in an embodiment of this application.

[0032] Figure 2 This is a signal timing diagram of a data writing circuit provided in an embodiment of this application.

[0033] Figure 3 This is a schematic diagram of another data read / write circuit provided in an embodiment of this application.

[0034] Figure 4 The signal timing diagram is provided for another data read circuit according to an embodiment of this application.

[0035] Figure 5 The following is a signal timing diagram of another data read / write circuit provided in an embodiment of this application.

[0036] Figure 6 This is a schematic diagram of another data read / write circuit provided in an embodiment of this application.

[0037] Figure 7 This is a signal timing diagram of another data read circuit provided in an embodiment of this application.

[0038] Figure 8 This is a schematic diagram of another data read / write circuit provided in an embodiment of this application.

[0039] Figure 9 This is a schematic diagram of another data read / write circuit provided in an embodiment of this application.

[0040] Figure 10 This is a schematic diagram of another data read / write circuit provided in an embodiment of this application.

[0041] Figure 11 This is a schematic diagram of the structure of a RAM control logic conversion circuit provided in an embodiment of this application.

[0042] Figure 12 The signal timing diagram of the RAM control logic conversion circuit provided in the embodiment of this application during a write operation.

[0043] Figure 13 The signal timing diagram of the RAM control logic conversion circuit provided in the embodiment of this application during a read operation. Detailed Implementation

[0044] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple. Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order. For example, the "first" in the first switch and the "second" in the second switch in the embodiments of this application are only used to distinguish different switches. The descriptions of "first" and "second" appearing in the embodiments of this application are only for illustration and to distinguish the described objects, and have no order, nor do they indicate a special limitation on the number of devices in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0045] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0046] To address the limitation of existing memory systems, which can only perform read and write operations on a fixed number of ports simultaneously and are therefore applicable to a limited range of scenarios, this application provides a data read and write circuit. This circuit uses a single-port RAM to implement the functions of a multi-port RAM, which is simple to implement, applicable to different application scenarios, and improves the flexibility of chip usage.

[0047] Figure 1 This is a schematic diagram of a data read / write circuit provided in an embodiment of this application, as shown below. Figure 1 As shown, the data read / write circuit includes a control circuit, a port selection circuit, and a single-port RAM.

[0048] The control circuit is used to process the first clock signal generated by the clock source and output a port selection signal. The clock period of the port selection signal is n times the clock period of the first clock signal, where n is an integer greater than or equal to 2.

[0049] For example, in the embodiments of this application, n is an integer greater than or equal to 2, and the specific value of n is not limited. In practical applications, the value of n can be determined in combination with the number of ports that are processing data simultaneously. For example, when two ports need to perform read and write operations simultaneously, n is 2; when four ports need to perform read and write operations simultaneously, n is 4.

[0050] In some examples, n is related to the number of ports used to implement a multi-port RAM using a single-port RAM. For example, when n is 2, a single-port RAM is used to implement the function of a dual-port RAM. As another example, when n is 4, a single-port RAM is used to implement the function of a 4-port RAM. This disclosure does not limit the value of n; the following embodiments use n=2 as an example for illustrative purposes.

[0051] The port selection circuit includes a first selection terminal A and n first input terminal groups B1 to B2. n And the first output terminal group C. The first selection terminal A is coupled to the output terminal Q of the control circuit. Each first input terminal group B1 to B n It is used to receive input signal groups. The port selection circuit is used to receive the port selection signal output by the output terminal Q, and in the i-th clock cycle of the first clock signal, selects and outputs the i-th first input terminal group B based on the port selection signal. i The received input signal group, where i is an integer greater than or equal to 1 and less than or equal to n, i.e., i = 1, 2, ..., n.

[0052] The single-port RAM includes a second input group D, which is coupled to a first output group C. The single-port RAM is used to receive the i-th output signal group output from the first output group C during the i-th clock cycle of a first clock signal, and to process the i-th output signal group.

[0053] For example, Figure 2 A signal timing diagram of a data write circuit provided in an embodiment of this application is shown below. Figure 2As shown in the figure, n is represented by a value of 2. The first clock signal is the clock signal generated by the clock source, and the port selection signal is the clock signal output by the output terminal Q of the control circuit. The clock period of the port selection signal is twice the clock period of the first clock signal.

[0054] In the first clock cycle of the first clock signal, the port selection circuit selects the input signal group to be received from the first input group B1 to the first input group B2, and outputs the input signal group from the first output group C. The input signal group is received by the second input group D of the single-port RAM, and the single-port RAM performs a write operation based on the input signal group.

[0055] During the second clock cycle of the first clock signal, the port selection circuit selects the input signal group to be received from the first input group B2 among the first input group B1 to the first input group B2, and outputs the input signal group by the first output group C. The input signal group is received by the second input group D of the single-port RAM, and the single-port RAM performs a write operation based on the input signal group.

[0056] In this way, the write processing of the input signal groups received by the two first input terminal groups is realized in two clock cycles of the first clock signal, which is one clock cycle of the port selection signal.

[0057] The data read / write circuit provided in this application embodiment has one clock cycle of the port selection signal corresponding to multiple clock cycles of the first clock signal. In each clock cycle of the first clock signal, a port is selected from multiple ports and data processing is performed on that port. This allows data processing of multiple ports to be performed simultaneously in one clock cycle of the port selection signal, thereby using a single-port RAM to implement the function of a multi-port RAM. The implementation method is simple, applicable to different application scenarios, and improves the flexibility of chip use.

[0058] For example, such as Figure 3 As shown, in Figure 1 Based on the illustrated embodiment, the data read / write circuit may further include a data output circuit. The data output circuit includes a second selection terminal E, a third input terminal F, and n third output terminals G1 to G2. n The second selection terminal E is coupled to the output terminal Q of the control circuit, and the third input terminal F is coupled to the second output terminal P of the single-port RAM. The third input terminal F is used to receive n data input signals output from the second output terminal P of the single-port RAM. The data output circuit is used to process the received n data input signals, generate n data output signals, and output n data output signals in the (n+2)th clock cycle of the first clock signal.

[0059] For example, Figure 4 A signal timing diagram of another data read circuit provided in an embodiment of this application is shown below. Figure 4 As shown in the figure, n is represented by a value of 2. The first clock signal is the clock signal generated by the clock source, and the port selection signal is the clock signal output by the output terminal Q of the control circuit. The clock period of the port selection signal is twice the clock period of the first clock signal.

[0060] In the second clock cycle of the first clock signal (reading data occurs in the next clock cycle after data is written to the single-port RAM, therefore the data output circuit can only receive the first data input signal from the second output terminal P starting from the second clock cycle), the third input terminal F of the data output circuit receives the first data input signal from the second output terminal P. The port selection circuit selects the third output terminal G1 from the third output terminals G1 to G2 to process the received first data input signal and generate the first data output signal. The read operation of the first port is completed in the second clock cycle of the first clock signal.

[0061] During the third clock cycle of the first clock signal, the third input terminal F of the data output circuit receives the second data input signal output from the second output terminal P. The port selection circuit selects the third output terminal G2 from the third output terminals G1 to G2 to read the received second data input signal and generate the second data output signal. The read operation of the second port is completed during the third clock cycle of the first clock signal.

[0062] In this way, the two data input signals output by the single-port RAM can be read and processed within two clock cycles of the first clock signal, which is also one clock cycle of the port selection signal.

[0063] For example, Figure 5 A signal timing diagram of another data read / write circuit provided in the embodiments of this application is shown below. Figure 5 As shown in the figure, n is represented by a value of 2. The first clock signal is the clock signal generated by the clock source, and the port selection signal is the clock signal output by the output terminal Q of the control circuit. The clock period of the port selection signal is twice the clock period of the first clock signal.

[0064] In the first clock cycle of the first clock signal, the port selection circuit selects the input signal group to be received from the first input group B1 to the first input group B2, and outputs the input signal group from the first output group C. The input signal group is received by the second input group D of the single-port RAM, and the single-port RAM performs a write operation based on the input signal group.

[0065] During the second clock cycle of the first clock signal, the port selection circuit selects the input signal group to receive from the first input group B2 (from the first input group B1 to the first input group B2), and outputs the input signal group from the first output group C. The second input group D of the single-port RAM receives the input signal group, and the single-port RAM performs a write operation based on the input signal group. Simultaneously, during this clock cycle, the data output circuit reads the data written in the first clock cycle: the third input F of the data output circuit receives the first data input signal output from the second output P, ​​and the port selection circuit selects the third output G1 (from the third output G1 to the third output G2) to read the received first data input signal, generating the first data output signal.

[0066] During the third clock cycle of the first clock signal, the third input terminal F of the data output circuit receives the second data input signal output by the second output terminal P. The port selection circuit selects the third output terminal G2 from the third output terminals G1 to G2 to read and process the received second data input signal, and generates the second data output signal.

[0067] In the fourth clock cycle of the first clock signal, the third output terminal G1 outputs the first data output signal, and the third output terminal G2 outputs the second data output signal. In this way, the read and write processing of the two data input signals output by the single-port RAM is realized in four clock cycles of the first clock signal, which is also two clock cycles of the port selection signal.

[0068] The data read / write circuit provided in this application embodiment has one clock cycle of the port selection signal corresponding to multiple clock cycles of the first clock signal. In each clock cycle of the first clock signal, a port is selected from multiple ports and data processing is performed on that port. This allows multiple ports to be read / written simultaneously in two clock cycles of the port selection signal, thereby implementing the function of a multi-port RAM using a single-port RAM. The implementation method is simple, applicable to different application scenarios, and improves the flexibility of chip use.

[0069] Figure 6 A schematic diagram of another data read / write circuit provided in the embodiments of this application is shown below. Figure 6 As shown above, Figure 1 or Figure 3 The control circuit in the illustrated embodiment may include: a first logic sub-circuit, a gated clock sub-circuit, and a port conversion sub-circuit.

[0070] The first logic sub-circuit includes n fourth input terminals H1 to H2. n and the fourth output terminal K, and each of the fourth input terminals H1 to H nIt is used to receive enable input signals. The first logic sub-circuit is used to generate and output an enable output signal based on the received n enable input signals.

[0071] Using an example where n is 2, the first logic sub-circuit includes two fourth input terminals (fourth input terminal H1 and fourth input terminal H2) and a fourth output terminal K. Fourth input terminal H1 receives the enable input signal from the first port, and fourth input terminal H2 receives the enable input signal from the second port. Based on the received enable input signals from the first and second ports, the first logic sub-circuit generates an enable output signal. The fourth output terminal K outputs this enable output signal.

[0072] For example, the first logic subcircuit may include (n-1) electronic components that implement logic functions, or it may include multiple electronic components that implement the same functions as the (n-1) electronic components. The first logic subcircuit outputs a valid enable output signal when one of the enable input signals from the n ports is valid. For example, if the enable input signal is set to be valid when it changes from high to low, the first logic subcircuit generates a high-level enable output signal when all port enable input signals are high, and the gated clock subcircuit does not respond to this enable output signal. When a port needs to read or write data, the enable input signal of that port switches from high to low, at which point the first logic subcircuit generates a low-level enable output signal, and the gated clock subcircuit responds to this enable output signal.

[0073] In another example, the first logic subcircuit may include (n-1) electronic components that implement OR logic functions, or it may include multiple electronic components that implement the same function as the (n-1) electronic components implementing OR logic functions. The first logic subcircuit outputs a valid enable output signal when one of the enable input signals at the n ports is valid. For example, it may be set to be valid when the enable input signal changes from low to high. When all the enable input signals at the ports are low, the first logic subcircuit generates a low-level enable output signal, and the gated clock subcircuit does not respond to this enable output signal. When a port needs to read or write data, the enable input signal at that port switches from low to high, at which point the first logic subcircuit generates a high-level enable output signal, and the gated clock subcircuit responds to this enable output signal.

[0074] like Figure 6As shown, the gated clock sub-circuit includes a fifth input terminal L, a first clock terminal CLK1, and a second clock terminal CLK2. The fifth input terminal L is coupled to the fourth output terminal K. The fifth input terminal L is used to receive the enable output signal output from the fourth output terminal K. The first clock terminal CLK1 is the clock input terminal of the control circuit, used to receive the first clock signal generated by the clock source. The second clock terminal CLK2 is used to receive the second clock signal, the clock period of which is n times the clock period of the first clock signal. The gated clock sub-circuit is used to process the first clock signal based on the enable output signal and the second clock signal, to generate and output a gated clock signal, the clock period of which is consistent with the clock period of the first clock signal.

[0075] The gated clock sub-circuit is used to generate a gated clock signal, also known as a clock gating signal. Using this sub-circuit, the clocks of functional units without execution tasks can be turned off, reducing unnecessary internal register toggling with clock cycles and thus lowering power consumption. Taking an n value of 2 as an example... Figure 7 As shown, both the first clock signal and the second clock signal are continuous clock signals. The gated clock signal obtained by the gated clock sub-circuit is a discrete clock signal. Before and after the arrival of the gated clock signal, since there is no need to perform read and write processing, the clock of the functional unit without the task to be executed is set to a low level, thereby reducing the toggling of the internal registers of these functional units.

[0076] like Figure 6 As shown, the port conversion sub-circuit includes a third clock terminal CLK3 and a fifth output terminal Q. The third clock terminal CLK3 is coupled to the clock output terminal M of the gated clock sub-circuit, and the fifth output terminal Q is the output terminal Q of the control circuit. The port conversion sub-circuit processes the gated clock signal output from the clock output terminal M to generate and output a port selection signal. Figure 7 Taking the gated clock signal shown as an example, the port conversion sub-circuit processes it, and the resulting port selection signal is as follows: Figure 2 , Figure 3 or Figure 5 As shown. By Figure 7 and Figure 2 , Figure 3 or Figure 5 It can be seen that the clock period of the port selection signal is twice the clock period of the first clock signal.

[0077] The data read / write circuit provided in this application, through a control circuit including a first logic sub-circuit, a gated clock sub-circuit, and a port conversion sub-circuit, adjusts the clock period of the first clock signal generated by the clock source, so that one clock period of the port selection signal corresponds to multiple clock periods of the first clock signal. By selecting one port from multiple ports and performing data processing on that port in each clock period of the first clock signal, data processing of multiple ports can be performed simultaneously in one clock period of the port selection signal. This allows a single-port RAM to implement the function of a multi-port RAM, which is simple to implement, applicable to different application scenarios, and improves the flexibility of chip use.

[0078] Figure 8 A schematic diagram of another data read / write circuit provided in the embodiments of this application is shown below. Figure 8 As shown above, Figure 6 The gated clock sub-circuit in the illustrated embodiment may include: a first delay unit, a first logic unit, and a gate unit.

[0079] The first delay unit includes a sixth input terminal L, a fourth clock terminal CLK2, and (n-1) sixth output terminals M. 11 To M 1(n-1) The sixth input terminal L is the fifth input terminal L of the gated clock sub-circuit, and the fourth clock terminal CLK2 is the second clock terminal CLK2 of the gated clock sub-circuit. The first delay unit is used to perform (n-1) delay processing on the enable output signal based on the second clock signal received by the fourth clock terminal CLK2, generating and outputting (n-1) delayed signals. The j-th delayed signal is generated by the j-th sixth output terminal M. 1j Output. The j-th delayed signal is j clock cycles slower than the enable output signal, where j is an integer greater than or equal to 1 and less than or equal to (n-1), i.e., j = 1, 2, ..., n-1.

[0080] In some examples, the first delay unit may include (n-1) registers. The enable output signal of the first delay unit is input, and after j delay processing through j registers, the j-th delayed signal is output.

[0081] like Figure 8 As shown, the first logic unit includes n seventh input terminals R1 to R2. n One of the seventh input terminals (e.g.) Figure 8 R shown n The fourth output terminal K is coupled to the remaining (n-1) seventh input terminals (such as...). Figure 8 R1 to R shown n-1 ) respectively connected to the (n-1) sixth output terminals M of the first delay unit 11 To M 1(n-1)Coupling. The first logic unit is used to generate and output a gating enable signal based on the enable output signal and (n-1) delayed signals.

[0082] In some examples, the first logic unit may include (n-1) electronic components that implement AND logic functions, or it may include (n-1) electronic components that implement OR logic functions. The embodiments of this application do not limit the electronic components included in the first logic unit.

[0083] like Figure 8 As shown, the gating unit includes an eighth input terminal T, a fifth clock terminal CLK1, and a gating output terminal M. The eighth input terminal T is coupled to the output terminal S of the first logic unit. The fifth clock terminal CLK1 is the first clock terminal CLK1 of the gating clock sub-circuit, and the gating output terminal M is the clock output terminal M of the gating clock sub-circuit. The gating unit is used to generate and output a gating clock signal based on the first clock signal input at the first clock terminal CLK1 and the gating enable signal input at the eighth input terminal T.

[0084] The gated clock signal generated by this gated unit can turn off the clock of functional components that are not performing tasks, reducing unnecessary internal register toggling with clock cycles and thus reducing power consumption.

[0085] like Figure 8 As shown, in some examples, the fourth output terminal K of the first logic sub-circuit is coupled to the enable terminal EN of the single-port RAM. The enable terminal EN of the single-port RAM is used to receive the enable output signal. The clock output terminal M of the gated clock sub-circuit is coupled to the clock terminal CLK of the single-port RAM.

[0086] By coupling the enable terminal EN of the single-port RAM to the fourth output terminal K, and coupling the clock terminal CLK of the RAM to the clock output terminal M of the gated clock sub-circuit, the fourth output terminal K outputs a valid enable output signal when there is a valid enable input signal among the enable input signals of the n ports of the first logic sub-circuit. Under the action of the valid enable output signal, the single-port RAM begins to process data.

[0087] Figure 9 A schematic diagram of another data read / write circuit provided in the embodiments of this application is shown below. Figure 9 As shown above, Figure 6 The port selection circuit in the illustrated embodiment may include: a first selection sub-circuit and n input sub-circuits.

[0088] The first selection sub-circuit includes a first selection input terminal A and an output terminal U. The first selection input terminal A is the first selection terminal A of the port selection circuit and is coupled to the output terminal Q of the control circuit to receive the port selection signal. The first selection sub-circuit is used to generate and output a first selection signal to enable the i-th input sub-circuit based on the port selection signal during the i-th clock cycle of the first clock signal.

[0089] Each input sub-circuit includes a first input enable terminal ENB, a ninth input terminal group B, and a seventh output terminal group W. There are n first input enable terminals ENB1 to ENB2. n All are coupled to the output terminal U of the first selector circuit. The n ninth input groups B1 to B... n These are n first input terminal groups B1 to B... n n seventh output groups W1 to W n All are coupled to the first output terminal group C. The first input enable terminal ENB is used to receive the first selection signal output by the output terminal U. The i-th input sub-circuit is used to receive the i-th input signal group, and when the i-th first selection signal is received, it generates and outputs the i-th output signal group.

[0090] The i-th seventh output terminal group W outputs the i-th output signal group through the first output terminal group C during the i-th clock cycle of the first clock signal. This allows the single-port RAM to receive the i-th output signal group output by the first output terminal group C during the i-th clock cycle of the first clock signal. Thus, during one clock cycle of the port selection signal, the data input from n ports is input to the single-port RAM for data processing, thereby realizing the function of a multi-port RAM using a single-port RAM.

[0091] For example, the i-th ninth input group B i Including write enable input B Wi Address input terminal B Ai and write data input terminal B Di Among them, the write enable input B Wi Used to input the write enable signal, address input terminal B. Ai Used for inputting address signals, write data input terminal B Di This is used to input write data. Therefore, the input signal group includes a write enable input signal, an address input signal, and a write data input signal.

[0092] For example, the i-th seventh output group W i Including the write enable output W Wi Address output terminal W Ai and write data output terminal W Di Among them, the write enable output terminal W WiUsed to output a write enable signal, address output terminal W Ai Used for outputting address signals, write data output terminal W Di This is used to output write data output signals. Therefore, the output signal group includes a write enable output signal, an address output signal, and a write data output signal.

[0093] Figure 10 A schematic diagram of another data read / write circuit provided in the embodiments of this application is shown below. Figure 10 As shown above, Figure 9 The data output circuit in the illustrated embodiment may include: a second selection sub-circuit and n data output sub-circuits.

[0094] The second selection sub-circuit includes a second selection input terminal E and an output terminal V. The second selection input terminal E is the second selection terminal E of the data output circuit and is coupled to the output terminal Q of the control circuit for receiving a port selection signal. Based on the port selection signal, the second selection sub-circuit generates and outputs a second selection signal to enable the i-th data output sub-circuit during the (i+1)-th clock cycle of the first clock signal.

[0095] Each data output sub-circuit includes a second input enable terminal EB, a tenth input terminal X, and an eighth output terminal G. There are n second input enable terminals EB1 to EB2. n All are coupled to the output terminal V of the second selector circuit. The n tenth input terminals X1 to X... n All are coupled to the third input terminal F. The n eighth output terminals G1 to G... n These are n third output terminals G1 to G... n The second input enable terminal EB is used to receive the second selection signal. The i-th data output sub-circuit is used to receive the tenth input terminal X. i The input data signal is processed upon receiving the i-th second selection signal to generate the i-th data output signal. During the (n+2)-th clock cycle of the first clock signal, the signal is output through the eighth output terminal G. i Output the i-th data signal.

[0096] Tenth input terminal X i In the i-th clock cycle of the first clock signal, the i-th data input signal output from the second output terminal P is received. When the i-th second selection signal is received, the received i-th data input signal is processed to generate the i-th data output signal. This allows the n data output signals output by the single-port RAM to be processed and n data output signals to be generated within n clock cycles of the first clock signal. Thus, multiple data output signals are generated within one clock cycle of the port selection signal, realizing the function of a multi-port RAM using a single-port RAM.

[0097] Furthermore, during the (n+2)th clock cycle of the first clock signal, the output is transmitted through the eighth output terminal G1 to G... n The n data output signals are output to perform a single read operation on the n data input signals output by the single-port RAM.

[0098] like Figure 10 As shown, in some examples, each data output sub-circuit also includes a clock terminal CK. i The clock output terminal M of the gated clock sub-circuit and the clock terminals CK of each data output sub-circuit i Coupled.

[0099] In some examples, the i-th data output sub-circuit includes a second delay unit. This second delay unit includes an enable terminal EB. i Data input terminal X i and clock terminal CK i Enable terminal EB i EB is the second input enable terminal. i Data input terminal X i For the tenth input terminal X i CK clock terminal i CK is the clock terminal for each data output sub-circuit. i Enable terminal EB i Used to receive the second selection signal, data input terminal X i Used to receive the i-th data input signal, clock terminal CK i The second delay unit is used to receive the gated clock signal. It is used to perform (n-i+1) delay processing on the i-th data input signal based on the gated clock signal, and generate and output the i-th data output signal.

[0100] Since reading data occurs in the next clock cycle after writing data to the single-port RAM, each data output sub-circuit can only receive the first data input signal output from the second output terminal P starting from the second clock cycle. In the (i+1)th clock cycle of the first clock signal, the data input terminal X of the second delay unit included in the i-th data output sub-circuit... i The second selection signal receives the i-th data input signal output from the second output terminal P. In the (i+1)-th clock cycle, the second selection signal selects the i-th data output sub-circuit (i.e., the i-th data output sub-circuit receives the i-th second selection signal) for data processing and generates the i-th data output signal.

[0101] The following example illustrates how to implement dual-port RAM functionality using a single-port RAM.

[0102] Figure 11This is a schematic diagram of the structure of a RAM control logic conversion circuit provided in an embodiment of this application, as shown below. Figure 11 As shown, the RAM control logic conversion circuit is located between the single-port RAM and the controller. The operating frequency of the single-port RAM and the RAM control logic conversion circuit is twice the operating frequency of the controller; that is, the controller's clock is divided by the clock of the single-port RAM and the RAM control logic conversion circuit. The RAM control logic conversion circuit enables the controller to perform alternating operations on the single-port RAM, thus allowing the single-port RAM to achieve the read / write function of a dual-port RAM.

[0103] In some examples, the controller is used to perform logical control on a single-port RAM and may include devices such as processors, arithmetic units, and coprocessors.

[0104] Figure 12 This is a signal timing diagram of the RAM control logic conversion circuit provided in the embodiments of this application during a write operation. Figure 13 For the signal timing diagram of the RAM control logic conversion circuit provided in the embodiments of this application during a read operation, please refer to [link / reference]. Figures 11 to 13 The controller's clock CLKA is divided by two with the clock of the single-port RAM and the RAM control logic conversion circuit, CLKB, for example, CLKA is 10MHz and CLKB is 20MHz. One cycle of the dual-port RAM can complete read and write operations on both ports 0 and 1, specifically including write to port 0, write to port 1, read from port 0, and read from port 1. The port selection signal port_sel is generated through register 2. The port_sel signal indicates which port is being processed in the current clock cycle. For example, setting port_sel to low level to process write operations on port 0, and high level to process write operations on port 1. Since read operations can only be performed after the write operation is completed, the read operation occurs in the next cycle after the address signal is transmitted to the single-port RAM. Therefore, port_sel is high level to process read operations on port 1, and low level to process read operations on port 0.

[0105] In implementation, to ensure that read and write operations on both ports can be completed, the enable signals of the ram0_ceb and ram1_ceb chips are ANDed, i.e., ram0_ceb & ram1_ceb, to obtain the CENB signal. Using register 1, the CENB signal is extended by one slow clock cycle to generate four finite clocks in the fast clock domain. The first finite clock completes the write operation on port 0, the second finite clock completes the write operation on port 1 and the read operation on port 0, the third finite clock completes the read operation on port 1, and the fourth finite clock holds ram0_rdata and ram1_rdata, and the controller reads the result.

[0106] In this embodiment, the controller performs alternating operations on the single-port RAM through a RAM control logic conversion circuit, thereby enabling the read and write functions of the dual-port RAM using the single-port RAM. This method is simple, applicable to different application scenarios, and improves the flexibility of chip usage.

[0107] Based on the above embodiments, this application also provides a storage device, which includes a controller and any of the above-described data read / write circuits. In some embodiments, the storage device may include multiple data read / write circuits, and the circuit structure of each data read / write circuit can be... Figure 1 , Figure 3 , Figure 6 , Figures 8 to 11 The circuits shown in the diagram may have the same or different circuit structures in different data read / write circuits.

[0108] This application embodiment also provides a terminal device, which includes a processor and a memory, the memory including any of the data read / write circuits described above. In some embodiments, the memory includes one or more data read / write circuits, and the circuit structure of each data read / write circuit can be as follows: Figure 1 , Figure 3 , Figure 6 , Figures 8 to 11 The circuits shown in the diagram may have the same or different circuit structures in different data read / write circuits.

[0109] The steps of the methods or algorithms described in this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an application-specific integrated circuit (ASIC). Alternatively, the ASIC can reside in a core network interface device. Of course, the processor and storage medium can also exist as discrete components in the core network interface device.

[0110] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in this application can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0111] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A data read / write circuit, characterized in that, The data read / write circuit includes: A control circuit is used to process a first clock signal generated by a clock source and output a port selection signal; wherein the clock period of the port selection signal is n times the clock period of the first clock signal, and n is an integer greater than or equal to 2. The control circuit includes: The first logic sub-circuit includes n fourth input terminals and a fourth output terminal; each fourth input terminal is used to receive an enable input signal; the first logic sub-circuit is used to generate and output an enable output signal based on the received n enable input signals. A gated clock sub-circuit includes a fifth input terminal, a first clock terminal, and a second clock terminal; the fifth input terminal is coupled to the fourth output terminal; the fifth input terminal is used to receive the enable output signal; the first clock terminal is used to receive a first clock signal generated by the clock source, and the second clock terminal is used to receive a second clock signal, the clock period of the second clock signal being n times the clock period of the first clock signal; the gated clock sub-circuit is used to process the first clock signal based on the enable output signal and the second clock signal, generate and output a gated clock signal, the clock period of the gated clock signal being consistent with the clock period of the first clock signal; The port conversion sub-circuit includes a third clock terminal and a fifth output terminal. The third clock terminal is coupled to the clock output terminal of the gated clock sub-circuit, and the fifth output terminal is the output terminal of the control circuit. The port conversion sub-circuit is used to process the gated clock signal output by the clock output terminal to generate and output a port selection signal. A port selection circuit includes a first selection terminal, n first input terminal groups, and a first output terminal group. The first selection terminal is coupled to the output terminal of the control circuit. Each first input terminal group is used to receive an input signal group. The port selection circuit is used to receive the port selection signal and, in the i-th clock cycle of the first clock signal, selects and outputs the input signal group received by the i-th first input terminal group based on the port selection signal, where i is an integer greater than or equal to 1 and less than or equal to n. A single-port RAM includes a second input terminal group coupled to a first output terminal group; the single-port RAM is used to receive the i-th output signal group output by the first output terminal group in the i-th clock cycle of the first clock signal, and to process the i-th output signal group.

2. The data read / write circuit according to claim 1, characterized in that, The data read / write circuit also includes: The data output circuit includes a second selection terminal, a third input terminal, and n third output terminals; the second selection terminal is coupled to the output terminal of the control circuit, and the third input terminal is coupled to the second output terminal of the single-port RAM; the third input terminal is used to receive n data input signals output from the second output terminal of the single-port RAM; the data output circuit is used to process the received n data input signals to generate n data output signals, and output the n data output signals in the (n+2)th clock cycle of the first clock signal.

3. The data read / write circuit according to claim 1, characterized in that, The gated clock sub-circuit includes: The first delay unit includes a sixth input terminal, a fourth clock terminal, and (n-1) sixth output terminals; the sixth input terminal is the fifth input terminal of the gated clock sub-circuit, and the fourth clock terminal is the second clock terminal of the gated clock sub-circuit; the first delay unit is used to perform (n-1) delay processing on the enable output signal based on the second clock signal to generate and output (n-1) delayed signals; wherein, the j-th delayed signal is j clock cycles slower than the enable output signal than the enable output signal, and j is an integer greater than or equal to 1 and less than or equal to (n-1); The first logic unit includes n seventh input terminals, one seventh input terminal is coupled to the fourth output terminal, and the remaining (n-1) seventh input terminals are respectively coupled to (n-1) sixth output terminals of the first delay unit; the first logic unit is used to generate and output a gating enable signal based on the enable output signal and the (n-1) delay signals; The gating unit includes an eighth input terminal and a fifth clock terminal. The eighth input terminal is coupled to the output terminal of the first logic unit, and the fifth clock terminal is the first clock terminal of the gating clock sub-circuit. The gating unit is used to generate and output a gating clock signal based on the first clock signal and the gating enable signal.

4. The data read / write circuit according to claim 1, characterized in that, The fourth output terminal of the first logic sub-circuit is coupled to the enable terminal of the single-port RAM, and the enable terminal of the single-port RAM is used to receive the enable output signal. The clock output terminal of the gated clock sub-circuit is coupled to the clock terminal of the single-port RAM.

5. The data read / write circuit according to claim 2, characterized in that, The port selection circuit includes: a first selection sub-circuit and n input sub-circuits; The first selection sub-circuit includes a first selection input terminal, which is the first selection terminal of the port selection circuit; the first selection input terminal is used to receive the port selection signal; the first selection sub-circuit is used to generate and output a first selection signal to enable the i-th input sub-circuit based on the port selection signal in the i-th clock cycle of the first clock signal. Each input sub-circuit includes a first input enable terminal, a ninth input terminal group, and a seventh output terminal group; n first input enable terminals are all coupled to the output terminal of the first selection sub-circuit, n ninth input terminal groups are respectively coupled to the n first input terminal groups, and n seventh output terminal groups are all coupled to the first output terminal group; the first input enable terminal is used to receive a first selection signal; the i-th input sub-circuit is used to receive the i-th input signal group, and when the i-th first selection signal is received, it generates and outputs the i-th output signal group.

6. The data read / write circuit according to claim 5, characterized in that, The ninth input terminal group includes a write enable input terminal, an address input terminal, and a write data input terminal, and the input signal group includes a write enable input signal, an address input signal, and a write data input signal; The seventh output terminal group includes a write enable output terminal, an address output terminal, and a write data output terminal, and the output signal group includes a write enable output signal, an address output signal, and a write data output signal.

7. The data read / write circuit according to claim 5, characterized in that, The data output circuit includes: a second selection sub-circuit and n data output sub-circuits; The second selection sub-circuit includes a second selection input terminal, which is the second selection terminal of the data output circuit; the second selection input terminal is used to receive the port selection signal; the second selection sub-circuit is used to generate and output a second selection signal to enable the i-th data output sub-circuit based on the port selection signal in the (i+1)-th clock cycle of the first clock signal; Each data output sub-circuit includes a second input enable terminal, a tenth input terminal, and an eighth output terminal; n second input enable terminals are all coupled to the output terminal of the second selection sub-circuit, and n tenth input terminals are all coupled to the third input terminal; n eighth output terminals are respectively coupled to n third output terminals; the second input enable terminal is used to receive a second selection signal; the i-th data output sub-circuit is used to receive the data input signal input by the tenth input terminal, and when the i-th second selection signal is received, it processes the received i-th data input signal to generate the i-th data output signal, and outputs the i-th data output signal in the (n+2)-th clock cycle of the first clock signal.

8. The data read / write circuit according to claim 7, characterized in that, The clock output terminal of the gated clock sub-circuit is coupled to the clock terminals of each data output sub-circuit.

9. The data read / write circuit according to claim 8, characterized in that, The i-th data output sub-circuit includes a second delay unit; The second delay unit includes an enable terminal, a data input terminal, and a clock terminal; the enable terminal is the second input enable terminal, the data input terminal is the tenth input terminal, and the clock terminal is coupled to the clock output terminal of the gated clock sub-circuit; the enable terminal is used to receive a second selection signal, the data input terminal is used to receive the i-th data input signal, and the clock terminal is used to receive the gated clock signal; the second delay unit is used to perform (n-i+1) delay processing on the i-th data input signal based on the gated clock signal, and generate and output the i-th data output signal.

10. A storage device, characterized in that, The storage device includes a controller and a data read / write circuit as described in any one of claims 1 to 9.

11. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory including data read / write circuitry as claimed in any one of claims 1 to 9.

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