Duty cycle correction circuit and chip

Abstract

The application provides a duty cycle correction circuit and a chip, a pre-charging module is added, and a capacitor can be pre-charged to a predetermined voltage after each comparison of a comparator ends, so that the charging time of a charge pump module on two charging and discharging nodes can be shortened, the analog voltage output by the two charging and discharging nodes can quickly reach the input voltage value at which the comparator can compare in the next comparison, the starting time required by the comparator for each comparison is shortened, the response time and the stabilization time of the loop of the duty cycle correction circuit itself are shortened, the clock duty cycle calibration efficiency is finally improved, and the transmission rate of a signal is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a duty cycle correction circuit and chip. Background Technology

[0002] Typically, clock signals are used as reference signals to synchronize the operating timing between internal and external circuits of certain chips (such as dynamic random access memory). However, when the clock signal from the external circuit is applied to the internal circuit, it often causes clock skew (including delay or clock deviation) due to signal paths within the internal circuit. Therefore, phase-locked loop (PLL) circuits and duty cycle correction circuits are usually used in conjunction to address this issue. The PLL circuit can be a DLL (Delay Locked Loop) or a PLL (Phase Locked Loop) circuit, used to synchronize the clock signals of the internal and external circuits to resolve clock skew, ensuring sufficient clock delay margin between the chip's internal and external circuits, thereby improving the system's timing functionality. The duty cycle correction circuit adjusts the clock duty cycle (typically 50%), allowing data to be sampled on both the rising and falling edges of the clock signal (i.e., high-speed data input and output operations), thereby increasing the signal transmission rate.

[0003] However, existing duty cycle correction circuits have the disadvantage of long startup time, which leads to long clock duty cycle calibration time and is not conducive to improving signal transmission rate. Summary of the Invention

[0004] The purpose of this invention is to provide a duty cycle correction circuit and chip that can shorten startup time and improve clock duty cycle calibration efficiency, which is beneficial to increasing signal transmission rate.

[0005] To achieve the above objectives, the present invention provides a duty cycle correction circuit, which includes a charge pump module, a comparator, a control module, a duty cycle correction module, a frequency divider module, and a pre-charge module, wherein...

[0006] The input terminal of the frequency divider module is coupled to the output terminal of the duty cycle correction module, and the frequency divider module is used to generate a second clock signal and a third clock signal based on the first clock signal output by the duty cycle correction module, wherein the second clock signal and the first clock signal have the same duty cycle, and the third clock signal is the inverted signal of the second clock signal;

[0007] The charge pump module has a first charge / discharge node and a second charge / discharge node. The first charge / discharge node is coupled to the non-inverting input terminal of the comparator, and the second charge / discharge node is coupled to the inverting input terminal of the comparator. The charge pump module is used to charge or discharge the first charge / discharge node and the second charge / discharge node under the control of the second clock signal and the third clock signal to output two corresponding analog voltages.

[0008] The output of the comparator is coupled to the input of the control module. The comparator is used to compare the two analog voltages output by the charge pump module under the control of the comparison enable signal.

[0009] The output of the control module is coupled to one input of the duty cycle correction module, and the control module is used to generate a corresponding adjustment control signal based on the comparison result of the comparator and provide it to the duty cycle correction module.

[0010] The duty cycle correction module is used to adjust the duty cycle of the first clock signal according to the adjustment control signal output by the control module.

[0011] The precharge module is coupled to the first charge / discharge node and the second charge / discharge node. Under the control of the precharge control signal, the precharge module is used to precharge the voltage of the first charge / discharge node and the second charge / discharge node to a predetermined voltage after the comparator comparison is completed.

[0012] Optionally, the pre-charge module includes a first MOSFET, a second MOSFET, a first channel switch, a second channel switch, a first inverter, and a voltage divider circuit; wherein the gate terminal of the first MOSFET, the input terminal of the first inverter, the control terminal of the first channel switch, and the control terminal of the second channel switch are all coupled to the pre-charge control signal; the source and drain terminals of the first MOSFET are respectively connected to the power supply voltage and one end of the voltage divider circuit; the output terminal of the first inverter is connected to the gate terminal of the second MOSFET; the source and drain terminals of the second MOSFET are respectively connected to the other end of the voltage divider circuit and ground; the input terminals of the first channel switch and the second channel switch are connected to the output terminal of the voltage divider circuit; the output terminal of the first channel switch is coupled to the first charge / discharge node; and the output terminal of the second channel switch is coupled to the second charge / discharge node.

[0013] Optionally, the charge pump module includes a first to a fourth current source, a third to a sixth MOSFET, a first capacitor, and a second capacitor; wherein, the first current source, the third MOSFET, the fourth MOSFET, and the second current source are connected in series to form a first charging / discharging branch, and the gate terminals of the third MOSFET and the fourth MOSFET are both coupled to the second clock signal; the third MOSFET is disposed between the first current source and the first charging / discharging node, and the fourth MOSFET is disposed between the first charging / discharging node and the second current source; one end of the first capacitor is connected to the first charging / discharging node and the other end is grounded; the third current source, the fifth MOSFET, the sixth MOSFET, and the fourth current source are connected in series to form a second charging / discharging branch, and the gate terminals of the fifth MOSFET and the sixth MOSFET are both coupled to the third clock signal; the fifth MOSFET is disposed between the third current source and the second charging / discharging node, and the sixth MOSFET is disposed between the second charging / discharging node and the fourth current source; one end of the second capacitor is connected to the second charging / discharging node and the other end is grounded.

[0014] Optionally, the duty cycle correction module includes a second inverter and multiple duty cycle correction units. The input terminal of the second inverter and the input terminals of the multiple duty cycle correction units are interconnected to form the input terminal of the duty cycle correction module for receiving the initial clock signal. The output terminal of the second inverter and the output terminals of all the duty cycle correction units are interconnected to form the output terminal of the duty cycle correction module.

[0015] Optionally, the duty cycle correction circuit further includes a negative feedback module, which includes a third inverter, a third channel switch, and a fourth channel switch. The input terminals of the third inverter and the third channel switch are both connected to the output terminal of the comparator. The output terminal of the third inverter is connected to the input terminal of the fourth channel switch. The output terminals of the third channel switch and the fourth channel switch are connected to the same input terminal of the control module. The control terminals of the third channel switch and the fourth channel switch are connected to mutually inverted clock signals.

[0016] Optionally, the duty cycle correction circuit further includes fifth to eighth channel switches. The fifth and sixth channel switches are respectively coupled between the frequency divider module and the charge pump module. The seventh channel switch is coupled between the first charge / discharge node and the non-inverting input of the comparator. The eighth channel switch is coupled between the second charge / discharge node and the inverting input of the comparator. When the fifth channel switch is turned on, the second clock signal is transmitted from the frequency divider module to the charge pump module. When the sixth channel switch is turned on, the third clock signal is transmitted from the frequency divider module to the charge pump module. When the seventh channel switch is turned on, the voltage of the first charge / discharge node is transmitted to the non-inverting input of the comparator. When the eighth channel switch is turned on, the voltage of the second charge / discharge node is transmitted to the inverting input of the comparator.

[0017] Optionally, the duty cycle correction circuit further includes a ninth to a tenth channel switch; wherein the input terminal of the ninth channel switch is connected to the second charge / discharge node, the output terminal of the ninth channel switch is connected to the non-inverting input terminal of the comparator, the input terminal of the tenth channel switch is connected to the first charge / discharge node, and the output terminal of the tenth channel switch is connected to the inverting input terminal of the comparator; or, the input terminal of the ninth channel switch is connected to the input terminal of the fifth channel switch, the output terminal of the ninth channel switch is connected to the output terminal of the sixth channel switch, the input terminal of the tenth channel switch is connected to the input terminal of the sixth channel switch, and the output terminal of the tenth channel switch is connected to the output terminal of the fifth channel switch.

[0018] Based on the same inventive concept, the present invention also provides a chip that includes the duty cycle correction circuit described in the present invention.

[0019] Optionally, the chip further includes a phase-locked loop circuit coupled to the duty cycle correction circuit, wherein the phase-locked loop circuit is disposed at the front end of the duty cycle correction circuit or at the rear end of the duty cycle correction circuit.

[0020] Optionally, the chip is a memory chip, and / or the phase-locked loop circuit is a PLL circuit or a DLL circuit.

[0021] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0022] 1. A pre-charge module has been added, which can pre-charge the voltage of the two input terminals of the comparator (i.e., the first charge / discharge node and the second charge / discharge node) to a predetermined voltage after each comparison. This shortens the charging time of the charge pump module for the two charge / discharge nodes, so that the analog voltage output by the two charge / discharge nodes can quickly reach the input voltage value that the comparator can compare in the next comparison. This shortens the start-up time required for each comparison of the comparator, and also shortens the response time and settling time of the duty cycle correction circuit itself. Ultimately, this improves the clock duty cycle calibration efficiency and is beneficial to the improvement of signal transmission rate.

[0023] 2. Adding a ninth and tenth channel switch before the input of the comparator or after the output of the frequency divider module to eliminate input offset can flip the voltage of the two input terminals of the comparator or the clock signal output by the frequency divider module in each comparison cycle. This makes the input offset of the two input terminals of the comparator have the same effect on the high and low levels of the clock, eliminating the inherent error of duty cycle adjustment and finally obtaining a clock signal with a more balanced duty cycle.

[0024] 3. By adding a negative feedback module between the comparator output and the control module, the feedback of the duty cycle correction circuit loop can be adjusted to always be negative feedback, thereby enhancing the stability of the duty cycle correction circuit, improving the nonlinear distortion of the duty cycle correction circuit, and suppressing the noise and interference inside the duty cycle correction circuit. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the circuit architecture design of an existing duty cycle correction circuit.

[0026] Figure 2 yes Figure 1 The diagram shows the timing sequence of the duty cycle correction circuit.

[0027] Figure 3 This is a schematic diagram of the circuit architecture design of the duty cycle correction circuit according to the first embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram illustrating a specific circuit connection example of the duty cycle correction circuit according to the first embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram illustrating a specific circuit connection example of the duty cycle correction module in the duty cycle correction circuit of the first embodiment of the present invention.

[0030] Figure 6 This is a timing diagram of the duty cycle correction circuit according to the first embodiment of the present invention.

[0031] Figure 7This is a schematic diagram illustrating a specific circuit connection example of the duty cycle correction circuit according to the second embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram illustrating a specific circuit connection example of the duty cycle correction circuit according to the third embodiment of the present invention.

[0033] Figure 9 and Figure 10 These are schematic diagrams illustrating two example chip architectures according to the fourth embodiment of the present invention. Detailed Implementation

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, the provision of these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. Although the terms first, second, third, etc., may be used to describe various elements, components, and / or portions, these elements, components, and / or portions should not be limited by these terms. These terms are used merely to distinguish one element, component, or portion from another element, component, or portion. Therefore, without departing from the teachings of the invention, the first element, component, or portion discussed below may be referred to as the second element, component, or portion. When used herein, the singular forms of "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0035] Figure 1The diagram shows an existing duty cycle correction circuit for adjusting the clock duty cycle. It includes a charge pump module, a comparator COMP, a control module, and a duty cycle correction module. The charge pump module converts the duty cycles of the clock signals CKA and CKB output by the duty cycle correction module into two analog voltages. The comparator COMP compares the analog voltages output by the charge pump module. The control module generates a control signal for the duty cycle correction module based on the comparison result of the comparator COMP. The duty cycle correction module receives the corresponding clock signal CLK and generates clock signals CKA and CKB (i.e., the duty cycle-adjusted clock signals) with varying duty cycles relative to the clock signal CLK, based on the control signal output by the control module.

[0036] The operating timing logic of the duty cycle correction circuit is as follows: Figure 2 As shown in the diagram, the signal CMPE is the enable signal for comparator COMP, and comparator COMP is not working when CMPE is low. The clock signal CLK is the initial clock signal. This duty cycle correction circuit mainly consists of a charging / discharging stage, a comparison stage, and a duty cycle adjustment stage. In the charging / discharging stage, two clock signals, CKA and CKB, are sent to the charge pump module, and the high-level widths of CKA and CKB represent the low-level and high-level widths of CLK, respectively. The high levels of CKA and CKB represent the charging time of the nodes in the charge pump module used to output the corresponding analog voltages, while the low levels of CKA and CKB control the discharging time of those nodes. In the comparison stage and the duty cycle adjustment stage, the two clock signals CKA and CKB are not sent to the charge pump module. In the duty cycle adjustment stage, the charge pump is disconnected from the comparator, and the corresponding capacitor in the charge pump is discharged to 0. Finally, the two analog voltages output by the charge pump module can represent the low-level and high-level widths of CLK, respectively. After several charge-discharge cycles, the comparator COMP is enabled, comparing the magnitudes of the two analog voltages output by the charge pump module. The comparison result is output to the control module to generate a control signal for the duty cycle correction module, which adjusts the clock duty cycle.

[0037] The disadvantages of the duty cycle correction circuit described above are: 1. Long startup time: The charging time for the analog voltage output node in the charge pump module is very long before it reaches the common-mode input voltage required by the comparator COMP. This results in a longer response time for the loop and an increased time for the loop to stabilize. 2. The input offset voltage of the comparator COMP will cause a fixed adjustment error in the duty cycle correction circuit.

[0038] Furthermore, when the aforementioned duty cycle correction circuit is applied to DDR memory chips, the clock signal ultimately output by the duty cycle correction circuit is the external clock signal of the DDR memory chip. When performing read and write operations on the DDR memory chip, data must be sent on both the rising and falling edges of this clock signal. If the duty cycle of this clock signal is lost, that is, if the duty cycle of the clock signal ultimately output by the duty cycle correction circuit is not 50%, then the width of the data sent on the rising and falling edges of this clock signal will be large and small, respectively. What is seen at the data sending end is an eye diagram with different sizes of eyes, and even the problem of incomplete data transmission may occur.

[0039] Based on this, the present invention provides a duty cycle correction circuit and chip, which, compared with the prior art, adds at least a pre-charge module. After each comparison of the comparator, the voltages of the two input terminals (i.e., the first charge / discharge node and the second charge / discharge node) of the comparator are pre-charged to a predetermined voltage. This shortens the charging time of the charge pump module for the two charge / discharge nodes, so that the analog voltages output by the two charge / discharge nodes can quickly reach the input voltage values ​​that the comparator can compare in the next comparison. This shortens the start-up time required for each comparison of the comparator, and also shortens the response time and settling time of the duty cycle correction circuit itself. Ultimately, this improves the clock duty cycle calibration efficiency and is beneficial to the improvement of signal transmission rate.

[0040] Furthermore, by adding a ninth and tenth channel switch before the input of the comparator or after the output of the frequency divider module to eliminate input offset, the voltages at the two inputs of the comparator or the clock signal output by the frequency divider module can be toggled in each comparison cycle of the comparator. This makes the input offset at the two inputs of the comparator have the same effect on the high and low levels of the clock, eliminating the inherent error of duty cycle adjustment and ultimately obtaining a clock signal with a more balanced duty cycle.

[0041] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0042] First Embodiment

[0043] Please refer to Figure 3 This embodiment provides a duty cycle correction circuit, which includes a charge pump module 10, a comparator 11, a control module 12, a duty cycle correction module 13, a frequency divider module 14, and a precharge module 15.

[0044] The input terminal of the frequency divider module 14 is coupled to the output terminal of the duty cycle correction module 13. The frequency divider module 14 is used to generate a second clock signal CKA and a third clock signal CKB based on the first clock signal CLKi (where i = 0 to m, and m is an integer greater than or equal to 0) output by the duty cycle correction module 13. The second clock signal CKA and the corresponding first clock signal CLKi have the same duty cycle. The third clock signal CKB is the inverted signal of the second clock signal CKA. The sum of the duty cycles of the second clock signal CKA and the third clock signal CKB is 1.

[0045] The charge pump module 10 has a first charge / discharge node a and a second charge / discharge node b. The first charge / discharge node a is coupled to the non-inverting input terminal "+" of the comparator 11, and the second charge / discharge node b is coupled to the inverting input terminal "-" of the comparator 11. The charge pump module 10 is used to charge or discharge the first charge / discharge node a and the second charge / discharge node b under the control of the second clock signal CKA and the third clock signal CKB, so as to output two corresponding analog voltages VA and VB.

[0046] The output of comparator 11 is coupled to the input of control module 12. Comparator 11 is used to compare the two analog voltages VA and VB output by charge pump module 10 under the control of comparator enable signal CMPE. The output of control module 12 is coupled to one input of duty cycle correction module 13, and control module 12 is used to generate a corresponding adjustment control signal control based on the comparison result of comparator 11 and provide it to duty cycle correction module 13. Duty cycle correction module 13 is used to adjust the duty cycle of its output first clock signal CLKi according to the adjustment control signal control output by control module 12. Precharge module 15 is coupled to the first charge / discharge node and the second charge / discharge node. Under the control of precharge control signal CKP, precharge module 15 is used to precharge the voltages VA and VB of the first charge / discharge node a and the second charge / discharge node b to a predetermined voltage after the comparison by comparator 11, for example, to half of the power supply voltage VDD connected to charge pump module 10 (i.e., VDD / 2).

[0047] As an example, please refer to Figure 4In this embodiment, the pre-charge module 15 includes a first MOSFET P1, a second MOSFET N1, a first channel switch Q1, a second channel switch Q2, a first inverter U1, and a voltage divider circuit. The first MOSFET P1 is a PMOS transistor, the second MOSFET N1 is an NMOS transistor, the first channel switch Q1 and the second channel switch Q2 can be transistors or MOSFETs, etc., and the voltage divider circuit consists of resistors R1 and R2 connected in series. The gate terminal of the first MOSFET PA, the input terminal of the first inverter U1, the control terminal of the first channel switch Q1, and the control terminal of the second channel switch Q2 are all coupled to the precharge control signal CKP. The source terminal of the first MOSFET P1 is connected to the power supply voltage VDD. The drain terminal of the first MOSFET P1 is connected to one end of the resistor R1 (i.e., one end of the voltage divider circuit). The output terminal of the first inverter U1 is connected to the gate terminal of the second MOSFET N1. The drain terminal of the second MOSFET N1 is connected to one end of the resistor R2 (i.e., the other end of the voltage divider circuit). The source terminal of the second MOSFET N1 is grounded. The series connection of resistors R1 and R2 is the output terminal of the voltage divider circuit. The input terminals of the first channel switch Q1 and the second channel switch Q2 are connected to the series connection of resistors R1 and R2. The output terminal of the first channel switch Q1 is coupled to the first charge / discharge node a, and the output terminal of the second channel switch Q2 is coupled to the second charge / discharge node b.

[0048] As an example, please continue to refer to Figure 4 The charge pump module 10 includes first to fourth current sources I1 to I4, a third MOSFET P2, a fourth MOSFET N2, a fifth MOSFET P3, a sixth MOSFET N3, a first capacitor C1, and a second capacitor C2. The first current source I1, the third MOSFET P2, the fourth MOSFET N2, and the second current source I2 are connected in series to form a first charging / discharging branch. The gate terminals of the third MOSFET P2 and the fourth MOSFET N2 are both coupled to a second clock signal CKA. The third MOSFET P2 is positioned between the first current source I1 and the first charging / discharging node a, and the fourth MOSFET N2 is positioned between the first charging / discharging node a and the second current source I2. One end of the first capacitor C1 is connected to the first charging / discharging node a and the non-inverting input terminal of the comparator 11, and the other end of the first capacitor C1 is connected to... The third current source I3, the fifth MOSFET P3, the sixth MOSFET N3 and the fourth current source I4 are connected in series to form the second charging and discharging branch. The gate terminals of the fifth MOSFET P3 and the sixth MOSFET N3 are both coupled to the third clock signal CKB. The fifth MOSFET P3 is located between the third current source I3 and the second charging and discharging node b. The sixth MOSFET N3 is located between the second charging and discharging node b and the fourth current source I4. One end of the second capacitor C2 is connected to the second charging and discharging node b and the inverting input terminal of the comparator 11, and the other end of the second capacitor C2 is grounded.

[0049] Optionally, the third MOSFET P2 and the fifth MOSFET P3 are PMOS transistors, and the fourth MOSFET N2 and the sixth MOSFET N3 are NMOS transistors. In other embodiments of the present invention, the third MOSFET P2 and the fifth MOSFET P3 can also be replaced with NMOS transistors or transistors, and the fourth MOSFET N2 and the sixth MOSFET N3 can also be replaced with PMOS transistors or transistors. In this case, the terminal connections of the third MOSFET P2, the fourth MOSFET N2, the fifth MOSFET P3, and the sixth MOSFET N3 can be adjusted adaptively.

[0050] As an example, please refer to Figure 5 The duty cycle correction module 13 in this embodiment includes a second inverter U2 and (n+1) duty cycle correction units 130 to 13n, where n is greater than or equal to 1 and is an integer. The input terminal of the second inverter U2 is interconnected with the input terminals of each duty cycle correction unit 130 to 13n to form the input terminal of the duty cycle correction module 13 for receiving the initial clock signal CLK. The output terminal of the second inverter U2 is interconnected with the output terminals of all the duty cycle correction units 130 to 13n to form the output terminal of the duty cycle correction module 13. Each duty cycle correction unit includes two PMOS transistors and two NMOS transistors. The source of the first PMOS transistor is connected to the power supply voltage VDD, and its drain is connected to the source of the second PMOS transistor. The gate of the first PMOS transistor is connected to the adjustment control signal EA. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and its gate is connected to the gate of the first NMOS transistor and connected to the initial clock signal CLK. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is grounded, and its gate is connected to the adjustment control signal EB. Specifically, for example, the duty cycle correction unit 130 includes PMOS transistors PM01 to PM02 and NMOS transistors NM01 to NM02. The source of PMOS transistor PM01 is connected to the power supply voltage VDD, and its drain is connected to the source of PMOS transistor PM02. The gate of PMOS transistor PM01 is connected to the adjustment control signal EA. <0> The drain of PMOS transistor PM02 is connected to the drain of NMOS transistor NM01. The gate of PMOS transistor PM02 is connected to the gate of NMOS transistor NM01 and connected to the initial clock signal CLK. The source of NMOS transistor NM01 is connected to the drain of NMOS transistor NM02. The source of NMOS transistor NM02 is grounded. The gate of NMOS transistor NM02 is connected to the adjustment control signal EB. <0> Similarly, the duty cycle correction unit 13n includes PMOS transistors PMn1 to PMn2 and NMOS transistors NMn1 to NMn2. The source terminal of PMOS transistor PMn1 is connected to the power supply voltage VDD, and the drain terminal is connected to the source terminal of PMOS transistor PMn2. The gate terminal of PMOS transistor PMn1 is connected to the adjustment control signal EA. <n>The drain of PMOS transistor PMn2 is connected to the drain of NMOS transistor NMn1. The gate of PMOS transistor PMn2 is connected to the gate of NMOS transistor NMn1 and connected to the initial clock signal CLK. The source of NMOS transistor NMn1 is connected to the drain of NMOS transistor NMn2. The source of NMOS transistor NMn2 is grounded. The gate of NMOS transistor NMn2 is connected to the adjustment control signal EB. <n>Among them, EA <0> ~EA <n>and EB <0> ~EB <n>This refers to the adjustment control signal (control) generated by the control module 12 based on the comparison result of the comparator 11.

[0051] Optionally, the duty cycle correction circuit in this embodiment further includes fifth to eighth channel switches Q5 to Q8. Fifth channel switch Q5 and sixth channel switch Q6 are respectively coupled between the frequency divider module 14 and the charge pump module 10. Seventh channel switch Q7 is coupled between the first charge / discharge node a and the non-inverting input of comparator 11. Eighth channel switch Q8 is coupled between the second charge / discharge node b and the inverting input of comparator 11. The control terminals of fifth channel switch Q5 and sixth channel switch Q6 are both connected to the control signal CKC. The seventh channel switch Q7... Both the control terminal and the control terminal of the eighth channel switch Q8 are connected to the control signal CKS. When the fifth channel switch Q5 is turned on, the second clock signal CKA is sent from the frequency divider module 14 to the charge pump module 10. When the sixth channel switch Q6 is turned on, the third clock signal CKB is sent from the frequency divider module 14 to the charge pump module 10. When the seventh channel switch Q7 is turned on, the voltage VA of the first charge / discharge node a is sent to the non-inverting input terminal of the comparator 11. When the eighth channel switch Q8 is turned on, the voltage VB of the second charge / discharge node b is sent to the inverting input terminal of the comparator 11.

[0052] It should be understood that the comparison enable signal CMPE, precharge control signal CKP, control signal CKC, and control signal CKS are used to control the timing of the entire duty cycle correction circuit in this embodiment. Their combination can be used to set the initial voltage for the first charge / discharge node a and the second charge / discharge node b of the duty cycle correction circuit in this embodiment, and to set the overall operating timing of the duty cycle correction circuit in this embodiment, including the charging / discharging stage, the comparison stage, the precharge stage, and the duty cycle adjustment stage, such as... Figure 6 As shown. Therefore, the comparison enable signal CMPE, precharge control signal CKP, control signal CKC, and control signal CKS can all be provided by the control module 12, or the control logic of the comparison enable signal CMPE, precharge control signal CKP, control signal CKC, and control signal CKS can all be integrated into the frequency divider module 14 (i.e., the comparison enable signal CMPE, precharge control signal CKP, control signal CKC, and control signal CKS are all provided by the frequency divider module 14), or the comparison enable signal CMPE, precharge control signal CKP, control signal CKC, and control signal CKS can all be provided by a circuit outside the duty cycle correction circuit of this embodiment, or a portion of the comparison enable signal CMPE, precharge control signal CKP, control signal CKC, and control signal CKS can be provided by one of the control module 12, the frequency divider module 14, and the external circuit, and another portion of the signals can be provided by the other of the control module 12, the frequency divider module 14, and the external circuit.

[0053] Please combine Figure 4 and Figure 6 In this embodiment, the duty cycle correction circuit controls the fifth channel switch Q5 and the sixth channel switch Q6 to be turned on during the charging and discharging phase. During the comparison phase, duty cycle adjustment phase, and pre-charging phase, the control signal CKC controls the fifth channel switch Q5 and the sixth channel switch Q6 to be turned off, so that the second clock signal CKA and the third clock signal CKB are not sent to the charge pump module 10. During the duty cycle adjustment phase, the control signal CKS controls the seventh channel switch Q7 and the eighth channel switch Q8 to be turned off. During the pre-charging phase, the pre-charging control signal CKP controls the first channel switch Q1 and the second channel switch Q2 to be turned on. At this time, no matter how large VA and VB are of the first capacitor C1 and the second capacitor C2, they will become the voltage generated by the voltage division of resistors R1 and R2 (when resistors R1 and R2 are the same, it becomes VDD / 2).

[0054] The principle behind the duty cycle correction module 13 adjusting the clock duty cycle is as follows:

[0055] In the first cycle, the initial clock signal CLK (which can be regarded as CLK0) is sent to the frequency divider module 14, and the generated second clock signal CKA and third clock signal CKB are denoted as CKA0 and CKB0. The comparator 11 compares VA and VB and determines whether the duty cycle of the initial clock signal CLK is greater than the target value (e.g., 50%) or less than the target value. If the duty cycle of the initial clock signal CLK is greater than the target value, the duty cycle correction module 13 reduces the duty cycle of the initial clock signal CLK; otherwise, it increases the duty cycle of the initial clock signal CLK, thereby obtaining the clock signal CLK1 with the adjusted duty cycle.

[0056] In the second cycle, the frequency divider module 14 generates second clock signals CKA and CKB based on the clock signal CLK1, denoted as CKA1 and CKB1. The comparator 11 compares VA and VB and then determines whether the duty cycle of the clock signal CLK1 is greater than or less than the target value. If the duty cycle of the clock signal CLK1 is greater than the target value, the duty cycle correction module 13 reduces the duty cycle of the clock signal CLK1; otherwise, it increases the duty cycle of the clock signal CLK1, thus obtaining the clock signal CLK2 with adjusted duty cycle.

[0057] This process continues until comparator 11 compares VA and VB and determines that the duty cycle of the current clock signal CLKi (where i = 0 to m, and m is an integer greater than or equal to 0) is equal to the target value. At this point, the duty cycle-adjusted clock signal CLKi output by the duty cycle correction module 13 can be locked and used as the final clock signal output to the external circuit.

[0058] The duty cycle correction circuit in this embodiment adds a pre-charge module compared to the prior art. After each comparison of the comparator, the voltage of the two input terminals of the comparator (i.e., the first charge / discharge node and the second charge / discharge node) is pre-charged to a predetermined voltage. This shortens the charging time of the charge pump module for the two charge / discharge nodes, so that the analog voltage output by the two charge / discharge nodes can quickly reach the input voltage value that the comparator can compare in the next comparison. This shortens the start-up time required for each comparison of the comparator, and also shortens the response time and settling time of the duty cycle correction circuit itself. Ultimately, this improves the clock duty cycle calibration efficiency and is beneficial to the improvement of signal transmission rate.

[0059] Second Embodiment

[0060] Please refer to Figure 7 This embodiment provides a duty cycle correction circuit, which differs from the first embodiment in that, in addition to the charge pump module 10, comparator 11, control module 12, duty cycle correction module 13, frequency divider module 14, precharge module 15 and fifth to eighth channel switches Q5 to Q8, the duty cycle correction circuit of this embodiment also includes a negative feedback module 16 and ninth to tenth channel switches Q9 to Q10.

[0061] The negative feedback module 16 includes a third inverter U3, a third channel switch Q3, and a fourth channel switch Q4. The input terminals of the third inverter U3 and the third channel switch Q3 are both connected to the output terminal of the comparator 11. The output terminal of the third inverter U3 is connected to the input terminal of the fourth channel switch Q4. The output terminals of the third channel switch Q3 and the fourth channel switch Q4 are connected to the same input terminal of the control module 12. The control terminal of the third channel switch Q3 is connected to the control signal CKS, and the control terminal of the fourth channel switch Q4 is connected to the control signal CKS_B. The control signal CKS is the inverted signal of the control signal CKS_B.

[0062] The input of the ninth channel switch Q9 is connected to the second charge / discharge node b, and the output of the ninth channel switch Q9 is connected to the non-inverting input of comparator 11. The input of the tenth channel switch Q10 is connected to the first charge / discharge node a, and the output of the tenth channel switch Q10 is connected to the inverting input of comparator 11. The control terminals of both the ninth channel switch Q9 and the tenth channel switch Q10 are connected to the control signal CKS_B.

[0063] In this embodiment, the negative feedback module 16 and the ninth to tenth channel switches Q9 to Q10 cooperate with each other under the control of the control signals CKS and CKS_B to control the two analog voltages VA and VB to be flipped and connected to the non-inverting or inverting input of the comparator 11 in each comparison cycle. This makes the input offset voltage of the comparator 11 evenly distributed to the high-level and low-level stages of the second clock signal CKA and the third clock signal CKB. Moreover, the loop feedback of the duty cycle correction circuit is always negative feedback, thereby eliminating the influence of the input offset voltage of the comparator 11 on the clock duty cycle adjustment, eliminating the inherent error of the duty cycle adjustment, enhancing the stability of the duty cycle correction circuit, improving the nonlinear distortion of the duty cycle correction circuit, and suppressing the noise and interference inside the duty cycle correction circuit. Finally, a clock signal with a more balanced duty cycle is obtained, and the adjustment accuracy of the clock duty cycle by the duty cycle correction circuit is improved.

[0064] Third Embodiment

[0065] Please refer to Figure 8 This embodiment provides a duty cycle correction circuit, which differs from the first embodiment in that, in addition to the charge pump module 10, comparator 11, control module 12, duty cycle correction module 13, frequency divider module 14, precharge module 15 and fifth to eighth channel switches Q5 to Q8, the duty cycle correction circuit of this embodiment also includes a negative feedback module 16 and ninth to tenth channel switches Q9 to Q10.

[0066] The negative feedback module 16 includes a third inverter U3, a third channel switch Q3, and a fourth channel switch Q4. The input terminals of the third inverter U3 and the third channel switch Q3 are both connected to the output terminal of the comparator 11. The output terminal of the third inverter U3 is connected to the input terminal of the fourth channel switch Q4. The output terminals of the third channel switch Q3 and the fourth channel switch Q4 are connected to the same input terminal of the control module 12. The control terminal of the third channel switch Q3 is connected to the control signal CKS, and the control terminal of the fourth channel switch Q4 is connected to the control signal CKS_B. The control signal CKS is the inverted signal of the control signal CKS_B.

[0067] The input of the ninth channel switch Q9 is connected to the input of the fifth channel switch Q5. The output of the ninth channel switch Q9 (on) is connected to the output of the sixth channel switch Q6. The input of the tenth channel switch Q10 is connected to the input of the sixth channel switch Q65. The output of the tenth channel switch Q10 is connected to the output of the fifth channel switch Q5. The control terminals of both the ninth channel switch Q9 and the tenth channel switch Q10 are connected to the control signal CKC_B, and the control signal CKC_B is the inverted version of the control signal CKC.

[0068] In this embodiment, the fifth to sixth channel switches Q5-Q6 and the ninth to tenth channel switches Q9-Q10 cooperate under the control of control signals CKC and CKC_B to control the second clock signal CKA and the third clock signal CKB to be flipped and connected to the charge pump module 10 in each comparison cycle. This causes the two analog voltages VA and VB output from the charge pump module 10 to be flipped and connected to the non-inverting or inverting input of the comparator 11 in each comparison cycle, thereby ensuring that the input offset voltage of the comparator 11 is evenly distributed to the second clock signal CKA and the third clock signal CKB. During the high and low levels of the clock signal CKB, and under the control of the control signals CKS and CKS_B, the negative feedback module 16 adjusts the loop feedback of the duty cycle correction circuit to always be negative feedback. This eliminates the influence of the input offset voltage of the comparator 11 on the clock duty cycle adjustment, eliminates the inherent error of the duty cycle adjustment, enhances the stability of the duty cycle correction circuit, improves the nonlinear distortion of the duty cycle correction circuit, and suppresses the noise and interference inside the duty cycle correction circuit. Finally, a clock signal with a more balanced duty cycle is obtained, and the adjustment accuracy of the clock duty cycle by the duty cycle correction circuit is improved.

[0069] Fourth embodiment

[0070] Please refer to Figure 9 and Figure 10 This embodiment also provides a chip, which includes the duty cycle correction circuit 1 described in any of the above embodiments of the present invention and a phase-locked loop circuit 2 coupled to the duty cycle correction circuit 1. The phase-locked loop circuit 2 can be disposed at the front end of the duty cycle correction circuit 1 (e.g., Figure 10 (as shown) or set at the rear end of the duty cycle correction circuit 1 (such as... Figure 9 (As shown).

[0071] Optionally, the chip in this embodiment can be a memory chip (e.g., a DDR memory chip), and the phase-locked loop circuit 2 can be a PLL circuit or a DLL circuit. Please refer to... Figure 9 When the phase-locked loop circuit 2 is positioned at the front end of the duty cycle correction circuit 1, it can be used to synchronize the clock signal of the internal circuit of the memory chip with the clock signal of the external circuit, thereby solving the clock skew problem. The duty cycle correction circuit 1 adjusts the duty cycle of the clock output by the phase-locked loop circuit 2 to the target value. Please refer to... Figure 10 When the phase-locked loop circuit 2 is located at the downstream end of the duty cycle correction circuit 1, it can synchronize the clock output by the duty cycle correction circuit 1 with the clock of the internal circuit of the memory chip, thereby solving the clock skew problem. Because the memory chip uses the duty cycle correction circuit 1 of this embodiment, its duty cycle can reach 50%. Therefore, when performing read and write operations on the memory chip based on a clock signal with a 50% duty cycle, the problems of uneven eye diagrams and incomplete data transmission at the data transmission end can be avoided.

[0072] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.< / n> < / n> < / n> < / n>

Claims

1. A duty cycle correction circuit, characterized in that, It includes a charge pump module, a comparator, a control module, a duty cycle correction module, a frequency divider module, and a precharge module, among which... The input terminal of the frequency divider module is coupled to the output terminal of the duty cycle correction module, and the frequency divider module is used to generate a second clock signal and a third clock signal based on the first clock signal output by the duty cycle correction module, wherein the second clock signal and the first clock signal have the same duty cycle, and the third clock signal is the inverted signal of the second clock signal; The charge pump module has a first charge / discharge node and a second charge / discharge node. The first charge / discharge node is coupled to the non-inverting input terminal of the comparator, and the second charge / discharge node is coupled to the inverting input terminal of the comparator. The charge pump module is used to charge or discharge the first charge / discharge node and the second charge / discharge node under the control of the second clock signal and the third clock signal to output two corresponding analog voltages. The output of the comparator is coupled to the input of the control module. The comparator is used to compare the two analog voltages output by the charge pump module under the control of the comparison enable signal. The output of the control module is coupled to one input of the duty cycle correction module, and the control module is used to generate a corresponding adjustment control signal based on the comparison result of the comparator and provide it to the duty cycle correction module. The duty cycle correction module is used to adjust the duty cycle of the first clock signal according to the adjustment control signal output by the control module. The precharge module is coupled to the first charge / discharge node and the second charge / discharge node. Under the control of the precharge control signal, the precharge module is used to precharge the voltage of the first charge / discharge node and the second charge / discharge node to a predetermined voltage after the comparator comparison is completed.

2. The duty cycle correction circuit as described in claim 1, characterized in that, The pre-charge module includes a first MOSFET, a second MOSFET, a first channel switch, a second channel switch, a first inverter, and a voltage divider circuit. The gate terminal of the first MOSFET, the input terminal of the first inverter, the control terminal of the first channel switch, and the control terminal of the second channel switch are all coupled to the pre-charge control signal. The source and drain terminals of the first MOSFET are respectively connected to the power supply voltage and one end of the voltage divider circuit. The output terminal of the first inverter is connected to the gate terminal of the second MOSFET. The source and drain terminals of the second MOSFET are respectively connected to the other end of the voltage divider circuit and ground. The input terminals of the first and second channel switches are connected to the output terminal of the voltage divider circuit. The output terminal of the first channel switch is coupled to the first charge / discharge node, and the output terminal of the second channel switch is coupled to the second charge / discharge node.

3. The duty cycle correction circuit as described in claim 1, characterized in that, The charge pump module includes a first to a fourth current source, a third to a sixth MOSFET, a first capacitor, and a second capacitor. The first current source, the third MOSFET, the fourth MOSFET, and the second current source are connected in series to form a first charging / discharging branch. The gate terminals of the third and fourth MOSFETs are both coupled to the second clock signal. The third MOSFET is positioned between the first current source and the first charging / discharging node, and the fourth MOSFET is positioned between the first charging / discharging node and the second current source. One end of the first capacitor is connected to the first charging / discharging node, and the other end is grounded. The third current source, the fifth MOSFET, the sixth MOSFET, and the fourth current source are connected in series to form a second charging / discharging branch. The gate terminals of the fifth and sixth MOSFETs are both coupled to the third clock signal. The fifth MOSFET is positioned between the third current source and the second charging / discharging node, and the sixth MOSFET is positioned between the second charging / discharging node and the fourth current source. One end of the second capacitor is connected to the second charging / discharging node, and the other end is grounded.

4. The duty cycle correction circuit as described in claim 1, characterized in that, The duty cycle correction module includes a second inverter and multiple duty cycle correction units. The input terminal of the second inverter and the input terminals of the multiple duty cycle correction units are interconnected to form the input terminal of the duty cycle correction module for receiving the initial clock signal. The output terminal of the second inverter and the output terminals of all the duty cycle correction units are interconnected to form the output terminal of the duty cycle correction module.

5. The duty cycle correction circuit as described in claim 1, characterized in that, It also includes a negative feedback module, which comprises a third inverter, a third channel switch, and a fourth channel switch. The input terminals of the third inverter and the third channel switch are both connected to the output terminal of the comparator. The output terminal of the third inverter is connected to the input terminal of the fourth channel switch. The output terminals of the third channel switch and the fourth channel switch are connected to the same input terminal of the control module. The control terminals of the third channel switch and the fourth channel switch are connected to mutually inverted control signals.

6. The duty cycle correction circuit as described in any one of claims 1-5, characterized in that, It also includes fifth to eighth channel switches. The fifth and sixth channel switches are respectively coupled between the frequency divider module and the charge pump module. The seventh channel switch is coupled between the first charge / discharge node and the non-inverting input of the comparator. The eighth channel switch is coupled between the second charge / discharge node and the inverting input of the comparator. When the fifth channel switch is turned on, the second clock signal is sent from the frequency divider module to the charge pump module. When the sixth channel switch is turned on, the third clock signal is sent from the frequency divider module to the charge pump module. When the seventh channel switch is turned on, the voltage of the first charge / discharge node is sent to the non-inverting input of the comparator. When the eighth channel switch is turned on, the voltage of the second charge / discharge node is sent to the inverting input of the comparator.

7. The duty cycle correction circuit as described in claim 6, characterized in that, It also includes a ninth to a tenth channel switch; wherein, the input terminal of the ninth channel switch is connected to the second charge / discharge node, the output terminal of the ninth channel switch is connected to the non-inverting input terminal of the comparator, the input terminal of the tenth channel switch is connected to the first charge / discharge node, and the output terminal of the tenth channel switch is connected to the inverting input terminal of the comparator; or, the input terminal of the ninth channel switch is connected to the input terminal of the fifth channel switch, the output terminal of the ninth channel switch is connected to the output terminal of the sixth channel switch, the input terminal of the tenth channel switch is connected to the input terminal of the sixth channel switch, and the output terminal of the tenth channel switch is connected to the output terminal of the fifth channel switch.

8. A chip, characterized in that, Includes the duty cycle correction circuit according to any one of claims 1-7.

9. The chip as described in claim 8, characterized in that, It also includes a phase-locked loop circuit coupled to the duty cycle correction circuit, wherein the phase-locked loop circuit is located at the front end of the duty cycle correction circuit or at the rear end of the duty cycle correction circuit.

10. The chip as described in claim 9, characterized in that, The chip is a memory chip, and / or the phase-locked loop circuit is a PLL circuit or a DLL circuit.

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