A feedback cut-off and false alarm detection system

Abstract

The application discloses a feedback cut-off and false alarm detection system, which comprises a signal trigger circuit, a false trigger detection circuit, a timing circuit and a signal synthesis circuit. When there is no specific trigger signal in space, the system is in a dormant state, and standby power consumption is almost zero. When there is a trigger signal in space, and the sum of the trigger signal and a pre-bias voltage is greater than a total switch-on voltage, the circuit is turned on to start working. The false trigger detection circuit can judge the false triggering of a non-specific signal and cut off the circuit when false triggering occurs. The timing circuit can realize the timing cut-off function of the circuit, and cut off the circuit when the working time of the circuit reaches a preset time, and the circuit continues to be dormant. The application has the characteristics of low power consumption, high sensitivity, low false alarm rate and stable closed-loop working of the circuit.

Description

Technical Field

[0001] This invention relates to a signal control circuit, specifically a passive wake-up structure for a circuit. Background Technology

[0002] With the development of IoT technology and advancements in manufacturing processes, technologies such as unmanned operation in remote areas and microcomputer monitoring within biological systems have gained wider application prospects. However, this also closely links the lifespan of devices with battery life. Currently, there are two common solutions: one is to use rechargeable batteries, which is convenient but affected by environmental factors; the other is to use wirelessly triggered wake-up sensor circuits, which are normally in a dormant state and only wake up and operate upon receiving specific signals, thereby greatly reducing power consumption and increasing battery life.

[0003] In recent years, both domestic and international researchers have explored various methods to implement and improve wireless sensor wake-up technology. Currently, a near-zero power wireless sensor wake-up circuit based on RF MEMS devices has been implemented. The circuit's front end integrates an antenna array to collect signals in a specific frequency band and generate a DC signal through an RF circuit. This signal causes the MEMS switch to close, thereby connecting the back-end circuit, which is powered by a commercial battery. This method ensures the circuit is disconnected in sleep mode and ideally achieves near-zero power consumption, but some problems still remain.

[0004] First, once the trigger signal disappears, the back-end circuit will be directly disconnected, which results in the working module having no buffer time at all, and the complete implementation of the function will be affected. Second, if the switch is closed due to an accident rather than level triggering, the circuit lacks an appropriate identification and response mechanism, so the node will give incorrect information. Summary of the Invention

[0005] Purpose of the invention: In view of the above-mentioned prior art, a near-zero power consumption feedback cutoff and false alarm detection system is proposed to solve the technical problems of existing passive wake-up systems that cannot work continuously and are subject to timed shutdown.

[0006] Technical solution: A feedback cutoff and false alarm detection system, including a signal triggering circuit, a false triggering detection circuit, a timing circuit, and a signal synthesis circuit;

[0007] The signal triggering circuit is used to control the switch to close according to the triggering signal, so as to connect the commercial battery and the commercial module power supply circuit, and the switch can remain closed under the high-level signal fed back by the signal synthesis circuit;

[0008] The false trigger detection circuit is used to compare the trigger signal or the high-level signal fed back by the signal synthesis circuit with a preset signal. If the trigger signal or the high-level signal fed back by the signal synthesis circuit is greater than the preset signal, the false trigger detection circuit outputs a high-level signal to the signal synthesis circuit.

[0009] The timing circuit starts working when the power supply circuit is turned on, and outputs a high level for a fixed duration to the signal synthesis circuit.

[0010] The signal synthesis circuit is used to perform AND logic operation on the output signals of the signal triggering circuit and the timing circuit. When both input signals are high level, the signal synthesis circuit outputs a high level signal to the signal triggering circuit and the false triggering detection circuit.

[0011] Furthermore, the signal triggering circuit includes a pre-biased battery and the switch; the negative terminal of the pre-biased battery serves as the DC positive input terminal of the signal triggering circuit, the positive terminal of the pre-biased battery is connected to the control terminal of the switch, and the negative terminal of the pre-biased battery is connected to the output terminal of the signal synthesis circuit.

[0012] Furthermore, the false trigger detection circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a voltage comparator; the positive terminal of the voltage comparator's power supply is connected to the positive terminal of the commercial battery, and the negative terminal of the voltage comparator's power supply is connected to one terminal of the switch; the first resistor is connected between the positive terminal of the voltage comparator's power supply and the inverting input terminal; the second resistor is connected between the inverting input terminal of the voltage comparator and the negative terminal of the power supply; the third resistor is connected between the non-inverting input terminal of the voltage comparator and the negative terminal of the power supply; and the fourth resistor is connected between the positive terminal of the voltage comparator's power supply and the output terminal of the voltage comparator; simultaneously, the non-inverting input terminal of the voltage comparator is connected to the DC positive input terminal of the signal trigger circuit.

[0013] Furthermore, the timing circuit includes a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, and an NE555 chip; pins 4 and 8 of the NE555 chip are connected and connected to the positive terminal of the commercial battery; pin 1 of the NE555 chip is connected to the terminal of the switch; pin 7 of the NE555 chip is connected to pins 4 and 8 of the NE555 chip through the fifth resistor; pins 2 and 6 of the NE555 chip are connected; pin 7 of the NE555 chip is connected to pins 2 and 6 of the NE555 chip through the sixth resistor; pins 2 and 6 of the NE555 chip are electrically connected to the positive terminal of the first capacitor; the negative terminal of the first capacitor is connected to pin 5 of the NE555 chip through the second capacitor; and pin 1 of the NE555 chip is connected to pin 5 of the NE555 chip through the second capacitor.

[0014] Furthermore, the signal synthesis circuit includes a seventh resistor, an eighth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first diode; one end of the seventh resistor is connected to the source of the first NMOS transistor, and the other end is connected to the positive terminal of the commercial battery; one end of the eighth resistor is connected to the source of the third NMOS transistor, and the other end is connected to the positive terminal of the commercial battery; the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, the drain of the second NMOS transistor is connected to the drain of the third NMOS transistor, and the anode of the first diode is connected to the source of the third NMOS transistor; the cathode of the first diode serves as the output terminal of the signal synthesis circuit and is connected to the cathode of the pre-biased battery; the drain of the first NMOS transistor is connected to pin 3 of the NE555 chip; and the drain of the second NMOS transistor is connected to the output terminal of the voltage comparator.

[0015] Furthermore, the switch is a MEMS switch, an NMOS transistor, a relay, or a BJT transistor.

[0016] Beneficial effects: 1. This invention uses a signal triggering circuit, a multi-false triggering detection circuit, a timing circuit, and a signal synthesis circuit to form an RF wake-up circuit, which realizes event-driven continuous sensing operation in a near-zero power mode (typically comparable to the leakage power of a general battery). That is, the commercial module can remain in a sleep state with almost zero power consumption, but can still be woken up by external signals of interest. High-power active electronic devices are turned on only when the signal is sensed and for the required duration, thereby overcoming the energy and lifespan limitations of wireless sensing systems.

[0017] 2. This invention employs a 555 timer combined with resistors and capacitors to construct a monostable timing circuit, which outputs a high-level signal for a set duration upon startup. Thus, even after the trigger signal disappears, if subsequent commercial modules have not yet fully implemented their functions, the system will not disconnect the circuit or forcibly interrupt module operation; instead, it will maintain a closed-loop state and continue supplying power until the timing ends, at which point the circuit will be cut off.

[0018] 3. This invention employs a voltage comparator to construct a false trigger detection circuit. Using the voltage comparator, the received signal is compared with a preset reference voltage. If the signal is less than the reference voltage, it is determined to be a false trigger, and a low-level output is generated, automatically shutting down the system.

[0019] 4. The near-zero power consumption feedback cutoff and false alarm detection system of the present invention can be implemented based on MEMS technology, and has the characteristics of low power consumption, high detection, low false alarm, miniaturization, tunable wake-up frequency, and low cost. Attached Figure Description

[0020] Figure 1This is a circuit diagram of a feedback cutoff and false alarm detection system with an input signal of radio frequency rectified signal provided in Example 1;

[0021] Figure 2 This is a circuit diagram of a feedback cutoff and false alarm detection system for an input signal that is a solar panel conversion signal, provided in Example 2.

[0022] Figure 3 This is a circuit diagram of a feedback cutoff and false alarm detection system where the input signal is an MCU control signal, as provided in Example 3.

[0023] Figure 4 This is a circuit diagram of a feedback cut-off and false alarm detection system where the control switch is a relay, as provided in Example 4. Detailed Implementation

[0024] The invention will now be further explained with reference to the accompanying drawings.

[0025] A feedback cutoff and false alarm detection system includes a signal triggering circuit 2, a false triggering detection circuit 3, a timing circuit 4, and a signal synthesis circuit 5. The signal triggering circuit 2 controls the closing of switch 22 based on a trigger signal, connecting the power supply circuit between the commercial battery 1 and the commercial module 6. Switch 22 remains closed under a high-level signal fed back from the signal synthesis circuit 5. The false triggering detection circuit 3 compares the trigger signal or the high-level signal fed back from the signal synthesis circuit 5 with a preset signal. If the trigger signal or the high-level signal fed back from the signal synthesis circuit 5 is greater than the preset signal, the false triggering detection circuit 3 outputs a high-level signal to the signal synthesis circuit 5. The timing circuit 4 starts operating when the power supply circuit is connected, outputting a high-level signal for a fixed duration to the signal synthesis circuit 5. The signal synthesis circuit 5 performs an AND logic operation on the output signals of the signal triggering circuit 2 and the timing circuit 4. When both input signals are high-level, the signal synthesis circuit 5 outputs a high-level signal to both the signal triggering circuit 2 and the false triggering detection circuit 3.

[0026] Among them, commercial module 6 includes, for example, microcontroller units, RF transceiver systems, network communication systems, and physical quantity sensors.

[0027] Example 1

[0028] like Figure 1 As shown, a feedback cutoff and false alarm detection system with an input signal of radio frequency rectified signal includes a commercial battery 1, a signal triggering circuit 2, a false triggering detection circuit 3, a timing circuit 4, a signal synthesis circuit 5, and a commercial module 6.

[0029] The signal triggering circuit 2 includes a MEMS switch 22, an antenna, a rectifier circuit, and a pre-biased battery 21. The antenna feed line is connected to the input terminal of the rectified current. The negative terminal of the rectifier circuit output is connected to one terminal S of the MEMS switch 22, and the positive terminal of the rectifier circuit output is connected to the negative terminal of the pre-biased battery 21. The positive terminal of the pre-biased battery 21 is connected to the control terminal G of the MEMS switch 22, and the other terminal D of the MEMS switch 22 is connected to the negative terminal of the commercial battery 1. In this embodiment, the trigger signal is generated by rectifying the video signal received by the antenna. When the trigger signal arrives, the sum of the signal and the pre-bias voltage provided by the pre-biased battery 21 is greater than the turn-on voltage of the MEMS switch 22, at which point the circuit is turned on and begins to work.

[0030] The false trigger detection circuit 3 includes a first resistor 31, a second resistor 32, a third resistor 33, a fourth resistor 34, and a voltage comparator 35. The positive terminal of the voltage comparator 35 is connected to the positive terminal of the commercial battery 1, and the negative terminal of the voltage comparator 35 is connected to the source of the MEMS switch 22. The first resistor 31 is connected between the positive terminal of the voltage comparator 35's power supply and its inverting input. The second resistor 32 is connected between the inverting input and the negative terminal of the voltage comparator 35's power supply. The third resistor 33 is connected between the non-inverting input and the negative terminal of the voltage comparator 35's power supply. The fourth resistor 34 is connected between the positive terminal of the voltage comparator 35's power supply and its output. The non-inverting input of the voltage comparator 35 is connected to the positive terminal of the rectifier circuit output. By modifying the values ​​of the first resistor 31 and the second resistor 32, the preset voltage at the inverting input of the voltage comparator 35 is controlled. If the trigger signal cannot reach the preset voltage value, the voltage comparator 35 outputs a low level, cuts off the circuit, and the system stops working.

[0031] The timing circuit 4 includes a fifth resistor 41, a sixth resistor 42, a first capacitor 44, a second capacitor 45, and an NE555 chip 43. Pins 4 and 8 of NE555 chip 43 are connected. Pins 4 and 8 of NE555 chip 43 are connected to the positive terminal of commercial battery 1. Pin 1 of NE555 chip 43 is connected to the source of MEMS switch 22. Pin 7 of NE555 chip 22 is connected to pins 4 and 8 of NE555 chip 43 through the fifth resistor 41. Pins 2 and 6 of NE555 chip 43 are connected. Pin 7 of NE555 chip 43 is connected to pins 2 and 6 of NE555 chip 43 through the sixth resistor 42. Pins 2 and 6 of NE555 chip 43 are electrically connected to the positive terminal of the first capacitor 44. The negative terminal of the first capacitor 44 is connected to pin 5 of NE555 chip 43 through the second capacitor 45. Pin 1 of NE555 chip 43 is connected to pin 5 of NE555 chip 43 through the second capacitor 45. The NE555 chip 43 operates in the working mode of the timing circuit 4. It realizes the function of starting the timing upon power-on by connecting the wires, that is, outputting a high level for a fixed duration, where the timing time τ = 1.1(R5+R6)*C1.

[0032] The signal synthesis circuit 5 includes a seventh resistor 51, an eighth resistor 52, a first NMOS transistor 53, a second NMOS transistor 54, a third NMOS transistor 55, and a first diode 56. One end of the seventh resistor 51 is connected to the source of the first NMOS transistor 53, and the other end is connected to the positive terminal of the commercial battery 1. One end of the eighth resistor 52 is connected to the source of the third NMOS transistor 55, and the other end is connected to the positive terminal of the commercial battery 1. The drain of the first NMOS transistor 53 is connected to the source of the second NMOS transistor 54, and the drain of the second NMOS transistor 54 is connected to the drain of the third NMOS transistor 55. The positive terminal of the first diode 56 is connected to the source of the third NMOS transistor 55, and the negative terminal of the first diode 56 is connected to the negative terminal of the pre-biased battery 21. The drain of the first NMOS transistor 53 is connected to pin 3 of the NE555 chip 43, and the drain of the second NMOS transistor 54 is connected to the output terminal of the voltage comparator 35. The signal synthesis circuit 5 performs an AND logic operation on the output of the voltage comparator 35 and the output of the NE555 chip 43. Only when both are at a high level will a high-level signal be generated and fed back to the MEMS switch 22.

[0033] Example 2

[0034] like Figure 2 As shown, a feedback cutoff and false alarm detection system with an input signal converted from a solar panel differs from Embodiment 1 in that the signal triggering circuit 2 lacks an antenna and rectifier circuit, incorporates a solar panel, and uses an NMOS transistor for the switch 22. Since the other structures are identical to Embodiment 1, only the signal triggering circuit 2 in Embodiment 2 will be described here.

[0035] The signal trigger circuit 2 includes an NMOS transistor switch 22, a solar panel, and a pre-biased battery 21. The negative terminal of the solar panel output is connected to the source of the NMOS transistor switch 22, the positive terminal of the solar panel output is connected to the negative terminal of the pre-biased battery 21, the positive terminal of the pre-biased battery 21 is connected to the gate of the NMOS transistor switch 22, and the drain of the NMOS transistor switch 22 is connected to the negative terminal of the commercial battery 1. The trigger signal is a DC signal output from the solar panel. When the trigger signal arrives, its superposition with the pre-bias voltage exceeds the turn-on voltage of the NMOS transistor switch 22, at which point the circuit is turned on and begins to operate.

[0036] Example 3

[0037] like Figure 3 As shown, a feedback cutoff and false alarm detection system with an input signal of MCU control signal differs from Embodiment 1 in that the signal triggering circuit 2 lacks an antenna and rectifier circuit, adds a microcontroller unit, and the switch 22 uses a BJT transistor. Since the other structures are completely identical to Embodiment 1, only the signal triggering circuit 2 in Embodiment 3 will be described here.

[0038] The signal triggering circuit 2 includes a BJT transistor switch 22, a microcontroller unit, and a pre-biased battery 21. The negative terminal of the microcontroller unit's output is connected to the emitter of the BJT transistor switch 22, the positive terminal of the microcontroller unit's output is connected to the negative terminal of the pre-biased battery 21, the positive terminal of the pre-biased battery 21 is connected to the base of the BJT transistor switch 22, and the collector of the BJT transistor switch 22 is connected to the negative terminal of the commercial battery 1. The trigger signal is a DC signal output by the control unit. When the trigger signal arrives, its superposition with the pre-biased voltage exceeds the turn-on voltage of the BJT transistor switch 22, at which point the circuit is turned on and begins to operate.

[0039] Example 4

[0040] like Figure 4 As shown, a feedback cutoff and false alarm detection system with an input signal of radio frequency rectified signal differs from Embodiment 1 in that the switch 22 in the signal triggering circuit 2 is a relay. Since the other structures are completely identical to Embodiment 1, only the signal triggering circuit 2 in Scheme 1 will be supplemented here to describe its structure.

[0041] The signal triggering circuit 2 includes an optional relay switch 22, an antenna, a rectifier circuit, and a pre-biased battery 21. The antenna feed line is connected to the input terminal of the rectified current. The negative terminal of the rectifier circuit output is connected to the negative terminal of the relay switch 22 coil. The negative terminal of the relay switch 22 is connected to contact 2. The positive terminal of the rectifier circuit output is connected to the negative terminal of the pre-biased battery 21. The positive terminal of the pre-biased battery 21 is connected to the positive terminal of the relay switch 22 coil. Contact 1 of the relay switch 22 is connected to the negative terminal of the commercial battery 1. Contact 2 of the relay switch 22 is connected to the negative terminal of the power supply of the voltage comparator 35. When the trigger signal arrives, the sum of the signal and the pre-biased voltage exceeds the turn-on voltage of the relay switch 22, at which point the circuit is activated and begins to operate.

[0042] The core working principle of the above four embodiments is the same, which will be explained in detail below:

[0043] like Figure 1-4 As shown, when the sum of the externally input DC-level trigger signal (including RF rectified signal, solar panel level signal, and microcontroller output signal) and the pre-bias voltage reaches the opening voltage of switch 22, switch 22 will close. At this time, the power supply circuit between commercial battery 5 and commercial module 6 is turned on, and the system starts working. Simultaneously, in the false trigger detection circuit 3, the input terminal of voltage comparator 35 compares the received trigger signal with the preset reference voltage. If it is less than the preset reference voltage, it is determined to be a false trigger, and a low level is output. At this time, switch 22 will be turned off after the false trigger closes. Otherwise, it is determined to be a non-false trigger, and a high level is output. After the system starts working, due to the conduction of the power supply circuit, the timing circuit 4 starts timing as soon as it is powered on, and outputs a high level for a fixed period of time. The signal synthesis circuit 5 performs an AND operation on the output of timing circuit 4 and the output of false trigger detection circuit 3, and feeds back the synthesis result to the non-inverting input terminals of switch 22 and voltage comparator 35 to ensure that the circuit closed loop works stably and is no longer affected by subsequent DC-level signals. When the timing ends, the signal synthesis circuit 5 outputs a low level, at which point switch 22 is opened, the system stops working, and the timing function is realized.

[0044] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A feedback cutoff and false alarm detection system, characterized in that, Includes a signal triggering circuit (2), a false triggering detection circuit (3), a timing circuit (4), and a signal synthesis circuit (5); 2 / 3 / 5 The signal triggering circuit (2) is used to control the switch (22) to close according to the triggering signal, so that the power supply circuit between the commercial battery (1) and the commercial module (6) is connected, and the switch (22) can remain closed under the high-level signal fed back by the signal synthesis circuit (5); The false trigger detection circuit (3) is used to compare the high-level signal fed back by the trigger signal or the signal synthesis circuit (5) with a preset signal. If the high-level signal fed back by the trigger signal or the signal synthesis circuit (5) is greater than the preset signal, the false trigger detection circuit (3) outputs a high-level signal to the signal synthesis circuit (5). The timing circuit (4) starts working when the power supply circuit is turned on, and outputs a high level for a fixed time to the signal synthesis circuit (5). The signal synthesis circuit (5) is used to perform AND logic operation on the output signals of the signal triggering circuit (2) and the timing circuit (4). When both input signals are high level, the signal synthesis circuit (5) outputs a high level signal to the signal triggering circuit (2) and the false triggering detection circuit (3). The signal triggering circuit (2) includes a pre-biased battery (21) and the switch (22); the negative terminal of the pre-biased battery (21) serves as the DC positive input terminal of the signal triggering circuit (2), the positive terminal of the pre-biased battery (21) is connected to the control terminal of the switch (22), and the negative terminal of the pre-biased battery (21) is connected to the output terminal of the signal synthesis circuit (5); The false trigger detection circuit (3) includes a first resistor (31), a second resistor (32), a third resistor (33), a fourth resistor (34), and a voltage comparator (35). The positive terminal of the power supply of the voltage comparator (35) is connected to the positive terminal of the commercial battery (1), and the negative terminal of the power supply of the voltage comparator (35) is connected to one terminal of the switch (22). The first resistor (31) is connected between the positive terminal of the power supply of the voltage comparator (35) and the inverting input terminal. The second resistor (32) is connected between the inverting input terminal of the voltage comparator (35) and the negative terminal of the power supply. The third resistor (33) is connected between the non-inverting input terminal of the voltage comparator (35) and the negative terminal of the power supply. The fourth resistor (34) is connected between the positive terminal of the power supply of the voltage comparator (35) and the output terminal of the voltage comparator (35). At the same time, the non-inverting input terminal of the voltage comparator (35) is connected to the DC positive input terminal of the signal trigger circuit (2). The signal synthesis circuit (5) includes a seventh resistor (51), an eighth resistor (52), a first NMOS transistor (53), a second NMOS transistor (54), a third NMOS transistor (55), and a first diode (56). One end of the seventh resistor (51) is connected to the drain of the first NMOS transistor (53) and the gate of the third NMOS transistor (55), and the other end is connected to the positive terminal of the commercial battery (1). One end of the eighth resistor (52) is connected to the drain of the third NMOS transistor (55), and the other end is connected to the positive terminal of the commercial battery (1). The first NMOS transistor (53)... The source of the first diode (53) is connected to the drain of the second NMOS transistor (54), the source of the second NMOS transistor (54) is connected to the source of the third NMOS transistor (55), the positive terminal of the first diode (56) is connected to the drain of the third NMOS transistor (55); the negative terminal of the first diode (56) serves as the output terminal of the signal synthesis circuit (5) and is connected to the negative terminal of the pre-biased battery (21); the gate of the first NMOS transistor (53) is connected to the third pin of the NE555 chip (43); and the gate of the second NMOS transistor (54) is connected to the output terminal of the voltage comparator (35).

2. The feedback cutoff and false alarm detection system according to claim 1, characterized in that, The timing circuit (4) includes a fifth resistor (41), a sixth resistor (42), a first capacitor (44), a second capacitor (45), and an NE555 chip (43); pins 4 and 8 of the NE555 chip (43) are connected and connected to the positive terminal of the commercial battery (1); pin 1 of the NE555 chip (43) is connected to the terminal of the switch (22); pin 7 of the NE555 chip (43) is connected to pins 4 and 8 of the NE555 chip (43) through the fifth resistor (41); the NE555 chip (43) Pins 2 and 6 of NE555 chip (43) are connected. Pin 7 of NE555 chip (43) is connected to pins 2 and 6 of NE555 chip (43) through the sixth resistor (42). Pins 2 and 6 of NE555 chip (43) are connected to the positive terminal of the first capacitor (44). The negative terminal of the first capacitor (44) is connected to pin 5 of NE555 chip (43) through the second capacitor (45). Pin 1 of NE555 chip (43) is connected to pin 5 of NE555 chip (43) through the second capacitor (45).

3. The feedback cutoff and false alarm detection system according to claim 1 or 2, characterized in that, The switch (22) is a MEMS switch, an NMOS transistor, a relay, or a BJT transistor.

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