A single-channel ultra-high-speed analog-to-digital converter based on multi-stage comparators
By optimizing the multi-stage comparator and asynchronous clock generation circuit, the problems of slow comparator comparison speed and incomplete reset in the asynchronous high-speed successive approximation analog-to-digital converter were solved, and high-speed and stable analog-to-digital conversion was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2023-04-13
- Publication Date
- 2026-05-19
AI Technical Summary
Existing asynchronous high-speed successive approximation analog-to-digital converters have slow comparator comparison speeds and suffer from incomplete reset and metastability issues, which affect quantization speed and stability.
By employing a multi-stage comparator structure, incorporating a MOSFET to act as positive feedback, and combining it with an asynchronous clock generation circuit and capacitor switch control logic, the comparator circuit and clock control are optimized, thus resolving the issues of incomplete comparator reset and metastability.
The comparison speed of the comparator was improved, the metastability problem was alleviated, the capacitor switch control logic was simplified, and the stability and power consumption performance of the circuit were improved.
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Figure CN116488654B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of mixed-signal integrated circuit design, specifically relating to a single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator. Background Technology
[0002] In recent years, with the continuous development of integrated circuit technology and the further improvement of analog-to-digital converter (ADC) performance, research on high-speed successive approximation ADCs (SAR ADCs) has become increasingly in-depth. Since they do not require operational amplifiers, high-speed successive approximation ADCs have a natural advantage in low power consumption, especially at the nanometer-level process node, where their speed has been greatly improved. Therefore, high-speed successive approximation ADCs have become a research hotspot in the ADC field. Because synchronous high-speed successive approximation ADCs require the generation of a high-frequency internal clock, which consumes a significant amount of power, and because the generation of a high-frequency clock becomes increasingly difficult as the sampling frequency continues to increase, asynchronous high-speed successive approximation ADC structures have been proposed.
[0003] For current asynchronous high-speed successive approximation analog-to-digital converters (ADCs), the comparator's comparison speed is one of the main reasons limiting its quantization speed. Commonly used comparators are two-stage structures, which are not fast enough. Furthermore, because the output voltage values of the third stage differ significantly before reset, incomplete reset can occur. Conversely, when the input voltage difference of the comparator is very small, metastability issues arise, affecting the generation of the subsequent comparator reset clock and the capacitor setting process. Summary of the Invention
[0004] To address the aforementioned problems in the prior art, this invention provides a single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator. The technical problem to be solved by this invention is achieved through the following technical solution:
[0005] A single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator includes: a bootstrap switch, a split-bridge DAC capacitor array, a comparator circuit, a shift circuit, an asynchronous clock generation circuit, and a capacitor switch control logic circuit.
[0006] A bootstrap switch is used to sample and hold the input signal to obtain a sampled voltage.
[0007] A split-bridge DAC capacitor array is used to complete the successive approximation process of voltage and generate the comparison voltage signal at the comparator input.
[0008] The comparator circuit includes an improved multi-stage comparator and a latch stage, used to compare and latch the comparator input signals obtained after each successive approximation, and generate a set signal to control the split bridge DAC capacitor array based on the comparison result; MOS transistors that act as positive feedback are added in some stages of the multi-stage comparator and between some adjacent stages.
[0009] A shift circuit is used to control the output of a memory comparator in the latch stage sequence.
[0010] An asynchronous clock generation circuit is used to generate clock signals corresponding to each stage. The asynchronous clock generation circuit adjusts the comparison and reset time of the comparator circuit by using the VBP and VBN signals generated after the first comparison result of the comparator circuit is latched. When the separation degree of the final output of the multi-stage comparator does not reach a predetermined value, the asynchronous clock generation circuit forces the generation of the falling edge of the comparator clock.
[0011] The capacitor switch control logic circuit is used to adjust the lower plate of the split-bridge DAC capacitor array according to the set signal, thereby changing the magnitude of the comparison voltage signal.
[0012] In one embodiment of the present invention, the first three stages of the comparator circuit are multiplexed structures. The fourth stage, the latch stage, contains eight parallel latch units used to sequentially store the comparator's output results. The normal operation of the latch stage is controlled by eight shift circuits. A transmission gate structure is added between the P and N signals at the output of the third stage of the comparator circuit.
[0013] In one embodiment of the present invention, the fourth stage of the comparator circuit includes transistor T7, MOSFETs M10P, M11P, M12P, M13P, M14P, M10N, M11N, M12N, M13N, M14N, a first inverter, a second inverter, a third inverter, and a fourth inverter; wherein,
[0014] The source of transistor T7 is connected to VDD, the gate is connected to the CK signal, and the drain is connected to the QD junction signal.
[0015] The source of the MOSFET M10P is connected to the QD signal, the gate is connected to the ON signal, and the drain is connected to the OP signal.
[0016] The source of the MOSFET M11P is grounded, the gate is connected to the ON signal, and the drain is connected to the OP signal.
[0017] The source of MOSFET M12P is connected to the drain of MOSFET M14P, the gate is connected to the QB signal, and the drain is connected to the OP signal.
[0018] The source of MOSFET M13P is grounded, the gate is connected to the RES signal, and the drain is connected to the OP signal.
[0019] The source of MOSFET M14P is grounded, the gate is connected to the P signal, and the drain is connected to the source of MOSFET M12P.
[0020] The source of the MOSFET M10N is connected to the QD signal, the gate is connected to the OP signal, and the drain is connected to the ON signal.
[0021] The source of the MOSFET M11N is grounded, the gate is connected to the OP signal, and the drain is connected to the ON signal.
[0022] The source of MOSFET M12N is connected to the drain of MOSFET M14N, the gate is connected to the QB signal, and the drain is connected to the ON signal.
[0023] The source of the MOSFET M13N is grounded, the gate is connected to the RES signal, and the drain is connected to the ON signal.
[0024] The source of MOSFET M14N is grounded, the gate is connected to the N signal, and the drain is connected to the source of MOSFET M12N.
[0025] The input of the first inverter is connected to the PB signal, and the output is connected to the PX signal.
[0026] The input of the second inverter is connected to the OP signal, and the output is connected to the PB signal.
[0027] The input of the third inverter is connected to the ON signal, and the output is connected to the NB signal.
[0028] The input of the fourth inverter is connected to the NB signal, and the output is connected to the NX signal.
[0029] In one embodiment of the present invention, the asynchronous clock generation circuit uses the output of the third stage of the comparator circuit as an excitation to generate a reset signal for the comparator circuit, wherein the rising edge of the comparator clock in the asynchronous clock generation circuit is spontaneously generated based on the generation of the falling edge.
[0030] In one embodiment of the present invention, when the separation degree of the final stage output of the multi-stage comparator does not reach a predetermined value, the asynchronous clock generation circuit forces the generation of the falling edge of the comparator clock, including:
[0031] The asynchronous clock generation circuit uses a pull-up transistor MP3 controlled by the CLKD signal added to the input of the CLKB signal. When the separation degree of the third stage output of the comparator circuit does not reach the predetermined value, the low level of the CLKB signal is pulled high.
[0032] In one embodiment of the present invention, the CLK signal in the asynchronous clock generation circuit is connected to an inverter for adjusting the delay, and the MOS transistor MN7 controlled by the VBN signal is used to adjust the duration of the reset phase.
[0033] In one embodiment of the present invention, the asynchronous clock generation circuit includes MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10; wherein,
[0034] The sources of MOSFETs MP1-MP7, MP9, and MP10 are connected in parallel and then connected to VDD. The drains of MOSFETs MP1-MP4 are connected in parallel to form the first node, and the gates of MOSFETs MP5 and MN4 are connected in parallel to form the second node. The first and second nodes are connected through the CLKB signal.
[0035] The gate of MOSFET MP1 is connected to the P signal;
[0036] The gate of MOSFET MP2 is connected to the N signal;
[0037] The gate of MOSFET MP3 is connected to the CLKD signal;
[0038] The gate of MOSFET MP4 is connected to node AA;
[0039] The drains of MOSFET MP5 and MOSFET MN4 are connected in parallel to form the third node, and the gates of MOSFET MP6 and MOSFET MN5 are connected in parallel to form the fourth node. The third node and the fourth node are connected through the CLKBB signal.
[0040] The drains of MOSFET MP6 and MOSFET MN5 are connected in parallel to form the fifth node, and the gates of MOSFET MP8 and MOSFET MN6 are connected in parallel to form the sixth node. The fifth and sixth nodes are connected through the CLK signal.
[0041] The drain of MOSFET MP7 is connected to the source of MOSFET MP8, and the gate of MOSFET MP7 is connected to the VBP signal.
[0042] The drains of MOSFET MP8 and MOSFET MN6 are connected in parallel to form the seventh node, and the gates of MOSFET MP9 and MOSFET MN8 are connected in parallel to form the eighth node. The seventh node and the eighth node are connected together.
[0043] The drains of MOSFET MP9 and MOSFET MN8 are connected via the CLKD signal;
[0044] The gate of MOSFET MP10 is connected to the gate of MOSFET MN10 via the RDY signal, and the drain of MOSFET MP10 is connected to the source of MOSFET MP11.
[0045] The gate of MOSFET MP11 is connected to the gate of MOSFET MN9 via the CLKS signal, and the drains of MOSFET MP11, MOSFET MN9 and MOSFET MN10 are connected via the AA node.
[0046] The drain of MOSFET MN1 is connected to the CLKB signal, the gate is connected to node AA, and the source is connected to the drains of MOSFETs MN2 and MN3.
[0047] The gate of MOSFET MN2 is connected to the CLKD signal, and the drains of MOSFETs MN2-MN5 and MOSFETs MN7-MN10 are connected in parallel and then connected to GND.
[0048] The gate of MOSFET MN3 is connected to the CLK signal;
[0049] The drain of MOSFET MN7 is connected to the source of MOSFET MN6, and the gate of MOSFET MN7 is connected to the VBN signal.
[0050] In one embodiment of the present invention, the capacitor switch control logic circuit includes MOSFETs M1, M2, M3, M4, and M5; wherein,
[0051] The source of MOSFET M1 is grounded, the gate is connected to the RES signal, and the drain is connected to the L terminal of the split bridge DAC capacitor array.
[0052] The source of MOSFET M2 is connected to VDD, the gate is connected to the L terminal of the split bridge DAC capacitor array, and the drain is connected to the H terminal of the split bridge DAC capacitor array.
[0053] The source of MOSFET M3 is grounded, the gate is connected to the H terminal of the split bridge DAC capacitor array, and the drain is connected to the L terminal of the split bridge DAC capacitor array.
[0054] The source of MOSFET M4 is grounded, the gate is connected to the PX / NX signal, and the drain is connected to the H terminal of the split bridge DAC capacitor array.
[0055] The source of MOSFET M5 is connected to VDD, the gate is connected to the PB / NB signal, and the drain is connected to the L terminal of the split bridge DAC capacitor array.
[0056] The beneficial effects of this invention are:
[0057] The overall design employs a multi-stage comparator and a single-stage latch stage (the multi-stage comparator serves as a pre-amplification stage) to improve the comparator's comparison speed and mitigate metastability issues. Specifically,
[0058] 1. By adding MOSFETs that act as positive feedback in some stages and between some adjacent stages of a multi-stage comparator, the comparison speed can be further accelerated.
[0059] 2. The comparison and reset times of the comparator circuit are adjusted by using the VBP and VBN signals generated after the first comparison result of the comparator circuit is latched; wherein, when the separation degree of the final stage output of the multi-stage comparator does not reach a predetermined value, the asynchronous clock generation circuit forces the falling edge of the comparator clock to solve the comparator metastability problem.
[0060] 3. A transmission gate structure is added to the output of the final stage comparator to improve the comparator's reset problem.
[0061] 4. To address the shortcomings of traditional capacitor switch control logic circuits, such as complex structure, high power consumption, and low stability, the circuit structure of the capacitor switch control logic section is simplified, while the positive feedback structure in the circuit improves the circuit's stability. Attached Figure Description
[0062] Figure 1 This is a schematic diagram of the structure of a single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator provided in an embodiment of the present invention;
[0063] Figure 2 This is a structural diagram of the split-bridge DAC capacitor array provided in an embodiment of the present invention;
[0064] Figure 3 This is a schematic diagram of a four-stage comparator circuit provided in an embodiment of the present invention;
[0065] Figure 4 This is a schematic diagram of the shift circuit provided in an embodiment of the present invention;
[0066] Figure 5 The timing waveform diagram of the quantization process provided in the embodiment of the present invention;
[0067] Figure 6 This is a structural diagram of the asynchronous clock generation circuit provided in an embodiment of the present invention;
[0068] Figure 7 This is an asynchronous clock timing waveform diagram provided in an embodiment of the present invention;
[0069] Figure 8 This is a structural diagram of the switched capacitor control logic circuit provided in an embodiment of the present invention. Detailed Implementation
[0070] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.
[0071] This invention designs a single-channel ADC, but it can also be used as a sub-ADC in multi-channel systems. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.
[0072] The embodiments of the present invention will be described below.
[0073] This invention provides a single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator, comprising: a bootstrap switch, a split-bridge DAC capacitor array, a comparator circuit, a shift circuit, an asynchronous clock generation circuit, and a capacitor switch control logic circuit, wherein...
[0074] A bootstrap switch is used to sample and hold the input signal to obtain a sampled voltage.
[0075] A split-bridge DAC capacitor array is used to complete the successive approximation process of voltage and generate the comparison voltage signal at the comparator input.
[0076] The comparator circuit includes an improved multi-stage comparator and a latch stage, which is used to compare and latch the comparator input signals obtained after each successive approximation, and generate a set signal to control the split-bridge DAC capacitor array based on the comparison result; MOS transistors that act as positive feedback are added in some stages of the multi-stage comparator and between some adjacent stages.
[0077] A shift circuit is used to control the output of a memory comparator in the latch stage sequence.
[0078] An asynchronous clock generation circuit is used to generate clock signals corresponding to each stage. The asynchronous clock generation circuit adjusts the comparison and reset time of the comparator circuit by using the VBP and VBN signals generated after the first comparison result of the comparator circuit is latched. When the separation degree of the final stage output of the multi-stage comparator does not reach a predetermined value, the asynchronous clock generation circuit forces the generation of the falling edge of the comparator clock.
[0079] The capacitor switch control logic circuit is used to adjust the lower plate of the bridged DAC capacitor array according to the set signal, thereby changing the magnitude of the comparison voltage signal.
[0080] In one optional implementation, the comparator circuit of this invention employs a three-stage comparator plus a latch stage structure, forming a four-stage comparator. The following explanation uses this comparator circuit as an example to illustrate the circuit structure and overall working principle of this single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator. Please refer to... Figure 1 As shown, Figure 1 The asynchronous clock in the middle refers to the asynchronous clock generation circuit. The PX / NX signals output by the four-stage comparator control the split-bridge DAC capacitor array through capacitor switch control logic. Based on 28nm CMOS technology and a power supply voltage of 0.9V, this embodiment of the invention can realize an 8-bit ultra-high-speed SAR ADC. The overall circuit of this single-channel ultra-high-speed analog-to-digital converter based on multi-stage comparators adopts a differential structure.
[0081] Where VIP and VIN are differential input signals; VP and VN are the positive and negative input signals of the comparator circuit, respectively; CLKBB is the comparator clock signal generated by the asynchronous clock generation circuit; P and N are the output signals of the third stage of the comparator circuit; PX and NX are the output signals of the latch stage in the comparator circuit; D OUT <7:0> represents the quantized output digital code.
[0082] The following is a detailed explanation of each circuit:
[0083] Boot switch
[0084] Because the on-resistance of a single MOSFET sampling switch varies with the input voltage, it can cause harmonic distortion in the sampled signal. Therefore, in medium- to high-precision SAR ADCs, a gate-voltage bootstrap switch is typically used to implement the sample-and-hold circuit. Please refer to the relevant technical documentation for details; further explanation is not provided here.
[0085] Split-bridge DAC capacitor array
[0086] Please refer to the split-bridge DAC capacitor array of this invention embodiment. Figure 1 A capacitor array preceding the input of the amplifier circuit. To reduce circuit power consumption while minimizing the total capacitance of the capacitor array, this embodiment of the invention employs V... CM -based switching timing. V CM -based switching timing can reduce circuit power consumption, but its disadvantage is the increased reference voltage V. CM In order to achieve V CM It has the same functionality as the -based timing method, but without adding a new reference voltage. The capacitor array in this embodiment of the invention adopts a split-bridge capacitor structure, such as... Figure 2As shown, VP and VN represent the positive and negative input terminals of the comparator circuit, respectively; C represents the unit capacitance of the capacitor array; PH and PL represent the bottom plate voltages of the P-terminal capacitor; and NH and NL represent the bottom plate voltages of the N-terminal capacitor. During the reset phase, all H nodes at the P / N terminals are reset to VDD, and all L nodes are reset to GND. During the first comparison, if VP > VN, the voltage of node PH1 is switched from VDD to GND, and the voltage of node NL1 is switched from GND to VDD; conversely, if VP > VN, the voltage of node PL1 is switched from GND to VDD, and the voltage of node NH1 is switched from VDD to GND. This process is repeated to achieve the comparator voltage. CM -Based voltage switching function with the same timing.
[0087] The voltage signal establishment time is positively correlated with the capacitance value; therefore, reducing the capacitance value of each bit can improve the speed of the ADC. To achieve this reduction in capacitance value, this embodiment of the invention employs a split bridge capacitor structure.
[0088] To minimize the capacitance value, during the final capacitor switching, only the capacitor with the higher voltage during the current comparison is switched. Therefore, the quantization range is still halved compared to the previous one, but the total capacitance value of the capacitor array is reduced by half.
[0089] comparator circuit
[0090] The comparator circuit is a key module in a high-speed SAR ADC. In the design of a high-speed SAR ADC, the most critical performance indicator for the comparator circuit is its comparison speed. Generally, when the input voltage difference at the comparator circuit's input terminals is small, the comparison speed is limited. To improve the overall comparison speed, this embodiment of the invention employs the following... Figure 3The circuit structure shown, from left to right, is as follows: first stage, second stage, third stage, and fourth stage. The circles in the diagram represent the improvements in the first three stages. Here, CLKBB is the comparator comparison clock, CLK is the comparator reset clock; VP and VN represent the positive and negative input signals of the comparator circuit, respectively; AAP and AAN are the first stage output signals of the comparator circuit; YP and YN are the second stage output signals of the comparator circuit; P and N are the third stage output signals of the comparator circuit; VR, PP, and FF are the drain voltages of the tail current transistors of the first, second, and third stages of the comparator circuit, respectively; CK is the latch stage enable signal; RES is the reset signal after quantization; QB is the latch stage enable signal; OP and ON are the latch stage output signals; PB and NB are the buffered signals after the latch stage output signals pass through an inverter; PX and NX are the latch stage output signals after being buffered by two inverters. The first three stages of the comparator circuit are multiplexed. The fourth stage, the latch stage, contains eight parallel latch units used to sequentially store the comparator's output. The normal operation of the latch stage is controlled by eight shift circuits. The latch unit is... Figure 3 As shown in the 4th Dynamiclatch diagram, the fourth stage should have seven more identical latching units. The fourth stage consists of eight latching units. For simplicity in drawing, the other seven latching units are not shown, provided the circuit structure is clearly represented. Figure 3 The eight latch units correspond to eight comparison processes. The fourth stage of the comparator circuit is as follows: Figure 3 As shown, it includes transistor T7, MOSFETs M10P, M11P, M12P, M13P, M14P, M10N, M11N, M12N, M13N, M14N, a first inverter, a second inverter, a third inverter, and a fourth inverter; wherein,
[0091] The source of transistor T7 is connected to VDD, the gate is connected to the CK signal, and the drain is connected to the QD signal.
[0092] The source of the MOS transistor M10P is connected to the QD signal, the gate is connected to the ON signal, and the drain is connected to the OP signal.
[0093] The source of the MOS transistor M11P is grounded, the gate is connected to the ON signal, and the drain is connected to the OP signal.
[0094] The source of the MOS transistor M12P is connected to the drain of the MOS transistor M14P, the gate is connected to the QB signal, and the drain is connected to the OP signal.
[0095] The source of the MOSFET M13P is grounded, the gate is connected to the RES signal, and the drain is connected to the OP signal.
[0096] The source of the MOS transistor M14P is grounded, the gate is connected to the P signal, and the drain is connected to the source of the MOS transistor M12P.
[0097] The source of the MOS transistor M10N is connected to the QD signal, the gate is connected to the OP signal, and the drain is connected to the ON signal.
[0098] The source of the MOS transistor M11N is grounded, the gate is connected to the OP signal, and the drain is connected to the ON signal.
[0099] The source of the MOS transistor M12N is connected to the drain of the MOS transistor M14N, the gate is connected to the QB signal, and the drain is connected to the ON signal.
[0100] The source of the MOSFET M13N is grounded, the gate is connected to the RES signal, and the drain is connected to the ON signal.
[0101] The source of the MOS transistor M14N is grounded, the gate is connected to the N signal, and the drain is connected to the source of the MOS transistor M12N.
[0102] The input terminal of the first inverter is connected to the PB signal, and the output terminal is connected to the PX signal;
[0103] The input terminal of the second inverter is connected to the OP signal, and the output terminal is connected to the PB signal;
[0104] The input terminal of the third inverter is connected to the ON signal, and the output terminal is connected to the NB signal;
[0105] The input terminal of the fourth inverter is connected to the NB signal, and the output terminal is connected to the NX signal.
[0106] The comparator circuit uses a common-source pre-amplifier structure in its first stage. The second stage further amplifies and latches the output of the first stage. The third stage latches the output of the second stage. The differential input transistor M in the first stage... 1P / M 1N The main function is to amplify the original voltage difference; the second-stage differential input transistor M... 3P / M 3N This achieves further amplification of the voltage difference, MOSFET M 4P / M 4N With MOSFET M 5P / M 5N A positive feedback loop is formed to quickly separate the amplified voltage difference, accelerating the comparison process in the second stage of the comparator. The differential input transistor M in the third stage... 6P / M 6N M acts as the differential input tube of the second stage 3P / M 3NA similar amplification effect transmits the voltage difference between YP and YN to the third stage, thus, in the third-stage MOSFET M... 7P / M 7N and MOSFET M 8P / M 8N Under the action of the positive feedback loop, the P and N voltage signals are further separated. The two-stage pre-amplification increases the amplification factor, greatly improving the comparison speed when comparing small voltage differences. Meanwhile, when comparing inputs with larger voltage differences (voltage difference greater than half the LSB voltage), the output AAP / AAN of the first-stage pre-amplification is sufficient to drive the third-stage latch stage without requiring a second amplification. The MOSFET M... 9P / M 9N It is mainly used to directly drive the output of the first stage to the third stage, which reduces the delay of the second stage and further reduces the comparison time when comparing large voltage differences.
[0107] The output of the third-stage comparator is connected to eight latch units, which generally have a large load and a long reset time. In order to further speed up the return of the P / N signals to the same initial voltage, a transmission gate structure is added between the P and N signals at the output of the third stage of the comparator circuit, which can alleviate the problem of incomplete reset of the third stage of the comparator.
[0108] When the rising edge of the comparator clock signal CLKBB arrives, the first and third stages of the comparator circuit start working first. The inverted signal CLK of CLKBB arrives later, causing the second stage to lag slightly behind the third stage. This means the output of the first stage might directly feed back to the third stage, potentially resulting in insufficient amplification of the comparator. To ensure that the second and third stages operate as synchronously as possible, a new MOSFET M is added. 12 M 13 A positive feedback structure is formed. When the FF node is pulled down by the CLRBB signal, the PP node is lifted, which speeds up the operation of the second stage. At the same time, the lifting of the PP node will in turn speed up the release process of the FF node. This can reduce the size of the T5 tube and reduce the load of the CLRBB signal.
[0109] When the voltages at the input terminals of the comparator are very close (the voltage difference is less than half the LSB voltage), the output of the third stage of the comparator circuit may not be able to generate two completely separated signals. In this case, the comparator output is insufficient to generate a set signal. To further separate the comparator output, this embodiment of the invention adds a latch stage after the three-stage comparator to form a four-stage comparator, further amplifying the small voltage difference of the third stage. The operation of the fourth stage is almost synchronous with the operation of the first three stages. It is turned on by the CK signal generated by the shift circuit. After being turned on, the voltage of the OP / ON signal begins to charge VDD at the same rate. As the comparison of the first three stages proceeds, the voltages of the P / N signals begin to separate, and then through the MOS transistor M... 14P / M 14N The voltage difference is transferred to OP / ON, in the MOSFET M 10P / M 10N MOSFET M 11P / M 11N Under the action of the formed positive feedback loop, the voltages of the OP / ON signals are rapidly separated to achieve latching of the comparison result. Here, the MOSFET M... 11P / M 11N A smaller size is sufficient to achieve positive feedback. The fourth stage reset is achieved through the MOSFET M. 13P / M 13N This is achieved by using a four-stage comparator. The first three stages are shared modules, and the eight latch units are sequentially used as the fourth stage. The comparison process for each bit is controlled by a shift circuit to manage the timing of the latch stages.
[0110] Shift circuit
[0111] The SAR control logic circuit in a SAR ADC typically includes N latch units to sequentially store the comparator outputs, and N shift circuits to control the N latch units to operate in the correct order and logic. The bit latch circuit is implemented as the fourth stage of the comparator circuit, and the shift circuit is as follows: Figure 4 As shown, QIN represents the input signal of the shift circuit; CLKBB is the comparison clock of the comparator circuit; QOUT is the output signal of the shift circuit; QB is the enable signal of the latch stage of the comparator circuit; and RES is the reset signal after quantization. The QIN of the shift circuit is the output QOUT of the previous stage shift circuit. The timing waveform of the quantization process is shown below. Figure 5As shown, its specific working principle is as follows: When the sampling signal CLKS level changes from high to low, the RES signal also changes from high to low, and the RESB changes from low to high. At this time, since the comparator circuit is still in the reset state, when the rising edge of the comparator clock arrives, the CK signal is pulled down to GND by MN1 and MN2, and the latch unit starts to work. The input of the comparator circuit is divided into large voltage difference (voltage difference greater than half of the LSB voltage) input and small voltage difference (voltage difference less than half of the LSB voltage) input. When the comparator circuit input is a large voltage difference input, the output of the third stage of the comparator circuit is two completely separated signals. In this way, the fourth stage of the comparator circuit acts as a signal storage function, saving the comparison result and setting it. When the comparator circuit input is a small voltage difference input, the output of the third stage of the comparator circuit is two incompletely separated signals. In this way, the latch stage will perform positive feedback latching of the small voltage difference, completing the further amplification of the voltage difference.
[0112] When the falling edge of the comparator clock arrives, node Q is charged to VDD by MP2 / MP3, node QB is discharged to GND by MN4, turning off its local latch unit. At the same time, QOUT is charged to VDD by MP5 / MP6, acting on the next latch unit, indicating the end of this comparison process.
[0113] Asynchronous clock generation circuit
[0114] Figure 1 The asynchronous clock in the text refers to the asynchronous clock generation circuit. This asynchronous clock generation circuit is as follows: Figure 6 As shown, P and N represent the output signals of the third stage of the comparator circuit; VBN is the signal that adjusts the comparator reset time, and VBP is the signal that adjusts the comparator comparison time; CLKS represents the sampling clock signal; and RDY represents the quantization end signal. The asynchronous clock generation circuit includes MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10; where,
[0115] The sources of MOSFETs MP1-MP7, MP9, and MP10 are connected in parallel and then connected to VDD; the drains of MOSFETs MP1-MP4 are connected in parallel to form a first node; the gates of MOSFETs MP5 and MN4 are connected in parallel to form a second node; the first node and the second node are connected through the CLKB signal.
[0116] The gate of MOS transistor MP1 is connected to the P signal;
[0117] The gate of MOS transistor MP2 is connected to the N signal;
[0118] The gate of MOS transistor MP3 is connected to the CLKD signal;
[0119] The gate of MOSFET MP4 is connected to node AA;
[0120] The drains of MOSFET MP5 and MOSFET MN4 are connected in parallel to form a third node, and the gates of MOSFET MP6 and MOSFET MN5 are connected in parallel to form a fourth node. The third node and the fourth node are connected through the CLKBB signal.
[0121] The drains of MOSFET MP6 and MOSFET MN5 are connected in parallel to form a fifth node, and the gates of MOSFET MP8 and MOSFET MN6 are connected in parallel to form a sixth node. The fifth node and the sixth node are connected through the CLK signal.
[0122] The drain of MOSFET MP7 is connected to the source of MOSFET MP8, and the gate of MOSFET MP7 is connected to the VBP signal.
[0123] The drains of MOSFET MP8 and MOSFET MN6 are connected in parallel to form a seventh node, and the gates of MOSFET MP9 and MOSFET MN8 are connected in parallel to form an eighth node. The seventh node is connected to the eighth node.
[0124] The drains of MOSFET MP9 and MOSFET MN8 are connected via the CLKD signal;
[0125] The gate of MOSFET MP10 is connected to the gate of MOSFET MN10 via the RDY signal, and the drain of MOSFET MP10 is connected to the source of MOSFET MP11.
[0126] The gate of MOSFET MP11 is connected to the gate of MOSFET MN9 via the CLKS signal, and the drains of MOSFET MP11, MOSFET MN9 and MOSFET MN10 are connected via the AA node.
[0127] The drain of MOS transistor MN1 is connected to the CLKB signal, the gate is connected to the AA node, and the source is connected to the drain of MOS transistors MN2 and MN3.
[0128] The gate of MOS transistor MN2 is connected to the CLKD signal, and the drains of MOS transistors MN2-MN5 and MOS transistors MN7-MN10 are connected in parallel and then connected to GND.
[0129] The gate of MOS transistor MN3 is connected to the CLK signal;
[0130] The drain of MOS transistor MN7 is connected to the source of MOS transistor MN6, and the gate of MOS transistor MN7 is connected to the VBN signal.
[0131] Asynchronous clock timing waveforms are as follows Figure 7 As shown, the asynchronous clock generation circuit uses the output of the third stage of the comparator circuit as a stimulus to generate the reset signal for the comparator circuit. The rising edge of the comparator clock in the asynchronous clock generation circuit is spontaneously generated based on the falling edge. Its specific operation is as follows: When the CLKS signal is high, the circuit samples. At this time, node AA is pulled down to ground by MOSFET MN9, the pull-down path of the CLKB signal is cut off, and the low level of node AA charges the CLKB signal to a high level through MOSFET MP4. The CLKBB signal is low, and the comparator circuit performs a reset operation. When the CLKS signal transitions from high to low, node AA is charged to high. Since the CLK and CLKD signals are also high, the pull-up path of the CLKB signal is disconnected and the pull-down path is opened. The CLKB signal is pulled down to low through MOSFETs MN1, MN2, and MN3. The CLRKB signal transitions from low to high, and the comparator circuit enters the comparison phase. Between the P / N signal changing from GND to a level with opposite polarity, the CLKB signal is charged to high by MOSFETs MP1 / MP2. Simultaneously, the CLRKB and CLK signals become low and high, respectively, and the comparator circuit enters the reset state. The CLK signal is followed by an adjustable delay inverter. MOSFET MN7, controlled by the VBN signal, can be used to adjust the duration of the reset phase, ensuring that the critical node voltage of the comparator has been fully reset before the next comparison begins. The CLK signal passes through an adjustable-delay inverter and a fixed-delay inverter to obtain the CLKD signal. The CLKD signal, like the CLK signal, changes from low to high. At this time, the P / N signal has been reset to VDD, the pull-up path of the CLKB signal is disconnected, and the pull-down path gradually becomes active. The CLKB signal begins to change from high to low, and then the CLRKB signal begins to flip from low to high. The comparator enters the next comparison state, and this process repeats until the least significant bit comparison is complete. After this, the comparison completion clock RDY signal changes from low to high, and node AA is switched to node MN. 10Pulling the CLKB signal down to GND locks it high, while the CLRKB and CLK signals remain low and high, respectively. This lock continues until the next sampling cycle ends, at which point the CLKS and RDY signals are both low, releasing the CLKB signal and allowing quantization of the new sampled voltage to begin. As the asynchronous clock principle dictates, this circuit structure uses fewer MOSFETs throughout the loop, making it suitable for high-speed comparator applications.
[0132] When the voltage difference between the input terminals of the comparator circuit is particularly small (less than half the LSB voltage), the output terminals P and N of the comparator circuit may drop together to near the common-mode voltage without significant separation. This indicates metastability. Since the P / N signals do not reach GND, the voltage of the CLKB signal cannot be effectively raised, and the comparator circuit cannot enter the reset state. This invention adds a pull-up transistor MP3 controlled by the CLKD signal at the CLKB signal. Even when metastability occurs and the CLKD signal is at a low level, the MP3 transistor can still pull the CLKB signal high, causing the comparator circuit to start resetting. Therefore, the asynchronous clock generation circuit effectively alleviates the comparator metastability problem.
[0133] In the first comparison, the capacitor corresponding to the DAC is at its maximum, thus requiring a longer DAC setup time. Therefore, the first reset time of the comparator must be sufficiently long to ensure the comparison voltage signal is fully established before the next comparison. The addition of the pull-down transistor MN7, controlled by the VBN signal, is to control the comparator's reset time. The VBN signal generated after the first comparison result is latched controls MN7, effectively extending the first comparator reset time. During the remaining seven resets, the VBN signal voltage remains constant.
[0134] When the sampling rate of the ADC decreases, in order to make the comparator work more stably, the levels VBN and VBP can be adjusted to change the comparison and reset time of the comparator to adapt to the requirements of different sampling rates.
[0135] Capacitor switch control logic circuit
[0136] Figure 1 The capacitor switch control logic in the figure represents the capacitor switch control logic circuit in the embodiment of the present invention. Compared with the traditional capacitor switch control logic, the capacitor switch control logic proposed in this invention has a greatly simplified circuit structure, consisting of only five MOS transistors in a single-ended configuration, such as... Figure 8As shown, PB and NB are the buffered signals of the latch stage output signal after passing through one stage of inverters; PX and NX are the signals of the latch stage output signal after passing through two stages of inverters; PH and PL represent the bottom plate voltage of the P-terminal capacitor; NH and NL represent the bottom plate voltage of the N-terminal capacitor. The capacitor switch control logic circuit includes MOSFETs M1, M2, M3, M4, and M5; where,
[0137] The source of the MOS transistor M1 is grounded, the gate is connected to the RES signal, and the drain is connected to the L terminal of the split bridge DAC capacitor array.
[0138] The source of the MOS transistor M2 is connected to VDD, the gate is connected to the L terminal of the split bridge DAC capacitor array, and the drain is connected to the H terminal of the split bridge DAC capacitor array.
[0139] The source of the MOS transistor M3 is grounded, its gate is connected to the H terminal of the split bridge DAC capacitor array, and its drain is connected to the L terminal of the split bridge DAC capacitor array.
[0140] The source of the MOS transistor M4 is grounded, the gate is connected to the PX / NX signal, and the drain is connected to the H terminal of the split bridge DAC capacitor array.
[0141] The source of the MOS transistor M5 is connected to VDD, the gate is connected to the PB / NB signal, and the drain is connected to the L terminal of the split bridge DAC capacitor array.
[0142] First, by eliminating the VCM reference level, the number of MOSFETs connected to the VCM level in the control logic is reduced, greatly simplifying the circuit structure. During the reset phase, RES is high, connecting the level at the L terminal of the capacitor array to GND through MOSFET M1. Then, MOSFET M2 turns on, connecting the level at the H terminal to VDD. Simultaneously, MOSFET M3 turns on, accelerating the discharge of MOSFET M1. MOSFETs M2 and M3 form positive feedback, speeding up the reset operation and increasing circuit stability. During the set phase, the arrival of X and B signals discharges and charges the corresponding H and L nodes, completing the 0 and 1 setting operations.
[0143] This invention employs a four-stage comparator structure (the first three stages are for preventing large voltage differences, and the fourth stage is for latching) to improve the comparator's comparison speed and alleviate metastability issues. Specifically, a positive feedback structure is added to the second stage to further accelerate the comparison speed. A transmission gate structure is added to the output of the third stage to improve the comparator's reset problem. A fourth latching stage is introduced to address the issue of incomplete separation of the third-stage output when comparing small voltage differences. The comparator reset signal is generated by using the third-stage output as an excitation, advancing the comparator's reset process. In the asynchronous clock generation circuit, a pull-up transistor MP3 controlled by the CLKD signal is added at the CLKB signal input, forcing the generation of the comparator reset signal when there is no significant separation in the third-stage output, thus mitigating the impact of comparator metastability on the comparator clock. A transistor MN7 controlled by the VBN signal is added to the asynchronous clock generation circuit to extend the reset time of the first comparator. The circuit structure of the capacitor switch control logic is simplified, and the positive feedback structure in the circuit improves the circuit's stability.
[0144] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0145] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator, characterized in that, include: The circuit includes a bootstrap switch, a split-bridge DAC capacitor array, a comparator circuit, a shift circuit, an asynchronous clock generation circuit, and a capacitor switch control logic circuit. The bootstrap switch is used to sample and hold the input signal to obtain a sampled voltage; The split-bridge DAC capacitor array is used to complete the successive approximation process of the voltage and generate the comparison voltage signal at the comparator input. The comparator circuit includes an improved multi-stage comparator and a latch stage, used to compare and latch the comparator input signals obtained after each successive approximation, and generate a set signal to control the split bridge DAC capacitor array based on the comparison result; MOS transistors that act as positive feedback are added in some stages of the multi-stage comparator and between some adjacent stages. The shift circuit is used to control the output of the memory comparator in the latch stage sequence; The asynchronous clock generation circuit is used to generate clock signals corresponding to each stage; the asynchronous clock generation circuit adjusts the comparison and reset time of the comparator circuit by using the VBP and VBN signals generated after the first comparison result of the comparator circuit is latched; wherein, when the separation degree of the final stage output of the multi-stage comparator does not reach a predetermined value, the asynchronous clock generation circuit forces the generation of the falling edge of the comparator clock. The capacitor switch control logic circuit is used to adjust the lower plate of the split bridge DAC capacitor array according to the set signal, thereby changing the magnitude of the comparison voltage signal.
2. The single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator according to claim 1, characterized in that, The first three stages of the comparator circuit are multiplexed structures. The fourth stage, the latch stage, contains eight parallel latch units used to sequentially store the comparator's output. The normal operation of the latch stage is controlled by eight shift circuits.
3. The single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator according to claim 2, characterized in that, The third stage of the comparator circuit incorporates a transmission gate structure between the P and N signals at its output.
4. The single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator according to claim 3, characterized in that, The fourth stage of the comparator circuit includes transistor T7, MOSFETs M10P, M11P, M12P, M13P, M14P, M10N, M11N, M12N, M13N, M14N, a first inverter, a second inverter, a third inverter, and a fourth inverter; wherein, The source of transistor T7 is connected to VDD, the gate is connected to the CK signal, and the drain is connected to the QD junction signal. The source of the MOS transistor M10P is connected to the QD signal, the gate is connected to the ON signal, and the drain is connected to the OP signal. The source of the MOS transistor M11P is grounded, the gate is connected to the ON signal, and the drain is connected to the OP signal. The source of the MOS transistor M12P is connected to the drain of the MOS transistor M14P, the gate is connected to the QB signal, and the drain is connected to the OP signal. The source of the MOSFET M13P is grounded, the gate is connected to the RES signal, and the drain is connected to the OP signal. The source of the MOS transistor M14P is grounded, the gate is connected to the P signal, and the drain is connected to the source of the MOS transistor M12P. The source of the MOS transistor M10N is connected to the QD signal, the gate is connected to the OP signal, and the drain is connected to the ON signal. The source of the MOS transistor M11N is grounded, the gate is connected to the OP signal, and the drain is connected to the ON signal. The source of the MOS transistor M12N is connected to the drain of the MOS transistor M14N, the gate is connected to the QB signal, and the drain is connected to the ON signal. The source of the MOSFET M13N is grounded, the gate is connected to the RES signal, and the drain is connected to the ON signal. The source of the MOS transistor M14N is grounded, the gate is connected to the N signal, and the drain is connected to the source of the MOS transistor M12N. The input terminal of the first inverter is connected to the PB signal, and the output terminal is connected to the PX signal; The input terminal of the second inverter is connected to the OP signal, and the output terminal is connected to the PB signal; The input terminal of the third inverter is connected to the ON signal, and the output terminal is connected to the NB signal; The input terminal of the fourth inverter is connected to the NB signal, and the output terminal is connected to the NX signal.
5. The single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator according to claim 4, characterized in that, The asynchronous clock generation circuit uses the output of the third stage of the comparator circuit as an excitation to generate a reset signal for the comparator circuit. The rising edge of the comparator clock in the asynchronous clock generation circuit is spontaneously generated based on the generation of the falling edge.
6. The single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator according to claim 4 or 5, characterized in that, When the separation degree of the final stage output of the multi-stage comparator does not reach a predetermined value, the asynchronous clock generation circuit forces the generation of the falling edge of the comparator clock. This process includes: The asynchronous clock generation circuit utilizes a pull-up transistor MP3 controlled by the CLKD signal at the input of the CLKB signal. When the separation degree of the third stage output of the comparator circuit does not reach a predetermined value, the low level of the CLKB signal is pulled high.
7. The single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator according to claim 6, characterized in that, In the asynchronous clock generation circuit, the CLK signal is connected to an inverter for adjusting the delay, and the MOS transistor MN7 controlled by the VBN signal is used to adjust the duration of the reset phase.
8. The single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator according to claim 7, characterized in that, The asynchronous clock generation circuit includes MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10; wherein, The sources of MOSFETs MP1-MP7, MP9, and MP10 are connected in parallel and then connected to VDD; the drains of MOSFETs MP1-MP4 are connected in parallel to form a first node; the gates of MOSFETs MP5 and MN4 are connected in parallel to form a second node; the first node and the second node are connected through the CLKB signal. The gate of MOS transistor MP1 is connected to the P signal; The gate of MOS transistor MP2 is connected to the N signal; The gate of MOS transistor MP3 is connected to the CLKD signal; The gate of MOSFET MP4 is connected to node AA; The drains of MOSFET MP5 and MOSFET MN4 are connected in parallel to form a third node, and the gates of MOSFET MP6 and MOSFET MN5 are connected in parallel to form a fourth node. The third node and the fourth node are connected through the CLKBB signal. The drains of MOSFET MP6 and MOSFET MN5 are connected in parallel to form a fifth node, and the gates of MOSFET MP8 and MOSFET MN6 are connected in parallel to form a sixth node. The fifth node and the sixth node are connected through the CLK signal. The drain of MOSFET MP7 is connected to the source of MOSFET MP8, and the gate of MOSFET MP7 is connected to the VBP signal. The drains of MOSFET MP8 and MOSFET MN6 are connected in parallel to form a seventh node, and the gates of MOSFET MP9 and MOSFET MN8 are connected in parallel to form an eighth node. The seventh node is connected to the eighth node. The drains of MOSFET MP9 and MOSFET MN8 are connected via the CLKD signal; The gate of MOSFET MP10 is connected to the gate of MOSFET MN10 via the RDY signal, and the drain of MOSFET MP10 is connected to the source of MOSFET MP11. The gate of MOSFET MP11 is connected to the gate of MOSFET MN9 via the CLKS signal, and the drains of MOSFET MP11, MOSFET MN9 and MOSFET MN10 are connected via the AA node. The drain of MOS transistor MN1 is connected to the CLKB signal, the gate is connected to the AA node, and the source is connected to the drain of MOS transistors MN2 and MN3. The gate of MOS transistor MN2 is connected to the CLKD signal, and the drains of MOS transistors MN2-MN5 and MOS transistors MN7-MN10 are connected in parallel and then connected to GND. The gate of MOS transistor MN3 is connected to the CLK signal; The drain of MOS transistor MN7 is connected to the source of MOS transistor MN6, and the gate of MOS transistor MN7 is connected to the VBN signal.
9. The single-channel ultra-high-speed analog-to-digital converter based on a multi-stage comparator according to claim 8, characterized in that, The capacitor switch control logic circuit includes MOSFETs M1, M2, M3, M4, and M5; wherein, The source of the MOS transistor M1 is grounded, the gate is connected to the RES signal, and the drain is connected to the L terminal of the split bridge DAC capacitor array. The source of the MOS transistor M2 is connected to VDD, the gate is connected to the L terminal of the split bridge DAC capacitor array, and the drain is connected to the H terminal of the split bridge DAC capacitor array. The source of the MOS transistor M3 is grounded, its gate is connected to the H terminal of the split bridge DAC capacitor array, and its drain is connected to the L terminal of the split bridge DAC capacitor array. The source of the MOS transistor M4 is grounded, the gate is connected to the PX / NX signal, and the drain is connected to the H terminal of the split bridge DAC capacitor array. The source of the MOS transistor M5 is connected to VDD, the gate is connected to the PB / NB signal, and the drain is connected to the L terminal of the split bridge DAC capacitor array.