Embedded component circuit board and method of making same

Abstract

The application provides an embedded component circuit board and a manufacturing method thereof. The circuit board comprises a substrate layer, a first conductive circuit pattern, a second conductive circuit pattern, an electronic component, an intermediate dielectric layer, a first outer dielectric layer, a second outer dielectric layer, a first connecting column, a second connecting column, a bump, a third conductive circuit pattern and a fourth conductive circuit pattern.

Description

Technical Field

[0001] This application relates to the field of circuit board manufacturing technology, and in particular to a circuit board with embedded components and a method for manufacturing the same. Background Technology

[0002] In existing embedded component circuit boards, the electrical connection between electronic components and the circuit layers is mostly achieved by laser drilling above the component's pads to create blind vias, followed by electroplating. However, laser drilling is difficult to control precisely, and the component pads are very small. This makes it easy for the drilling position to deviate. Any misalignment directly affects the reliability of the embedded component circuit board. Summary of the Invention

[0003] In view of this, it is necessary to provide a circuit board with embedded components and a method for manufacturing the same, which can avoid laser drilling above the pads of electronic components and improve the reliability of the circuit board with embedded components.

[0004] This application provides a circuit board with embedded components, including:

[0005] A substrate layer, the substrate layer including a first surface and a second surface, and the substrate layer further having through holes that penetrate the substrate layer;

[0006] A first conductive circuit pattern is disposed on the first surface;

[0007] A second conductive circuit pattern is disposed on the second surface;

[0008] An electronic component is disposed within the through hole. The electronic component includes a front side and a back side, and the front side of the electronic component is provided with a solder pad.

[0009] An intermediate dielectric layer is disposed on the first surface of the substrate layer and covers the electronic component and the first conductive circuit pattern, such that the pads are exposed in the intermediate dielectric layer;

[0010] A first outer dielectric layer is disposed on the second surface of the substrate layer and covers the second conductive circuit pattern;

[0011] The second outer dielectric layer is disposed on the surface of the intermediate dielectric layer away from the substrate layer;

[0012] A first connecting post is disposed on a portion of the surface of the second conductive line pattern and penetrates the first outer dielectric layer;

[0013] The second connecting post is disposed on a portion of the surface of the first conductive line pattern and penetrates the second outer dielectric layer and a portion of the intermediate dielectric layer;

[0014] The bump is disposed on the surface of the pad and exposed in the second outer dielectric layer;

[0015] A third conductive circuit pattern is disposed on the surface of the first outer dielectric layer away from the substrate layer, and at least a portion of the third conductive circuit pattern is electrically connected to the second conductive circuit pattern through the first connecting post; and

[0016] A fourth conductive circuit pattern is disposed on the surface of the second outer dielectric layer away from the intermediate dielectric layer. At least a portion of the fourth conductive circuit pattern is electrically connected to the first conductive circuit pattern through the second connecting post or electrically connected to the pad through the bump.

[0017] Optionally, the intermediate medium layer, the first outer medium layer, and the second outer medium layer are all made of Ajinomoto film.

[0018] Optionally, the thickness of the electronic component is not less than the sum of the thicknesses of the substrate layer, the first conductive circuit pattern, and the second conductive circuit pattern.

[0019] This application also provides a method for manufacturing a circuit board with embedded components, including:

[0020] A metal substrate is provided, the metal substrate comprising a substrate layer and two first copper foil layers, the two first copper foil layers being respectively disposed on a first surface and a second surface of the substrate layer;

[0021] The two first copper foil layers are respectively fabricated into a first conductive circuit pattern on the first surface and a second conductive pattern on the second surface;

[0022] A through-hole is formed in the substrate layer;

[0023] Cover the second surface with tape;

[0024] An electronic component is placed in the through hole. The electronic component has a front side and a back side. The front side of the electronic component is provided with a pad, and the side of the electronic component with the pad is positioned away from the tape.

[0025] An intermediate dielectric layer is laminated onto the first surface, such that the electronic component is embedded in the intermediate dielectric layer and the pads are exposed in the intermediate dielectric layer;

[0026] Remove the tape;

[0027] A bump is provided on the surface of the pad;

[0028] A first outer dielectric layer is pressed onto the second surface, so that the second conductive circuit pattern is completely covered by the first outer dielectric layer;

[0029] A second outer dielectric layer is laminated onto the surface of the intermediate dielectric layer on the side near the pad, so that the bump is completely covered by the second outer dielectric layer;

[0030] The second outer dielectric layer is ground to expose the surface of the bumps away from the pads;

[0031] A first opening is formed in the first outer dielectric layer, and a portion of the second conductive line pattern is exposed from the first opening;

[0032] A second opening is formed in the second outer dielectric layer and a portion of the intermediate dielectric layer, and a portion of the first conductive line pattern is exposed from the second opening;

[0033] Electroplating is performed on the surfaces of the first outer dielectric layer and the second outer dielectric layer, inside the first opening and inside the second opening, and etching is performed after electroplating to form a third conductive circuit pattern, a fourth conductive circuit pattern, a first connecting post, and a second connecting post.

[0034] The third conductive circuit pattern is electrically connected to the corresponding second conductive circuit pattern through the first connecting post in the first opening, the fourth conductive circuit pattern is electrically connected to the corresponding first conductive circuit pattern through the second connecting post in the second opening, and a portion of the fourth conductive circuit pattern is electrically connected to the pad through the bump, forming the embedded component circuit board.

[0035] Optionally, the bumps are made by the following method:

[0036] Liquid photoresist is coated onto the surface of the pads;

[0037] After placing a photomask on the surface of the liquid photoresist, the surface of the liquid photoresist is exposed and developed to form a groove;

[0038] Electroplating is performed within the groove to form the protrusion;

[0039] Remove the remaining liquid photoresist.

[0040] Optionally, before pressing the intermediate dielectric layer onto the first surface, the method further includes:

[0041] Plasma cleaning is performed on the first surface, the first conductive circuit pattern, and the front side of the electronic component.

[0042] Before the first outer dielectric layer is pressed onto the second surface, the method further includes:

[0043] Plasma cleaning is performed on the second surface, the second conductive circuit pattern, and the back of the electronic component.

[0044] Optionally, before placing the electronic component within the through-hole, the method further includes:

[0045] The first surface, the second surface, the surface of the first conductive circuit pattern, and the surface of the second conductive circuit pattern are pre-treated to enhance surface roughness.

[0046] Optionally, the through hole is created by laser drilling.

[0047] Optionally, the first opening and the second opening are formed by laser drilling.

[0048] Optionally, the first opening is formed by locally etching after applying a resist dry film to the surface of the first outer dielectric layer away from the substrate layer, and the second opening is formed by locally etching after applying a resist dry film to the surface of the second outer dielectric layer away from the intermediate dielectric layer.

[0049] Compared to existing technologies, this application has at least the following advantages: by setting bumps on the surface of the pads of the electronic component, the fourth conductive line pattern is electrically connected to the electronic component through drilling and copper plating, thus overcoming the influence of alignment accuracy during drilling of the electronic component. This allows the electronic component to be effectively electrically connected to the fourth conductive line, improving the reliability of the embedded component circuit board. Attached Figure Description

[0050] Figure 1 A schematic diagram of a metal substrate provided for an embodiment of this application.

[0051] Figure 2 A schematic diagram illustrating the fabrication of a first conductive circuit pattern and a second conductive circuit pattern, provided for embodiments of this application.

[0052] Figure 3 A schematic diagram of an intermediate provided for an embodiment of this application.

[0053] Figure 4 A schematic diagram of the covering tape provided in an embodiment of this application.

[0054] Figure 5 This is a schematic diagram of the placement of electronic components provided for an embodiment of this application.

[0055] Figure 6 This is a schematic diagram of plasma cleaning provided for an embodiment of this application.

[0056] Figure 7 A schematic diagram of the compression intermediate medium layer provided in the embodiments of this application.

[0057] Figure 8 This is a schematic diagram illustrating the removal of the adhesive tape as provided in an embodiment of this application.

[0058] Figure 9 This is another schematic diagram of plasma cleaning provided for an embodiment of this application.

[0059] Figure 10 A schematic diagram illustrating the fabrication of raised dots provided for an embodiment of this application.

[0060] Figures 11A to 11F A schematic diagram illustrating the detailed steps of creating raised dots as provided in the embodiments of this application.

[0061] Figure 12 This is a schematic diagram of the second outer medium layer provided in an embodiment of this application.

[0062] Figure 13 This is a schematic diagram of grinding the second outer dielectric layer as provided in an embodiment of this application.

[0063] Figure 14 This is a schematic diagram illustrating the formation of the first opening and the second opening, provided for an embodiment of this application.

[0064] Figure 15 This is a schematic diagram of an embedded component circuit board provided for an embodiment of this application.

[0065] Figure 16 A schematic diagram of the first outer dielectric layer and the second outer dielectric layer provided for embodiments of this application.

[0066] Figure 17 This is a schematic diagram illustrating the formation of a first cylindrical groove, a second cylindrical groove, and a third cylindrical groove, provided for an embodiment of this application.

[0067] Figure 18 Another schematic diagram of the embedded component circuit board provided for an embodiment of this application.

[0068] Figure 19 This is a schematic diagram of the second outer medium layer provided in an embodiment of this application.

[0069] Figure 20 This is a schematic diagram illustrating the formation of the first columnar groove and the second columnar groove, provided for an embodiment of this application.

[0070] Figure 21 A schematic diagram of the lamination of the first outer dielectric layer and the fabrication of the fourth conductive circuit pattern, the second connecting post and the protrusion provided for the embodiments of this application.

[0071] Figure 22 A schematic diagram of the compression intermediate and the third outer medium layer provided in the embodiments of this application.

[0072] Figure 23 This is a schematic diagram of placing electronic components and pressing a fourth outer dielectric layer according to an embodiment of this application.

[0073] Figure 24 A schematic diagram of a circuit board provided for an embodiment of this application.

[0074] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application.

[0075] Explanation of main component symbols

[0076] Intermediate 100

[0077] Embedded component circuit board 200, 300

[0078] Metal substrate 1

[0079] Substrate layer 10

[0080] First surface 101

[0081] Second surface 102

[0082] Metal foil layer 11

[0083] First conductive circuit diagram 111

[0084] Second conductive circuit diagram 112

[0085] Through hole 12

[0086] 20 tapes

[0087] Electronic Components 30

[0088] Front 301

[0089] Back 302

[0090] Pad 31

[0091] upper surface 311

[0092] 32 bumps

[0093] Liquid photoresist 33

[0094] Groove 34

[0095] Intermediate layer 40

[0096] First outer dielectric layer 50

[0097] First opening 51

[0098] Third columnar groove 52

[0099] Second outer dielectric layer 60

[0100] Second opening 61

[0101] First cylindrical groove 62

[0102] Second cylindrical groove 63

[0103] Third conductive circuit diagram 71

[0104] First connecting post 711

[0105] Fourth conductive circuit diagram 72

[0106] Second connecting post 721

[0107] Third outer dielectric layer 80

[0108] Fourth outer dielectric layer 81

[0109] Fifth conductive circuit diagram 82 Detailed Implementation

[0110] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0111] Please see Figures 1 to 15 The first embodiment of this application provides an embedded component circuit board 200 (see reference). Figure 15 The method for making ) includes the following steps.

[0112] First step, please refer to Figure 1 A metal substrate 1 is provided.

[0113] The metal substrate 1 includes a substrate layer 10 and two metal foil layers 11. The substrate layer 10 includes a first surface 101 and a second surface 102 opposite to each other. The two metal foil layers 11 are respectively disposed on the first surface 101 and the second surface 102.

[0114] In this embodiment, preferably, the substrate layer 10 may be polypropylene (PP). The metal foil layer 11 may be, but is not limited to, copper foil.

[0115] Step 2, please refer to Figure 2 The metal foil layer 11 is fabricated into a first conductive line pattern 111 located on the first surface 101 and a second conductive line pattern 112 located on the second surface 102.

[0116] Specifically, in the second step, a photosensitive film can be covered on the surface of the metal foil layer 11, and then the photosensitive film is exposed and developed, and the metal foil layer 11 is etched to form the first conductive circuit pattern 111 and the second conductive circuit pattern 112.

[0117] Step 3, please refer to Figure 3 A through-hole 12 is formed in the gap region between the first conductive line pattern 111 and the second conductive line pattern 112 in a direction perpendicular to the substrate layer 10, and the through-hole 12 penetrates the substrate layer 10. In this way, an intermediate body 100 is formed.

[0118] In this embodiment, the through hole 12 is formed in the gap area between the first conductive circuit pattern 111 and the second conductive circuit pattern 112 using a laser cutting method. After forming the through hole 12, the cut surface of the substrate layer 10 (i.e., the inner wall of the through hole 12) is cleaned.

[0119] For the fourth step, please refer to [link / reference]. Figure 4 Adhesive tape 20 is applied to the second surface 102 (e.g., the second conductive line pattern 112).

[0120] In some embodiments, prior to the fourth step, the manufacturing method further includes:

[0121] The surfaces of the first surface 101, the second surface 102, the first conductive circuit pattern 111, and the second conductive circuit pattern 112 are pre-treated, for example, by polishing to increase surface roughness, so that they can be more tightly bonded to the object to be pressed during the subsequent pressing process.

[0122] Step 5, please refer to Figure 5 Electronic components 30 are placed in the through-hole 12 by a pick-and-place machine.

[0123] The electronic component 30 includes a front side 301 and a back side 302, with the front side 301 and the back side 302 being disposed opposite to each other, and a solder pad 31 being disposed on the front side 301.

[0124] In this embodiment, when setting the electronic component 30, the front side 301 faces upward, that is, in a direction away from the tape 20, so that the back side 302 directly contacts the tape 20.

[0125] In this embodiment and in the subsequent embodiments 2 and 3, the electronic component 30 may be, for example, a chip.

[0126] Step 6, please refer to Figure 6 The first surface 101, the first conductive line pattern 111, the front side 301, and the pad 31 are plasma cleaned using a plasma machine.

[0127] Step 7, please refer to Figure 7 , press an intermediate dielectric layer 40 onto the first surface 101 such that the electronic component 30 is embedded in the intermediate dielectric layer 40, and the upper surface 311 of the pad 31 (i.e., the surface away from the front surface 301) is exposed from the intermediate dielectric layer 40.

[0128] In this embodiment, preferably, the intermediate dielectric layer 40 may be Aginomoto Build-up Film (ABF).

[0129] Step 8, please refer to Figure 8 to remove the adhesive tape 20.

[0130] Step 9, please refer to Figure 9 to perform plasma cleaning on the second surface 102, the second conductive circuit pattern 112 and the back surface 302 by a plasma machine.

[0131] Step 10, please refer to Figure 10 to provide bumps 32 on the upper surface 311 of the pad 31, such that the bumps 32 are electrically connected to the electronic component 30 via the pad 31.

[0132] In addition, Step 10 further includes pressing a first outer dielectric layer 50 onto the second surface 102 such that the portion close to the second conductive circuit pattern 112 is completely covered by the first outer dielectric layer 50.

[0133] In this embodiment, preferably, the first outer dielectric layer 50 may be Aginomoto Build-up Film (ABF).

[0134] Please also refer to Figures 11A to 11F , which shows the detailed manufacturing steps of forming the bumps 32 in Step 10.

[0135] Please refer to Figure 11A and Figure 11B , firstly coat liquid photoresist 33 on the surface of the pad 31 (see Figure 11B ).

[0136] See Figure 11C and Figure 11D , next, after arranging a photomask (not shown) on the surface of the liquid photoresist 33, expose and develop the surface of the liquid photoresist 33 to form a groove 34 (see Figure 11D ).

[0137] See Figure 11E , then perform plating in the groove 34 to form the bump 32. The material of the bump 32 is, for example, copper.

[0138] Reference Figure 11F Finally, the remaining liquid photoresist 33 is removed.

[0139] In the eleventh step, refer to Figure 12 a second outer dielectric layer 60 is pressed on the surface of the intermediate dielectric layer 40 on a side close to the pad 31, so that the bump 32 is completely covered by the second outer dielectric layer 60.

[0140] In this embodiment, preferably, the second outer dielectric layer 60 may be Aginomoto Build-up Film (ABF).

[0141] In the twelfth step, refer to Figure 13 the second outer dielectric layer 60 is grinded to expose the upper surface of the bump 32 (that is, the surface away from the pad 31).

[0142] In this embodiment, the grinding adopts a Chemical Mechanical Polishing (CMP) method.

[0143] In the thirteenth step, refer to Figure 14 drilling is performed on the surface of the first outer dielectric layer 50 away from the intermediate dielectric layer 40 to form a first opening 51, so that part of the second conductive circuit pattern 112 is exposed from the first opening 51.

[0144] In addition, the thirteenth step further includes drilling on the surface of the second outer dielectric layer 60 away from the intermediate dielectric layer 40 and passing through part of the intermediate dielectric layer 40 to form a second opening 61, so that part of the first conductive circuit pattern 111 is exposed from the second opening 61.

[0145] In the fourteenth step, refer also to Figure 15 plating is performed on the surfaces of the first outer dielectric layer 50 and the second outer dielectric layer 60, inside the first opening 51 and inside the second opening 61, and etching is performed after plating to form a third conductive circuit pattern 71, a fourth conductive circuit pattern 72, a first connection post 711 and a second connection post 721, wherein the first connection post 711 is formed in the first opening 51, and the second connection post 721 is formed in the second opening 61.

[0146] Specifically, in step fourteen, the third conductive pattern 71 near the first outer dielectric layer 50 is electrically connected to the corresponding second conductive pattern 112 via the first connecting post 711 within the first opening 51. The fourth conductive pattern 72 is electrically connected to the first conductive pattern 111 via the second connecting post 721 within the second opening 61. A portion of the fourth conductive pattern 72 is electrically connected to the pad 31 via the bump 32. Thus, the embedded component circuit board 200 is formed.

[0147] It is understood that in this embodiment, before step fourteen, that is, before forming the embedded component circuit board 200, the method of manufacturing the embedded component circuit board 200 may further press other dielectric layers (not shown) onto the third conductive line pattern 71 or the fourth conductive line pattern 72, and drill holes in the corresponding dielectric layers, and form the corresponding conductive line patterns (not shown) after electroplating and etching.

[0148] In the first embodiment of this application, by creating bumps 32 on the upper surface 311 of the pad 31, an electrical connection is established between the fourth conductive line pattern 72 and the electronic component 30. This allows for precise alignment, and the bumps 32 will not easily deviate from the pad 31 when the embedded component circuit board 200 expands or contracts. This improves the reliability of the embedded component circuit board 200.

[0149] Please refer to the following: Figures 16 to 18 The second embodiment of this application provides another method for manufacturing an embedded component circuit board 200. This second embodiment is identical to steps one through eight of the first embodiment, differing only in the steps after step eight. Therefore, in the second embodiment, only steps after step eight are specifically described. To distinguish steps nine through fourteen in the first embodiment, the description in the second embodiment begins with step fifteen. That is, in the second embodiment, the method for manufacturing the embedded component circuit board 200 includes at least steps one through eight and steps fifteen through seventeen.

[0150] Step 15, please refer to Figure 16 A second outer dielectric layer 60 is pressed onto the surface of the intermediate dielectric layer 40 near the first surface 101, so that the upper surface 311 of the pad 31 is completely covered by the second outer dielectric layer 60.

[0151] Additionally, in the fifteenth step, a first outer dielectric layer 50 is laminated onto the surface of the second conductive circuit pattern 112, such that the second surface 102, the second conductive circuit pattern 112, the side of the intermediate dielectric layer 40 away from the pad 31, and the back surface 302 of the electronic component 30 are all covered by the first outer dielectric layer 50.

[0152] Step sixteen, please refer to Figure 17 After applying a resist dry film to the surface of the second outer dielectric layer 60 away from the intermediate dielectric layer 40, local etching is performed to form the first cylindrical groove 62 and the second cylindrical groove 63.

[0153] In the sixteenth step, a portion of the first conductive circuit pattern 111 is exposed in the first cylindrical groove 62, and a portion of the solder pad 31 is exposed in the second cylindrical groove 63.

[0154] In the sixteenth step, a resist dry film is applied to the surface of the first outer dielectric layer 50 on the side away from the intermediate dielectric layer 40, and then local etching is performed to form a third cylindrical groove 52, in which a portion of the second conductive circuit pattern 112 is exposed.

[0155] Step seventeen, please refer to the following: Figure 18 Electroplating is performed on the surface of the second outer dielectric layer 60, inside the first cylindrical groove 62, and inside the second cylindrical groove 63, and etching is performed after electroplating to form the third conductive circuit pattern 71, the first connecting post 711, the fourth conductive circuit pattern 72, the second connecting post 721, and the bump 32.

[0156] In step seventeen, the third conductive circuit pattern 71 is electrically connected to the corresponding second conductive circuit pattern 112 via the first connecting post 711 within the third cylindrical groove 52. The fourth conductive circuit pattern 72 is electrically connected to the corresponding first conductive circuit pattern 111 via the second connecting post 721 within the first cylindrical groove 62, and electrically connected to the corresponding pad 31 via the bump 32 within the second cylindrical groove 63. Thus, the embedded component circuit board 200 is formed.

[0157] Please refer to the following: Figures 19 to 22 The third embodiment of this application provides another method for manufacturing an embedded component circuit board 300. This third embodiment is identical to steps one through eight of the first embodiment, differing only in the steps after step eight. Therefore, in the third embodiment, only steps after step eight are specifically described. To distinguish steps nine through fourteen in the first embodiment and steps fifteen through seventeen in the second embodiment, the description in the third embodiment begins with step eighteen. That is, in the third embodiment, the method for manufacturing the embedded component circuit board 300 includes at least steps one through eight and steps eighteen through twenty-three.

[0158] Step 18, please refer to Figure 19 A second outer dielectric layer 60 is pressed onto the surface of the intermediate dielectric layer 40 near the first surface 101, so that the upper surface 311 of the pad 31 is completely covered by the second outer dielectric layer 60.

[0159] Step nineteen, please refer to Figure 20 After attaching a resist dry film to the surface of the second outer dielectric layer 60 away from the intermediate dielectric layer 40, local etching is performed to form the first cylindrical groove 62 and the second cylindrical groove 63.

[0160] In the nineteenth step, a portion of the first conductive circuit pattern 111 is exposed in the first cylindrical groove 62, and a portion of the solder pad 31 is exposed in the second cylindrical groove 63.

[0161] Step 20, please refer to Figure 21 A first outer dielectric layer 50 is pressed onto the surface of the second conductive circuit pattern 112, so that the second conductive circuit pattern 112 is completely covered by the first outer dielectric layer 50.

[0162] Additionally, in the twentieth step, the process includes covering the side of the first outer dielectric layer 50 away from the intermediate dielectric layer 40 with an anti-plating dry film (not shown) and electroplating the surface of the second outer dielectric layer 60, the first cylindrical groove 62, and the second cylindrical groove 63 to form a fourth conductive circuit pattern 72, a second connecting post 721, and a bump 32.

[0163] Specifically, the fourth conductive pattern 72 near the second outer dielectric layer 60 is electrically connected to the corresponding first conductive pattern 111 through the second connecting post 721 in the first cylindrical groove 62, and electrically connected to the corresponding pad 31 through the bump 32 in the second cylindrical groove 63. The resist dry film is then removed.

[0164] Step 21, please refer to Figure 22 An intermediate body 100 (see reference) is sequentially pressed onto the surface of the first outer dielectric layer 50 away from the intermediate dielectric layer 40. Figure 3 The first outer dielectric layer 50 and the third outer dielectric layer 80 are disposed between the first outer dielectric layer 50 and the intermediate body 100. A through-hole 12 is provided within the intermediate body 100.

[0165] Step 22, please refer to Figure 23 Another electronic component 30 is placed within the through-hole 12 of the intermediate body 100, such that the pads 31 of the electronic component 30 face away from the intermediate dielectric layer 40. A fourth outer dielectric layer 81 is then pressed together, covering the electronic component 30.

[0166] Step 23, please refer to Figure 24 After applying a resist dry film to the side of the fourth outer dielectric layer 81 away from the third outer dielectric layer 80, local etching is performed to form corresponding cylindrical grooves. Electroplating is then performed, followed by etching to form the fifth conductive line pattern 82. Thus, the embedded component circuit board 300 is obtained.

[0167] It is understood that before the embedded component circuit board 300 is formed, i.e. before the 23rd step, the method of manufacturing the embedded component circuit board 300 may continue to press other dielectric layers (not shown) onto the fifth conductive line pattern 82, and drill holes in the corresponding dielectric layers, and form the corresponding conductive line pattern (not shown) after electroplating and etching.

[0168] It is understood that in the third embodiment of this application, by first fabricating the fourth conductive circuit pattern 72 on one side (e.g., the first surface 101), and then laminating other dielectric layers (e.g., the fourth outer dielectric layer 81) and components (e.g., the intermediate body 100) onto the other side (e.g., the second surface 102), the embedded component circuit board 300 is layered. It is understood that this layering method in the third embodiment can also be applied to the first and second embodiments described above.

[0169] Please refer to it again. Figure 15 This application also provides an embedded component circuit board 200, which is manufactured using the manufacturing method of the embedded component circuit board 200 in Embodiment 1 or Embodiment 2.

[0170] Specifically, the embedded component circuit board 200 includes a substrate layer 10, a first conductive line pattern 111, a second conductive line pattern 112, an electronic component 30, an intermediate dielectric layer 40, a first outer dielectric layer 50, a second outer dielectric layer 60, a first connecting post 711, a second connecting post 721, a bump 32, a third conductive line pattern 71, and a fourth conductive line pattern 72.

[0171] The substrate layer 10 includes a first surface 101 and a second surface 102. The first conductive circuit pattern 111 is disposed on the first surface 101, and the second conductive circuit pattern 112 is disposed on the second surface 102.

[0172] The substrate layer 10 includes a through-hole 12 that penetrates the substrate layer 10. The electronic component 30 is disposed within the through-hole 12. The electronic component 30 has a pad 31, with the side having the pad 31 facing outwards from the through-hole 12. The thickness of the electronic component 30 is not less than the sum of the thicknesses of the substrate layer 10, the first conductive circuit pattern 111, and the second conductive circuit pattern 112.

[0173] The intermediate dielectric layer 40 is disposed on the first surface 101 of the substrate layer 10 and covers the electronic component 30 and the first conductive circuit pattern 111. The upper surface 311 of the pad 31 exposes the intermediate dielectric layer 40.

[0174] The first outer dielectric layer 50 is disposed on the second surface 102 of the substrate layer 10 and covers the second conductive circuit pattern 112. The second outer dielectric layer 60 is disposed on the surface of the intermediate dielectric layer 40 away from the substrate layer 10.

[0175] The first connecting post 711 is disposed on a portion of the surface of the second conductive circuit pattern 112 and penetrates the first outer dielectric layer 50. The second connecting post 721 is disposed on a portion of the surface of the first conductive circuit pattern 111 and penetrates the second outer dielectric layer 60 and a portion of the intermediate dielectric layer 40. The bump 32 is disposed on the surface of the pad 31 and exposed in the second outer dielectric layer 60.

[0176] The third conductive circuit pattern 71 is disposed on the surface of the first outer dielectric layer 50 away from the substrate layer 10, and at least a portion of the third conductive circuit pattern 71 is electrically connected to the second conductive circuit pattern 112 through the first connecting post 711. The fourth conductive circuit pattern 72 is disposed on the surface of the second outer dielectric layer 60 away from the intermediate dielectric layer 40, and at least a portion of the fourth conductive circuit pattern is electrically connected to the first conductive circuit pattern 111 through the second connecting post 721 or electrically connected to the pad 31 through the bump 32.

[0177] This application avoids the need for drilling to electrically connect the fourth conductive line pattern 72 to the electronic component 30 by providing bumps 32 on the surface of the pad 31 of the electronic component 30, thus overcoming the impact of alignment accuracy issues during drilling of the electronic component 30. This allows the electronic component 30 to be effectively electrically connected to the fourth conductive line pattern 72, improving the reliability of the embedded component circuit board 200.

[0178] Those skilled in the art should recognize that the above embodiments are only used to illustrate this application and are not intended to limit this application. As long as they are within the essential spirit and scope of this application, appropriate changes and variations made to the above embodiments should fall within the scope of protection claimed in this application.

Claims

1. A circuit board with embedded components, characterized in that, include: A substrate layer, the substrate layer including a first surface and a second surface, and the substrate layer further having through holes that penetrate the substrate layer; A first conductive circuit pattern is disposed on the first surface; A second conductive circuit pattern is disposed on the second surface; An electronic component is disposed within the through hole. The electronic component includes a front side and a back side, and the front side of the electronic component is provided with a solder pad. An intermediate dielectric layer is disposed on the first surface of the substrate layer and covers the electronic component and the first conductive circuit pattern, such that the pads are exposed in the intermediate dielectric layer; A first outer dielectric layer is disposed on the second surface of the substrate layer and covers the second conductive circuit pattern; The second outer dielectric layer is disposed on the surface of the intermediate dielectric layer away from the substrate layer; A first connecting post is disposed on a portion of the surface of the second conductive circuit pattern and penetrates the first outer dielectric layer; The second connecting post is disposed on a portion of the surface of the first conductive line pattern and penetrates the second outer dielectric layer and a portion of the intermediate dielectric layer; The bump is disposed on the surface of the pad and exposed in the second outer dielectric layer; A third conductive circuit pattern is disposed on the surface of the first outer dielectric layer away from the substrate layer, and at least a portion of the third conductive circuit pattern is electrically connected to the second conductive circuit pattern through the first connecting post. and A fourth conductive circuit pattern is disposed on the surface of the second outer dielectric layer away from the intermediate dielectric layer. At least a portion of the fourth conductive circuit pattern is electrically connected to the first conductive circuit pattern through the second connecting post or electrically connected to the pad through the bump.

2. The embedded component circuit board as described in claim 1, characterized in that, The intermediate medium layer, the first outer medium layer, and the second outer medium layer are all made of Ajinomoto film.

3. The embedded component circuit board as described in claim 1, characterized in that, The thickness of the electronic component is not less than the sum of the thicknesses of the substrate layer, the first conductive circuit pattern, and the second conductive circuit pattern.

4. A method for manufacturing a circuit board with embedded components, characterized in that, include: A metal substrate is provided, the metal substrate comprising a substrate layer and two first copper foil layers, the two first copper foil layers being respectively disposed on a first surface and a second surface of the substrate layer; The two first copper foil layers are respectively fabricated into a first conductive circuit pattern on the first surface and a second conductive circuit pattern on the second surface. A through-hole is formed in the substrate layer; Cover the second surface with tape; An electronic component is placed in the through hole. The electronic component has a front side and a back side. The front side of the electronic component is provided with a pad, and the side of the electronic component with the pad is positioned away from the tape. An intermediate dielectric layer is laminated onto the first surface, such that the electronic component is embedded in the intermediate dielectric layer and the pads are exposed in the intermediate dielectric layer; Remove the tape; A bump is provided on the surface of the pad; A first outer dielectric layer is pressed onto the second surface, so that the second conductive circuit pattern is completely covered by the first outer dielectric layer; A second outer dielectric layer is laminated onto the surface of the intermediate dielectric layer on the side closest to the pad, such that the bump is completely covered by the second outer dielectric layer; The second outer dielectric layer is ground to expose the surface of the bumps away from the pads; A first opening is formed in the first outer dielectric layer, and a portion of the second conductive line pattern is exposed from the first opening; A second opening is formed in the second outer dielectric layer and a portion of the intermediate dielectric layer, and a portion of the first conductive line pattern is exposed from the second opening; Electroplating is performed on the surfaces of the first outer dielectric layer and the second outer dielectric layer, inside the first opening and inside the second opening, and etching is performed after electroplating to form a third conductive circuit pattern, a fourth conductive circuit pattern, a first connecting post, and a second connecting post. The third conductive circuit pattern is electrically connected to the corresponding second conductive circuit pattern through the first connecting post in the first opening, the fourth conductive circuit pattern is electrically connected to the corresponding first conductive circuit pattern through the second connecting post in the second opening, and a portion of the fourth conductive circuit pattern is electrically connected to the pad through the bump, forming the embedded component circuit board.

5. The method for manufacturing an embedded component circuit board as described in claim 4, characterized in that, The bumps are created by the following method: Liquid photoresist is coated onto the surface of the pads; After placing a photomask on the surface of the liquid photoresist, the surface of the liquid photoresist is exposed and developed to form a groove; Electroplating is performed within the groove to form the protrusion; Remove the remaining liquid photoresist.

6. The method for manufacturing an embedded component circuit board as described in claim 4, characterized in that, Before the intermediate dielectric layer is laminated onto the first surface, the method further includes: performing plasma cleaning on the first surface, the first conductive circuit pattern, and the front side of the electronic component; Before laminating the first outer dielectric layer onto the second surface, the method further includes: performing plasma cleaning on the second surface, the second conductive circuit pattern, and the back surface of the electronic component.

7. The method for manufacturing an embedded component circuit board as described in claim 4, characterized in that, Before placing the electronic component in the through hole, the method further includes: pre-treating the first surface, the second surface, the surface of the first conductive circuit pattern, and the surface of the second conductive circuit pattern to enhance surface roughness.

8. The method for manufacturing an embedded component circuit board as described in claim 4, characterized in that, The through hole was created using laser drilling.

9. The method for manufacturing an embedded component circuit board as described in claim 4, characterized in that, The first opening and the second opening are formed by laser drilling.

10. The method for manufacturing an embedded component circuit board as described in claim 4, characterized in that, The first opening is formed by locally etching a resist dry film applied to the surface of the first outer dielectric layer away from the substrate layer. The second opening is formed by locally etching a resist dry film applied to the surface of the second outer dielectric layer away from the intermediate dielectric layer.

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