Memory and method of making the same
By forming multiple active pillars and dielectric layers on the substrate of dynamic random access memory, the problem of high word line resistance is solved, improving the fabrication efficiency and performance of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-11
- Publication Date
- 2026-07-24
AI Technical Summary
Existing dynamic random access memory (DRAM) has a small word line width and high resistance, which makes the memory difficult to manufacture and results in poor performance.
Multiple spaced active pillars are formed on the substrate, and each straight segment of each bit line is electrically connected to at least two active pillars. By filling the dielectric layer and conductive layer between the insulating layer to form the word line, the width and density of the gate are increased, and the number of bends of the bit line is reduced.
This improves memory performance, reduces manufacturing complexity, and decreases gate resistance, thereby enhancing overall memory performance.
Smart Images
Figure CN116489987B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a memory and a method for manufacturing the same. Background Technology
[0002] With the continuous development of semiconductor and memory technologies, electronic devices are increasingly miniaturized and integrated. Dynamic Random Access Memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read / write speeds. DRAM typically consists of multiple memory cells, each usually including a transistor and a capacitor. The capacitor stores data, and the transistor controls the reading and writing of data in the capacitor. However, the current structure has a small word line width and high word line resistance, making the memory difficult to manufacture and resulting in poor performance. Summary of the Invention
[0003] In view of the above problems, embodiments of this application provide a memory and a method for manufacturing the same, which reduces the manufacturing difficulty of the memory and improves the performance of the memory.
[0004] A first aspect of this application provides a method for manufacturing a memory, comprising:
[0005] A substrate is provided in which a plurality of spaced bit lines are formed, each bit line comprising a plurality of straight line segments connected end to end in sequence and adjacent straight line segments having an included angle.
[0006] A plurality of spaced active pillars and a plurality of spaced insulating layers are formed on the substrate. Each straight segment of each bit line is electrically connected to at least two of the active pillars. The insulating layer extends along a first direction and covers the outer peripheral surface of the active pillars.
[0007] A first support layer is filled between adjacent insulating layers;
[0008] A portion of the insulating layer away from the substrate is removed to form a filling space that exposes the outer peripheral surface of the active pillar.
[0009] A dielectric layer and a conductive layer are formed between the active pillars exposed in the filled space and close to the substrate to form word lines.
[0010] The method for manufacturing the memory provided in this application has at least the following advantages:
[0011] In the memory fabrication method provided in this application embodiment, each bit line in the substrate includes multiple straight line segments. These segments are connected end-to-end and adjacent segments form an angle. By forming multiple spaced active pillars on the substrate, and electrically connecting these active pillars to the bit lines, the active pillars are staggered on the substrate, increasing the density of active pillars and thus improving memory performance. Simultaneously, each straight line segment of each bit line is electrically connected to at least two active pillars, reducing the number of bends in each bit line and facilitating memory fabrication. Furthermore, an insulating layer covers the outer periphery of the active pillars. After removing part of the insulating layer, a dielectric layer and a conductive layer are formed between the exposed active pillars. A portion of the conductive layer and a portion of the dielectric layer form the gate. The staggered arrangement of multiple active pillars on the substrate increases the width of the gate along the radial direction of the active pillars, improving the gate formation quality, reducing gate resistance, and further improving memory performance.
[0012] A second aspect of this application provides a memory comprising: a substrate having a plurality of spaced bit lines formed therein, each bit line comprising a plurality of straight line segments connected end-to-end and adjacent straight line segments having an included angle; a plurality of spaced active pillars formed on the substrate, each straight line segment of each bit line being electrically connected to at least two active pillars; a plurality of spaced insulating layers formed on the substrate, each insulating layer extending along a first direction and covering the outer peripheral surface of a lower region of the active pillars; a dielectric layer formed on the outer peripheral surface of a middle region of the active pillars; a plurality of spaced conductive layers formed on the insulating layers, the conductive layers extending along the first direction and covering the outer peripheral surface of the dielectric layers to form word lines; and a support layer filling the spaces between the insulating layers, the conductive layers, and the active pillars.
[0013] The memory provided in this application has at least the following advantages:
[0014] In the memory provided in this application embodiment, each bit line in the substrate includes multiple straight line segments. These segments are connected end-to-end and adjacent segments form an angle. By forming multiple spaced active pillars on the substrate, and electrically connecting these active pillars to the bit lines, the active pillars are arranged in an alternating pattern on the substrate, increasing the density of the active pillars and thus improving the memory performance. Each straight line segment of each bit line is electrically connected to at least two active pillars, reducing the number of bends in each bit line and facilitating memory fabrication. Furthermore, a portion of the conductive layer and a portion of the dielectric layer form the gate, which covers the outer peripheral surface of the active pillars. The alternating arrangement of multiple active pillars on the substrate increases the width of the gate along the radial direction of the active pillars, improving the formation quality of the gate, reducing its resistance, and further enhancing the memory performance. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a flowchart illustrating the method for manufacturing the memory in an embodiment of this application;
[0017] Figure 2 This is a schematic diagram of the structure of the bit line and word line in the embodiments of this application;
[0018] Figure 3 This is a top view of the embodiment of this application after the active pillar and insulating layer have been formed;
[0019] Figure 4 for Figure 3 Schematic diagram of the structure at point AA;
[0020] Figure 5 for Figure 3 Schematic diagram of the structure at point BB;
[0021] Figure 6 This is a top view of the embodiment of this application after the first support layer has been formed;
[0022] Figure 7 for Figure 6 Schematic diagram of the structure at point AA;
[0023] Figure 8 for Figure 6 Schematic diagram of the structure at point BB;
[0024] Figure 9 This is a top view of the embodiment of this application after removing part of the first support layer;
[0025] Figure 10 for Figure 9 Schematic diagram of the structure at point AA;
[0026] Figure 11 for Figure 9 Schematic diagram of the structure at point BB;
[0027] Figure 12 This is a top view of the embodiment of this application after the formation of the dielectric layer and the conductive layer;
[0028] Figure 13 for Figure 12 Schematic diagram of the structure at point AA;
[0029] Figure 14 for Figure 12Schematic diagram of the structure at point BB;
[0030] Figure 15 This is a top view of the active line formed in the embodiment of this application;
[0031] Figure 16 for Figure 15 Schematic diagram of the structure at point AA;
[0032] Figure 17 This is a top view of the embodiment of this application after the initial trench has been formed;
[0033] Figure 18 for Figure 17 Schematic diagram of the structure at point AA;
[0034] Figure 19 for Figure 17 Schematic diagram of the structure at point BB;
[0035] Figure 20 This is a top view of the embodiment of this application after the first trench has been formed;
[0036] Figure 21 for Figure 20 Schematic diagram of the structure at point AA;
[0037] Figure 22 for Figure 20 Schematic diagram of the structure at point BB;
[0038] Figure 23 This is a top view of the active column after rounding corners in the embodiments of this application;
[0039] Figure 24 This is a top view of the embodiment of this application after the second support layer has been formed;
[0040] Figure 25 for Figure 24 Schematic diagram of the structure at point AA;
[0041] Figure 26 for Figure 24 A schematic diagram of the structure at point BB.
[0042] Explanation of reference numerals in the attached figures:
[0043] 10 - Position line; 11 - First straight segment;
[0044] 12 - Second straight segment; 20 - Line;
[0045] 30 - Substrate; 40 - Active pillar;
[0046] 41 - Active wire; 42 - First trench;
[0047] 43 - Initial trench; 50 - Insulation layer;
[0048] 51-First surrounding portion; 52-First connecting portion;
[0049] 53 - Initial insulation layer; 54 - Space filling;
[0050] 60 - First support layer; 70 - Dielectric layer;
[0051] 80 - Conductive layer; 81 - Second circumferential portion;
[0052] 82 - Second connecting part; 90 - Second support layer. Detailed Implementation
[0053] As integrated circuit dimensions shrink, memory fabrication becomes increasingly difficult. The distance between adjacent word lines decreases, making defects more likely during word line fabrication and impacting memory performance. Therefore, this application provides a method for fabricating a memory, including a substrate on which active pillars are formed. Multiple bit lines are formed within the substrate, each bit line comprising multiple straight line segments. These segments are sequentially connected end-to-end, with adjacent segments forming an angle. Each straight line segment of each bit line is electrically connected to at least two active pillars, resulting in a staggered arrangement of active pillars on the substrate. This increases the density of active pillars, expands the gate width, and thus improves memory performance. Simultaneously, it reduces the number of bends per bit line, facilitating memory fabrication.
[0054] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0055] See Figure 1 , Figure 1 This is a flowchart of a method for manufacturing a memory according to an embodiment of this application. The method includes the following steps:
[0056] Step S100: Provide a substrate, in which multiple spaced bit lines are formed, each bit line including multiple straight line segments, the multiple straight line segments being connected end to end in sequence and adjacent straight line segments having an included angle.
[0057] The substrate provides support and can be a semiconductor substrate. The semiconductor substrate can be made of one or more of the following materials: silicon, germanium, silicon germanide, silicon carbide, silicon on insulator (SOI), or germanium on insulator (GOI).
[0058] Multiple spaced bit lines 10 are formed within the substrate (see reference) Figure 2 Each position line 10 includes multiple straight line segments, which are connected end to end in sequence and adjacent straight line segments have an angle, so that each position line 10 forms a broken line shape.
[0059] Specifically, the multiple straight line segments corresponding to each bit line 10 include: multiple segments along the second direction ( Figure 2 The first straight segment 11 extending in the Y1 direction (as shown), and along the third direction ( Figure 2 The second straight line segment 12 extends in the Y2 direction (as shown), and connects two adjacent first straight line segments 11, such that each bit line 10 forms a wavy zigzag to make full use of the space of the substrate. For example, the angle formed by the second direction and the third direction can be 30°-150°, for example, 120°.
[0060] Step S200: A plurality of spaced active pillars and a plurality of spaced insulating layers are formed on the substrate. Each straight segment of each bit line is electrically connected to at least two active pillars. The insulating layers extend along a first direction and cover the outer peripheral surface of the active pillars.
[0061] See Figures 3 to 5 A plurality of active pillars 40 and a plurality of insulating layers 50 are formed on the substrate 30. For ease of distinction, in the embodiments of this application, the active pillars 40 in the top view are all filled with patterns, wherein the top view is a partial view of the memory, for example... Figure 2 A view of the local area enclosed by the dashed line. Multiple active columns are arranged at 40 intervals, with 10 bit lines per line (see...). Figure 2 Each straight segment of the bitline has at least two active posts 40 connected to it. For example, multiple active posts 40 are in contact with the corresponding bitline 10 to achieve electrical connection between the active posts 40 and the bitline 10. By connecting multiple active posts 40 on each straight segment, the bending of each bitline 10 after passing through an active post 40 is avoided, thereby reducing the number of bends of each bitline 10 and reducing the manufacturing difficulty of the bitline 10.
[0062] In some possible examples, bit line 10 covers the orthographic projection of multiple active pillars 40 onto substrate 30. With this configuration, the entire bottom surface of the active pillars 40 is in contact with bit line 10, resulting in a larger contact area between the active pillars 40 and bit line 10, thereby reducing the contact resistance between the active pillars 40 and bit line 10.
[0063] The active pillar 40 is used to form the source region, drain region, and channel region, with the channel region located between the source and drain regions. The source, drain, and channel regions are arranged in a direction perpendicular to the substrate 30, and one of the source and drain regions is in contact with the substrate 30. The active region can be made of a semiconductor material. For example, the material of the active pillar 40 can be the same as or different from the material of the substrate 30. The substrate 30 and the active pillar 40 located on the substrate 30 are formed by etching the semiconductor material, with the bit line 10 being a buried bit line.
[0064] In one possible example, taking a plane parallel to the substrate 30 as a cross-section, the multiple active pillars 40 are arranged in a hexagonal close-packed structure. (See [reference needed] for details on hexagonal close-packed structures.) Figure 3 The active pillars 40 are grouped into sets of seven, with the centers of six active pillars 40 forming a virtual hexagon. Specifically, the centers of these six active pillars 40 are located at the six vertices of the virtual hexagon, and the center of the seventh active pillar 40 is located at the center of the virtual hexagon. The cross-sectional shape of the active pillar 40, taken as a plane parallel to the substrate, does not need to be circular; this does not affect the arrangement of the multiple active pillars 40.
[0065] This configuration increases the density of the active pillars 40. When the capacitors on the active pillars 40 are also arranged in a hexagonal close-packed structure, it increases the capacitor density, thereby increasing the memory density. Furthermore, the capacitors can be directly placed above the active pillars 40 without the need for capacitor contact pads to bridge the gap between the capacitors and the active pillars 40, reducing the complexity of memory fabrication. For example, when the active pillars 40 are arranged in a square pattern, capacitor contact pads need to be fabricated above the active pillars 40 to allow the capacitors to be arranged in a hexagonal close-packed structure.
[0066] Continue reading Figures 3 to 5 Multiple insulating layers 50 are spaced apart, and the multiple insulating layers 50 are arranged along a first direction ( Figure 3 It extends in the X direction (as shown) and covers the outer peripheral surface of the active pillar 40. For example... Figure 3 As shown, each insulating layer 50 corresponds to at least one active region located in the first direction and covers the outer peripheral surface of the at least one active region. The insulating layer 50 can be made of silicon oxide, silicon nitride, or silicon oxynitride, etc.
[0067] Specifically, such as Figure 3 As shown, each insulating layer 50 includes a first surrounding portion 51 and a first connecting portion 52, wherein the first surrounding portion 51 is as follows: Figure 3As shown by the dashed line, the area covers the outer periphery of the active column 40. The first connecting portion 52 connects two adjacent first surrounding portions 51, and the first connecting portion 52 extends along the first direction. That is, the first surrounding portion 51 corresponds to the active column 40 and surrounds the active column 40 completely. The first connecting portion 52 connects two adjacent first surrounding portions 51 along the first direction.
[0068] Step S300: Fill the first support layer between adjacent insulating layers.
[0069] See Figures 6 to 8 A first support layer 60 is formed between adjacent insulating layers 50 through a deposition process, and the first support layer 60 fills the space between adjacent insulating layers 50. For example, the first support layer 60 is filled between adjacent insulating layers 50 by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0070] like Figure 7 and Figure 8 As shown, the surface of the first support layer 60 facing away from the substrate 30 can be flush with the surface of the insulating layer 50 facing away from the substrate 30, that is, the top surface of the first support layer 60 is flush with the top surface of the insulating layer 50. The material of the first support layer 60 can be silicon oxide, silicon nitride, or silicon oxynitride, and its material is different from that of the insulating layer 50 to reduce damage to the first support layer 60 during subsequent removal of the insulation. For example, the insulating layer 50 is made of silicon oxide (e.g., SiO2), and the first support layer 60 is made of silicon nitride (e.g., Si3N4).
[0071] Step S400: Remove the portion of the insulating layer away from the substrate to form a filling space, which exposes the outer peripheral surface of the active pillar.
[0072] See Figures 9 to 11 Remove the portion of the insulating layer 50 away from the substrate 30, for example, by etching away that portion of the insulating layer 50. Figure 10 and Figure 11 As shown, the upper middle insulating layer 50 is removed, while the lower insulating layer 50 is retained. After removing part of the insulating layer 50, a filling space 54 is formed, which exposes the outer peripheral surface of the source pillar 40. Specifically, the filling space 54 exposes the outer peripheral surface of the channel region to facilitate the formation of the dielectric layer 70 and the conductive layer 80 on the outer peripheral surface of the channel region.
[0073] Step S500: A dielectric layer and a conductive layer are formed between the active pillars exposed in the fill space and close to the substrate to form word lines.
[0074] See Figures 12 to 14 A dielectric layer 70 is formed on the outer peripheral surface of the active pillar 40 exposed in the filling space 54 and close to the substrate 30, and a conductive layer 80 is formed on the outer peripheral surface of the dielectric layer 70. The conductive layer 80 fills the space between the dielectric layer 70 and the first support layer 60. The conductive layer 80 and the dielectric layer 70 form a word line. The dielectric layer 70 and the conductive layer 80 surrounding the outer peripheral surface of the dielectric layer 70 form a gate, i.e., the gate is part of the word line 20, which extends along a first direction. Specifically, the dielectric layer 70 can be an oxide layer, which forms a gate oxide layer; the conductive layer 80 can be made of metal, and the conductive layer 80 surrounding the outer peripheral surface of the dielectric layer 70 forms a gate conductive layer.
[0075] In some possible embodiments, Figure 2 The second direction shown in the diagram forms a 60° angle with the first direction, and the third direction also forms a 60° angle with the first direction. The first spacing between adjacent word lines 20 is equal to the second spacing between adjacent bit lines 10. This arrangement facilitates the formation of multiple active pillars 40 arranged in a hexagonal close-packed structure (see...). Figure 3 This reduces the manufacturing difficulty of the active pillar 40 with its hexagonal close-packed structure.
[0076] In some possible examples, forming a dielectric layer and a conductive layer between active pillars exposed in the fill space and close to the substrate to form word lines (step 500) may include:
[0077] Step S501: Remove at least the outer peripheral surface of the active pillar exposed in the filling space and close to the substrate to thin the active pillar and expand the filling space.
[0078] like Figure 13 and Figure 14 As shown, at least a portion of the outer peripheral surface of the active pillar 40 exposed within the filling space 54 and close to the substrate 30 is removed to thin the active pillar 40 and expand the filling space 54, thereby increasing the formation space of the gate and improving the formation quality of the gate.
[0079] For example, the entire active pillar 40 exposed within the filling space 54 is etched using processes such as wet etching, resulting in the etching of the entire outer peripheral surface of the active pillar 40 exposed within the filling space 54. This thins the active pillar 40 and increases the volume of the filling space 54. The thinning of the active pillar 40 refers to a reduction in the radial distance of the active pillar 40, i.e., a reduction in the diameter of the etched active pillar 40. Taking a plane parallel to the substrate 30 as a cross-section, the etched active pillar 40 is located within the region of the original active pillar 40.
[0080] Step S502: A dielectric layer is formed on the outer peripheral surface of the active pillar near the substrate, and a gap exists between the dielectric layer and the first support layer.
[0081] like Figure 13 and Figure 14 As shown, a dielectric layer 70 is formed on the outer peripheral surface of the portion of the active pillar 40 exposed within the filling space 40 and close to the substrate 30. Specifically, the dielectric layer 70 is formed on the outer peripheral surface of the active pillar 40 located at the lower part of the filling space 54, and the dielectric layer 70 circumferentially surrounds and covers this portion of the active pillar 40. The dielectric layer 70 is not in contact with the first support layer 60 to provide the space required for forming the conductive layer 80.
[0082] In some possible examples, the active pillar 40 is made of silicon, and the dielectric layer 70 is made of silicon oxide. The dielectric layer 70 is grown on the outer peripheral surface of the active pillar 40 exposed in the filling space 54 by a thermal oxidation process. Then, the portion of the active pillar 40 away from the substrate 30 is removed, while the portion of the active pillar 40 close to the substrate 30 retains the dielectric layer 70.
[0083] In some other possible examples, a dielectric layer 70 is formed on the outer peripheral surface of the active pillar 40 exposed in the filling space 54 by a deposition process, and then the dielectric layer 70 on the part of the active pillar 40 away from the substrate 30 is removed by etching by controlling the parameters in the etching process, while retaining the desired dielectric layer 70.
[0084] Step S503: A conductive layer is formed on the outer peripheral surface of the dielectric layer, and the conductive layer fills the space between the dielectric layer and the first support layer.
[0085] Continue reading Figure 13 and Figure 14 A conductive layer 80 is deposited on the outer peripheral surface of the dielectric layer 70, and the conductive layer 80 fills the space between the dielectric layer 70 and the first support layer 60. That is, the conductive layer 80 fills the space formed between the dielectric layer 70 and the first support layer 60. The conductive layer 80 includes a second surrounding portion 81 surrounding the dielectric layer 70, and a second connecting portion 82 connecting adjacent second surrounding portions 81. The second surrounding portion 81 is as follows... Figure 13 As shown in the area enclosed by the dashed line, the second surrounding portion 82 and the dielectric layer 70 form the gate, and the conductive layer 80 and the dielectric layer 70 form the word line 20 (see...). Figure 2 That is, a portion of word line 20 is used as a gate.
[0086] It should be noted that the conductive layer 80 also includes an extension portion, which connects to the outer side of the outermost second surrounding portion 81, where the outer side refers to the side of the second surrounding portion 81 that is away from the other second surrounding portions 81. For example, the leftmost second surrounding portion 81 has an extension portion connected to its left side and a second connecting portion 82 connected to its right side; the rightmost second surrounding portion 81 has an extension portion connected to its right side and a second connecting portion 82 connected to its left side. By providing the extension portion, the conductive layer 80 can be connected to the peripheral circuitry, thereby realizing the control function of the word line 20.
[0087] Specifically, a conductive layer 80 is formed on the outer peripheral surface of the dielectric layer 70, and the conductive layer 80 fills the space between the dielectric layer 70 and the first support layer 60, which may include:
[0088] An initial conductive layer is deposited within the expanded fill space 54, filling the space between the dielectric layer 70 and the first support layer 60 and covering the dielectric layer 70. The initial conductive layer is also deposited between the dielectric layer 70 and the first support layer 60, further covering the dielectric layer 70. For example, the initial conductive layer completely fills the expanded fill space 54.
[0089] After the initial conductive layer is formed, the initial conductive layer shown above the dielectric layer 70 is removed to expose the dielectric layer 70. The remaining initial conductive layer forms a conductive layer 80, the surface of the conductive layer 80 facing away from the substrate 30 being flush with the surface of the dielectric layer 70 facing away from the substrate 30. See also Figure 13 and Figure 14 The initial conductive layer on the side of the dielectric layer 70 facing away from the substrate 30 is removed by an etching process, and the remaining initial conductive layer forms the conductive layer 80. The upper surface of the conductive layer 80 is flush with the upper surface of the dielectric layer 70. That is, the required conductive layer 80 is formed by deposition and etching back.
[0090] In summary, the memory fabrication method in this embodiment includes multiple straight line segments for each bit line 10 within the substrate 30. These segments are sequentially connected end-to-end, with adjacent segments forming an angle. By forming multiple spaced active pillars 40 on the substrate 30, the density of the active pillars 40 is increased through staggered arrangement, thereby improving memory performance. Each straight line segment of each bit line 10 is electrically connected to at least two active pillars 40, reducing the number of bends in each bit line 10 and facilitating memory fabrication. Furthermore, an insulating layer 50 covers the outer peripheral surface of the active pillars 40. After removing a portion of the insulating layer 50, a dielectric layer 70 and a conductive layer 80 are formed between the exposed active pillars 40. The dielectric layer 70 and a portion of the conductive layer 80 form the gate. The staggered arrangement of the multiple active pillars 40 on the substrate 30 increases the width of the gate along the radial direction of the active pillars 40, thereby improving the gate formation quality, reducing gate resistance, and further enhancing memory performance.
[0091] See some possible examples. Figures 15 to 22 Multiple spaced active pillars and multiple spaced insulating layers are formed on a substrate. Each straight segment of each bit line is electrically connected to at least two active pillars. The insulating layers extend along a first direction and cover the outer peripheral surface of the active pillars (step S200). This may include the following process:
[0092] Step S201: Form multiple spaced active lines on the substrate, each active line corresponding to and electrically connected to a bit line.
[0093] For details, please refer to Figure 2 , Figure 15 and Figure 16 Multiple active lines 41 are formed at intervals through an etching process, and each active line 41 is parallel to the others. Each active line 41 corresponds to a bit line 10 and is electrically connected to the corresponding bit line 10 to realize the electrical connection between the active line 41 and the bit line 10.
[0094] For example, each active line 41 includes multiple first active segments extending along a second direction and multiple second active segments extending along a third direction, wherein the second active segments connect two adjacent first active segments. The first active segments correspond to and contact the first straight segment of the bit line 10, and the second active segments correspond to and contact the second straight segment of the bit line 10.
[0095] Step S202: An initial insulating layer is formed on the substrate, and the initial insulating layer fills the spaces between adjacent active lines.
[0096] Continue reading Figure 15 and Figure 16 An initial insulating layer 53 is deposited on the substrate 30, filling the spaces between the active lines 41 to isolate each active line 41. Specifically, the initial insulating layer 53 is deposited to fill the spaces between and cover the active lines 41, and then the initial insulating layer 53 above the active lines 41 is etched away to expose the active lines 41.
[0097] Step S203: Remove part of the initial insulation layer and part of the active wire to form multiple spaced first trenches. The first trenches divide the active wires into multiple active posts. The remaining initial insulation layer forms part of the first circumferential portion and a first connecting portion connecting the first circumferential portion.
[0098] See Figures 17 to 22 The initial insulating layer 53 and the active line 41 are etched to form multiple spaced first trenches 42. The first trenches 42 extend along the first direction and divide the active line 41 into multiple active pillars 40.
[0099] Specifically, a portion of the initial insulation layer 53 and a portion of the active wire 41 are removed to form multiple initially spaced trenches 43 extending along the first direction. For example... Figures 17 to 19 As shown, the initial trench 43 exposes the substrate 30, and the width of the initial trench 43 is approximately equal along the first direction.
[0100] After the initial trench 43 is formed, a portion of the initial insulating layer 53 exposed within the initial trench 43 is removed to thin the initial insulating layer 53 located between adjacent initial trenches 43, forming a first trench 42. Figures 20 to 22 As shown, the initial insulating layer 53 exposed in the initial trench 43 is etched to thin the initial insulating layer 53, and the thinned initial insulating layer 53 forms the first connection portion 52 (see reference). Figure 3 The surface area of the active post 40 exposed in the initial trench 43 increases, and the expanded initial trench 43 forms the first trench 42.
[0101] In some possible examples, such as Figure 20 As shown, with a plane parallel to the substrate as the cross-section, the cross-sectional shape of the active pillar 40 is similar to a quadrilateral, for example, the cross-sectional shape of the active pillar 40 is a parallelogram or a rhombus. After the step of removing part of the initial insulating layer 53 exposed in the initial trench 43 to thin the initial insulating layer 53 located between adjacent initial trenches 43 to form the first trench 42, the method further includes: removing part of the active pillar 40 exposed in the first trench 42 so that the outer peripheral surface of the active pillar 40 is rounded.
[0102] Specifically, the active pillar 40 exposed in the first trench 42 is wet-etched using an alkaline solution, resulting in a rounded transition on the outer periphery of the active pillar 40, such as... Figure 23 As shown, the active column 40 is approximately cylindrical or elliptical. The alkaline solution can be potassium hydroxide or SC1 solution, which reacts faster at sharp corners, rounding the corners of the quadrilateral active column 40. This results in a more uniform dielectric layer 70 and conductive layer 80, improving the quality of the subsequently formed structure.
[0103] Step S204: A partial first circumferential portion is formed on the outer peripheral surface of the active post exposed in the first trench.
[0104] Specifically, a portion of the first surrounding part 51 is formed on the outer peripheral surface of the active column 40 through a thermal oxidation process. Through this step and the previous step, the first surrounding part 51 covering the outer peripheral surface of the active column 40 is formed.
[0105] In some possible examples, after forming a dielectric layer and a conductive layer between the active pillars exposed in the fill space and close to the substrate to form a word line (step S500), the method further includes forming a second support layer in the remaining fill space, the second support layer covering the conductive layer.
[0106] See Figures 24 to 26 A second support layer 90 is deposited on the conductive layer 80 and the dielectric layer 70 to insulate and isolate the conductive layer 80. The second support layer 90 fills the remaining fill space 54, and the active pillar 40 is exposed away from the surface of the substrate 30.
[0107] The material of the second support layer 90 can be the same as that of the first support layer 60, so that the second support layer 90 and the first support layer 60 are integrated, reducing or avoiding delamination or separation between the second support layer 90 and the first support layer 60. The surface of the second support layer 90 facing away from the substrate 30 can be flush with the surface of the first support layer 60 facing away from the substrate 30. With this configuration, the first support layer 60 and the second support layer 90 form a flat surface, which facilitates the fabrication of other structures on top of it.
[0108] In some possible examples, after forming a dielectric layer and a conductive layer between the active pillars exposed in the fill space and close to the substrate to form word lines (step S500), the method further includes forming a capacitor electrically connected to each active pillar, with the capacitor facing the corresponding active pillar.
[0109] For example, the bottom surface of the capacitor is in contact with and directly opposite the top surface of the active post 40. This achieves electrical connection between the capacitor and the active post 40 on the one hand, and ensures the contact area between the capacitor and the active post 40 on the other hand, thereby reducing the contact resistance between the capacitor and the active post 40.
[0110] This application also provides a memory, see embodiments thereof. Figure 2 , Figures 24 to 26 It includes a substrate 30, an active pillar 40, an insulating layer 50, a dielectric layer 70, a conductive layer 80, and a support layer. The substrate 30 provides support and can be a semiconductor substrate. The semiconductor substrate can be made of one or more of the following materials: silicon, germanium, silicon germanide, silicon carbide, silicon on insulator (SOI), or germanium on insulator (GOI).
[0111] Multiple spaced bit lines 10 are formed within the substrate 30 (see reference) Figure 2Each bit line 10 comprises multiple straight line segments, which are connected end-to-end and adjacent segments form an angle, thus forming a zigzag shape for each bit line 10. Specifically, the multiple straight line segments corresponding to each bit line 10 include: multiple first straight line segments 11 extending along a second direction, and second straight line segments 12 extending along a third direction. The second straight line segments 12 connect two adjacent first straight line segments 11, so that each bit line 10 forms a wavy zigzag shape to fully utilize the space of the substrate 30. For example, the angle formed by the first direction and the second direction is 30°-150°, such as 120°.
[0112] Multiple active pillars 40 are formed on the substrate 30, and the active pillars 40 are arranged at intervals. Each straight segment of each bit line 10 is electrically connected to at least two active pillars 40. For example, the active pillars 40 are in contact with the bit line 10 to achieve electrical connection between the active pillars 40 and the bit line 10. By electrically connecting multiple active pillars 40 on each straight segment, the bending of each bit line 10 after passing through each active pillar 40 is avoided, thereby reducing the number of bends of each bit line 10 and reducing the fabrication difficulty of the bit line 10.
[0113] In some possible examples, bit line 10 covers the orthographic projection of multiple active pillars 40 onto substrate 30. With this configuration, the entire bottom surface of the active pillars 40 is in contact with bit line 10, resulting in a larger contact area between the active pillars 40 and bit line 10, thereby reducing the contact resistance between the active pillars 40 and bit line 10.
[0114] In other possible examples, with a plane parallel to the substrate 30 as the cross-section, multiple active pillars 40 are arranged in a hexagonal close-packed structure. For example... Figure 24 As shown, every seven active pillars 40 form a group, with the centers of six active pillars 40 forming a virtual hexagon. That is, the centers of these six active pillars 40 are located at the six vertices of the virtual hexagon, and the center of the seventh active pillar 40 is located at the center of the virtual hexagon.
[0115] This configuration increases the density of the active pillars 40. When the capacitors on the active pillars 40 are also arranged in a hexagonal close-packed structure, it increases the capacitor density, thereby increasing the memory density. Furthermore, the capacitors can be directly placed above the active pillars 40 without the need for capacitor contact pads to bridge the gap between the capacitors and the active pillars 40, reducing the complexity of memory fabrication. For example, when the active pillars 40 are arranged in a square pattern, capacitor contact pads need to be fabricated above the active pillars 40 to allow the capacitors to be arranged in a hexagonal close-packed structure.
[0116] A plurality of insulating layers 50 are also formed on the substrate 30, the plurality of insulating layers 50 being spaced apart and extending along a first direction. Each insulating layer 50 covers the outer peripheral surface of the lower region of the active pillar 40 along its extending direction, wherein the lower region of the active pillar 40 refers to the region of the active pillar 40 close to the substrate 30.
[0117] The dielectric layer 70 is formed on the outer peripheral surface of the central region of the active pillar 40, that is, the dielectric layer 70 covers the outer peripheral surface of the central region of the active pillar 40. Multiple spaced conductive layers 80 are formed on the insulating layer 50. The conductive layers 80 extend along the first direction and cover the outer peripheral surface of the dielectric layer 70. The conductive layers 80 and the dielectric layer 70 form word lines.
[0118] In some possible examples, such as Figure 2 The angle between the second direction and the first direction is 60°, and the angle between the third direction and the first direction is also 60°. The first spacing between adjacent word lines 20 is equal to the second spacing between adjacent bit lines 10. This arrangement facilitates the formation of multiple active pillars in a hexagonal close-packed structure, reducing the manufacturing difficulty of active pillars in a hexagonal close-packed structure.
[0119] A support layer is filled between the insulating layers 50, between the conductive layers 80, and between the upper region of the active pillar 40, isolating the insulating layers 50, conductive layers 80, and active pillar 40. Specifically, the support layer includes a first support layer 60 and a second support layer 90. The first support layer 60 is filled between the insulating layers 50 and between the conductive layers 80, and extends to the upper region of the active pillar 40. The second support layer 90 is filled between the first support layer 60 and the upper region of the active pillar 40.
[0120] In this embodiment of the memory, each bit line 10 within the substrate 30 includes multiple straight line segments. These segments are sequentially connected end-to-end, with adjacent segments forming an angle. By forming multiple spaced active pillars 40 on the substrate 30, the density of the active pillars 40 is increased through their staggered arrangement, thereby improving memory performance. Each straight line segment of each bit line 10 is electrically connected to at least two active pillars 40, reducing the number of bends in each bit line 10 and facilitating memory fabrication. Furthermore, a dielectric layer 70 and a portion of a conductive layer 80 form a gate. The gate covers the outer peripheral surface of the active pillars 40, and the staggered arrangement of the multiple active pillars 40 on the substrate 10 increases the width of the gate along the radial direction of the active pillars 40, thereby improving the gate formation quality, reducing gate resistance, and further enhancing memory performance.
[0121] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0122] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for manufacturing a memory, characterized in that, include: A substrate is provided in which a plurality of spaced bit lines are formed, each bit line comprising a plurality of straight line segments connected end to end in sequence and adjacent straight line segments having an included angle. A plurality of spaced-apart active pillars and a plurality of spaced-apart insulating layers are formed on the substrate. Each insulating layer includes a first surrounding portion covering the outer peripheral surface of the active pillar and a first connecting portion connecting two adjacent first surrounding portions and extending along a first direction. Each straight segment of each bit line is electrically connected to at least two active pillars. The insulating layer extends along the first direction and covers the outer peripheral surface of the active pillar. It includes a plurality of spaced-apart active lines formed on the substrate. Each active line corresponds to and is electrically connected to one bit line. An initial insulating layer is formed on the substrate, the initial insulating layer filling the spaces between adjacent active lines; A portion of the initial insulation layer and a portion of the active wire are removed to form multiple spaced first trenches, which divide the active wire into multiple active posts. A first support layer is filled between adjacent insulating layers; A portion of the insulating layer away from the substrate is removed to form a filling space that exposes the outer peripheral surface of the active pillar. A dielectric layer and a conductive layer are formed between the active pillars exposed in the filled space and close to the substrate to form word lines.
2. The method for manufacturing a memory according to claim 1, characterized in that, Each bit line corresponds to a plurality of straight line segments, including: a plurality of first straight line segments extending along a second direction, and a second straight line segment extending along a third direction, wherein the second straight line segment connects two adjacent first straight line segments.
3. The method for manufacturing a memory according to claim 2, characterized in that, The angle between the second direction and the first direction is 60°, and the angle between the third direction and the first direction is 60°. The first spacing between adjacent word lines is equal to the second spacing between adjacent bit lines.
4. The method for manufacturing a memory according to claim 1, characterized in that, With a plane parallel to the substrate as the cross-section, the multiple active pillars are arranged in a hexagonal close-packed structure.
5. The method for manufacturing a memory according to claim 1, characterized in that, Removing a portion of the initial insulation layer and a portion of the active wires forms multiple spaced first trenches, which divide the active wires into multiple active posts, including: Remove part of the initial insulation layer and part of the active wire to form multiple spaced initial trenches extending along a first direction; The portion of the initial insulating layer exposed within the initial trench is removed to thin the initial insulating layer located between adjacent initial trenches, forming the first trench.
6. The method for manufacturing a memory according to claim 5, characterized in that, With a plane parallel to the substrate as the cross-section, the active pillar has a quadrilateral cross-sectional shape; After the step of removing a portion of the initial insulating layer exposed within the initial trench to thin the initial insulating layer located between adjacent initial trenches to form the first trench, the method further includes: Remove the portion of the active post exposed within the first trench to allow the outer periphery of the active post to be rounded.
7. The method for manufacturing a memory according to claim 6, characterized in that, The portion of the active post exposed within the first trench is etched using an alkaline solution wet etching process.
8. The method for manufacturing a memory according to claim 1, characterized in that, A portion of the first surrounding portion is formed on the outer peripheral surface of the active column through a thermal oxidation process.
9. The method for manufacturing a memory according to any one of claims 1-4, characterized in that, Forming a dielectric layer and a conductive layer between the active pillars exposed in the filled space and close to the substrate to form word lines, including: At least a portion of the outer peripheral surface of the active pillar exposed within the filling space and close to the substrate is removed to thin the active pillar and expand the filling space; The dielectric layer is formed on the outer peripheral surface of the active pillar near the substrate, and a gap exists between the dielectric layer and the first support layer. The conductive layer is formed on the outer peripheral surface of the dielectric layer, and the conductive layer fills the space between the dielectric layer and the first support layer.
10. The method for manufacturing a memory according to claim 9, characterized in that, The conductive layer is formed on the outer peripheral surface of the dielectric layer, and the conductive layer fills the space between the dielectric layer and the first support layer, comprising: An initial conductive layer is deposited within the expanded filling space, the initial conductive layer filling the space between the dielectric layer and the first support layer and covering the dielectric layer; The initial conductive layer located above the dielectric layer is removed to expose the dielectric layer, and the retained initial conductive layer forms the conductive layer, the surface of the conductive layer facing away from the substrate being flush with the surface of the dielectric layer facing away from the substrate.
11. The method for manufacturing a memory according to any one of claims 1-4, characterized in that, After forming a dielectric layer and a conductive layer between the active pillars exposed in the filled space and close to the substrate to form a word line, the method further includes: A second support layer is formed within the remaining filling space, and the second support layer covers the conductive layer.
12. The method for manufacturing a memory according to any one of claims 1-4, characterized in that, After forming a dielectric layer and a conductive layer between the active pillars exposed in the filled space and close to the substrate to form a word line, the method further includes: A capacitor electrically connected to each of the active posts is formed, and the capacitor is directly opposite the corresponding active post.
13. A memory, formed using the method of manufacturing the memory according to any one of claims 1-12, characterized in that, include: A substrate in which multiple spaced bit lines are formed, each bit line comprising multiple straight line segments connected end to end and adjacent straight line segments having an included angle. A plurality of spaced active pillars are formed on the substrate, and each straight segment of each bit line is electrically connected to at least two of the active pillars; A plurality of spaced insulating layers are formed on the substrate, each insulating layer extending along a first direction and covering the outer peripheral surface of the lower region of the active pillar; A dielectric layer is formed on the outer peripheral surface of the central region of the active column; Multiple spaced conductive layers are formed on the insulating layer, the conductive layers extending along a first direction and covering the outer peripheral surface of the dielectric layer to form word lines; A support layer is filled between the insulating layers, between the conductive layers, and between the active pillars.
14. The memory according to claim 13, characterized in that, Each bit line corresponds to a plurality of straight line segments, including: a plurality of first straight line segments extending along a second direction, and a second straight line segment extending along a third direction, wherein the second straight line segment connects two adjacent first straight line segments.
15. The memory according to claim 14, characterized in that, The angle between the second direction and the first direction is 60°, and the angle between the third direction and the first direction is 60°. The first spacing between adjacent word lines is equal to the second spacing between adjacent bit lines.
16. The memory according to any one of claims 13-15, characterized in that, With a plane parallel to the substrate as the cross-section, the multiple active pillars are arranged in a hexagonal close-packed structure.