Pixel, display device including the same, and method of manufacturing the display device

Abstract

A pixel according to an embodiment of the disclosure includes: a circuit element on a base layer; a protection layer on the circuit element; a first electrode and a second electrode facing each other on the protection layer; a first insulating layer disposed on the first electrode and the second electrode; a light emitting element on the first insulating layer in a region between the first electrode and the second electrode; a first contact electrode on a first end portion of the light emitting element to connect the first end portion of the light emitting element to the first electrode; a second contact electrode on a second end portion of the light emitting element to connect the second end portion of the light emitting element to the second electrode; and a cavity in the protection layer and the first insulating layer below the light emitting element corresponding to the region between the first electrode and the second electrode.

Description

Technical Field

[0001] Embodiments of this disclosure relate to pixels, display devices including pixels, and methods of manufacturing display devices. Background Technology

[0002] Recently, interest in information display has been increasing. Therefore, research and development of display devices are ongoing. Summary of the Invention

[0003] Technical issues

[0004] Embodiments of this disclosure provide pixels including light-emitting elements, display devices including pixels, and methods for manufacturing display devices.

[0005] Technical solution

[0006] According to embodiments of this disclosure, a pixel includes: a circuit element on a base layer; a protective layer on the circuit element; a first electrode and a second electrode on the protective layer opposite to each other; a first insulating layer on the first electrode and the second electrode; a light-emitting element in the region between the first electrode and the second electrode on the first insulating layer; a first contact electrode on a first end of the light-emitting element to connect the first end of the light-emitting element to the first electrode; a second contact electrode on a second end of the light-emitting element to connect the second end of the light-emitting element to the second electrode; and a cavity corresponding to the region between the first electrode and the second electrode in the protective layer and the first insulating layer below the light-emitting element.

[0007] In one embodiment, the cavity may have a first width in its lower region corresponding to the protective layer, and a second width smaller than the first width in its upper region corresponding to the first insulating layer.

[0008] In an implementation, the second width may be less than the length of the light-emitting element.

[0009] In one embodiment, the first contact electrode and the second contact electrode may be spaced apart from each other by a second width.

[0010] In one embodiment, the first contact electrode and the second contact electrode may be located in the same layer and may be separated from each other by a cavity.

[0011] In one embodiment, the first contact electrode can be electrically connected to the first electrode through a first contact hole passing through the first insulating layer, and the second contact electrode can be electrically connected to the second electrode through a second contact hole passing through the first insulating layer.

[0012] In one embodiment, the pixel may further include a conductive film remaining on the sidewall of the cavity below the first and second electrodes. The conductive film may include the same material as the first and second contact electrodes.

[0013] In one embodiment, the conductive films located below the first electrode and the second electrode can be spaced apart from each other.

[0014] In an embodiment, the pixel may further include: a first insulating pattern on the first contact electrode; and a second insulating pattern on the second contact electrode and spaced apart from the first insulating pattern.

[0015] In an implementation, the first insulating pattern and the second insulating pattern may include the same photoresist material.

[0016] In one embodiment, the first contact electrode may be located below the first insulating pattern, and the second contact electrode may be located below the second insulating pattern.

[0017] In an embodiment, the protective layer may include at least one organic insulating film, and the first insulating layer may include at least one inorganic insulating film.

[0018] In an embodiment, the pixel may further include at least one of a first dam and a second dam, the first dam being located below the first electrode and the second electrode and overlapping with a region of the first electrode and a region of the second electrode, and the second dam being located in a non-emissive region surrounding an emissive region including the first electrode, the second electrode and the light-emitting element.

[0019] According to embodiments of the present disclosure, a display device includes a base layer and pixels on the base layer, wherein the pixels include: circuit elements on the base layer; a protective layer on the circuit elements; a first electrode and a second electrode on the protective layer opposite to each other; a first insulating layer on the first electrode and the second electrode; a light-emitting element in the region between the first electrode and the second electrode on the first insulating layer; a first contact electrode on a first end of the light-emitting element to connect the first end of the light-emitting element to the first electrode; a second contact electrode on a second end of the light-emitting element to connect the second end of the light-emitting element to the second electrode; and a cavity corresponding to the region between the first electrode and the second electrode in the protective layer and the first insulating layer below the light-emitting element.

[0020] According to embodiments of the present disclosure, a method for manufacturing a display device includes: sequentially forming circuit elements and a protective layer on a base layer; forming a first electrode and a second electrode opposite to each other on the protective layer; forming a first insulating layer to cover the first electrode and the second electrode; forming a cavity in the first insulating layer and the protective layer below a region between the first electrode and the second electrode; providing a light-emitting element on the first insulating layer and aligning the light-emitting element between the first electrode and the second electrode such that the light-emitting element overlaps the cavity on the first insulating layer; forming a conductive film on a pixel region including the light-emitting element; and etching the conductive film to break at an upper and lower portion of the region in which the cavity is formed, and forming a first contact electrode and a second contact electrode on a first end and a second end of the light-emitting element, respectively.

[0021] In one embodiment, forming a cavity may include: forming a first photomask on the remaining area of ​​the first insulating layer, except for the upper portion of a region corresponding to the region between the first electrode and the second electrode; and etching the first insulating layer in the region exposed by the first photomask with the full thickness of the first insulating layer, and forming a trench in the protective layer with a width greater than the etch width of the first insulating layer.

[0022] In an embodiment, forming the first contact electrode and the second contact electrode may include: forming a second photomask on a region of the conductive film that overlaps with a region of the first end of the light-emitting element and a region of the first electrode, and a region of the second end of the light-emitting element and a region of the second electrode; and etching the conductive film using the second photomask to simultaneously form the first contact electrode and the second contact electrode.

[0023] Further details of the implementation methods for solving the above problems are included in the detailed description and accompanying drawings.

[0024] Beneficial effects

[0025] According to embodiments of this disclosure, the number of masks used to manufacture pixels including light-emitting elements can be reduced, and short-circuit defects between the first and second ends of the light-emitting elements can be effectively prevented.

[0026] The effects of this disclosure are not limited to the embodiments described herein, and many more different effects are included in this specification. Attached Figure Description

[0027] Figure 1 This is a perspective view showing a display device according to an embodiment of the present disclosure.

[0028] Figure 2a and Figure 2b This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0029] Figure 3a and Figure 3b This is a schematic cross-sectional view showing the configuration of a display panel according to an embodiment of the present disclosure.

[0030] Figure 4a This is a perspective view showing a light-emitting element according to an embodiment of the present disclosure.

[0031] Figures 4b to 4d This is a cross-sectional view showing a light-emitting element according to an embodiment of the present disclosure.

[0032] Figure 5 This is a plan view showing a display panel according to an embodiment of the present disclosure.

[0033] Figures 6a to 6c This is a circuit diagram illustrating a pixel according to an embodiment of the present disclosure.

[0034] Figure 7 and Figure 8 This is a plan view showing pixels according to an embodiment of the present disclosure.

[0035] Figures 9a to 9c This is a cross-sectional view showing pixels according to an embodiment of the present disclosure.

[0036] Figure 10 This is a plan view showing pixels according to an embodiment of the present disclosure.

[0037] Figures 11a to 11c This is a cross-sectional view showing pixels according to an embodiment of the present disclosure.

[0038] Figures 12a to 12l This is a cross-sectional view showing a method for manufacturing a display device according to embodiments of the present disclosure. Detailed Implementation

[0039] This disclosure can be modified in various embodiments, and specific embodiments will be described and illustrated in the accompanying drawings. In the following description, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0040] On the other hand, this disclosure is not limited to the disclosed embodiments, and can be modified and implemented in various forms. Furthermore, each of the following embodiments can be implemented alone or in combination with at least one other embodiment.

[0041] In the accompanying drawings, some components not directly related to the features of this disclosure may be omitted in order to clearly illustrate the embodiments of this disclosure. In the drawings, identical or similar components are represented by the same reference numerals and symbols as much as possible, even though they are shown in different drawings, and redundant descriptions will be omitted.

[0042] Figure 1 This is a perspective view showing a display device DD according to an embodiment of the present disclosure. Figure 2a and Figure 2b This is a cross-sectional view showing a display device DD according to an embodiment of the present disclosure.

[0043] Figure 3a and Figure 3b This is a schematic cross-sectional view showing the configuration of a display panel DP according to an embodiment of the present disclosure.

[0044] First, refer to Figure 1 A display device DD may include a display area DA and a non-display area NA (also known as a "border area"). The display area DA may be an area that includes pixels for displaying an image. The non-display area NA may be an area other than the display area DA, and the image may not be displayed in the non-display area NA. For example, the non-display area NA may surround the display area DA along its edge or perimeter.

[0045] The display area DA can have various shapes and can include pixels. For example, the display area DA can have various shapes, such as rectangular, circular and elliptical shapes, and pixels can be arranged in the display area DA.

[0046] The display area DA can be formed on at least one surface of the display device DD. As an example, the display area DA can be formed on the front surface of the display device DD, and can also be additionally formed on the side surface and / or rear surface of the display device DD.

[0047] A non-display area NA may be disposed around a display area DA to surround at least one area of ​​the display area DA. The non-display area NA may include lines, pads, and / or drive circuitry connected to the pixels of the display area DA.

[0048] The display device DD can be configured in various shapes. As an example, the display device DD can be configured in a rectangular plate shape, but this disclosure is not limited thereto. For example, the display device DD can have shapes such as circular or elliptical. Furthermore, in Figure 1 In this illustration, the display device DD is shown as including angled corners (e.g., the angle between the two sides of the display device DD at each corner of the display device DD is 90° or about 90°), but this disclosure is not limited thereto. For example, the display device DD may include curved corners.

[0049] For convenience, Figure 1In the diagram, the display device DD is shown as having a rectangular plate shape, comprising a pair of short sides and a pair of long sides. The direction of extension of the short sides is denoted as a first direction DR1, the direction of extension of the long sides is denoted as a second direction DR2, and a direction perpendicular to the direction of extension of the long and short sides (e.g., the thickness or height direction of the display device DD) is denoted as a third direction DR3. However, the directions may vary depending on the shape of the display device DD.

[0050] The display device DD can be flexible, such that at least one area of ​​it is deformable, or the display device DD can be non-flexible, such that its entire area is substantially non-deformable. That is, the display device DD can be a flexible display device or a rigid display device. When at least one area of ​​the display device DD is flexible, the display device DD can deform into a folded, bent, or rolled shape at its flexible portion.

[0051] refer to Figure 2a The display device DD may include a display panel DP and a window WD disposed on the display panel DP. In one embodiment, the window WD may be manufactured integrally with the display panel DP. For example, the window WD may be formed directly on one surface of the display panel DP. In another embodiment, after the window WD is manufactured separately from the display panel DP, the window WD may be attached to the display panel DP by an adhesive (e.g., optically clear adhesive) component OCA.

[0052] The display panel DP may include pixels for displaying images and may be a display panel of various types and / or structures. As an example, the display panel DP may be a self-emissive display panel, such as an OLED display panel using organic light-emitting diodes (OLEDs) as light-emitting elements, a nano / micron-scale LED display panel using nano / micron-sized light-emitting diodes (LEDs) (which have nanometer or micrometer-sized dimensions, but are not limited thereto) as light-emitting elements, a QD OLED display panel using OLEDs and quantum dots (QDs), or a QD nano / micron LED display panel using nano / micron LEDs and QDs, but this disclosure is not limited thereto.

[0053] A window WD (Display Window) can be installed on the display panel DP to protect its exposed surfaces. The window WD protects the display panel DP from external impacts and provides an input and / or display surface to the user.

[0054] Window WDs can be made of various materials such as glass and plastic, and can be formed as a single layer or multiple layers. Furthermore, window WDs can be flexible in at least one area, or they can be non-flexible.

[0055] refer to Figure 2bThe display device DD may also include a touch sensor TS. In some embodiments, the display device DD may include other sensors (e.g., fingerprint sensors, pressure sensors, and temperature sensors) and / or input sensing devices having various types and / or methods.

[0056] A touch sensor TS can be disposed on at least one surface of the display panel DP to detect user touch input. As an example, the touch sensor TS can be disposed on the front surface of the display panel DP (the upper surface on which the image is displayed) between the display panel DP and the window WD, but this disclosure is not limited thereto.

[0057] In some embodiments, the touch sensor TS can be integrally manufactured with the display panel DP. For example, the sensor electrodes and / or sensor elements constituting the touch sensor TS can be directly formed on at least one surface of the display panel DP.

[0058] In another embodiment, the touch sensor TS may be manufactured separately from the display panel DP and then disposed around the display panel DP. As an example, the touch sensor TS may be disposed on and / or attached to at least one surface of the display panel DP.

[0059] refer to Figure 3a The display panel DP may include a base layer (BSL). The display panel DP may also include a pixel circuit layer (PCL), a display element layer (DPL), and a thin-film encapsulation layer (TFE) sequentially disposed on one surface of the base layer (BSL). However, the structure of the display panel DP is not limited to this. For example, some components of the display panel DP may be omitted or replaced by other components. Furthermore, some components may be combined together. In some embodiments, the display panel DP may also include additional components.

[0060] For example, when the display panel DP is the display panel of a passive display device, the pixel circuit layer PCL can be omitted. In this case, the lines used only to drive the pixels can be located below the display element layer DPL, or the lines can be directly connected to the display element layer DPL and / or formed on the display element layer DPL.

[0061] In some implementations, instead of forming a thin-film encapsulation layer (TFE), an upper substrate can be disposed on one surface of the base layer (BSL). The upper substrate can be bonded to the base layer (BSL) using a sealing material.

[0062] The base layer (BSL) can be a rigid substrate (or film) or a flexible substrate (or film). In one embodiment, when the base layer (BSL) is a rigid substrate, it can be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate. In another embodiment, when the base layer (BSL) is a flexible substrate, it can be one of a film substrate comprising a polymeric organic material and a plastic substrate. In some embodiments, the base layer (BSL) can comprise glass fiber reinforced plastic (FRP).

[0063] A pixel circuit layer (PCL) may be disposed on one surface of a base layer (BSL). The PCL may include circuit elements for constituting pixel circuitry for each pixel, as well as various lines connected to the circuit elements. For example, the PCL may include transistors and storage capacitors constituting pixel circuitry for each pixel, and gate lines, data lines, and power lines connected to the pixel circuitry. According to some embodiments, the gate lines may at least include scan lines and may optionally include other types of control lines. In some embodiments, the PCL may also include at least one insulating layer, which includes a protective layer covering the circuit elements and / or lines.

[0064] The display element layer (DPL) can be disposed on the pixel circuit layer (PCL). The display element layer (DPL) can include light-emitting elements that constitute the light source of each pixel. In an embodiment, the light-emitting element can be an inorganic LED (e.g., a nano / micron-sized inorganic LED with nanometer or micrometer-sized dimensions), but is not limited thereto.

[0065] A thin-film encapsulation layer (TFE) can be disposed on the display element layer (DPL). The TFE can be an encapsulation substrate or a multilayer encapsulation film. When the TFE is in the form of an encapsulation film, it can include inorganic and / or organic films. For example, the TFE can have a multilayer structure in which inorganic films, organic films, and inorganic films are stacked sequentially. The TFE protects the pixels by preventing or substantially preventing external air and moisture from penetrating into the display element layer (DPL) and the pixel circuit layer (PCL).

[0066] refer to Figure 3b The display panel DP may also include a light conversion layer LCL for converting light emitted from the display element layer DPL. For example, when considering that the display panel DP emits light in the upward direction (e.g., third-direction DR3) of the display element layer DPL to display an image on the front surface of the display panel DP, the light conversion layer LCL may be disposed on the display element layer DPL. As an example, the light conversion layer LCL may be disposed between the display element layer DPL and the thin-film encapsulation layer TFE.

[0067] The light conversion layer (LCL) may include a color filter, comprising a color filter material having a color (e.g., a set or predetermined color) corresponding to the color of each pixel and / or color conversion particles (e.g., quantum dots) corresponding to the color (e.g., a set or predetermined color), thereby converting the wavelength of light generated in each pixel region of the display element layer (DPL). For example, the LCL may optionally transmit light with a specific wavelength from the light generated by the display element layer (DPL), and / or may convert the wavelength of light generated by the display element layer (DPL).

[0068] exist Figure 3a and Figure 3b In this document, an example configuration of a display panel DP is described, assuming it is an emitting display panel; however, this disclosure is not limited thereto. For example, the configuration of the display panel DP can vary depending on the type of display device DD.

[0069] Figure 4a This is a perspective view showing a light-emitting element (LD) according to an embodiment of the present disclosure. Figures 4b to 4d This is a cross-sectional view showing a light-emitting element (LD) according to an embodiment of the present disclosure. For example, Figures 4b to 4d It shows Figure 4a Different implementations of the configuration of the light-emitting element (LD). Figures 4a to 4d The diagram shows a rod-shaped light-emitting element (LD) with a circular columnar shape, but the type and / or shape of the light-emitting element (LD) according to this disclosure are not limited thereto.

[0070] refer to Figures 4a to 4d The light-emitting element (LD) includes a first semiconductor layer SCL1, a second semiconductor layer SCL2, and an active layer ACT interposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2. As an example, the light-emitting element (LD) may include a first semiconductor layer SCL1, an active layer ACT, and a second semiconductor layer SCL2 stacked sequentially in the direction of its length L.

[0071] The light-emitting element (LD) can be configured as a rod-shaped structure extending in one direction. When assuming that the extension direction of the light-emitting element (LD) is the direction of length L, the light-emitting element (LD) can include a first end EP1 and a second end EP2 in the extension direction.

[0072] One of the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can be disposed at the first end EP1 of the light-emitting element LD. The other of the first semiconductor layer SCL1 and the second semiconductor layer SCL2 can be disposed at the second end EP2 of the light-emitting element LD. As an example, the second semiconductor layer SCL2 and the first semiconductor layer SCL1 can be disposed at the first end EP1 and the second end EP2 of the light-emitting element LD, respectively.

[0073] According to some embodiments, the light-emitting element (LD) can be a rod-shaped light-emitting element (also referred to as a "rod-shaped light-emitting diode") manufactured in a rod shape by etching methods, etc. In this disclosure, the term "rod-shaped" includes all rod-shaped and bar-shaped shapes that are long in the length L direction (i.e., have an aspect ratio greater than 1), such as circular cylinders and polygonal cylinders. The shape of the cross-section of the rod-shaped shape is not particularly limited. For example, the length L of the light-emitting element LD can be greater than its diameter D (or the width of the cross-section).

[0074] Light-emitting elements (LDs) can have small dimensions ranging from nanometers to micrometers. As an example, an LD can have a diameter D (or width) and / or length L ranging from nanometers to micrometers. However, the size of an LD is not limited to this. For example, the size of an LD can vary depending on the design requirements of various devices (e.g., a display device DD that uses a light-emitting device including an LD as its light source).

[0075] The first semiconductor layer SCL1 can be a semiconductor layer of a first conductivity type. For example, the first semiconductor layer SCL1 can include an N-type semiconductor layer. As an example, the first semiconductor layer SCL1 can include an N-type semiconductor layer comprising any semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductivity type dopant such as silicon (Si), germanium (Ge), or tin (Sn). In some embodiments, the first semiconductor layer SCL1 can be made of various materials.

[0076] The active layer ACT can be disposed on the first semiconductor layer SCL1 and can be formed as a single quantum well structure or a multi-quantum well structure. The position of the active layer ACT can be varied depending on the type and / or structure of the light-emitting element LD. The active layer ACT can emit light with wavelengths from 400 nm to 900 nm and can have a dual heterostructure. According to some embodiments, materials such as AlGaN or AlInGaN can be used to form the active layer ACT. In some embodiments, the active layer ACT can be made of various materials.

[0077] The second semiconductor layer SCL2 can be disposed on the active layer ACT and can include a semiconductor layer of a different type than the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 can include a P-type semiconductor layer. As an example, the second semiconductor layer SCL2 can include a P-type semiconductor layer comprising any semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductivity type dopant such as magnesium (Mg). In some embodiments, the second semiconductor layer SCL2 can be made of various materials.

[0078] In this implementation, the first semiconductor layer SCL1 and the second semiconductor layer SCL2 may have different lengths (or thicknesses) in the direction of the length L of the light-emitting element LD. As an example, the first semiconductor layer SCL1 may have a greater length (or thickness) than the second semiconductor layer SCL2 in the direction of the length L of the light-emitting element LD. Therefore, the active layer ACT of the light-emitting element LD may be positioned closer to the first end EP1 than the second end EP2.

[0079] When a voltage greater than or equal to a threshold voltage is applied between the two ends of the light-emitting element (LD) (e.g., the first end EP1 and the second end EP2), electrons and holes recombine with each other in the active layer ACT, and thus the light-emitting element LD emits light. By controlling the emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source for various light-emitting devices, including pixels of a display device DD.

[0080] In an embodiment, in addition to the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2, the light-emitting element LD may further include an insulating film INF surrounding the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2 (e.g., surrounding the outer peripheral surfaces of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2). The light-emitting element LD may additionally include at least one phosphor layer, an active layer, a semiconductor layer, and / or an electrode layer disposed at one end of the first semiconductor layer SCL1, the active layer ACT, and / or the second semiconductor layer SCL2.

[0081] For example, such as Figure 4c As shown, the light-emitting element LD may further include an electrode layer ETL1 disposed at one end (e.g., the first end EP1) of the second semiconductor layer SCL2. In this case, the electrode layer ETL1 may be located at the first end EP1 of the light-emitting element LD.

[0082] In some implementations, such as Figure 4d As shown, the light-emitting element LD may further include another electrode layer ETL2 disposed at one end of the first semiconductor layer SCL1 (e.g., the second end EP2). As an example, electrode layers ETL1 and ETL2 may be disposed at the first end EP1 and the second end EP2 of the light-emitting element LD, respectively.

[0083] Electrode layers ETL1 and ETL2 can be ohmic contact electrodes, but are not limited to this. For example, electrode layers ETL1 and ETL2 can be Schottky contact electrodes.

[0084] Electrode layers ETL1 and ETL2 may comprise metals or conductive oxides. As an example, electrode layers ETL1 and ETL2 may be made of one or a mixture of metals such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and copper (Cu), or their oxides or alloys, and transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), or indium oxide (In2O3). The materials included in electrode layers ETL1 and ETL2 may be the same or different.

[0085] Electrode layers ETL1 and ETL2 can be substantially transparent or semi-transparent. Therefore, light generated by the light-emitting element LD can pass through electrode layers ETL1 and ETL2 to be emitted to the outside of the light-emitting element LD. In some embodiments, electrode layers ETL1 and ETL2 can be opaque when light generated by the light-emitting element LD does not pass through electrode layers ETL1 and ETL2 and is emitted to the outside of the light-emitting element LD through areas other than the two ends of the light-emitting element LD.

[0086] In some embodiments, the light-emitting element (LD) may further include an insulating film INF disposed on its surface (e.g., the outer peripheral surface of the LD). The insulating film INF may be formed on the surface of the LD to surround the active layer ACT (e.g., at least around the outer peripheral surface of the active layer ACT). In some embodiments, the insulating film INF may also surround a region of the first semiconductor layer SCL1 and the second semiconductor layer SCL2. For example, the insulating film INF may surround the outer peripheral surfaces of the first semiconductor layer SCL1 and the second semiconductor layer SCL2.

[0087] When the light-emitting element (LD) includes electrode layers ETL1 and ETL2, the insulating film INF may at least partially cover the outer peripheral surfaces of electrode layers ETL1 and ETL2, or may not at least partially cover the outer peripheral surfaces of electrode layers ETL1 and ETL2. That is, the insulating film INF may optionally be formed on the surfaces of electrode layers ETL1 and ETL2.

[0088] The insulating film INF can expose both ends of the light-emitting element (LD) along its length L. For example, the insulating film INF can expose at least one of the first semiconductor layer SCL1 and the second semiconductor layer SCL2, and the electrode layers ETL1 and ETL2 at the first end EP1 and the second end EP2 of the light-emitting element LD. In some embodiments, the insulating film INF can surround the outer peripheral surfaces of the first semiconductor layer SCL1 and the second semiconductor layer SCL2, and the electrode layers ETL1 and ETL2, and can expose the ends of each electrode layer ETL1 and ETL2. In some embodiments, the insulating film INF may not be disposed on the surface of the light-emitting element LD.

[0089] When the insulating film INF is configured to cover the surface of the light-emitting element LD (e.g., the outer peripheral surface of the active layer ACT), short circuits between the active layer ACT and at least one electrode (e.g., the pixel electrode and / or contact electrode described below) can be prevented or protected. Therefore, the electrical stability of the light-emitting element LD can be ensured. In this disclosure, the term "connection (or coupling)" can refer comprehensively to both physical and / or electrical connections (or couplings). In some cases, the term "connection (or coupling)" can refer comprehensively to both direct and indirect connections (or couplings), as well as integral and non-integral connections (or couplings).

[0090] The insulating film INF may include a transparent insulating material. For example, the insulating film INF may include silicon dioxide selected from SiO2 or not identified as SiO2 (SiO2). x ), Si3N4 or silicon nitride (SiN) not identified as Si3N4 x Al2O3 or aluminum oxide not identified as Al2O3 (Al x O y ) and TiO2 or titanium dioxide (TiO2) not identified as TiO2 x The present disclosure includes at least one insulating material, but is not limited thereto.

[0091] In some embodiments, when the insulating film INF is formed on the surface of the light-emitting element (LD), surface defects of the LD can be reduced or minimized, thereby improving the lifespan and efficiency of the LD. In some embodiments, when the insulating film INF is formed on the surface of each LD, unwanted short circuits between the LDs can be prevented even when multiple LDs are densely arranged.

[0092] In embodiments of this disclosure, the light-emitting element (LD) can be manufactured using a surface treatment process. For example, when multiple LDs are mixed in a flowable solution (or solvent) and provided to each emitting region (e.g., the emitting region of each pixel), the LDs can each be surface-treated to disperse uniformly or substantially uniformly without unevenly agglomerating in the solution. As a related non-limiting embodiment, the insulating film INF itself can be formed as a hydrophobic film using a hydrophobic material, or a hydrophobic film made of a hydrophobic material can be additionally formed on the insulating film INF.

[0093] Light-emitting devices, including light-emitting elements (LDs), can be used in various types of devices that require a light source, such as display devices (DDs). For example, multiple LDs can be arranged in each pixel of a display panel (DP), and the LDs can serve as the light source for each pixel. However, the applications of LDs are not limited to the examples above. For instance, LDs can be used in other types of devices that require a light source, such as lighting devices.

[0094] Figure 5 This is a plan view illustrating a display panel DP according to an embodiment of the present disclosure. According to some embodiments, Figure 5 The display panel DP can be used Figures 4a to 4d The light-emitting element (LD) described in the embodiments serves as the light source for each pixel. For example, each pixel unit (PXU) of the display panel DP and each pixel constituting the pixel unit PXU may include one or more light-emitting elements (LDs).

[0095] For convenience, Figure 5 The structure of the display panel DP is briefly shown based on the display area DA. However, according to some embodiments, at least one driving circuit unit, line, and / or pad, not shown, may be further provided in the display panel DP.

[0096] refer to Figure 5 The display panel (DP) may include a base layer (BSL) and pixels disposed on the base layer (BSL). According to some implementations, a pixel may include a first pixel PXL1, a second pixel PXL2, and / or a third pixel PXL3. Hereinafter, when describing any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, a pixel will be referred to as "pixel PXL," or when describing at least two of its pixels together, pixels will be referred to as "pixels PXL."

[0097] The display panel DP and the base layer BSL used to form the display panel DP may include a display area DA for displaying images and a non-display area NA other than the display area DA.

[0098] The display area DA can be located in the central area of ​​the display panel DP, and the non-display area NA can be located in the edge area of ​​the display panel DP, surrounding the display area DA along its edge or periphery. However, the positions of the display area DA and the non-display area NA can be changed. The display area DA can constitute the screen on which the image is displayed, and the non-display area NA can be an area other than the display area DA.

[0099] Pixel PXL can be set in display area DA on base layer BSL. As an example, display area DA may include multiple pixel areas in which pixel PXL is set. Non-display area NA may be set around display area DA, and various lines, pads and / or embedded circuit units connected to pixel PXL in display area DA may be set in non-display area NA.

[0100] Pixel PXL can be based on stripe arrangement structure or The arrangement of the structures is regular within the display area DA, but this disclosure is not limited thereto. The arrangement structure can be referred to as an RGBG matrix structure (e.g., Matrix structure or RGBG structure (e.g., structure)). It is a registered trademark of Samsung Display Co., Ltd. of South Korea. In some embodiments, the pixels PXL can be arranged in various structures and / or ways in the display area DA.

[0101] According to some implementations, pixels PXL of two or more types that emit light of different colors can be disposed in the display area DA. As an example, a first pixel PXL1 emitting a first color of light, a second pixel PXL2 emitting a second color of light, and a third pixel PXL3 emitting a third color of light can be arranged in the display area DA. At least one first pixel PXL1, at least one second pixel PXL2, and at least one third pixel PXL3 disposed adjacent to each other can constitute a pixel unit PXU capable of emitting light of various colors.

[0102] According to some embodiments, the first pixel PXL1 can be a red pixel emitting red light, the second pixel PXL2 can be a green pixel emitting green light, and the third pixel PXL3 can be a blue pixel emitting blue light. In some embodiments, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can each include a first-color light-emitting element (LD), a second-color light-emitting element (LD), and a third-color light-emitting element (LD) as light sources, thereby emitting first-color light, second-color light, and third-color light, respectively. In some embodiments, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can each include light-emitting elements (LDs) of the same color. However, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can each include light conversion layers (LCLs) of different colors disposed on the light-emitting elements (LDs), thereby emitting first-color light, second-color light, and third-color light, respectively.

[0103] However, the color, type, and / or number of pixels PXL that make up each pixel unit PXU are not particularly limited. For example, the color of the light emitted by each pixel PXL can be varied.

[0104] Pixel PXL may include at least one light source driven by control signals (e.g., setting or pre-defined control signals (e.g., scan signals and data signals)) and / or power sources (e.g., setting or pre-defined power sources (e.g., a first power source and a second power source)). In embodiments, the light source may include, according to... Figures 4a to 4d One or more light-emitting elements (LDs) in the embodiments are, for example, one or more rod-shaped light-emitting elements (LDs) having small dimensions ranging from nanometers to micrometers. In some embodiments, various types of light-emitting elements can be used as the light source for the pixel PXL. For example, in an embodiment, the light source for the pixel PXL can be formed using a light-emitting element with a core-shell structure.

[0105] In some implementations, the pixel PXL may have a structure according to at least one of the embodiments described below. For example, each pixel PXL may have a structure applying any of the embodiments described below, or may have a structure combining at least two embodiments.

[0106] In this embodiment, each pixel PXL can be formed as an active pixel, but this disclosure is not limited thereto. For example, pixel PXL can be formed as a pixel of a passive or active light-emitting display device having various structures and / or driving methods.

[0107] Figures 6a to 6c This is a circuit diagram illustrating a pixel PXL according to an embodiment of the present disclosure. For example, Figures 6a to 6c An implementation of a pixel PXL applicable to an active display device is shown, and different implementations related to the structure of the light-emitting unit (EMU) are also shown.

[0108] According to some implementation methods Figures 6a to 6c Each of the pixels PXL shown can be set in Figure 5 Any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 in the display panel DP. In some embodiments, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may have substantially the same or similar structures.

[0109] refer to Figures 6a to 6c The pixel PXL may include a light-emitting unit (EMU) that generates light with a brightness corresponding to the data signal. In some embodiments, the pixel PXL may also optionally include a pixel circuit (PXC) for driving the light-emitting unit (EMU).

[0110] The pixel circuit PXC can be connected between the first power supply VDD and the light-emitting unit EMU. Furthermore, the pixel circuit PXC can be connected to the scan line SL and data line DL of the corresponding pixel PXL to control the operation of the light-emitting unit EMU in response to the scan signals and data signals provided from the scan line SL and data line DL. In some embodiments, the pixel circuit PXC can also optionally be connected to the sensing signal line SSL and the sensing line SENL.

[0111] A pixel circuit (PXC) may include one or more transistors and capacitors. For example, a pixel circuit (PXC) may include a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor Cst.

[0112] The first transistor M1 is connected between the first power supply VDD and the first electrode ELT1 of the light-emitting unit EMU. The gate electrode of the first transistor M1 is connected to the first node N1. The first transistor M1 provides the drive current to the light-emitting unit EMU in response to the voltage control of the first node N1. That is, the first transistor M1 can be a drive transistor that controls the drive current of the pixel PXL.

[0113] In one embodiment, the first transistor M1 may optionally include a bottom metal layer BML (also referred to as a "bottom metal electrode", "bottom electrode", or "bottom light blocking layer"). The gate electrode of the first transistor M1 and the bottom metal layer BML may overlap each other and an insulating layer may be inserted between them.

[0114] In the described embodiment where the first transistor M1 includes a bottom metal layer BML, when driving the pixel PXL, a reverse bias technique (or synchronization technique) can be used as needed to apply a reverse bias voltage to the bottom metal layer BML of the first transistor M1 to move the threshold voltage of the first transistor M1 in a negative or positive direction. As an example, the bottom metal layer BML can be connected to one electrode of the first transistor M1 (e.g., a source electrode), and a source synchronization technique can be applied to move the threshold voltage of the first transistor M1 in a negative or positive direction. In some embodiments, when the bottom metal layer BML is disposed beneath the semiconductor layer constituting the channel of the first transistor M1, the bottom metal layer BML serves as a light-blocking pattern to stabilize the operating characteristics of the first transistor M1. However, the function and / or utilization methods of the bottom metal layer BML are not limited to this.

[0115] The second transistor M2 is connected between the data line DL and the first node N1. The gate electrode of the second transistor M2 is connected to the scan line SL. When a scan signal with a gate on-state voltage (e.g., a high-level voltage) is provided from the scan line SL, the second transistor M2 is turned on to electrically connect the data line DL and the first node N1.

[0116] During each frame period, the data signal for the corresponding frame is provided to the data line DL, and the data signal is transmitted to the first node N1 via a second transistor M2 that is turned on during the period of providing a scan signal with a gate on voltage. That is, the second transistor M2 can be a switching transistor for transmitting each data signal to the pixel PXL.

[0117] One electrode of the storage capacitor Cst is connected to the first node N1, and its other electrode is connected to the second electrode of the first transistor M1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1 during each frame period.

[0118] A third transistor M3 is connected between the first electrode ELT1 of the light-emitting unit EMU (or the second electrode of the first transistor M1) and the sensing line SENL. The gate electrode of the third transistor M3 is connected to the sensing signal line SSL. The third transistor M3 can transmit the voltage value applied to the first electrode ELT1 of the light-emitting unit EMU to the sensing line SENL based on the sensing signal provided to the sensing signal line SSL during a sensing period (e.g., a set or predetermined sensing period). The voltage value transmitted through the sensing line SENL can be provided to external circuitry (e.g., a timing controller), and the external circuitry can extract characteristic information (e.g., the threshold voltage of the first transistor M1, etc.) of each pixel PXL based on the provided voltage value. The extracted characteristic information can be used to convert image data to compensate for characteristic deviations between pixels PXL.

[0119] exist Figures 6a to 6c In this disclosure, transistors included in the pixel circuit PXC (e.g., all of the first transistor M1, the second transistor M2, and the third transistor M3) are shown as N-type transistors, but this disclosure is not necessarily limited thereto. That is, at least one of the first transistor M1 to the third transistor M3 may be changed to a P-type transistor.

[0120] In some implementations, the structure and driving method of pixel PXL can be varied. For example, besides Figures 6a to 6c In addition to the embodiments shown, the pixel circuit PXC can be formed as a pixel circuit with various structures and / or driving methods.

[0121] As an example, the pixel circuit PXC may not include the third transistor M3. In some embodiments, the pixel circuit PXC may also include other circuit elements, such as a compensation transistor for compensating the threshold voltage of the first transistor M1, an initialization transistor for initializing the voltage of the first electrode ELT1 of the first node N1 and / or the light-emitting unit EMU, an emitter control transistor for controlling the period of providing drive current to the light-emitting unit EMU, and / or a boost capacitor for boosting the voltage of the first node N1.

[0122] In this implementation, when pixel PXL is a pixel of a passive light-emitting display device, the pixel circuit PXC can be omitted. In this case, the light-emitting unit EMU can be directly connected to the scan line SL, data line DL, first power line PL1, second power line PL2 and / or other signal lines or power lines.

[0123] The light-emitting unit (EMU) may include one or more light-emitting elements (LDs) connected between a first power supply (VDD) and a second power supply (VSS).

[0124] For example, the light-emitting unit (EMU) may include a first electrode ELT1 (or also referred to as the "first pixel electrode" or "first alignment electrode") connected to a first power supply VDD via a pixel circuit PXC and a first power line PL1, a second electrode ELT2 (or also referred to as the "second pixel electrode" or "second alignment electrode") connected to a second power supply VSS via a second power line PL2, and a plurality of light-emitting elements (LDs) connected between the first electrode ELT1 and the second electrode ELT2.

[0125] The first power supply VDD and the second power supply VSS can have different potentials, causing the light-emitting element LD to emit light. As an example, the first power supply VDD can be set to a high potential power supply, and the second power supply VSS can be set to a low potential power supply.

[0126] In the implementation method, such as in Figure 6a As in the implementation, the light-emitting unit (EMU) may include a plurality of light-emitting elements (LDs) connected in parallel in the same direction between the first electrode ELT1 and the second electrode ELT2. Each of the light-emitting elements (LDs) may include a first terminal EP1 (e.g., a P-type terminal) connected to the first power supply VDD via the first electrode ELT1, the pixel circuit PXC, and the first power line PL1, and a second terminal EP2 (e.g., an N-type terminal) connected to the second power supply VSS via the second electrode ELT2 and the second power line PL2. That is, the light-emitting elements (LDs) may be connected in parallel in the forward direction between the first electrode ELT1 and the second electrode ELT2.

[0127] Each of the light-emitting elements (LDs) connected in the forward direction between the first power supply VDD and the second power supply VSS can constitute each effective light source. The effective light sources can be gathered to form the light-emitting unit (EMU) of the pixel PXL.

[0128] The first terminal EP1 of the light-emitting element LD can be connected to the pixel circuit PXC through one electrode of the light-emitting unit EMU (e.g., the first electrode ELT1), and can be connected to the first power supply VDD through the pixel circuit PXC and the first power line PL1. The second terminal EP2 of the light-emitting element LD can be connected to the second power supply VSS through another electrode of the light-emitting unit EMU (e.g., the second electrode ELT2) and the second power line PL2.

[0129] exist Figure 6a In the embodiments described, pixel PXL includes a light-emitting unit (EMU) with a parallel structure, but this disclosure is not limited thereto. For example, pixel PXL may include a light-emitting unit (EMU) with a series structure or a series-parallel structure. As an example, such as Figure 6b As in the implementation, the light-emitting unit (EMU) may include multiple light-emitting elements (LDs) divided and connected in two series stages.

[0130] refer to Figure 6b The light-emitting unit (EMU) may include a first series stage and a second series stage. The first series stage includes a first electrode ELT1, a second electrode ELT2, and one or more first light-emitting elements LD1 connected in the forward direction between the first electrode ELT1 and the second electrode ELT2. The second series stage includes a third electrode ELT3, a fourth electrode ELT4, and one or more second light-emitting elements LD2 connected in the forward direction between the third electrode ELT3 and the fourth electrode ELT4.

[0131] The first electrode of the light-emitting unit (EMU) (e.g., the first electrode ELT1) can be the anode of the EMU. The last electrode of the EMU (e.g., the fourth electrode ELT4) can be the cathode of the EMU. The remaining electrodes of the EMU (e.g., the second electrode ELT2 and the third electrode ELT3) can be integrally or non-integrally connected to each other to form a first intermediate electrode IET1. In this case, the second electrode ELT2 and the third electrode ELT3 can be integrally connected to be regarded as a single first intermediate electrode IET1.

[0132] In some implementations, the number of series stages constituting each light-emitting unit (EMU) can vary depending on the implementation method. For example, as... Figure 6c As in the implementation, the light-emitting unit (EMU) may include multiple light-emitting elements (LDs) divided and connected in four series stages.

[0133] refer to Figure 6cThe light-emitting unit (EMU) may include a first series stage, a second series stage, a third series stage, and a fourth series stage. The first series stage includes a first electrode ELT1, a second electrode ELT2, and one or more first light-emitting elements LD1 connected in the forward direction between the first electrode ELT1 and the second electrode ELT2. The second series stage includes a third electrode ELT3, a fourth electrode ELT4, and one or more second light-emitting elements LD2 connected in the forward direction between the third electrode ELT3 and the fourth electrode ELT4. The third series stage includes a fifth electrode ELT5, a sixth electrode ELT6, and one or more third light-emitting elements LD3 connected in the forward direction between the fifth electrode ELT5 and the sixth electrode ELT6. The fourth series stage includes a seventh electrode ELT7, an eighth electrode ELT8, and one or more fourth light-emitting elements LD4 connected in the forward direction between the seventh electrode ELT7 and the eighth electrode ELT8.

[0134] In other words, each cascade stage may include a pair of pixel electrodes (e.g., two pixel electrodes) and one or more light-emitting elements (LDs) connected between the pair of pixel electrodes. Here, the number of LDs constituting the cascade stage may be the same or different, and the number of LDs is not particularly limited.

[0135] The first pixel electrode (e.g., first electrode ELT1) of the light-emitting unit (EMU) can be the anode of the EMU. The last pixel electrode (e.g., eighth electrode ELT8) of the EMU can be the cathode of the EMU.

[0136] The remaining electrodes of the light-emitting unit (EMU) (e.g., the second electrode ELT2 to the seventh electrode ELT7) can constitute each intermediate electrode. For example, the second electrode ELT2 and the third electrode ELT3 can be integrally or non-integrally connected to each other to form the first intermediate electrode IET1. Similarly, the fourth electrode ELT4 and the fifth electrode ELT5 can be integrally or non-integrally connected to each other to form the second intermediate electrode IET2, and the sixth electrode ELT6 and the seventh electrode ELT7 can be integrally or non-integrally connected to each other to form the third intermediate electrode IET3. In this case, the second electrode ELT2 and the third electrode ELT3 can be integrally considered as a first intermediate electrode IET1, the fourth electrode ELT4 and the fifth electrode ELT5 can be integrally considered as a second intermediate electrode IET2, and the sixth electrode ELT6 and the seventh electrode ELT7 can be integrally considered as a third intermediate electrode IET3.

[0137] Assuming that the light-emitting unit (EMU) is formed using light-emitting elements (LDs) under the same conditions (e.g., the same size and / or number), power efficiency can be improved when the LDs are connected in series or series-parallel configurations. In some embodiments, in pixels PXL where the LDs are connected in parallel or series-parallel configurations, even if a short-circuit defect occurs in some series stages, a certain level of brightness can still be achieved through the remaining LDs in the series stages, thereby reducing the likelihood of dark spot defects in the pixel PXL.

[0138] Figures 6a to 6c Embodiments showing light-emitting elements (LDs) connected in parallel or series-parallel configurations are illustrated, but this disclosure is not limited thereto. For example, in one embodiment, the light-emitting elements (LDs) constituting the light-emitting unit (EMU) of each pixel PXL may be connected in series only.

[0139] Each of the light-emitting elements (LDs) may include a first terminal EP1 (e.g., a P-type terminal) connected to a first power supply VDD via a pixel electrode (e.g., a first electrode ELT1), a pixel circuit PXC, a first power line PL1, etc., and a second terminal EP2 (e.g., an N-type terminal) connected to a second power supply VSS via at least another pixel electrode (e.g., an eighth electrode ELT8), a second power line PL2, etc. That is, the light-emitting elements (LDs) can be connected in the forward direction between the first power supply VDD and the second power supply VSS. As described above, each of the light-emitting elements (LDs) connected in the forward direction between the first power supply VDD and the second power supply VSS can constitute each effective light source. The effective light sources can be concentrated to constitute the light-emitting unit (EMU) of pixel PXL.

[0140] When a drive current is provided through the corresponding pixel circuit (PXC), the light-emitting element (LD) can emit light with a brightness corresponding to the drive current. For example, during each frame period, the pixel circuit (PXC) can provide a drive current to the light-emitting unit (EMU) corresponding to the grayscale value presented in the corresponding frame. Therefore, while the light-emitting element (LD) emits light with a brightness corresponding to the drive current, the light-emitting unit (EMU) can also emit light with a brightness corresponding to the drive current.

[0141] In an implementation, in addition to the light-emitting element (LD) constituting the effective light source, the light-emitting unit (EMU) may also include at least one inactive light source. As an example, in at least one series stage, at least one inactive light-emitting element may be further connected, with the inactive light-emitting element arranged in opposite directions or with at least one end floating. Even when a positive driving voltage is applied between the pixel electrodes, the inactive light-emitting element can remain inactive and therefore can be substantially kept in a non-emitting state.

[0142] Figure 7 and Figure 8 This is a plan view illustrating pixel PXL according to an embodiment of the present disclosure. For example, Figure 7 An example structure of pixel region PXA is shown based on the light-emitting unit EMU in pixel PXL, which includes a series-parallel structure. Figure 8 An example structure of pixel region PXA is shown based on the light-emitting unit EMU in pixel PXL, which includes a parallel structure of light-emitting units EMU.

[0143] For the sake of convenience, although Figure 7 It shows having, as Figure 6b The present disclosure is not limited to the two-stage series-parallel structure of the light-emitting unit (EMU) in the embodiment described above. For example, the light-emitting unit (EMU) can be formed as a three-stage or more series-parallel structure (e.g., Figure 6c (A four-stage series-parallel structure), and the structure of the light-emitting unit (EMU) can be varied according to the number of series stages constituting the EMU.

[0144] Figure 7 and Figure 8 The described embodiments illustrate a light-emitting unit (EMU) with a parallel structure, wherein the first pixel electrode and the second pixel electrode are formed by dividing the electrodes, which are separated into four electrodes, into two groups and connecting the four electrodes; however, this disclosure is not limited thereto. For example, an EMU with a parallel structure may include fewer electrodes (e.g., two or three electrodes).

[0145] also, Figure 7 and Figure 8 An embodiment is shown in which the pixel region PXA has a rectangular plate shape comprising a pair of short sides and a pair of long sides. The extension direction of the short sides is indicated by a first direction DR1, and the extension direction of the long sides is indicated by a second direction DR2. However, the extension direction can be varied depending on the size and / or shape of the pixel region PXA.

[0146] First, refer to Figures 5 to 7 Pixel PXL may include multiple light-emitting element array regions AR corresponding to a series stage of light-emitting unit (EMU). For example, pixel PXL may include a first light-emitting element array region AR1 corresponding to a first series stage and a second light-emitting element array region AR2 corresponding to a second series stage. The first light-emitting element array region AR1 and the second light-emitting element array region AR2 may be configured to be spaced apart from each other in pixel region PXA.

[0147] When the light-emitting unit (EMU) of pixel PXL consists of only one cascaded stage, only a single light-emitting element array region AR (or emission region EA) can be set in pixel region PXA. However, as will be described below... Figure 8As in the implementation, even when the light-emitting unit (EMU) of pixel PXL includes only one series stage, multiple light-emitting elements (LDs) connected in parallel in the series stage can be divided and set in two or more light-emitting element array regions (ARs).

[0148] According to the described implementation, in each pixel region PXA, a region including at least one light-emitting element array region AR can constitute the emission region EA of the corresponding pixel PXL. The remaining regions of the pixel region PXA other than the emission region EA can be non-emission regions NEA. According to the implementation, the non-emission regions NEA can be disposed around the emission region EA to surround the emission region EA.

[0149] That is, the pixel region PXA may include an emitting region EA capable of emitting light through a light-emitting element LD and a non-emitting region NEA other than the emitting region EA. In some embodiments, the emitting region EA may include at least one light-emitting element array region AR corresponding to at least one cascaded level.

[0150] Each light-emitting element array region AR can be an area in which light-emitting elements LDs in each cascade stage can be arranged and / or aligned to emit light, and may also be referred to as a "light-emitting element alignment region" or "sub-emission region". Each light-emitting element array region AR may include at least one pair of pixel electrodes ELT and one or more light-emitting elements LDs connected between the pixel electrodes ELT.

[0151] For example, the first light-emitting element array region AR1 may include a first electrode ELT1, a second electrode ELT2, and one or more first light-emitting elements LD1 connected between the first electrode ELT1 and the second electrode ELT2. Similarly, the second light-emitting element array region AR2 may include a third electrode ELT3, a fourth electrode ELT4, and one or more second light-emitting elements LD2 connected between the third electrode ELT3 and the fourth electrode ELT4.

[0152] In some embodiments, each light-emitting element array region AR may further include a contact electrode CNE for stably connecting a pixel electrode ELT to an adjacent light-emitting element LD and / or for connecting two consecutive cascaded stages. In describing this embodiment, the first electrode ELT1 to the fourth electrode ELT4 are defined as pixel electrodes, and the contact electrode CNE will be described as an element separate from the pixel electrodes. However, this disclosure is not limited thereto. For example, the first electrode ELT1 to the fourth electrode ELT4 and the contact electrode CNE can be collectively considered as pixel electrodes.

[0153] According to some embodiments, the first light-emitting element array region AR1 and the second light-emitting element array region AR2 may have substantially the same or similar structures, but this disclosure is not limited thereto. In some embodiments, the number of light-emitting elements LD disposed in the first light-emitting element array region AR1 and the second light-emitting element array region AR2 may be the same or different, or the shapes of the pixel electrode ELT and / or the contact electrode CNE may be the same or different.

[0154] When describing the structure of a pixel PXL more globally, a pixel PXL may include multiple pixel electrodes ELT formed in a corresponding pixel region PXA, light-emitting elements LD arranged between the pixel electrodes ELT in each light-emitting element array region AR, and contact electrodes CNE for stably connecting the light-emitting elements LD to the pixel electrodes ELT.

[0155] According to some implementations, the pixel electrode ELT, the light-emitting element LD, and the contact electrode CNE can be sequentially arranged on a surface of the base layer BSL that forms the pixel PXL. The cross-sectional structure of the pixel PXL will be described in detail below.

[0156] The pixel electrode ELT may include at least one pair of electrodes disposed in each light-emitting element array region AR. For example, the pixel electrode ELT may include a first electrode ELT1 and a second electrode ELT2 disposed opposite to each other in a first light-emitting element array region AR1, and a third electrode ELT3 and a fourth electrode ELT4 disposed opposite to each other in a second light-emitting element array region AR2.

[0157] In each light-emitting element array region AR, the first electrode ELT1 to the fourth electrode ELT4 are arranged to be spaced apart from each other in the first direction DR1 and may extend in the second direction DR2, but this disclosure is not limited thereto. In an embodiment, the first direction DR1 may be horizontal (or row direction) and the second direction DR2 may be vertical (or column direction), but this disclosure is not limited thereto.

[0158] In some embodiments, in each pixel region PXA, the first electrode ELT1 to the fourth electrode ELT4 may have a uniform or non-uniform width, and may or may not include bent portions. That is, the shape and / or arrangement of each of the first electrode ELT1 to the fourth electrode ELT4 may vary depending on the embodiment.

[0159] Some of the first electrodes ELT1 to the fourth electrodes ELT4 can be formed in such a way that an alignment line is first formed and then broken to separate pixel electrodes ELT in the region between a pixel PXL and its adjacent pixels PXL (e.g., the upper and / or lower regions of each pixel region PXA). Therefore, the number of alignment signals used to align the light-emitting element LD in each pixel region PXA can be reduced, and each pixel electrode ELT can be formed as a separate electrode corresponding to each cascade stage in pixel PXL.

[0160] The pair of pixel electrodes ELTs constituting each cascade stage can be positioned relatively close to each other in each light-emitting element array region (AR), and can be positioned relatively far apart from each other in the remaining regions. For example, a pair of pixel electrodes ELTs can be positioned opposite each other with a first interval in each light-emitting element array region (AR), and can be positioned opposite each other with a second interval greater than the first interval in the non-emitting region (NEA).

[0161] Therefore, in the operation of providing and aligning the light-emitting elements (LDs) in each pixel region PXA, the LDs can be arranged in the desired area. For example, when aligning the LDs in the pixel region PXA by applying an alignment signal (e.g., setting or pre-setting an alignment signal) to the pixel electrodes ELTs (or alignment lines separated into pixel electrodes ELTs), a strong electric field is generated in the LD array region AR where the distance between adjacent pixel electrodes ELTs is relatively short. Therefore, the LDs can be arranged on adjacent pixel electrodes ELTs in the LD array region AR.

[0162] One of the pixel electrodes ELTs (e.g., the first electrode ELT1) can be connected to the pixel circuit PXC and / or the first power line PL1 via the first contact portion CNT1. The other pixel electrode ELT (e.g., the fourth electrode ELT4) can be connected to the second power line PL2 via the second contact portion CNT2.

[0163] According to some implementations, the pixel electrode ELT can be connected to the light-emitting element LD via the contact electrode CNE. For example, each pixel electrode ELT can be connected to at least one first end EP1 or second end EP2 of an adjacent light-emitting element LD via each contact electrode CNE.

[0164] Light-emitting elements (LDs) can be divided and arranged in a light-emitting element array region AR. The light-emitting elements (LDs) can be arranged between a pair of adjacent pixel electrodes (ELTs) disposed in each light-emitting element array region AR. Here, the light-emitting element (LD) arranged between the pair of adjacent pixel electrodes (ELTs) can mean that at least a portion of the region of the light-emitting element (LD) is disposed in the region between the pair of adjacent pixel electrodes (ELTs) and the region above and / or below it.

[0165] For example, a light-emitting element (LD) may include a first light-emitting element LD1 and a second light-emitting element LD2, which are divided and arranged in a first light-emitting element array region AR1 and a second light-emitting element array region AR2. The first light-emitting element LD1 may be connected between a first electrode ELT1 and a second electrode ELT2, and the second light-emitting element LD2 may be connected between a third electrode ELT3 and a fourth electrode ELT4.

[0166] In some implementations, the light-emitting element (LD) can be connected to each pixel electrode (ELT) via each contact electrode (CNE). In some implementations, the light-emitting elements (LDs) disposed in two consecutive series stages can be connected in series via at least one contact electrode (CNE).

[0167] For example, a pixel PXL may include a contact electrode CNE disposed on each pixel electrode ELT and connecting a first end EP1 or a second end EP2 of one or more light-emitting elements LD adjacent to the pixel electrode ELT to the pixel electrode ELT. As an example, a pixel PXL may include first contact electrodes CNE1 to third contact electrodes CNE3.

[0168] The first contact electrode CNE1 can be disposed on the first terminal EP1 of the first light-emitting element LD1 and the first electrode ELT1. The first contact electrode CNE1 can connect the first terminal EP1 of the first light-emitting element LD1 to the first electrode ELT1.

[0169] The second contact electrode CNE2 can be disposed on the second end EP2 of the first light-emitting element LD1 and the second electrode ELT2 to connect the second end EP2 of the first light-emitting element LD1 to the second electrode ELT2. In addition, the second contact electrode CNE2 can also be disposed on the first end EP1 of the second light-emitting element LD2 and the third electrode ELT3 to connect the first end EP1 of the second light-emitting element LD2 to the third electrode ELT3.

[0170] For this purpose, the second contact electrode CNE2 can extend from the first light-emitting element array region AR1 to the second light-emitting element array region AR2 to connect the second electrode ELT2 to the third electrode ELT3. In an embodiment, the second contact electrode CNE2 may include multiple individual electrodes disposed in the first light-emitting element array region AR1 and the second light-emitting element array region AR2, and these individual electrodes may be connected by bridging patterns or the like. The first series stage and the second series stage can be connected through the second contact electrode CNE2.

[0171] The third contact electrode CNE3 can be disposed on the second end EP2 of the second light-emitting element LD2 and the fourth electrode ELT4 to connect the second end EP2 of the second light-emitting element LD2 to the fourth electrode ELT4.

[0172] In the manner described above, the pixel electrode ELT and the light-emitting element LD can be connected in a desired form using the contact electrode CNE. For example, the first light-emitting element LD1 and the second light-emitting element LD2 can be connected in series using the contact electrode CNE.

[0173] In some implementations, to improve the utilization of the light-emitting elements (LDs) provided to each light-emitting element array region AR, the alignment signal used to align the LDs can be adjusted, or a magnetic field can be formed to bias and align the LDs, such that a larger number (or proportion) of LDs are aligned in a specific direction within the light-emitting element array region AR. In this case, the pixel electrode ELT can be connected using a contact electrode CNE according to the arrangement direction of more LDs. Therefore, the utilization of the LDs can be improved, and the light efficiency of the pixel PXL can be improved.

[0174] In the implementation, each contact electrode CNE is directly formed on the first end EP1 or the second end EP2 of the adjacent light-emitting element LD, and is connected to the first end EP1 or the second end EP2 of the light-emitting element LD.

[0175] In some embodiments, an insulating layer not shown (e.g., as described below) Figures 9a to 9c A first insulating layer (INS1) can be inserted between each contact electrode (CNE) and its corresponding pixel electrode (ELT), and each contact electrode (CNE) and its corresponding pixel electrode (ELT) can be connected through each contact hole (CH) passing through the insulating layer (e.g., first contact hole CH1 and second contact hole CH2). In this case, the pixel electrode (ELT) is stably covered by the insulating layer, thereby preventing the pixel electrode (ELT) from being damaged in subsequent processes.

[0176] For example, the first contact electrode CNE1 can be electrically connected to the first electrode ELT1 through the first contact hole CH1, and the third contact electrode CNE3 can be electrically connected to the fourth electrode ELT4 through the fourth contact hole CH4. The second contact electrode CNE2, which is commonly connected to the second electrode ELT2 and the third electrode ELT3, can be electrically connected to the second electrode ELT2 through the second contact hole CH2, and can be electrically connected to the third electrode ELT3 through the third contact hole CH3.

[0177] In this implementation, the pixel electrode ELT and its corresponding contact electrode CNE can be connected via a contact hole CH outside each light-emitting element array region AR (e.g., in the non-emitting region NEA). In this case, since the process of forming the contact hole CH in the insulating layer can be performed at least by avoiding the area where the light-emitting element LD is arranged, damage to the light-emitting element LD can be prevented or reduced.

[0178] refer to Figure 8 The light-emitting unit (EMU) can have a corresponding Figure 6a The implementation method uses a first-level series structure (i.e., a parallel structure). In this case, each pixel region PXA may include a single light-emitting element array region AR or may include multiple light-emitting element array regions AR.

[0179] For example, such as Figure 7 As in the implementation method, even in Figure 8 In this embodiment, the first electrode ELT1 and the second electrode ELT2 can be disposed in the first light-emitting element array region AR1, and the third electrode ELT3 and the fourth electrode ELT4 can be disposed in the second light-emitting element array region AR2. The first electrode ELT1 and the third electrode ELT3 can be connected using a first contact electrode CNE1, and the second electrode ELT2 and the fourth electrode ELT4 can be connected using a second contact electrode CNE2. In this case, the first electrode ELT1 and the third electrode ELT3 can be electrically formed into one electrode (e.g., a first pixel electrode), and the second electrode ELT2 and the fourth electrode ELT4 can be electrically formed into one electrode (e.g., a second pixel electrode). The light-emitting element LD connected between the first electrode ELT1 and the second electrode ELT2 can be connected in parallel with the light-emitting element LD connected between the third electrode ELT3 and the fourth electrode ELT4.

[0180] In another embodiment, only one of the first electrode ELT1 and the third electrode ELT3 may be formed, and / or only one of the second electrode ELT2 and the fourth electrode ELT4 may be formed.

[0181] Figures 9a to 9c This is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure. For example, Figures 9a to 9c It shows along Figure 7 Different implementations of the cross-section of pixel PXL intercepted by line I-I'. Figure 9a Compared to the implementation method, Figure 9b The implementation also includes residual RSD of the conductive film within the cavity CVT, and Figure 9c The implementation also includes an insulating pattern INP disposed on the contact electrode CNE.

[0182] As an example of a circuit element that can be set in the pixel circuitry layer (PCL) Figures 9a to 9c An arbitrary transistor M is shown (e.g., a transistor M connected to the first electrode ELT1 via a first contact portion CNT1 and a bridging pattern BRP). In some embodiments, as an example of a line that can be disposed in the pixel circuit layer PCL, Figures 9a to 9c The second power line PL2 is shown, which is connected to the fourth electrode ELT4 via the second contact portion CNT2.

[0183] First, refer to Figures 5 to 9a According to the embodiments described in this disclosure, the pixel PXL and the display panel DP including the pixel PXL may include a pixel circuit layer PCL and a display element layer DPL disposed on one surface of the base layer BSL and overlapping each other. For example, the display area DA may include a pixel circuit layer PCL disposed on one surface of the base layer BSL and a display element layer DPL disposed on the pixel circuit layer PCL. However, the relative positions of the pixel circuit layer PCL and the display element layer DPL on the base layer BSL may vary depending on the embodiment.

[0184] The circuit elements of the pixel circuit PXC constituting the corresponding pixel PXL and the lines connected to it can be disposed in each pixel region PXA of the pixel circuit layer PCL. For example, the pixel circuit layer PCL may include a plurality of transistors M and storage capacitors Cst disposed in each pixel region PXA and constituting the pixel circuit PXC of the corresponding pixel PXL. In some embodiments, the pixel circuit layer PCL may also include one or more power lines and / or signal lines connected to each pixel circuit PXC and / or light-emitting unit EMU. For example, the pixel circuit layer PCL may include a first power line PL1, a second power line PL2, and signal lines such as scan lines SL and data lines DL.

[0185] In some embodiments, in addition to circuit elements and lines, the pixel circuit layer PCL may include multiple insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and / or a protective layer PSV, which are sequentially stacked on one surface of the base layer BSL. According to some embodiments, the protective layer PSV may be formed entirely in the display area DA to cover the circuit elements of each pixel PXL and the lines connected thereto, but this disclosure is not limited thereto.

[0186] In some embodiments, the pixel circuit layer PCL may further include a first conductive layer, which includes at least one light-blocking layer (or a bottom metal layer BML of the transistor M) disposed below at least some of the transistors M. The first conductive layer may include at least one conductive material that is conductive, and the conductive material that can constitute the first conductive layer is not particularly limited.

[0187] A buffer layer (BFL) can be disposed on a surface of the base layer (BSL) on which a first conductive layer is optionally formed. The buffer layer (BFL) can prevent or substantially prevent impurities from diffusing into each circuit element. The buffer layer (BFL) can be formed as a single layer or multiple layers and can include at least one inorganic insulating material and / or an organic insulating material. For example, the buffer layer (BFL) can include various types of organic / inorganic insulating materials, such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ) and silicon oxynitride (SiO) x N y ).

[0188] A semiconductor layer may be disposed on a buffer layer BFL. The semiconductor layer may include a semiconductor pattern SCP for each transistor M. The semiconductor pattern SCP may include a channel region overlapping the gate electrode GE and a first conductive region and a second conductive region (e.g., a source region and a drain region) disposed on both sides of the channel region.

[0189] According to some embodiments, the semiconductor pattern SCP can be a semiconductor pattern made of polycrystalline silicon, amorphous silicon, or oxide semiconductor. In some embodiments, the channel region of the semiconductor pattern SCP can be an undoped semiconductor pattern and can be an intrinsic semiconductor, and the first conductive region and the second conductive region of the semiconductor pattern SCP can each be a doped semiconductor pattern (e.g., a set or predetermined impurity).

[0190] In some implementations, the semiconductor pattern SCP of the transistor M constituting each pixel circuit PXC can be made of substantially the same or similar materials. For example, the semiconductor pattern SCP of the transistor M can be made of the same material selected from polycrystalline silicon, amorphous silicon, and oxide semiconductors.

[0191] In an implementation, some and other transistors in transistor M may include semiconductor patterns SCPs made of different materials. For example, in transistor M, the semiconductor patterns SCPs of some transistors may be made of polycrystalline silicon or amorphous silicon, and the semiconductor patterns SCPs of the remaining transistors M may be made of oxide semiconductors.

[0192] A gate insulating layer GI can be disposed on a semiconductor layer. The gate insulating layer GI can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or at least one organic insulating material. For example, the gate insulating layer GI can include various types of organic / inorganic insulating materials, such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ) and silicon oxynitride (SiO) x N y ).

[0193] A second conductive layer may be disposed on the gate insulating layer GI. The second conductive layer may include the gate electrode GE of each transistor M. For example, the gate electrode GE may be configured to overlap with each semiconductor pattern SCP, with the gate insulating layer GI interposed therebetween. In some embodiments, the second conductive layer may also include an electrode and / or line (e.g., a set or predetermined line) of a storage capacitor Cst (e.g., a scan line SL). The second conductive layer may include at least one conductive material having conductivity, and the conductive material capable of constituting the second conductive layer is not particularly limited.

[0194] The first interlayer insulating layer ILD1 can be disposed on the second conductive layer. The first interlayer insulating layer ILD1 can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or at least one organic insulating material. For example, the first interlayer insulating layer ILD1 can include various types of organic / inorganic insulating materials, including silicon nitride (SiN). x ), silicon dioxide (SiO) x ) and silicon oxynitride (SiO) x N y Furthermore, the materials constituting the first interlayer insulation layer ILD1 are not particularly restricted.

[0195] A third conductive layer may be disposed on the first interlayer insulating layer ILD1. The third conductive layer may include a first transistor electrode TE1 and a second transistor electrode TE2 for each transistor M. Here, the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode and a drain electrode, respectively. The first transistor electrode TE1 and the second transistor electrode TE2 of the transistor M may be connected to a first conductive region and a second conductive region of the semiconductor pattern SCP of the respective transistor M through corresponding vias passing sequentially through the first interlayer insulating layer ILD1 and the gate insulating layer GI. In some embodiments, the third conductive layer may also include an electrode and / or a line (e.g., a set or predetermined line) of a storage capacitor Cst (e.g., a data line DL). The third conductive layer may include at least one conductive material to be conductive, and the conductive material capable of constituting the third conductive layer is not particularly limited.

[0196] The second interlayer insulating layer (ILD2) can be disposed on the third conductive layer. The second interlayer insulating layer (ILD2) can be formed as a single layer or multiple layers, and can include at least one inorganic insulating material and / or at least one organic insulating material. For example, the second interlayer insulating layer (ILD2) can include various types of organic / inorganic insulating materials, including silicon nitride (SiN). x ), silicon dioxide (SiO) x ) and silicon oxynitride (SiO) x N y Furthermore, the materials constituting the second interlayer insulation layer ILD2 are not particularly restricted.

[0197] A fourth conductive layer may be disposed on the second interlayer insulating layer ILD2. The fourth conductive layer is a bridging pattern BRP and / or line (e.g., set or predetermined lines (e.g., first power line PL1 and / or second power line PL2)) connecting the pixel circuit layer PCL and the display element layer DPL. The bridging pattern BRP can be connected to the first pixel electrode (e.g., first electrode ELT1) of the light-emitting unit EMU via a first contact portion CNT1. The second power line PL2 can be connected to the last pixel electrode (e.g., fourth electrode ELT4) of the light-emitting unit EMU via a second contact portion CNT2. The fourth conductive layer may include at least one conductive material to be conductive, and the conductive material capable of constituting the fourth conductive layer is not particularly limited.

[0198] A protective layer PSV can be disposed on the fourth conductive layer. The protective layer PSV can be formed as a single layer or multiple layers and can include at least one inorganic insulating material and / or at least one organic insulating material. For example, the protective layer PSV may include at least one organic insulating layer and can substantially planarize the surface of the pixel circuit layer PCL. In embodiments, the organic insulating film may include at least one selected from acrylic resins (polyacrylate resins), epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, and benzocyclobutene resins, but this disclosure is not limited thereto.

[0199] In embodiments of this disclosure, the protective layer PSV can be etched to a thickness in at least one light-emitting element array region AR in which a light-emitting element LD is disposed, thereby forming a cavity CVT beneath the light-emitting element LD. For example, the protective layer PSV can form a cavity CVT beneath the light-emitting element LD by etching a first width W1 beneath the light-emitting element LD.

[0200] The display element layer (DPL) can be disposed on the protective layer (PSV). The display element layer (DPL) may include a light-emitting unit (EMU) for each pixel (PXL). The light-emitting unit (EMU) can be connected to the pixel circuit (PXC) and / or power lines (e.g., setting or pre-setting power lines (e.g., second power line PL2) of the corresponding pixel (PXL) through one or more contact portions (e.g., first contact portion CNT1 and second contact portion CNT2) passing through the protective layer (PSV). Each contact portion may be formed in the form of at least one contact hole or at least one through hole, but this disclosure is not limited thereto.

[0201] For example, the pixel electrode ELT, light-emitting element LD, and contact electrode CNE constituting the light-emitting unit EMU of the corresponding pixel PXL can be disposed in each pixel region PXA of the display element layer DPL. For example, the display element layer DPL may include multiple pixel electrodes ELT (e.g., first electrode ELT1 to fourth electrode ELT4) disposed in the light-emitting element array region AR of each pixel PXL, multiple light-emitting elements LD connected in series, parallel, or series-parallel between the pixel electrodes ELT, and multiple contact electrodes CNE connecting the pixel electrodes ELT and the light-emitting elements LD.

[0202] exist Figures 9a to 9c In each of them, a light-emitting element LD is shown, but as in Figure 7 and Figure 8 As in the implementation, each pixel PXL may include multiple light-emitting elements LD connected in the forward direction between the first pixel electrode and the last pixel electrode (e.g., the first electrode ELT1 and the fourth electrode ELT4). Therefore, in the description Figures 9a to 9cIn the implementation of this method and other implementations described below, it is assumed that each pixel PXL includes multiple light-emitting elements LD.

[0203] In some embodiments, the display element layer DPL may further include at least one conductive layer and / or at least one insulating layer. For example, the display element layer DPL may further include a first insulating layer INS1 disposed on the pixel electrode ELT, and may optionally include an outer coating OC that completely covers the upper portion of the light-emitting unit EMU in which the pixel electrode ELT, light-emitting element LD, contact electrode CNE, etc. are formed.

[0204] Pixel electrodes ELTs can be configured to be spaced apart from each other in the emission region EA. As an example, in each light-emitting element array region AR, the pair of adjacent pixel electrodes ELTs (e.g., first electrode ELT1 and second electrode ELT2 or third electrode ELT3 and fourth electrode ELT4) can be opposite each other on the protective layer PSV.

[0205] According to some implementations, each pixel electrode ELT may have a separate pattern for each pixel PXL or a pattern commonly connected to multiple pixels PXL. For example, each of the first electrode ELT1 to the fourth electrode ELT4 may have an independent pattern in which its two ends are disconnected in the peripheral region of the corresponding pixel region PXA and / or in the region between adjacent pixel regions PXA. In an implementation, at least one pixel electrode (e.g., the first electrode ELT1) may have an independent pattern that is disconnected in the peripheral region of the corresponding pixel region PXA and / or in the region between adjacent pixel regions PXA. One end of at least another pixel electrode (e.g., the fourth electrode ELT4) may extend in a first direction DR1 or a second direction DR2 and may be integrally connected to the pixel electrode (e.g., a set or predetermined pixel electrode) of another adjacent pixel PXL in the first direction DR1 or the second direction DR2 (e.g., the fourth electrode ELT4 of the adjacent pixel PXL).

[0206] The pixel electrode ELT may include at least one conductive material to be conductive. As an example, the pixel electrode ELT may include at least one metal selected from various metallic materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and copper (Cu), or an alloy including said at least one metal. Alternatively, the pixel electrode ELT may include at least one conductive material selected from conductive oxides and conductive polymers. Conductive oxides may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), or fluorine-doped tin oxide (FTO). Conductive polymers may include poly(3,4-ethylenedioxythiophene) (PEDOT), but this disclosure is not limited thereto. For example, the pixel electrode ELT may include other conductive materials, such as carbon nanotubes or graphene. In other words, the pixel electrode ELT may include at least one conductive material selected from a variety of conductive materials to have conductivity, and the materials constituting the pixel electrode ELT are not particularly limited. In some embodiments, the pixel electrode ELT may include the same conductive material or different conductive materials.

[0207] Furthermore, each of the pixel electrodes ELTs can be formed as a single layer or multiple layers. As an example, each of the pixel electrodes ELTs may include a reflective electrode layer comprising a reflective conductive material. In some embodiments, each of the pixel electrodes ELTs may also optionally include at least one transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive capping layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0208] A first insulating layer INS1 is disposed on one surface of the base layer BSL (including the pixel electrode ELT). According to some embodiments, the first insulating layer INS1 may be formed first to completely cover the first electrode ELT1 and the second electrode ELT2. After the light-emitting element LD is provided and aligned on the first insulating layer INS1, the first insulating layer INS1 is partially opened to expose a region of the pixel electrode ELT, or one or more contact holes (e.g., first contact hole CH1 and second contact hole CH2) may be formed in the first insulating layer INS1 to connect the pixel electrode ELT to the contact electrode CNE. Because the pixel electrode ELT is formed and then covered by the first insulating layer INS1, damage to the pixel electrode ELT in subsequent processes can be prevented or reduced.

[0209] The first insulating layer INS1 can be formed as a single layer or multiple layers, and may include at least one inorganic insulating material and / or at least one organic insulating material. In an embodiment, the first insulating layer INS1 may include at least one inorganic insulating film, the inorganic insulating film including at least one inorganic insulating material, such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or aluminum oxide (AlO x ).

[0210] In embodiments of this disclosure, the first insulating layer INS1 may have an opening of a second width W2 in at least one light-emitting element array region AR in which a light-emitting element LD is disposed, thereby forming a cavity CVT below the light-emitting element LD. According to some embodiments, the second width W2 may be smaller than the length of the light-emitting element LD (see [link to relevant documentation]). Figure 4a (L). As an example, the second width W2 can be 0.5 μm smaller or larger than the length L of the light-emitting element LD. Therefore, the light-emitting element LD can be stably arranged on the cavity CVT.

[0211] In embodiments of this disclosure, the cavity CVT can have a reverse conical shape. For example, the cavity CVT can have a first width W1 in its lower region corresponding to the protective layer PSV, and a second width W2 smaller than the first width W1 in its upper region corresponding to the first insulating layer INS1. In this case, during the process of forming the contact electrode CNE performed after forming the cavity CVT, the conductive layer can be automatically disconnected (or opened) during the process of forming the conductive layer to form the contact electrode CNE. Therefore, short-circuit defects between the first end EP1 and the second end EP2 of the light-emitting element LD can be effectively prevented.

[0212] Light-emitting elements (LDs) can be provided and aligned in each emission region EA (or each light-emitting element array region AR) in which a first insulating layer INS1, etc., is formed. In an embodiment, a dam structure, such as a dike, can be formed in the display region DA before the LDs are provided to surround each emission region EA (or each light-emitting element array region AR). Subsequently, multiple light-emitting elements (LDs) can be provided to the emission region EA of each pixel PXL by inkjet printing, slot coating, or various other methods, and alignment signals (e.g., setting or pre-setting alignment signals) (or alignment voltages) can be applied to each of the pixel electrodes ELT (e.g., alignment lines divided into pixel electrodes ELTs) to align the LDs between the pixel electrodes ELT.

[0213] In one embodiment, the light-emitting element (LD) may be disposed on the first insulating layer INS1, arranged in the region between a pair of adjacent pixel electrodes ELTs disposed in each emitting region EA (or each light-emitting element array region AR). In some embodiments, the light-emitting element (LD) may be arranged to overlap with or not overlap with at least one of the pair of pixel electrodes ELTs.

[0214] For example, at least one first light-emitting element LD1 can be disposed on the first insulating layer INS1 in the region between the first electrode ELT1 and the second electrode ELT2, such that the first end EP1 and the second end EP2 of the first light-emitting element LD1 face the first electrode ELT1 and the second electrode ELT2, respectively. The first end EP1 of the first light-emitting element LD1 may overlap with or may not overlap with the first electrode ELT1, and the second end EP2 of the first light-emitting element LD1 may overlap with or may not overlap with the second electrode ELT2.

[0215] Similarly, at least one second light-emitting element LD2 can be disposed on the first insulating layer INS1 in the region between the third electrode ELT3 and the fourth electrode ELT4, such that the first end EP1 and the second end EP2 of the second light-emitting element LD2 face the third electrode ELT3 and the fourth electrode ELT4, respectively. The first end EP1 of the second light-emitting element LD2 may overlap with or may not overlap with the third electrode ELT3, and the second end EP2 of the second light-emitting element LD2 may overlap with or may not overlap with the fourth electrode ELT4.

[0216] In embodiments of this disclosure, the light-emitting element LD can be disposed on the first insulating layer INS1 to be positioned on the cavity CVT. For example, the central region of the first light-emitting element LD1 can be located on the cavity CVT, and the first end EP1 and the second end EP2 of the first light-emitting element LD1 can be disposed on the first insulating layer INS1 at both sides of the cavity CVT.

[0217] exist Figures 9a to 9c In the diagram, a cross-section of pixel PXL is shown based on a first light-emitting element LD1, but the cavity CVT can also be formed below a second light-emitting element LD2. The second light-emitting element LD2 can be disposed on the cavity CVT in substantially the same structure and / or manner as the first light-emitting element LD1.

[0218] Contact electrodes CNE can be respectively disposed on the first end EP1 and the second end EP2 of the light-emitting element LD. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on the first end EP1 and the second end EP2 of the first light-emitting element LD1, and on the first electrode ELT1 and the second electrode ELT2. The first contact electrode CNE1 connects the first end EP1 of the first light-emitting element LD1 to the first electrode ELT1 through the first contact hole CH1. The second contact electrode CNE2 connects the second end EP2 of the first light-emitting element LD1 to the second electrode ELT2 through the second contact hole CH2.

[0219] Similarly, the second contact electrode CNE2 and the third contact electrode CNE3 can be respectively disposed on the first end EP1 and the second end EP2 of the second light-emitting element LD2 (e.g., on the third electrode ELT3 and the fourth electrode ELT4). The second contact electrode CNE2 connects the first end EP1 of the second light-emitting element LD2 to the third electrode ELT3 through the third contact hole CH3. The third contact electrode CNE3 connects the second end EP2 of the second light-emitting element LD2 to the fourth electrode ELT4 through the fourth contact hole CH4.

[0220] The contact electrode CNE can be made of various transparent conductive materials. As an example, the contact electrode CNE may include at least one selected from various transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), indium oxide (In₂O₃), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO). Therefore, light emitted from the light-emitting element LD through the corresponding first terminal EP1 and second terminal EP2 can pass through the contact electrode CNE to be emitted to the outside of the pixel PXL.

[0221] In embodiments of this disclosure, contact electrodes CNEs can be disposed on the same layer and can be formed at the same time (e.g., in parallel or simultaneously). For example, contact electrodes CNEs can be formed from a conductive film and can be patterned at the same time (e.g., in parallel or simultaneously). As an example, a pair of contact electrodes CNEs disposed in each light-emitting element array region AR (e.g., first contact electrode CNE1 and second contact electrode CNE2, or second contact electrode CNE2 and third contact electrode CNE3) can be separated by a single mask process to be spaced apart from each other on a cavity CVT formed in the light-emitting element array region AR. The pair of contact electrodes CNEs can be stably disconnected (or opened) by the cavity CVT and can be spaced apart from each other in the upper region of the cavity CVT by a second width W2 (i.e., a distance corresponding to the second width W2).

[0222] When the contact electrodes CNE are patterned at the same time (e.g., in parallel or simultaneously) as described above, the manufacturing process of the pixel PXL and the display panel DP including the pixel PXL can be simplified. In some embodiments, when the cavity CVT is formed below the light-emitting element LD, the conductive film can be stably disconnected below the light-emitting element LD during the process of patterning and / or forming the conductive film for forming the contact electrodes CNE. Therefore, electrical stability can be ensured and short-circuit defects between the first terminal EP1 and the second terminal EP2 of the light-emitting element LD can be prevented.

[0223] The outer coating OC can be disposed on the contact electrode CNE. For example, the outer coating OC can be completely formed in the display area DA to cover the pixel electrode ELT, the first insulating layer INS1, the light-emitting element LD, and the contact electrode CNE. The outer coating OC may include at least one inorganic film and / or organic film. In some embodiments, the outer coating OC may be made of a low-refractive-index material to improve the light efficiency of the pixel PXL.

[0224] In embodiments, the outer coating OC may include a thin-film encapsulation layer with a multilayer structure. For example, the outer coating OC may be formed as a thin-film encapsulation layer with a multilayer structure, including at least two inorganic insulating layers and at least one organic insulating layer interposed between the at least two inorganic insulating layers. However, the structural materials and / or structure of the outer coating OC can be varied.

[0225] refer to Figure 9b When the conductive material introduced into the cavity CVT is not completely removed during the process of forming the conductive film used to form the contact electrode CNE, the pixel PXL may include residual conductive film RSD remaining on or inside the cavity CVT. The residual conductive film RSD may include the same material as the contact electrode CNE.

[0226] However, when the residual RSD of the conductive film remains below one of the pair of pixel electrodes ELT (e.g., only below one of the pair of pixel electrodes ELT) or even when the residual RSD remains below the pair of pixel electrodes ELT, the residual RSD of the conductive film below the pair of pixel electrodes ELT can be separated from each other. For example, the conductive film used to form the contact electrode CNE can be completely removed from the bottom surface (e.g., the central region) of the cavity CVT, and therefore, the residual RSD of the conductive film below the pair of pixel electrodes ELT can be separated from each other. Therefore, the residual RSD of the conductive film can not cause short-circuit defects.

[0227] refer to Figure 9cPixel PXL may further include insulating patterns INP disposed on the contact electrode CNE. For example, pixel PXL may further include a first insulating pattern INP1 disposed on the first contact electrode CNE1 and a second insulating pattern INP2 disposed on the second contact electrode CNE2 and separated from the first insulating pattern INP1. In some embodiments, when pixel PXL includes a third contact electrode CNE3, pixel PXL may further include an insulating pattern disposed on the third contact electrode CNE3.

[0228] In some embodiments, an insulating pattern INP can be formed using a photomask used in the process of forming a patterned conductive film for the contact electrode CNE. For example, after the contact electrode CNE is formed, the photomask may not be removed and may be cured to form an insulating pattern INP that stably anchors the light-emitting element LD and the contact electrode CNE. In this case, the insulating pattern INP may comprise the same photoresist material. In some embodiments, the area in which each insulating pattern INP is formed may correspond to the area in which each contact electrode CNE is formed. For example, a first contact electrode CNE1 may be located below a first insulating pattern INP1 (e.g., only below the first insulating pattern INP1), and a second contact electrode CNE2 may be located below a second insulating pattern INP2 (e.g., only below the second insulating pattern INP2).

[0229] exist Figures 9a to 9c In one embodiment, the pixel PXL includes at least one cavity CVT located below the light-emitting element LD. As an example, the pixel PXL may include at least one cavity CVT disposed in each light-emitting element array region AR.

[0230] Each cavity CVT can be formed in a protective layer PSV and a first insulating layer INS1 to correspond to the region between a pair of pixel electrodes ELTs opposite each other in each light-emitting element array region AR, below one or more light-emitting elements LDs (e.g., multiple first light-emitting elements LD1 or multiple second light-emitting elements LD2) arranged in each light-emitting element array region AR. The cavity CVT can have a first width W1 corresponding to the etch width of the protective layer PSV in its lower region corresponding to the protective layer PSV and a second width W2 corresponding to the etch width of the first insulating layer INS1 in its upper region corresponding to the first insulating layer INS1. In this case, the second width W2 can be smaller than the length L of each light-emitting element LD. Therefore, the light-emitting elements LD can be arranged on the cavity CVT between a pair of pixel electrodes ELTs.

[0231] According to the embodiments described in this disclosure, during the process of forming and etching the conductive film for forming the contact electrode CNE, the contact electrode CNE can be automatically and / or effectively disconnected via the cavity CVT. Therefore, the contact electrode CNE can be formed simultaneously using a single photomask, and furthermore, short-circuit defects between the first end EP1 and the second end EP2 of the light-emitting element LD can be prevented.

[0232] In this implementation, the second width W2 can be smaller than the first width W1, and therefore the cavity CVT can have a reverse tapered shape. In this case, the conductive film can be automatically disconnected via the cavity CVT during the process of forming the conductive film to form the contact electrode CNE (e.g., deposition). Therefore, short-circuit defects between the first end EP1 and the second end EP2 of the light-emitting element LD can be prevented more effectively.

[0233] Figure 10 This is a plan view illustrating pixel PXL according to an embodiment of the present disclosure. For example, Figure 10 It shows Figure 7 The implementation method is modified.

[0234] Figures 11a to 11c This is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure. For example, Figures 11a to 11c It shows along Figure 10 Different implementations of the cross-section of pixel PXL intercepted by line II-II' are shown. Figures 9a to 9c The implementation method is modified.

[0235] In description Figures 10 to 11c When implementing the method, with Figures 7 to 9c Components that are identical or similar to those in the embodiments are indicated by the same reference numerals, and their detailed descriptions will be omitted.

[0236] refer to Figures 10 to 11c The pixel PXL may also include a first dam BNK1 and a second dam BNK2. The first dam BNK1 is disposed at least in the emission region EA to overlap with the pixel electrode ELT, and the second dam BNK2 may be disposed in the non-emission region NEA to surround each emission region EA. Figures 10 to 11c In some embodiments, pixel PXL is shown to include both the first dam BNK1 and the second dam BNK2, but this disclosure is not limited thereto. For example, in some embodiments, pixel PXL may include only one of the first dam BNK1 and the second dam BNK2.

[0237] The first dam BNK1 can be disposed below the pixel electrode ELT. For example, the first dam BNK1 can be disposed below the pixel electrode ELT to overlap with a region of each of the pixel electrodes ELT in the thickness direction of the substrate.

[0238] The first embankment BNK1 can be used to form the wall structure surrounding the light-emitting element LD, and can be formed in a separate pattern or a single integrated pattern. For example, as Figures 10 to 11c As shown, the first dam BNK1 may include multiple individual dam patterns, each overlapping a region of at least one pixel electrode ELT and separated between a pair of adjacent pixel electrodes ELT. However, this disclosure is not limited thereto. For example, in an embodiment, the first dam BNK1 may be formed as an integral dam pattern including openings or slots corresponding to each light-emitting element array region AR.

[0239] The first dike BNK1 may include an insulating material, which includes at least one inorganic material and / or at least one organic material. As an example, the first dike BNK1 may include at least one inorganic film, which includes various inorganic insulating materials, such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ) and silicon oxynitride (SiO) x N y Alternatively, the first dike BNK1 may include at least one organic film, which includes various organic insulating materials, or the first dike BNK1 may be formed as a single-layer insulator or a multi-layer insulator comprising a combination of organic and inorganic materials. That is, the structural materials and / or pattern shape of the first dike BNK1 can be varied.

[0240] Because the first dam BNK1 is located below a region of each of the pixel electrodes ELT, the pixel electrode ELT can protrude upward in the region where the first dam BNK1 is formed. Therefore, the first dam BNK1 can form a reflective dam (also called a "reflective barrier") together with the pixel electrode ELT. For example, the pixel electrode ELT and / or the first dam BNK1 can be made of a reflective material, or at least one reflective film with reflectivity can be formed on the protruding sidewalls of the pixel electrode ELT and / or the first dam BNK1. Therefore, light emitted from the first end EP1 and the second end EP2 of the light-emitting element LD facing the pixel electrode ELT can be directed more towards the front of the display panel DP. As described above, when a region of the pixel electrode ELT protrudes upward using the first dam BNK1, the proportion of light directed towards the front of the display panel DP from the light generated from the pixel PXL can be increased, thereby improving the light efficiency of the pixel PXL.

[0241] The second dike BNK2 can be a structure that defines the emission region EA of each pixel PXL, and can be, for example, a pixel defining film. For example, the second dike BNK2 can be disposed around the emission region EA of each pixel PXL. As an example, the second dike BNK2 can be disposed in the boundary region of each pixel region PXA and / or in the region between adjacent pixel regions PXA.

[0242] The second dam BNK2 may partially overlap with the pixel electrode ELT or may not partially overlap with the pixel electrode ELT. For example, each pixel electrode ELT may extend into the non-emitting region NEA to overlap with the second dam BNK2, or it may be disconnected in the emitting region EA to not overlap with the second dam BNK2.

[0243] In some embodiments, the second dam BNK2 may overlap with the first contact portion CNT1 and / or the second contact portion CNT2, or it may not overlap with the first contact portion CNT1 and / or the second contact portion CNT2. For example, the first contact portion CNT1 and / or the second contact portion CNT2 may be formed in the non-emission region NEA to overlap with the second dam BNK2, or it may be formed in the emission region EA to not overlap with the second dam BNK2.

[0244] The second barrier BNK2 may include at least one light-blocking material and / or at least one reflective material to prevent light leakage between adjacent pixels PXL. For example, the second barrier BNK2 may include at least one black matrix material selected from various types of black matrix materials (e.g., at least one light-blocking material currently known) and / or a color filter material with a specific color. As an example, the second barrier BNK2 may be formed as a black opaque pattern to block light transmission. In an embodiment, a reflective film (not shown) may be formed on the surface (e.g., sidewall) of the second barrier BNK2 to further increase the light efficiency of the pixel PXL.

[0245] In some implementations, during the operation of providing the light-emitting element LD to each pixel PXL, the second dam BNK2 can serve as a dam structure defining each emission region EA to which the light-emitting element LD should be provided. For example, each emission region EA can be separated by the second dam BNK2, and thus, the desired type and / or amount of light-emitting element ink can be provided to the emission region EA.

[0246] In some embodiments, during the process of forming the first dike BNK1, the second dike BNK2 may be formed in parallel with (e.g., simultaneously or substantially simultaneously with) the first dike BNK1 on the same layer. In other embodiments, the second dike BNK2 may be formed in the same layer or a different layer from the first dike BNK1 by a process separate from the process of forming the first dike BNK1. As an example, the second dike BNK2 may be formed on the first dike BNK1 (e.g., on the first insulating layer INS1). In some embodiments, the position of the second dike BNK2 may vary depending on the implementation. Furthermore, the second dike BNK2 may partially overlap with the first dike BNK1 or may not partially overlap with the first dike BNK1.

[0247] Figures 12a to 12l This is a cross-sectional view showing a method for manufacturing a display device DD according to embodiments of the present disclosure. For example, Figures 12a to 12l The sequence shows the manufacturing process including according to Figures 7 to 9c The operation of manufacturing pixels PXL in the display device DD of the embodiment of the pixel PXL is described. For convenience, Figures 12a to 12l It shows the corresponding Figure 9a A cross-section of pixel PXL in one embodiment. In some embodiments, a method for manufacturing pixel PXL and a display device DD including pixel PXL according to an embodiment will be described based on a method for forming cavity CVT and display element layer DPL.

[0248] refer to Figures 7 to 12a First, a pixel circuit layer (PCL) is formed on the base layer (BSL). For example, after forming the circuit elements and lines of the corresponding pixel PXL in each pixel region PXA on the base layer (BSL), a protective layer (PSV) covering the circuit elements and lines can be formed. The pixel circuit layer (PCL) can be formed using typical backplane processes, and therefore, a detailed description of the method for forming the pixel circuit layer (PCL) will be omitted.

[0249] In some implementations, the protective layer PSV may include at least one organic insulating layer, and thus the surface of the pixel circuit layer PCL can be planarized. One or more contact portions for connection to the display element layer DPL may be formed on the protective layer PSV, for example, a first contact portion CNT1 and a second contact portion CNT2 for each pixel PXL.

[0250] refer to Figures 7 to 12b At least one pair of electrodes ELT1 and ELT2, which are opposite to each other, are formed in each pixel region PXA on the pixel circuit layer PCL. For example, the first electrode ELT1 and the second electrode ELT2 may be formed opposite to each other in the first light-emitting element array region AR1, and the third electrode ELT3 and the fourth electrode ELT4 may be formed opposite to each other in the second light-emitting element array region AR2.

[0251] According to some embodiments, one of the pixel electrodes ELT (e.g., the first electrode ELT1) may be configured to be connected to at least one circuit element (e.g., at least one transistor M) via a first contact portion CNT1, and the other of the pixel electrodes ELT (e.g., the fourth electrode ELT4) may be configured to be connected to a second power line PL2 via a second contact portion CNT2.

[0252] Pixel electrodes (ELTs) can be formed using various processes for forming conductive films (such as deposition processes) and various processes for patterning conductive films (such as wet etching processes). In other words, there are no particular limitations on the methods for forming pixel electrodes (ELTs).

[0253] refer to Figures 7 to 12c A first insulating layer INS1 is formed on one surface of the base layer BSL (including the pixel electrode ELT) to cover the pixel electrode ELT. As an example, the first insulating layer INS1 may be formed on the display area DA of the base layer BSL to completely cover the display area DA in which the pixel electrode ELT of each pixel PXL is formed.

[0254] According to some embodiments, the first insulating layer INS1 can be formed by forming at least one inorganic insulating film on one surface of the base layer BSL (including the pixel electrode ELT). In embodiments, the first insulating layer INS1 can be formed by various processes for forming insulating films (such as deposition processes), and the method of forming the first insulating layer INS1 is not particularly limited.

[0255] refer to Figures 7 to 12d A first photomask PRM1 (also known as a "first photoresist pattern") can be formed on the first insulating layer INS1 to cover the remaining area except for the region where each cavity CVT is to be formed. For example, the first photomask PRM1 can be formed and / or disposed on the remaining area except for one area on the first insulating layer INS1 in each light-emitting element array region AR corresponding to the area between a pair of pixel electrodes ELT (e.g., the area between the first electrode ELT1 and the second electrode ELT2, or the area between the third electrode ELT3 and the fourth electrode ELT4). Various photoresist materials can be used to form the first photomask PRM1.

[0256] refer to Figures 7 to 12eBy using a first photomask PRM1, a cavity CVT can be formed in the first insulating layer INS1 and the protective layer PSV below the region between a pair of pixel electrodes ELTs. For example, the first insulating layer INS1 can be etched with its full thickness in the region exposed by the first photomask PRM1 using dry etching, thereby etching the first insulating layer INS1 with an opening of a second width W2 corresponding to the exposed region. In some embodiments, the protective layer PSV can be etched and / or ashed in the exposed region accordingly, at least its thickness.

[0257] According to some embodiments, the first insulating layer INS1 and the protective layer PSV can be made of materials with different etching rates. For example, the first insulating layer INS1 can be formed to include at least one inorganic insulating film, and the protective layer PSV can be formed to include at least one organic insulating film. In this case, due to the difference in etching rates between the first insulating layer INS1 and the protective layer PSV, a trench with a first width W1 larger than the etching width (i.e., the second width W2) of the first insulating layer INS1 can be formed in the protective layer PSV. Therefore, a cavity CVT with an inverted conical shape can be formed.

[0258] refer to Figures 7 to 12f After forming the cavity CVT, the first photomask PRM1 is removed.

[0259] refer to Figures 7 to 12g A light-emitting element LD is provided on a first insulating layer INS1, and the light-emitting element LD is aligned between a pair of pixel electrodes ELT on the first insulating layer INS1 in the region including the cavity CVT. For example, multiple light-emitting elements LD can be provided in each pixel region PXA (e.g., emission region EA) on the first insulating layer INS1 by inkjet method, slit coating method or various other methods, and an alignment signal (e.g., a set or predetermined alignment signal) (or alignment voltage) can be applied to each of the pixel electrodes ELT (or alignment lines separated into pixel electrodes ELT) to align the light-emitting elements LD between the pixel electrodes ELT.

[0260] As an example, in the first light-emitting element array region AR1, the first light-emitting element LD1 can be aligned on a region of the first light-emitting element array region AR1 in which a cavity CVT is formed, such that the first end EP1 and the second end EP2 of the first light-emitting element LD1 are on the first electrode ELT1 and the second electrode ELT2, respectively. Similarly, in the second light-emitting element array region AR2, the second light-emitting element LD2 can be aligned on a region of the second light-emitting element array region AR2 in which a cavity CVT is formed, such that the first end EP1 and the second end EP2 of the second light-emitting element LD2 are on the third electrode ELT3 and the fourth electrode ELT4, respectively.

[0261] refer to Figures 7 to 12h A contact hole CH is formed for connection between each contact electrode CNE and its corresponding pixel electrode ELT formed in subsequent processes. As an example, a first contact hole CH1 and a second contact hole CH2 can be formed through the first insulating layer INS1 to expose a region of the first electrode ELT1 and a region of the second electrode ELT2, respectively. Similarly, a third contact hole CH3 and a fourth contact hole CH4 can be formed through the first insulating layer INS1 to expose a region of the third electrode ELT3 and a region of the fourth electrode ELT4, respectively.

[0262] refer to Figures 7 to 12i A conductive film CDL is formed on a pixel region PXA, which includes an emission region EA in which a cavity CVT and a light-emitting element LD are disposed. For example, in a display region DA, which includes pixel regions PXA, each of which includes multiple light-emitting elements LD, the conductive film CDL can be formed by various processes (such as deposition processes) for forming the conductive film CDL.

[0263] Because the cavity CVT is formed below the light-emitting element (LD), the lower surface of the LD (e.g., the central region of the LD) floats on the cavity CVT. Therefore, even if seam defects or the like occur at the lower portion of the LD, the conductive film CDL does not adhere to the lower surface of the LD. In some embodiments, during the subsequent photolithography process for patterning the conductive film CDL, light can pass through the cavity CVT onto the lower region of the LD. Therefore, residues of the conductive film CDL can be prevented from remaining below the LD, thereby preventing short-circuit defects caused by CDL residues.

[0264] In some implementations, during the process of forming the conductive film CDL, a conductive material can be introduced into the cavity CVT, allowing the conductive film CDL to be formed within the cavity CVT. For example, the conductive film CDL can even be formed on the sidewalls and bottom surface of the cavity CVT.

[0265] However, when the cavity CVT has a reverse conical shape, the conductive film CDL can be disconnected inside the cavity CVT. For example, due to the reverse conical shape, conductive material may not be deposited on the rear surface of the pixel electrode ELT located inside the cavity CVT (e.g., the area at the starting point of the reverse cone and its periphery). Therefore, from the start of the operation of forming the conductive film CDL, the conductive film CDL can be automatically disconnected below the light-emitting element LD.

[0266] On the other hand, even when the conductive film CDL is deposited on the back surface of the pixel electrode ELT located inside the cavity CVT according to process conditions, the conductive film CDL can be disconnected in the subsequent process of etching the conductive film CDL due to its reverse tapered shape.

[0267] In embodiments of this disclosure, a reverse-tapered cavity CVT is formed after the pixel electrode ELT is formed, but this disclosure is not limited thereto. For example, in another embodiment, a cavity with a reverse-tapered shape can be formed inside the protective layer PSV before the pixel electrode ELT is formed. In this case, the conductive film can be automatically disconnected during the operation of forming the conductive film (e.g., a metal film) for forming the pixel electrode ELT.

[0268] refer to Figures 7 to 12j Based on the area where each contact electrode CNE is to be formed, a second photomask PRM2 (also known as a "second photoresist pattern") is formed on the conductive film CDL. For example, the second photomask PRM2 may be formed on a region of the conductive film CDL that overlaps with a region of the first end EP1 of the light-emitting element LD and its adjacent pixel electrode ELT (e.g., first electrode ELT1 and / or third electrode ELT3) and a region of the second end EP2 of the light-emitting element LD and its adjacent pixel electrode ELT (e.g., second electrode ELT2 and / or fourth electrode ELT4).

[0269] refer to Figures 7 to 12k Using a second photomask PRM2, contact electrodes CNE are formed on the first end EP1 and the second end EP2 of the light-emitting element LD by etching the conductive film CDL. For example, the conductive film CDL can be etched using the second photomask PRM2 by wet etching, thereby forming a first contact electrode CNE1 on the first end EP1 and the first electrode ELT1 of the first light-emitting element LD1, a second contact electrode CNE2 on the second end EP2 of the first light-emitting element LD1, a second electrode ELT2 on the second end EP1 of the second light-emitting element LD2, a third contact electrode CNE3 on the second end EP2 and the fourth electrode ELT4 of the second light-emitting element LD2.

[0270] For example, the conductive film CDL can be etched to break at the upper and lower portions of the region in which the cavity CVT is formed, thereby simultaneously forming the contact electrode CNE and thus stably separating the contact electrode CNE. For example, because the cavity CVT is pre-formed, the contact electrode CNE located on the first end EP1 and the second end EP2 of the light-emitting element LD connected between a pair of pixel electrodes ELT can be stably separated.

[0271] refer to Figures 7 to 12After patterning the contact electrode CNE, the second photomask PRM2 can be removed. Subsequently, an outer coating OC can optionally be formed to form the pixel PXL.

[0272] In another embodiment, a second photomask PRM2 can be used to form the image based on... Figure 9c and Figure 11c The implementation method uses the insulating pattern INP instead of removing the second photomask PRM2. As an example, the second photomask PRM2 can be cured to form each insulating pattern INP on each contact electrode CNE.

[0273] According to the above embodiments, even when an alignment error occurs in the second photomask PRM2 around the light-emitting element LD, the conductive film CDL can stably disconnect in the region between the first end EP1 and the second end EP2 of the light-emitting element LD. In some embodiments, the conductive film CDL can even automatically disconnect below the light-emitting element LD. Therefore, short-circuit defects caused by residues in the conductive film CDL and / or contact electrodes CNE can be effectively prevented.

[0274] As described above, the pixel PXL according to various embodiments of the present disclosure includes a light-emitting element LD and a cavity CVT formed beneath each light-emitting element LD in a first insulating layer INS1 and a protective layer PSV. According to the pixel PXL, the display device DD including the pixel PXL, and the method of manufacturing the display device DD, short-circuit defects that may occur beneath the light-emitting element LD can be prevented in the process of forming contact electrodes CNE for connecting the light-emitting element LD between a pair of pixel electrodes ELT (e.g., first electrode ELT1 and second electrode ELT2 or third electrode ELT3 and fourth electrode ELT4).

[0275] According to the pixel PXL, the display device DD including the pixel PXL, and the method for manufacturing the display device DD, the first insulating layer INS1 and the protective layer PSV can be simultaneously etched using a first photomask PRM1 through a single mask process to form a cavity CVT under the light-emitting element array region AR. In this case, due to the difference in etching rate between the first insulating layer INS1 and the protective layer PSV, the protective layer PSV can be etched with a wider width than the first insulating layer INS1, and therefore, a cavity CVT with an inverted tapered shape can be formed under the light-emitting element array region AR.

[0276] Therefore, starting from the operation of forming the conductive film CDL for forming the contact electrode CNE, the conductive film CDL can be automatically disconnected (or opened) by the cavity CVT, thereby more effectively preventing short-circuit defects between the first end EP1 and the second end EP2 of the light-emitting element LD.

[0277] According to the pixel PXL, the display device DD including the pixel PXL, and the method for manufacturing the display device DD, the contact electrode CNE can be formed simultaneously using a second photomask PRM2 through a single mask process. Therefore, the number of masks used to manufacture the pixel PXL can be reduced, and the manufacturing efficiency of the display device DD can be improved.

[0278] The technical spirit of this disclosure has been specifically described with reference to the foregoing embodiments. However, it should be noted that the embodiments are provided for the purpose of describing this disclosure and not for limiting it. Furthermore, those skilled in the art will understand that various modifications can be made without departing from the scope and spirit of this disclosure.

[0279] The scope of this disclosure is not limited to the details described in the detailed description herein, but should be defined by the claims. Furthermore, it should be understood that all modifications and embodiments contemplated from the meaning and scope of the claims and their equivalents are included within the scope of this disclosure.

Claims

1. Pixel, including: Circuit elements, on the base layer; A protective layer is applied to the circuit element. The first electrode and the second electrode are opposite to each other on the protective layer; A first insulating layer is provided on the first electrode and the second electrode; The light-emitting element is located on the first insulating layer in the region between the first electrode and the second electrode; A first contact electrode is provided on a first end of the light-emitting element to connect the first end of the light-emitting element to the first electrode; A second contact electrode is provided on the second end of the light-emitting element to connect the second end of the light-emitting element to the second electrode; as well as The cavity, corresponding to the region between the first electrode and the second electrode, is located in the protective layer and the first insulating layer beneath the light-emitting element.

2. The pixel according to claim 1, wherein, The cavity has a first width in the lower region of the cavity corresponding to the protective layer, and a second width smaller than the first width in the upper region of the cavity corresponding to the first insulating layer.

3. The pixel according to claim 2, wherein, The second width is less than the length of the light-emitting element.

4. The pixel according to claim 2, wherein, The first contact electrode and the second contact electrode are spaced apart from each other by the second width.

5. The pixel according to claim 1, wherein, The first contact electrode and the second contact electrode are located in the same layer and are separated from each other by the cavity.

6. The pixel according to claim 1, wherein, The first contact electrode is electrically connected to the first electrode through a first contact hole passing through the first insulating layer, and The second contact electrode is electrically connected to the second electrode through a second contact hole that passes through the first insulating layer.

7. The pixel of claim 1 further includes a conductive film remaining on the sidewall of the cavity below the first electrode and the second electrode. in, The conductive film comprises the same material as the first contact electrode and the second contact electrode.

8. The pixel according to claim 7, wherein, The conductive films located below the first electrode and the second electrode are spaced apart from each other.

9. The pixel according to claim 1, further comprising: A first insulating pattern is formed on the first contact electrode; as well as A second insulating pattern is located on the second contact electrode and is spaced apart from the first insulating pattern.

10. The pixel according to claim 9, wherein, The first insulating pattern and the second insulating pattern comprise the same photoresist material.

11. The pixel according to claim 9, wherein, The first contact electrode is located below the first insulating pattern, and The second contact electrode is located below the second insulating pattern.

12. The pixel according to claim 1, wherein, The protective layer includes at least one organic insulating film, and The first insulating layer comprises at least one inorganic insulating film.

13. The pixel of claim 1, further comprising at least one of a first dike and a second dike, the first dike being located below the first electrode and the second electrode and overlapping with a region of the first electrode and a region of the second electrode, the second dike being located in a non-emissive region surrounding an emitting region including the first electrode, the second electrode and the light-emitting element.

14. A display device, including: base layer; as well as Pixels, on the base layer, The pixels include: Circuit elements, on the base layer; A protective layer is applied to the circuit element. The first electrode and the second electrode are opposite to each other on the protective layer; A first insulating layer is provided on the first electrode and the second electrode; The light-emitting element is located on the first insulating layer in the region between the first electrode and the second electrode; A first contact electrode is provided on a first end of the light-emitting element to connect the first end of the light-emitting element to the first electrode; A second contact electrode is provided on the second end of the light-emitting element to connect the second end of the light-emitting element to the second electrode; and The cavity, corresponding to the region between the first electrode and the second electrode, is located in the protective layer and the first insulating layer beneath the light-emitting element.

15. The display device according to claim 14, wherein, The cavity has a first width in the lower region of the cavity corresponding to the protective layer, and a second width smaller than the first width in the upper region of the cavity corresponding to the first insulating layer.

16. The display device according to claim 15, wherein, The second width is less than the length of the light-emitting element.

17. The display device according to claim 14, wherein, The first contact electrode and the second contact electrode are located in the same layer and are separated from each other by the cavity.

18. A method for manufacturing a display device, the method comprising: Circuit elements and a protective layer are formed sequentially on the base layer; A first electrode and a second electrode are formed on the protective layer, facing each other. A first insulating layer is formed to cover the first electrode and the second electrode; A cavity is formed in the first insulating layer and the protective layer below the region between the first electrode and the second electrode; A light-emitting element is provided on the first insulating layer, and the light-emitting element is aligned between the first electrode and the second electrode such that the light-emitting element is on the first insulating layer and overlaps with the cavity; A conductive film is formed on the pixel region including the light-emitting element; as well as The conductive film is etched to be broken at the upper and lower portions of the region in which the cavity is formed, and a first contact electrode and a second contact electrode are formed on the first end and the second end of the light-emitting element, respectively.

19. The method according to claim 18, wherein, Forming the cavity includes: A first photomask is formed on the remaining area of ​​the first insulating layer, except for the upper portion of a region corresponding to the region between the first electrode and the second electrode; and The first insulating layer is etched in the area exposed by the first photomask with the full thickness of the first insulating layer, and a trench with a width greater than the etch width of the first insulating layer is formed in the protective layer.

20. The method according to claim 18, wherein, Forming the first contact electrode and the second contact electrode includes: A second photomask is formed on a region of the conductive film that overlaps with a region of the first end and the first electrode of the light-emitting element and a region of the second end and the second electrode of the light-emitting element; and The conductive film is etched using the second photomask to simultaneously form the first contact electrode and the second contact electrode.

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