A linear voltage regulator with high power supply rejection ratio and a voltage regulating method

Abstract

The application belongs to the field of integrated circuits, and particularly relates to a linear voltage stabilizer with high power supply rejection ratio and a voltage stabilizing method; the linear voltage stabilizer comprises an error operational amplifier, an output stage, an auxiliary current source circuit, a power tube, a feedback resistor and a load capacitor; the error operational amplifier, the output stage, the power tube, the feedback resistor and the load capacitor constitute a feedback loop to provide a stable output voltage; the auxiliary current source circuit is used for transmitting a power supply ripple to a power tube gate to offset power supply noise coupling introduced by a power tube transconductance and an output resistor path. The application can greatly improve the power supply rejection ratio performance of the linear voltage stabilizer by adopting an auxiliary current source design technology.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a linear voltage regulator with high power supply rejection ratio and a voltage regulation method. Background Technology

[0002] Linear voltage regulators can perform DC-DC voltage conversion for medium and low power applications under relatively low voltage drop conditions, supplying power to core components, such as... Figure 1 As shown, a typical linear regulator includes an error operational amplifier, an output stage, a power transistor, a feedback resistor, and a load capacitor. For high-performance analog devices such as AD / DA converters, frequency synthesizers, and RF power amplifiers, power supply noise directly impacts the performance of these devices, requiring linear regulators to have strong noise suppression capabilities. Therefore, improving the power supply rejection ratio (PSRR) of linear regulators is crucial for high-performance analog devices.

[0003] For a PMOS power transistor linear regulator, the source of the power transistor is connected to the input power supply, and it is a common gate amplification structure when viewed from the power supply end. In order to prevent noise on the input power supply from being amplified through the transconductance of the power transistor and coupled to the output of the linear regulator, the gate and source of the power transistor need to have equal ripple changes. Figure 2 This is a common linear regulator circuit structure. Its output stage consists of transistors M1 and M2. Transistor M2 and the power transistor MP form a current mirror structure to drive the power transistor. Since transistor M2 is a diode, its gate will follow the power supply voltage V. IN The dynamic changes ensure that the gate and source of the power transistor have equal ripple amplitudes, thus improving the power supply rejection ratio.

[0004] The drawback of the aforementioned linear regulator is that it can only suppress power supply coupling noise caused by the transconductance of the power transistor. However, due to the channel modulation effect, the power transistor has a finite output resistance, and power supply noise can be coupled to the output terminal through the output resistance of the power transistor. Furthermore, as the feature size decreases, the channel modulation effect of the MOS device is enhanced, which has a more significant impact on the power supply rejection ratio performance. Summary of the Invention

[0005] To improve the power supply rejection ratio (PSRR) performance of linear regulators, this invention proposes a novel high PSRR linear regulator. By employing an auxiliary current source design technique, it can effectively suppress power supply noise coupling through the power transistor, and features a simple structure and low power consumption.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a high power supply rejection ratio (PSRR) linear regulator, comprising an error operational amplifier, an output stage, an auxiliary current source circuit, a power transistor, a feedback resistor, and a load capacitor. The error operational amplifier, output stage, power transistor, feedback resistor, and load capacitor form a feedback loop to provide a stable output voltage. The auxiliary current source circuit is used to transmit power supply ripple to the gate of the power transistor, canceling power supply noise coupling introduced by the power transistor transconductance and the output resistor path, thereby improving the PSRR performance.

[0008] In a second aspect, the present invention also provides a linear voltage regulator method with high power supply rejection ratio (PSRR). The method is applied to a linear voltage regulator with high PSRR as described in the first aspect of the present invention, wherein an error operational amplifier, an output stage, a power transistor, a feedback resistor, and a load capacitor form a feedback loop to provide a stable output voltage. The method specifically includes:

[0009] When the output voltage V OUT Due to the power supply voltage V IN When the change is positive, the feedback resistor provides a feedback voltage to the error operational amplifier;

[0010] The input voltage V of the error op-amp FB A positive change also occurs, causing the output voltage of the error operational amplifier to change inversely;

[0011] The current of the PMOS transistor in the output stage changes in the opposite direction, the current of the auxiliary current source circuit changes in the positive direction, and the current of the NMOS transistor in the output stage changes in the opposite direction.

[0012] The output stage NMOS transistor and power transistor form a current mirror structure to drive the power transistor. The gate of the NMOS transistor changes with the power supply voltage V. IN Dynamic changes ensure that the gate and source of the power transistor have equal ripple amplitudes.

[0013] The auxiliary current source circuit transmits the power supply ripple to the gate of the power transistor, canceling the power supply coupling noise introduced by the power transistor's transconductance and output resistance path, causing the power transistor's current to change inversely, ultimately resulting in the output voltage V. OUT Stablize.

[0014] The beneficial effects of this invention are as follows:

[0015] (1) By adopting auxiliary current source design technology, the present invention can significantly improve the power supply rejection ratio performance of the linear regulator;

[0016] (2) The circuit structure of this invention is simple and the design complexity is low;

[0017] (3) The bias current of the circuit of the present invention is small and does not significantly increase the power consumption of the system. Attached Figure Description

[0018] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the following figures are provided for illustration:

[0019] Figure 1 This is a block diagram of a common linear voltage regulator;

[0020] Figure 2 This is a common linear voltage regulator circuit diagram;

[0021] Figure 3 This is a block diagram of a high power supply rejection ratio linear regulator according to an embodiment of the present invention;

[0022] Figure 4 This is a circuit diagram of a high power supply rejection ratio linear regulator according to an embodiment of the present invention;

[0023] Figure 5 This is a small-signal circuit diagram of a high power supply rejection ratio linear regulator according to an embodiment of the present invention;

[0024] Figure 6 This is a flowchart of a high power supply rejection ratio linear voltage regulation method according to an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] The present invention provides a high power supply rejection ratio linear regulator, such as... Figure 3 The circuit includes an error operational amplifier, an output stage, an auxiliary current source circuit, a power transistor, a feedback resistor, and a load capacitor. The error operational amplifier, output stage, power transistor, feedback resistor, and load capacitor form a feedback loop to provide a stable output voltage. The auxiliary current source circuit is used to transmit power supply ripple to the gate of the power transistor to cancel the power supply noise coupling introduced by the power transistor transconductance and the output resistor path.

[0027] Figure 4 The circuit structure diagram of the high power supply rejection ratio linear regulator according to an embodiment of the present invention is as follows: Figure 4 As shown in the embodiments of the present invention:

[0028] The feedback resistor includes R F1 and R F2 R F1 One end is connected to the drain of the power transistor MP and the load capacitor C. L One end is connected to R F2 The error amplifier's - terminal, R F2One end is connected to GND.

[0029] The load capacitor C L One end is connected to the drain of the power transistor MP and the feedback resistor R. F1 One end is connected to GND.

[0030] One end of the error operational amplifier is connected to a feedback resistor R. F1 R F2 The + terminal is connected to the reference voltage V. REF The output terminal is connected to the gate of the output stage M1 transistor and the gate of the auxiliary current source M3 transistor.

[0031] The output stage includes transistors M1 and M2. The drain of transistor M1 is connected to the gate and drain of transistor M2, the drain of auxiliary current source transistor M3, and the gate of power transistor MP. The source of transistor M2 is connected to the power supply V. IN .

[0032] The auxiliary current source circuit includes transistor M3, whose gate is connected to the output of the error operational amplifier, the gate of transistor M1, the drain of transistor M1, the gate and drain of transistor M2, the gate of power transistor MP, and the source of transistor V. IN .

[0033] The source of the power transistor MP is connected to V. IN .

[0034] In embodiments of the present invention, in such Figure 2 Based on the original linear regulator shown, this embodiment of the invention introduces an NMOS transistor M3 as an auxiliary current source to provide an additional gate-to-source path for the power transistor.

[0035] Figure 5 This is a small-signal circuit diagram for a high power supply rejection ratio linear regulator. Point Y is the gate of M1, and point X is the drain of M2, where g m1 g m2 g m3 g mp These are the transconductances of transistors M1, M2, M3, and MP, respectively. ds1 g ds3 g dsp These are the trans-resistances between the source and drain of transistors M1, M3, and MP, respectively. β is the feedback coefficient, equal to R. F2 / (R F1 +R F2 The error operational amplifier gain is A. EA / (1+sR a C a ), where A EA R is the gain of the error operational amplifier. a C a G represents the resistor and capacitor located at the dominant pole of the amplifier at its output node.L For the transimpedance of the output load, C L This is the load capacitance. In steady state, the load current is the current flowing through the power transistor, equal to [g...]. mp (v i -v x )+g dsp (v i -v o The power supply rejection ratio is equal to the output voltage v. o and input voltage v i The ratio of can be expressed as:

[0036] v o =[g mp (v i -v x )+g dsp (v i -v o )]×(G L +sC L (1)

[0037] Among them G L +sC L This is the equivalent impedance at the output terminal. Figure 5 Chinese v x The KCL equation for the node sequence is:

[0038] (v i -v x (g) m2 +g ds3 )+g m3 (v i -v y ) = v x g ds1 +g m1 v y (2)

[0039] Summarized as follows:

[0040]

[0041] v y and v o The relationship can be represented as:

[0042]

[0043] Through equations (1), (3), and (4), the power supply rejection ratio v o / v i It can be represented as:

[0044]

[0045] Since the feedback resistance is much larger than the output impedance, the open-loop gain A of the linear regulator can be obtained by ignoring the feedback resistance. ol for:

[0046]

[0047] Substituting (6) into (5), the power supply rejection ratio equation (5) can be expressed as:

[0048]

[0049] The power supply rejection ratio in the low-frequency band can be simplified as follows:

[0050]

[0051] Use R in (8) L =1 / G L and r dsp =1 / g dsp replace:

[0052]

[0053] As can be seen from equation (9), by increasing the open-loop gain A ol This can improve the power supply rejection ratio (PSRR) performance, which is a common method for optimizing the PSRR in linear regulators. Furthermore, setting the numerator term in equation (9) to zero can significantly improve the PSRR performance, as can be expressed by the following equation:

[0054]

[0055] Where A MP The power stage gain is g. mp r dsp A M3 The gain of transistor M3 in the auxiliary current source circuit is g. m3 / (g m2 +g ds3 As can be seen from equation (10), this invention, through the introduction of an auxiliary current source circuit, designs the gain of the auxiliary current source circuit M3 to be the reciprocal of the power stage gain, thereby canceling the power supply noise coupling introduced by the power transistor transconductance and output resistor path and improving the power supply rejection ratio performance. In the operation of a linear regulator, as the load current decreases, i.e., the power stage gain A... MP Increase, due to A MP Inversely proportional to the gate-source voltage of MP, as the gate potential of the power transistor increases, the current in M1 and M2 decreases. Therefore, |V GS1 | and | V GS2 |Voltage drop, gate-source voltage V of transistor M3 GS3 Increase, drain-source voltage V DS3As the voltage decreases, transistor M3 gradually enters the linear region, reducing the gain A of the auxiliary current source circuit. M3 Decrease. Therefore, A MP A M3 The product can be designed to be approximately 1, so that the gain of the auxiliary current source circuit changes synchronously with the load current, thereby improving the power supply rejection ratio performance of the linear regulator under full load.

[0056] Based on the above analysis, this invention also proposes a linear voltage regulation method with high power supply rejection ratio, such as... Figure 6 As shown, the method includes:

[0057] 101. When the output voltage V OUT Due to the power supply voltage V IN When the change is positive, the feedback resistor provides a feedback voltage to the error operational amplifier;

[0058] 102. Input voltage V of the error operational amplifier FB A positive change also occurs, causing the output voltage of the error operational amplifier to change inversely;

[0059] 103. The current of the PMOS transistor in the output stage changes in the opposite direction, the current of the auxiliary current source circuit changes in the positive direction, and the current of the NMOS transistor in the output stage changes in the opposite direction.

[0060] 104. The NMOS transistor and power transistor in the output stage form a current mirror structure to drive the power transistor. The gate of the NMOS transistor changes with the power supply voltage V. IN Dynamic changes ensure that the gate and source of the power transistor have equal ripple amplitudes.

[0061] 105. The auxiliary current source circuit transmits the power supply ripple to the gate of the power transistor, canceling the power supply coupling noise introduced by the power transistor's transconductance and output resistance path, causing the power transistor's current to change inversely, ultimately resulting in the output voltage V. OUT Stablize.

[0062] It is understood that in this invention, the positive change is relative to the negative change. When the positive change refers to an increase, the negative change refers to a decrease; when the positive change refers to a decrease, the negative change refers to an increase. The same applies to other verbs that refer to the opposite meaning.

[0063] In this embodiment of the invention, when the power supply voltage V IN Decrease, output voltage V OUT As a result, V decreases. FB This also reduces the current, increases the output of the error amplifier, increases the current flowing through M1, decreases the current flowing through M3, and leads to an increase in the current flowing through M2; after the current is mirrored through M2 and MP, the current in MP increases, ultimately causing V to decrease. OUTThe addition of an auxiliary current source accelerates the increase of the current in M2, thus enabling the linear regulator to achieve voltage regulation.

[0064] In this embodiment of the invention, when the power supply voltage V IN Increase, output voltage V OUT As it increases, V FB As a result, the output of the error amplifier decreases, causing the current flowing through M1 to decrease and the current flowing through M3 to increase, leading to a decrease in the current flowing through M2. After the current is mirrored through M2 and MP, the current through MP decreases, ultimately causing V to... OUT The reduction in current (M2) achieves voltage regulation. The introduction of an auxiliary current source accelerates the reduction of M2 current, enabling the linear regulator to have a faster voltage regulation response.

[0065] In a preferred embodiment of the present invention, a high power supply rejection ratio (PSRR) linear voltage regulator method is also proposed. This method can also be applied to a high PSRR linear voltage regulator as described in the above embodiments. The error operational amplifier, output stage, power transistor, feedback resistor, and load capacitor form a feedback loop to provide a stable output voltage. For details, please refer to the following:

[0066] When the output voltage V OUT As the load changes and decreases, V FB Consequently, the error amplifier's output increases, leading to an increase in the current flowing through M1 and a decrease in the current flowing through M3, resulting in an increase in the current flowing through M2. After the currents through M2 and MP are mirrored, the current through MP increases, ultimately affecting the output voltage V. OUT The addition of an auxiliary current source accelerates the increase of the current in M2, thus enabling the linear regulator to achieve voltage regulation.

[0067] When the output voltage V OUT As the load changes, V FB As the current increases, the output of the error amplifier decreases, causing the current flowing through M1 to decrease, while the current flowing through M3 increases, resulting in a decrease in the current flowing through M2. After the current is mirrored through M2 and MP, the current in MP decreases, ultimately affecting the output voltage V. OUT The reduction in current (M2) achieves voltage regulation. The introduction of an auxiliary current source accelerates the reduction of M2 current, enabling the linear regulator to have a faster voltage regulation response.

[0068] It is understandable that the load change could be due to a change in load current caused by the load capacitance. This change in load current alters the output of the error amplifier, and through a series of processing steps, ultimately changes the output voltage V. OUT It is stable and serves to stabilize voltage.

[0069] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A linear regulator with high power supply rejection ratio, characterized in that, It includes an error operational amplifier, output stage, auxiliary current source circuit, power transistor, feedback resistor, and load capacitor; the error operational amplifier, output stage, power transistor, feedback resistor, and load capacitor form a feedback loop to provide a stable output voltage; the auxiliary current source circuit is used to transmit power supply ripple to the gate of the power transistor, canceling the power supply noise coupling introduced by the transconductance of the power transistor and the output resistor path. One end of the error operational amplifier is connected to a feedback resistor R. F1 R F2 The + terminal is connected to the reference voltage V. REF The output terminal is connected to the gate of the output stage M1 transistor and the gate of the auxiliary current source M3 transistor; The output stage includes transistors M1 and M2; the drain of transistor M1 is connected to the gate and drain of transistor M2, the drain of auxiliary current source transistor M3, and the gate of power transistor MP, with its source connected to GND; the source of transistor M2 is connected to power supply V. IN ; The auxiliary current source circuit includes transistor M3, whose gate is connected to the output of the error operational amplifier, the gate of transistor M1, the drain of transistor M1, the gate and drain of transistor M2, the gate of power transistor MP, and the source of transistor V. IN .

2. A linear regulator with high power supply rejection ratio according to claim 1, characterized in that, The feedback resistor includes R F1 and R F2 ;R F1 One end is connected to the drain of the power transistor MP and the load capacitor C. L One end is connected to R F2 The error amplifier's - terminal, R F2 One end is connected to GND.

3. A linear regulator with high power supply rejection ratio according to claim 2, characterized in that, The load capacitor C L One end is connected to the drain of the power transistor MP and the feedback resistor R. F1 One end is connected to GND.

4. A linear regulator with high power supply rejection ratio according to claim 1, characterized in that, The source of the power transistor MP is connected to V. IN .

5. A method for linear voltage regulation with high power supply rejection ratio, applied to a linear voltage regulator with high power supply rejection ratio as described in any one of claims 1 to 4, characterized in that, An error operational amplifier, output stage, power transistor, feedback resistor, and load capacitor form a feedback loop to provide a stable output voltage; the method specifically includes: When the output voltage V OUT Due to the power supply voltage V IN When the change is positive, the feedback resistor provides a feedback voltage to the error operational amplifier; The input voltage V of the error op-amp FB A positive change also occurs, causing the output voltage of the error operational amplifier to change inversely; The current of the PMOS transistor in the output stage changes in the opposite direction, the current of the auxiliary current source circuit changes in the positive direction, and the current of the NMOS transistor in the output stage changes in the opposite direction. The output stage NMOS transistor and power transistor form a current mirror structure to drive the power transistor. The gate of the NMOS transistor changes with the power supply voltage V. IN Dynamic changes ensure that the gate and source of the power transistor have equal ripple amplitudes. The auxiliary current source circuit transmits the power supply ripple to the gate of the power transistor, canceling the power supply coupling noise introduced by the power transistor's transconductance and output resistance path, causing the power transistor's current to change inversely, ultimately resulting in the output voltage V. OUT Stablize.

6. A linear voltage regulation method with high power supply rejection ratio according to claim 5, characterized in that, The gain of the auxiliary current source circuit is the reciprocal of the gain of the power transistor.

7. A linear voltage regulation method with high power supply rejection ratio according to claim 5, characterized in that, The formula for calculating the gain of the auxiliary current source circuit is as follows: in, This represents the gain of the auxiliary current source circuit, and its value is g. m3 / (g m2 +g ds3 A MP The gain of the power transistor is g. mp r dsp g m2 g m3 g mp The transconductances of transistors M2, M3, and MP are respectively. g ds3 g dsp These are the trans-resistances between the source and drain of transistors M3 and MP, respectively.

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