Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a display area and a non-display area surrounding the display area at least partially; the display panel comprises: a first power bus located in the display area; a second power bus located in the non-display area and electrically connected with the first power bus; and a third power bus located in the non-display area; the display area further comprises: a plurality of pixel circuits and light emitting elements electrically connected with the pixel circuits; the first power bus is connected with the light emitting elements; and the third power bus is connected with the pixel circuits. The display panel and the display device provided by the application are beneficial to reducing the voltage drop of the signal line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous updating of display panel technology, display panels are gradually developing towards thin, high screen ratio and ultra-narrow frame. The display panel usually includes a display area and a non-display area located at the periphery of the display area, and the non-display area is used to arrange signal lines. With the non-display area of the display panel becoming narrower and narrower, the line width of the signal lines located in the non-display area also becomes smaller and smaller, resulting in an increase in the voltage drop of the signal lines.

[0003] Therefore, how to reduce the voltage drop of the signal lines becomes a problem faced by those skilled in the art. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device, which are beneficial to reduce the voltage drop of the signal lines.

[0005] In a first aspect, the embodiments of the present application provide a display panel, comprising a display area and a non-display area at least partially surrounding the display area; the display panel comprises: a first power bus located in the display area; a second power bus located in the non-display area and electrically connected with the first power bus; and a third power bus located in the non-display area; the display area further comprises: a plurality of pixel circuits and light emitting elements electrically connected with the pixel circuits; the first power bus is connected with the light emitting elements; and the third power bus is connected with the pixel circuits.

[0006] Based on the same inventive concept, in a second aspect, the embodiments of the present application provide a display device comprising the display panel according to the first aspect.

[0007] According to the display panel and the display device provided by the embodiments of the present application, the inventors break through the conventional thinking and no longer arrange all the power buses electrically connected with the light emitting elements in the non-display area, but divide the power buses electrically connected with the light emitting elements into the first power bus and the second power bus in parallel, the first power bus is arranged in the display area, and the second power bus is arranged in the non-display area. In this way, it is not only beneficial to realize a narrow frame, but also beneficial to reduce the overall impedance of the power buses electrically connected with the light emitting elements, thereby reducing the voltage drop (IR Drop) of the power buses electrically connected with the light emitting elements, which is beneficial to improve the display effect and reduce power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0008] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, with reference to the attached drawings, in which the same or similar reference signs refer to the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 Fig. 1 shows a top view of a display panel according to an embodiment of the present application;

[0010] Figure 2 Fig. 2 shows another top view of a display panel according to an embodiment of the present application;

[0011] Figure 3 Fig. 3 shows a signal line distribution in the middle Q region of a display panel according to an embodiment of the present application; Figure 2

[0012] Figure 4 Fig. 4 shows a cross-sectional structure in the A-A direction of a display panel according to an embodiment of the present application; Figure 3

[0013] Figure 5 Fig. 5 shows a film layer structure of a display panel according to an embodiment of the present application;

[0014] Figure 6 Fig. 6 shows another film layer structure of a display panel according to an embodiment of the present application;

[0015] Figure 7 Fig. 7 shows a wiring structure of a display panel according to an embodiment of the present application;

[0016] Figure 8 Fig. 8 shows a cross-sectional structure in the B-B direction of a display panel according to an embodiment of the present application; Figure 3

[0017] Fig. 9 shows a cross-sectional structure in the C-C direction of a display panel according to an embodiment of the present application; Figure 9 Figure 3 Fig. 10 shows a cross-sectional structure in the D-D direction of a display panel according to an embodiment of the present application;

[0018] Figure 10 Figure 3 Fig. 11 shows a circuit structure of a pixel circuit in a display panel according to an embodiment of the present application;

[0019] Figure 11 Fig. 12 shows another circuit structure of a pixel circuit in a display panel according to an embodiment of the present application;

[0020] Figure 12 Fig. 13 shows a partial layout structure of a display panel according to an embodiment of the present application;

[0021] Figure 13 Fig. 14 shows a cross-sectional structure in the E-E direction of a display panel according to an embodiment of the present application;

[0022] Figure 14 Fig. 15 shows a cross-sectional structure in the F-F direction of a display panel according to an embodiment of the present application; Figure 13

[0023] Figure 15 ​​​​​Fig. 6 shows another schematic diagram of a film layer structure of a display panel according to an embodiment of the present application;

[0024] Figure 16 Fig. 7 shows another schematic diagram of a wiring structure in a display panel according to an embodiment of the present application;

[0025] Figure 17 Fig. 8 shows a schematic diagram of a display device according to an embodiment of the present application; Figure 1 Fig. 9 shows a schematic diagram of a cross-sectional structure along F-F direction in Fig. 8;

[0026] Figure 18 Fig. 10 shows a schematic diagram of a cross-sectional structure along G-G direction in Fig. 8. DETAILED DESCRIPTION

[0027] The features and exemplary embodiments of the various aspects of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely configured to explain the present application and are not configured to limit the present application. The present application can be implemented without some of the specific details described below. The following description of the embodiments is merely provided to give a better understanding of the present application by showing examples of the present application.

[0028] It should be noted that, in this document, the terms such as first and second are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Also, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the elements defined by the statement “include” do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0029] It should be understood that, when describing the structure of a component, when a layer or a region is referred to as being located “on” or “above” another layer or another region, it can mean that it is directly located above the other layer or the other region, or other layers or regions are included therebetween. Also, if the component is flipped, the layer or the region will be located “under” or “below” the other layer or the other region.

[0030] It should be understood that the term "and / or" as used herein merely describes an associated relationship, that is, there can be three cases, for example, A and / or B, which can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0031] The term "connection" can mean "electrical connection" or "electrical connection without an intermediate transistor". The term "insulation" can mean "electrical insulation" or "electrical isolation". The term "drive" can mean "control" or "operation". The term "part" can mean "local". The term "end" can mean "end section" or "end edge". The display panel can be a display device or a module / part of a display device.

[0032] Various modifications and changes can be made to the present application in light of the foregoing without departing from the spirit or scope of the application, which is defined in the appended claims. Accordingly, the present application is intended to embrace all modifications and alterations to this application that fall within the scope of the claims (the technical solutions claimed to be protected), and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other as long as they do not conflict.

[0033] The present application provides a display panel and a display device, which will be described below with reference to the accompanying drawings.

[0034] As shown in Figure 1 The display panel 100 can include a display area AA and a non-display area NA at least partially surrounding the display area AA.

[0035] The display panel 100 can include a first power bus 11, a second power bus 12, and a third power bus 13. The first power bus 11 is located in the display area AA, and the second power bus 12 and the third power bus 13 are located in the non-display area NA.

[0036] The display area AA of the display panel 100 can further include a plurality of pixel circuits 21 and light emitting elements 22 electrically connected to the pixel circuits 21. The pixel circuit 21 can be used to generate a driving current to drive the light emitting element 22 to emit light. The light emitting element can include at least one of an organic light emitting diode (OLED) and a mirco-LED (Micro Light Emitting Diode).

[0037] The first power bus 11 and the second power bus 12 are electrically connected, and the first power bus 11 is connected to the light emitting element 22. It can be understood that the first power bus 11 and the second power bus 12 can be in a parallel relationship.

[0038] The third power bus 13 is connected with the pixel circuit 21.

[0039] For example, the light emitting element 22 can include a first electrode, a light emitting layer and a second electrode, the pixel circuit 21 can be electrically connected with the first electrode, and the first power bus 11 and the second power bus 12 can be electrically connected with the second electrode. The first electrode can be an anode, and the second electrode can be a cathode, or the first electrode can be a cathode, and the second electrode can be an anode.

[0040] It can be understood that the first power bus 11 can be directly in contact with the light emitting element 22, or the first power bus 11 can be connected with the light emitting element 22 through a connecting structure, or the first power bus 11 can be connected with the light emitting element 22 through a contact hole.

[0041] The first power bus 11 and the second power bus 12 can be electrically connected with a first power terminal V1, and the first power terminal V1 can be used to provide a negative voltage signal. The third power bus 13 can be electrically connected with a second power terminal V2, and the second power terminal V2 can be used to provide a positive voltage signal. The non-display area NA can include a binding area BA, and the first power terminal V1 and the second power terminal V2 can be located in the binding area BA. Optionally, the binding area BA can further include a plurality of pads (not shown).

[0042] According to the display panel provided by the embodiment of the present application, the inventor breaks through the conventional thinking, and no longer sets the power bus connected with the light emitting element 22 in the non-display area, but divides the power bus connected with the light emitting element 22 into the parallel first power bus 11 and the second power bus 12. The first power bus 11 is located in the display area AA, and the second power bus 12 is located in the non-display area NA. In this way, it is not only conducive to realizing a narrow frame, but also conducive to reducing the overall impedance of the power bus electrically connected with the light emitting element 22, thereby reducing the voltage drop of the power bus electrically connected with the light emitting element 22, and conducive to improving the display effect and reducing power consumption.

[0043] In some embodiments, as shown in Figure 2 The display area AA can include adjacent first and second display areas AA1 and AA2, and in the first direction X, the first display area AA1 is located between the non-display area NA and the second display area AA2. The first power bus 11 can be located in the first display area AA1. The first power bus 11 can not be provided in the second display area AA2.

[0044] In the embodiment of the present application, the first power bus 11 is located in the first display area AA1 close to the non-display area NA and close to the second power bus 12, so that the electrical connection between the first power bus 11 and the second power bus 12 can be more conveniently realized.

[0045] Exemplarily, in the first direction X, two sides of the second display area AA2 can each be distributed with one first display area AA1.

[0046] In some embodiments, as shown in Figure 3 The display panel can further include a first power signal line 30, which is electrically connected with the third power bus 13. The third power bus 13 is electrically connected with the pixel circuit 21 in the display area AA through the first power signal line 30. A plurality of pixel circuits 21 can be arrayed and distributed in the display area AA. The first power signal line 30 is arranged in both the first display area AA1 and the second display area AA2, so as to facilitate the first power signal line 30 to provide a power signal for the plurality of pixel circuits 21 arrayed and distributed.

[0047] The first power signal line 30 in the second display area AA2 can include a plurality of sub-signal lines located in different film layers and electrically connected with each other. For example, the first power signal line 30 in the second display area AA2 can include a plurality of first sub-signal lines and a plurality of second sub-signal lines located in different film layers and electrically connected with each other, the first power bus 11 can be located in the same film layer as at least one first sub-signal line in the second display area AA2, and at least one second sub-signal line in the second display area AA2 is located in a different film layer from the first power bus 11.

[0048] It should be noted that when the first power bus 11 and the first sub-signal line are located in the same film layer, they are made of the same material and by the same process method and steps. In the embodiments of the present application, when two or more structures are located in the same film layer, the materials of these structures can be the same and can be made by the same process method and steps.

[0049] Figure 3 Exemplarily shown in FIG. 1B, the first power signal line 30 in the second display area AA2 includes a first sub-signal line 321, a second sub-signal line 322 and a third sub-signal line 323 located in different film layers and electrically connected with each other, the first power bus 11 can be located in the same film layer as the first sub-signal line 321, and the second sub-signal line 322 and the third sub-signal line 323 can be located in different film layers from the first power bus 11.

[0050] It can be understood that, in the case that the first power bus 11 is not arranged in the first display area AA1, Figure 3 In the position of the first power bus 11, a sub-signal line of the first power signal line 30 can be arranged. In the embodiments of the present application, the position of the first power bus 11 in the first display area AA1 is not arranged with a sub-signal line of the first power signal line 30, but is arranged with the first power bus 11, which is equivalent to that the first power bus 11 occupies the position of at least one sub-signal line of the first power signal line 30, so that it is not necessary to additionally increase the film layer to arrange the first power bus 11, which is conducive to the thinning of the display panel.

[0051] It should be noted that, Figure 3 The same filled signal lines represent the same film layer. As Figure 2 indicated, the width of the first display area AA1 in the first direction X is d1, and the width of the second display area AA2 in the first direction X is d2, d1 < d2. Since the width of the first display area AA1 is smaller, the area of the first power signal line 30 occupied by the first power bus 11 is smaller, and the influence on the overall voltage drop of the first power signal line 30 is smaller, so that the influence on the display quality can be reduced without additional film layers to set the first power bus 11.

[0052] Optionally, 2d1 < d2, when the display panel has two first display areas AA1, and the two first display areas AA1 are located between the non-display area NA and the second display area AA2, the left and right sides of the second display area AA2 can include substantially the same first power bus 11, so that the signal environment on both sides of the second display area AA2 is substantially the same, and the display effect of the display panel is improved.

[0053] For example, as Figure 2 indicated, the first display area AA1 can include an arc-shaped edge, and the second display area AA2 includes a straight edge. The arc-shaped edge of the first display area AA1 can be an R round corner edge, so that the first power bus 11 only occupies a local display area corresponding to the R corner, and the influence on the overall voltage drop of the first power signal line 30 is relatively small.

[0054] As Figure 4 indicated, the display panel can include a substrate 01, and the plurality of sub-signal lines of the first power signal line 30 can be located on one side of the substrate 01. In the second display area AA2, the plurality of sub-signal lines of the first power signal line 30 can be distributed in at least two film layers. For example, in the second display area AA2, the first power signal line 30 can include a first sub-signal line 321 and a second sub-signal line 322, the first sub-signal line 321 and the second sub-signal line 322 are located in different film layers, and in the thickness direction of the display panel, the first sub-signal line 321 is located on the side of the second sub-signal line 322 away from the substrate 01. The first power bus 11 can be located in the same film layer as the first sub-signal line 321.

[0055] The thickness direction of the display panel is the film layer stacking direction of the display panel. The sub-signal lines of different film layers are provided with an insulating layer. Figure 4 In the embodiment, a metal layer or a semiconductor layer can also be provided between the second sub-signal line 322 and the substrate 01, and the insulating layer between the second sub-signal line 322 and the substrate 01 can include multiple.

[0056] The first power bus 11 needs to be connected with the light emitting element, which can be located on the side of the first power signal line 30 away from the substrate (not shown in the figure), for example, the first power bus 11 can be electrically connected with the light emitting element through the contact hole, and the first power bus 11 and the first sub-signal line 321 away from the substrate are arranged in the same layer, which can facilitate the electrical connection between the first power bus 11 and the light emitting element, for example, the depth of the contact hole between the first power bus 11 and the light emitting element can be avoided.

[0057] The contact hole between the first power bus 11 and the light emitting element can directly lap the first power bus 11 and the light emitting element, and the first power bus 11 can also directly lap the contact hole, and the contact hole can be connected to the light emitting element through other connection structures.

[0058] In some embodiments, in order to further reduce the voltage drop of the first power signal line 30, as shown in Figure 3 and Figure 4 , in the second display area AA2, the first power signal line 30 can include a third sub-signal line 323, and in the thickness direction of the display panel, the third sub-signal line 323 can be located between the first sub-signal line 321 and the second sub-signal line 322.

[0059] The first sub-signal line 321, the second sub-signal line 322 and the third sub-signal line 323 are electrically connected with each other. For example, the first sub-signal line 321 can be connected with the third sub-signal line 323 through the contact hole, and the third sub-signal line 323 can be connected with the second sub-signal line 322 through the contact hole, so as to realize the electrical connection among them.

[0060] In some embodiments, the sub-signal lines located in the same film layer as the first power bus 11 can be arranged in a grid structure. For example, still taking the first sub-signal line 321 and the first power bus 11 located in the same film layer as an example, as shown in Figure 3 , the first sub-signal line 321 can include a first sub-wire 3211 extending along a first direction X and a second sub-wire 3212 extending along a second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X can be the row direction, and the second direction Y can be the column direction. In this way, a plurality of first sub-signal lines 321 and a plurality of second sub-wires 3212 can constitute a grid-shaped first sub-signal line 321, thereby more facilitating the reduction of the voltage drop of the first power signal line 30.

[0061] For example, the first sub-wire 3211 and the second sub-wire 3212 can be located in the same film layer.

[0062] The first power bus 11 can be in a grid structure to reduce the voltage drop of the first power bus 11.

[0063] For example, as shown in Figure 3As shown, the first power bus 11 can include a plurality of first sub-buses 111 extending along the second direction Y and a plurality of second sub-buses 112 extending along the first direction X, the first direction X and the second direction Y being perpendicular to each other, so that the plurality of first sub-buses 111 and the plurality of second sub-buses 112 can form a grid-shaped first power bus 11.

[0064] The first sub-buses 111 and the second sub-buses 112 can be located in the same film layer.

[0065] For example, as shown in FIG. 1, the first power bus 11 can include a first sub-bus 111 and a second sub-bus 112. Figure 3 As shown, the first power signal lines 11 in the first display area AA1 can have a grid-shaped structure, so as to reduce the voltage drop of the first power signal lines 11.

[0066] For example, in the first display area AA1, the first power signal lines 11 can include a plurality of fourth sub-signal lines 314 extending along the first direction X and a plurality of fifth sub-signal lines 315 extending along the second direction Y. The plurality of fourth sub-signal lines 314 and the plurality of fifth sub-signal lines 315 can cross each other to form a grid-shaped first power signal line 11.

[0067] The fourth sub-signal lines 314 and the fifth sub-signal lines 315 can be located in different film layers.

[0068] In some embodiments, the second sub-signal lines located in the different film layers from the first power bus 11 and located in the second display area AA2 and the first power signal lines 11 in the first display area AA1 can be located in the same film layer. In this way, the first power signal lines 11 can be arranged in the first display area AA1 and the second display area AA2 without increasing the number of film layers, which is conducive to the thinning of the display panel.

[0069] For example, the second sub-signal lines 322 and the fourth sub-signal lines 314 can be located in the same film layer, and the third sub-signal lines 323 and the fifth sub-signal lines 315 can be located in the same film layer. The second sub-signal lines 322 and the fourth sub-signal lines 314 can both extend along the first direction X, and the second sub-signal lines 322 and the fourth sub-signal lines 314 can be directly overlapped.

[0070] For example, as shown in FIG. 1, the first power bus 11 can include a first sub-bus 111 and a second sub-bus 112. Figure 5 or Figure 6As shown, the display panel may include a first metal layer M1, a capacitor metal layer MC, a second metal layer M2, and a third metal layer M3, with the first metal layer M1, capacitor metal layer MC, second metal layer M2, and third metal layer M3 sequentially located away from the substrate 01. A first sub-signal line 321 may be located in the third metal layer M3, a second sub-signal line 322 may be located in the capacitor metal layer MC, and a third sub-signal line 323 may be located in the second metal layer M2. A first branch line 111 and a second branch line 112 may be located in the third metal layer M3. A fourth sub-signal line 314 may be located in the capacitor metal layer MC, and a fifth sub-signal line 315 may be located in the second metal layer M2. The data line 52 of the display panel may be located in the second metal layer M2.

[0071] As an example, the display panel can be a low-temperature polysilicon (LTPS) type display panel. For example... Figure 5 As shown, the display panel may include a first semiconductor layer 201, which may include an active layer of transistors. The active layer may be made of low-temperature polycrystalline silicon, such as P-Si. The insulating layer of the display panel may include a first gate insulating layer GI1, a capacitor insulating layer IMD, a first interlayer dielectric layer ILD1, a first planarization layer PLN1, and a second planarization layer PLN2. The display panel may also include a pixel definition layer PDL and support pillars PS.

[0072] As another example, the display panel can be a low-temperature polycrystalline oxide (LTPO) type display panel. For example... Figure 6 As shown, the display panel may also include a second semiconductor layer 202, which may include an active layer of transistors. The material of the active layer may include metal oxides, such as indium gallium zinc oxide (IGZO). Figure 6 and Figure 5 The similarities will not be discussed further, such as... Figure 6 As shown, the display panel may also include a gate metal layer MG, and the insulating layer may also include a second gate insulating layer GI2, a third gate insulating layer GI3, and a second interlayer dielectric layer ILD2.

[0073] For details on the positional relationships of each film layer, please refer to [reference needed]. Figure 5 , Figure 6 This will not be elaborated upon here.

[0074] It should be noted that, given the presence of other structures within the display panel, sometimes the grid-like wiring may not be as... Figure 3The shown comparison is regular horizontal and vertical alternation. The inventors have found that if the first electrode of the light emitting element is not flat, the display panel will have color deviation and other problems. In the thickness direction of the display panel, the structure in the metal layer close to the first electrode can include a block structure to improve the flatness of the first electrode and prevent color shift of the display panel at different viewing angles when the first electrode is not flat.

[0075] For example, the mesh structure of the first power bus 11 and / or the first sub-wire 321 can be as shown in FIG. 11A. Figure 7 As shown in FIG. 11B, the mesh wire can include a block structure 101, which can at least partially overlap the first electrode of the light emitting element in the thickness direction of the display panel. Figure 7

[0076] In some embodiments, the first power bus 11 and the first power signal line 30 in the first display area AA1 can at least partially overlap in the thickness direction of the display panel. In this way, even if the first display area AA1 is provided with both the first power bus 11 and the first power signal line 30, the pixel aperture ratio of the first display area AA1 can be ensured due to the at least partial overlap of the two.

[0077] For example, as shown in FIG. 11C, the first power bus 11 includes a first branch 111 and a second branch 112, and the first power signal line 30 in the first display area AA1 includes a fourth sub-signal line 314 and a fifth sub-signal line 315. Figure 3 As shown in FIG. 11D, the first branch 111 and the fifth sub-signal line 315 can at least partially overlap, and the second branch 112 and the fourth sub-signal line 314 can at least partially overlap. Figure 4

[0078] In the second display area AA2, the sub-signal lines of different film layers of the first power signal line 30 can at least partially overlap in the thickness direction of the display panel, which can ensure the pixel aperture ratio of the second display area AA2. Alternatively, the sub-signal lines of different film layers of the first power signal line 30 can also overlap.

[0079] For example, as shown in FIG. 11E, the first power signal line 30 of the second display area AA2 can include a first sub-signal line 321, a second sub-signal line 322, and a third sub-signal line 323. The first sub-signal line 321 includes a first sub-wire 3211 and a second sub-wire 3212. Figure 3 As shown in FIG. 11F, the first sub-wire 3211 and the second sub-signal line 322 can at least partially overlap, and the second sub-wire 3212 and the third sub-signal line 323 can at least partially overlap. Figure 4 It should be noted that,

[0080] Figure 3 ​​​In order to show different signal lines extending in the same direction and overlapping each other, the different signal lines extending in the same direction are shown in different line widths, which does not mean that the line widths of the different signal lines extending in the same direction and overlapping each other must be different. For example, the line widths of the different signal lines extending in the same direction and overlapping each other can be the same, and even within the process error range, the signal lines extending in the same direction and overlapping each other described in the above embodiments can overlap in the thickness direction of the display panel.

[0081] In some embodiments, as shown in FIG. 1A, the first display area AA1 includes an arc-shaped edge L1, and the non-display area NA includes a corner area NR adjacent to the arc-shaped edge L1. The corner area NR can include a connection line 51, and the connection line 51 can be connected between the first power bus 11 and the second power bus 12. The second power bus 12 is connected to the first power terminal V1. The power signal provided by the first power terminal V1 can reach the first power bus 11 through the second power bus 12. Figure 2

[0082] For example, as shown in FIG. 1B, in the second direction Y, the non-display area NA can include two opposite corner areas NR, and the connection line 51 can be arranged only in the corner area NR close to the binding area BA. Of course, the connection line 51 can also be arranged in the corner area NR away from the binding area BA. Figure 2

[0083] In some embodiments, as shown in FIG. 1C, the intersection point of the connection line 51 and the arc-shaped edge L1 is a tangent point P, a tangent line L2 passes through the tangent point P, and the connection line 51 can be perpendicular to the tangent line L2. In this way, the length of the connection line 51 can be minimized, which is beneficial to reduce the voltage drop of the connection line 51 and reduce the frame of the display panel. Figure 2

[0084] For example, as shown in FIG. 1D, the second power bus 12 can include a first segment 12a, an arc-shaped segment 12b, and a second segment 12c. The arc-shaped segment 12b is connected between the first segment 12a and the second segment 12c, and the second segment 12c is connected to the first power terminal V1. Within the range of process error, the arc-shaped segment 12b can be parallel to the arc-shaped edge L1. In this way, the space utilization of the corner area NR can be optimized, which is beneficial to reduce the frame of the display panel. Figure 2

[0085] For example, as shown in FIG. 1E, the second segment 12c can include a first sub-segment 12c1 and a second sub-segment 12c2, and the first sub-segment 12c1 is connected between the arc-shaped segment 12b and the second sub-segment 12c1. Figure 2

[0086] ​​​​​The third power bus 13 can include a third segment 133 connected between the fourth segment 134 and the first power signal line 30 of the display area, and the fourth segment 134 connected to the second power terminal V2 of the display panel.

[0087] The first sub-segment 12c1 and the third segment 133 can extend along a first direction X, and the second sub-segment 12c2 and the fourth segment 134 can extend along a second direction Y, the first direction X and the second direction Y intersecting.

[0088] In some embodiments, as shown in FIG. 1B, the second power bus 12 includes a plurality of sub-buses located in different film layers and connected to each other. For example, the second power bus 12 can include a first sub-bus 121, a second sub-bus 122, and a third sub-bus 123 located in different film layers and connected to each other. The connecting line 51, the first power bus 11, and at least one sub-bus can be located in the same film layer. In this way, the connecting line 51 can not need to be punched when connecting the first power bus 11 and the second power bus 12. In addition, if the resistance is suddenly changed, it is easy to become a weak point of static electricity, and connecting the metal in the same film layer can avoid sudden change of resistance at the connection. Figure 3 For example, as shown in FIG. 1B, the second sub-bus 122 can be located between the third sub-bus 123 and the first sub-bus 121, and the third sub-bus 123 can be located between the second sub-bus 122 and the substrate 01.

[0089] Figure 8 In some embodiments, as shown in FIG. 1B, the first power bus 11 can be connected to the sub-bus farthest from the substrate 01 through the first contact hole h1. For example, in the thickness direction of the display panel, the first sub-bus 121 is farthest from the substrate 01, and the first power bus 11 can be connected to the first sub-bus 121 through the first contact hole h1. The first contact hole h1 can be located in the non-display area NA.

[0090] In some embodiments, as shown in FIG. 1B, the first power bus 11 can be connected to the sub-bus farthest from the substrate 01 through the first contact hole h1. For example, in the thickness direction of the display panel, the first sub-bus 121 is farthest from the substrate 01, and the first power bus 11 can be connected to the first sub-bus 121 through the first contact hole h1. The first contact hole h1 can be located in the non-display area NA. Figure 8 For example, as shown in FIG. 1B, the first sub-bus 121 and the first electrode 221 can be located in the same film layer. For example, the first sub-bus 121 and the first electrode 221 can be located in the anode layer RE.

[0091] Figure 5 For example, as shown in FIG. 1B, the first sub-bus 121 and the first electrode 221 can be located in the same film layer. For example, the first sub-bus 121 and the first electrode 221 can be located in the anode layer RE. Figure 6 For example, as shown in FIG. 1B, the first sub-bus 121 and the first electrode 221 can be located in the same film layer. For example, the first sub-bus 121 and the first electrode 221 can be located in the anode layer RE.

[0092] For example, as shown in FIG. 1B, the first sub-bus 121 and the first electrode 221 can be located in the same film layer. For example, the first sub-bus 121 and the first electrode 221 can be located in the anode layer RE.

[0093] ​​The second power bus 12 and the first power bus 11 need to be connected to the second electrode of the light-emitting element in the display area. In the thickness direction of the display panel, relative to the other sub-buses, the first sub-bus 121 is closer to the second electrode 222 of the light-emitting element 22, and the first sub-bus 121 can be connected to the second electrode 222. This avoids the need for a deep contact hole between the second power bus 12 and the second electrode 222 of the light-emitting element 22. Understandably, in this case, the first power bus 11 connects to the second electrode 222 of the light-emitting element 22 through the first sub-bus 121.

[0094] For example, such as Figure 8 As shown, the first sub-bus 121 and the second electrode 222 of the light-emitting element 22 can be connected through the third contact hole h3. It can be understood that since the first power bus 11 and the first sub-bus 121 are connected through the first contact hole h1, and the first sub-bus 121 and the second electrode 222 of the light-emitting element 22 are connected through the third contact hole h3, the first power bus 11 and the second electrode 222 of the light-emitting element 22 are electrically connected.

[0095] For example, the third contact hole h3 between the first sub-bus 121 and the second electrode 222 of the light-emitting element 22 may be located in the non-display area NA.

[0096] For example, the third sub-bus 123 may be located in the second metal layer M2, the second sub-bus 122 may be located in the third metal layer M3, and the connecting line 51 and the first power bus 11 may be located in the third metal layer M3.

[0097] In some embodiments, such as Figure 9 As shown, the non-display area NA may include a shift register VSR, which can be used to output a gate control signal, which can be used to control the transistors in the pixel circuit 21 to turn on or off.

[0098] The orthographic projections of the sub-buses other than the first sub-bus 121 onto the substrate 01 can be located on the side of the orthographic projection of the shift register VSR onto the substrate 01 that is furthest from the display area AA. For example, the orthographic projections of the second sub-bus 122 and the third sub-bus 123 onto the substrate 01 can be located on the side of the orthographic projection of the shift register VSR onto the substrate 01 that is furthest from the display area AA. It is understood that the orthographic projections of the second sub-bus 122 and the third sub-bus 123 onto the substrate 01 may not overlap with the orthographic projection of the shift register VSR onto the substrate 01, which can reduce signal interference between the second power bus 12 and the shift register VSR.

[0099] In some embodiments, in order to reduce the voltage drop of the third power bus 13, such as Figure 10As shown, the third power bus 13 can also be configured with multi-layered and interconnected traces. For example, the third power bus 13 may include a first trace 1301 and a second trace 1302, with the first trace 1301 located between the second trace 1302 and the substrate 01.

[0100] For example, such as Figure 5 or Figure 6 As shown, the first trace 1301 can be located in the second metal layer M2, and the second trace 1302 can be located in the third metal layer M3.

[0101] In some embodiments, such as Figure 1 As shown, the display panel includes a data cable 52. Figure 11 or Figure 12 As shown, the pixel circuit includes a driving transistor T1, and the data signal on the data line 52 can be written into the gate g1 of the driving transistor T1. The gate g1 of the driving transistor T1 is connected to the connection portion 53.

[0102] For example, such as Figure 11 or Figure 12 As shown, the pixel circuit may include a third transistor T3 and a fourth transistor T4. The first terminal of the third transistor T3 is connected to the source or drain of the driving transistor T1, and the second terminal of the third transistor T3 is connected to the gate g1 of the driving transistor T1. The first terminal of the fourth transistor T4 is connected to the first reset signal line Vref1, and the second terminal of the fourth transistor T4 is connected to the gate g1 of the driving transistor T1. The connection portion 53 is connected to the second terminals of the third transistor T3 and the fourth transistor T4.

[0103] In the thickness direction of the display panel, the first power bus 11 may be located between the connection portion 53 and the data line 52, and the first power bus 11 and the connection portion 53 may at least partially overlap, and / or, the sub-signal line located on the same film layer as the first power bus 11 may at least partially overlap with the connection portion 53. For example, the first sub-signal 321 in the second display area AA2 and the first power bus 11 are located on the same film layer, and in the thickness direction of the display panel, the first sub-signal 321 and the connection portion 53 may at least partially overlap.

[0104] Within one frame, the signal on the data line 52 may change frequently. The signals on the first power bus 11 and the second power signal line 12 are usually fixed signals. When the first power bus 11 and / or the first sub-signal 321 overlap with the connection part 53 at least partially, the interference of the signal on the data line 52 on the signal on the connection part 53 can be reduced, thereby improving the stability of the gate potential of the driving transistor T1.

[0105] The driving transistor T1 can be a P-type transistor, such as... Figure 13 and Figure 14As shown, the active layer of the driving transistor T1 may be located in the first semiconductor layer, and the active layer of the driving transistor T1 may include a channel c1 and source s1 and drain d1 located on both sides of the channel. The gate g1 of the driving transistor T1 may be located in the first metal layer M1. The gate g1 of the driving transistor T1 may be reused as the first plate c11 of the storage capacitor Cst. The second plate c12 of the storage capacitor Cst may be located in the capacitor metal layer MC. The second plate c12 of the storage capacitor Cst may include a cutout area. The connection portion 53 may be located on the side of the second plate c12 facing away from the substrate 01, and the connection portion 53 is connected to the gate g1 through a via. The first power bus 11 and / or the first sub-signal 321 may be located on the side of the connection portion 53 facing away from the substrate 01, and the data line 52 may be located on the side of the first power bus 11 and / or the first sub-signal 321 facing away from the substrate 01.

[0106] It is understandable that when a first power bus 11 is provided in the first display area AA1, but not in the second display area AA2, the first power bus 11 in the first display area AA1 and the connecting part 53 may at least partially overlap in the thickness direction of the display panel, and / or the first sub-signal 321 in the second display area AA2 and the connecting part 53 may at least partially overlap.

[0107] The fifth sub-signal line 315 in the first display area AA1 can be electrically connected to the transistor T5 in the pixel circuit through a contact hole, and the third sub-signal line 323 in the second display area AA2 can be electrically connected to the transistor T5 in the pixel circuit through a contact hole.

[0108] For example, such as Figure 15 As shown, the display panel may further include a fourth metal layer M4, which is located between the third metal layer M3 and the anode layer RE. The connection portion 53 may be located on the second metal layer M2, the first power bus 11 and / or the first sub-signal 321 may be located on the third metal layer M3, and the data line 52 may be located on the fourth metal layer M4.

[0109] In other embodiments, the first power bus 11 and the data line 52 may be located on the same film layer. In this case, both the first power bus 11 and the data line 52 may extend along the second direction Y. When the first power bus 11 and the data line 52 are arranged on the same layer, it is beneficial to shield signal interference between different data lines 52.

[0110] For example, at least one first power bus 11 may be spaced between two adjacent data lines 52. This improves the effectiveness of signal shielding.

[0111] like Figure 11 or Figure 12As shown, the pixel circuit can further include a second transistor T2, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. The connection relationship of each transistor can refer to Figure 11 or Figure 12 which will not be described here.

[0112] It should be noted that the transistors of the pixel circuit can be P-type transistors or N-type transistors. When the signal received by the gate of the P-type transistor is low, the P-type transistor is turned on, and when the signal received by the gate of the P-type transistor is high, the P-type transistor is turned off. When the signal received by the gate of the N-type transistor is high, the N-type transistor is turned on, and when the signal received by the gate of the N-type transistor is low, the N-type transistor is turned off.

[0113] As shown in Figure 11 , the transistors T1-T7 are P-type transistors. Alternatively, as shown in Figure 12 , the third transistor T3 and the fourth transistor T4 are N-type transistors, and the other transistors are P-type transistors.

[0114] In addition, the first reset signal line Vref1 and the second reset signal line Vref2 are used to transmit a reset signal, and the reset signal can be a negative voltage signal. The voltage amplitude on the first reset signal line Vref1 and the second reset signal line Vref2 can be different.

[0115] The first reset signal line Vref1 and the second reset signal line Vref2 can be arranged in the display area AA. For example, as shown in Figure 2 , the non-display area NA of the display panel 100 can further include a first reset bus 141 and a second reset bus 142. The first reset bus 141 is connected with the first reset signal line Vref1 and a first reset signal end V3, and the first reset signal provided by the first reset signal end V3 can be transmitted to the first reset signal line Vref1 through the first reset bus 141. The second reset bus 142 is connected with the second reset signal line Vref2 and a second reset signal end V4, and the second reset signal provided by the second reset signal end V4 can be transmitted to the second reset signal line Vref2 through the second reset bus 142. Figure 2 The relative arrangement of the first reset bus 141 and the second reset bus 142 in the first direction X is shown in the figure, which is not used to limit the present application. For example, the first reset bus 141 and the second reset bus 142 can be located in the non-display area on the same side of the display panel, or the first reset bus 141 and the second reset bus 142 are arranged in the non-display area on both sides in the first direction X.

[0116] In addition, Figure 11 and Figure 12In the figure, S1, S2, S3, S1N, S2N, S1P represent scan lines, and EM represents an emission control signal line. When the signals on the scan lines S1, S2, S3, S1P and the emission control signal line EM are low, the transistors connected thereto can be controlled to be turned on, and when the signals on the scan lines S1, S2, S3, S1P and the emission control signal line EM are high, the transistors connected thereto can be controlled to be turned off. When the signals on the scan lines S1N, S2N are high, the transistors connected thereto can be controlled to be turned on, and when the signals on the scan lines S1N, S2N are low, the transistors connected thereto can be controlled to be turned off.

[0117] The display panel can include a substrate 01 and an organic layer located on one side of the substrate 01.

[0118] As introduced above, the display panel can include a plurality of metal layers and a plurality of insulating layers located on one side of the substrate 01. Some of the insulating layers can be made of organic materials, and the insulating layers made of organic materials can also be referred to as organic layers. For example, as shown in the figure, the first planarization layer PLN1 and / or the second planarization layer PLN2 can be made of organic materials, for example, the first planarization layer PLN1 and / or the second planarization layer PLN2 can include polyimide (PI), and the organic layer can include the first planarization layer PLN1 and / or the second planarization layer PLN2. Figure 5 or Figure 6 As introduced above, the display panel can include a plurality of metal layers and a plurality of insulating layers located on one side of the substrate 01. Some of the insulating layers can be made of organic materials, and the insulating layers made of organic materials can also be referred to as organic layers. For example, as shown in the figure, the first planarization layer PLN1 and / or the second planarization layer PLN2 can be made of organic materials, for example, the first planarization layer PLN1 and / or the second planarization layer PLN2 can include polyimide (PI), and the organic layer can include the first planarization layer PLN1 and / or the second planarization layer PLN2.

[0119] The inventors have found that the organic layer can release water vapor, leading to peeling of the metal wiring.

[0120] Still taking the example that the second power bus 12 includes a plurality of sub-buses located in different film layers and connected to each other, the sub-bus located on the side of the organic layer away from the substrate 01 can include a hollow area. The hollow area can help release water vapor, thereby avoiding peeling and improving the reliability of the display panel.

[0121] For example, as shown in the figure, the second sub-bus 122 of the second power bus 12 can be located between the first planarization layer PLN1 and the second planarization layer PLN2. As shown in the figure, the second sub-bus 122 can include a hollow area HA. Figure 16 Figure 9

[0122] As introduced above, the first power bus 11 can connect the second electrode 222 of the light-emitting element 22 through the second power bus 12.

[0123] In other embodiments, a contact hole can also be provided in the display area AA to directly connect the first power bus 11 and the second electrode 222.

[0124] For example, as shown in the figure, the second sub-bus 122 of the second power bus 12 can be located between the first planarization layer PLN1 and the second planarization layer PLN2. As shown in the figure, the second sub-bus 122 can include a hollow area HA. Figure 17 ​​As shown, the light emitting element 22 includes a first electrode 221, a light emitting layer 223, and a second electrode 222, the second electrode 222 is located on the side of the light emitting layer 223 away from the first electrode 221, the first power bus 11 is connected with the second electrode 222 through a second contact hole h2, and the second contact hole h2 is located in the display area.

[0125] In this case, in order to avoid signal interference, the light emitting layers of different light emitting elements are insulated from each other. For example, the light emitting layer includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like in sequence away from the substrate, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, and the like of different light emitting elements are insulated from each other.

[0126] Based on the same inventive concept, the present application also provides a display device, which comprises the display panel provided by the present application. Please refer to Figure 18 , Figure 18 is a structural schematic diagram of a display device provided by an embodiment of the present application. Figure 18 The display device 1000 provided by the present application comprises the display panel 100 provided by any one of the above embodiments of the present application. Figure 18 The embodiment only takes a mobile phone as an example to describe the display device 1000, and it can be understood that the display device provided by the embodiments of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices with display functions, and the present application does not specifically limit this. The display device provided by the embodiments of the present application has the beneficial effects of the display panel provided by the embodiments of the present application, and specific descriptions can be referred to the specific descriptions of the display panel in the above embodiments, which will not be described here.

[0127] According to the above embodiments of the present application, these embodiments do not describe all the details, nor limit the present application to only the specific embodiments described. Obviously, according to the above description, many modifications and changes can be made. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their entire scope and equivalents.

Claims

1. A display panel, characterized by, Includes a display area and a non-display area that at least partially surrounds the display area; The display panel includes: A first power bus is located in the display area; The second power bus is located in the non-display area and is electrically connected to the first power bus; The third power bus is located in the non-display area; The display area further includes: a plurality of pixel circuits and light-emitting elements electrically connected to the pixel circuits; The first power bus is connected to the light-emitting element; The third power bus is connected to the pixel circuit; The display area includes an adjacent first display area and a second display area. In a first direction, the first display area is located between the non-display area and the second display area, and the first power bus is located in the first display area. The display panel also includes: A first power signal line is located in the first display area and the second display area and is electrically connected to the third power bus. The first power signal line in the second display area includes a plurality of first sub-signal lines and a plurality of second sub-signal lines located in different film layers and electrically connected to each other. The first power bus and at least one first sub-signal line are located in the same film layer, and at least one second sub-signal line and the first power bus are located in different film layers.

2. The display panel of claim 1, wherein, The display panel includes a substrate, and the first sub-signal line is located on the side of the second sub-signal line away from the substrate.

3. The display panel of claim 2, wherein, The first power signal line in the second display area also includes a third sub-signal line, which is located between the first sub-signal line and the second sub-signal line.

4. The display panel of claim 1, wherein, The display panel includes a data line, and the pixel circuit includes a driving transistor, the gate of which is connected to a connection portion. In the thickness direction of the display panel, the first power bus is located between the connection portion and the data line, the first power bus at least partially overlaps with the connection portion, and / or, the first sub-signal line located on the same film layer as the first power bus at least partially overlaps with the connection portion.

5. The display panel of claim 1, wherein, The second sub-signal line, which is located on a different film layer than the first power bus, and the first power signal line within the first display area, are located on the same film layer.

6. The display panel of claim 1, wherein, In the thickness direction of the display panel, the first power bus at least partially overlaps with the first power signal line in the first display area.

7. The display panel of claim 1, wherein, The display panel includes data lines, and the first power bus and the data lines are located on the same film layer.

8. The display panel of claim 7, wherein, There is at least one first power bus spacing between two adjacent data lines.

9. The display panel of claim 1, wherein, The first power bus has a mesh-like structure; And / or, the first power signal lines within the first display area are arranged in a grid-like structure; And / or, the sub-signal lines located on the same film layer as the first power bus are in a grid-like structure.

10. The display panel of claim 1, wherein, The width of the first display area in the first direction is smaller than the width of the second display area in the first direction.

11. The display panel of claim 1, wherein, The first display area includes an arc-shaped edge, and the non-display area includes a corner area adjacent to the arc-shaped edge. The corner area includes a connecting line that connects the first power bus and the second power bus. The second power bus is connected to the first power terminal of the display panel.

12. The display panel of claim 11, wherein, The second power bus includes a plurality of sub-buses located in different film layers and connected with each other, the connection line, the first power bus and at least one of the sub-buses are located in the same film layer.

13. The display panel of claim 11, wherein, The display panel includes a substrate, and the second power bus includes a plurality of sub-buses stacked in sequence and connected with each other in a direction away from the substrate, and the first power bus is connected with a sub-bus farthest from the substrate through a first contact hole.

14. The display panel of claim 13, wherein, The display area includes light emitting elements, the light emitting elements include a first electrode, a light emitting layer and a second electrode, the second electrode is located on a side of the light emitting layer away from the first electrode, a sub-bus farthest from the substrate is a first sub-bus, the first sub-bus and the first electrode are located in the same film layer, and the first sub-bus is connected with the second electrode.

15. The display panel of claim 14, wherein, The non-display area includes a shift register, and a projection of the sub-bus other than the first sub-bus on the substrate is located on a side of a projection of the shift register on the substrate away from the display area.

16. The display panel of claim 11, wherein, An intersection of the connection line and the arc-shaped edge is a tangent point, and the connection line is perpendicular to a tangent line passing through the tangent point.

17. The display panel of claim 11, wherein, The second power bus includes a first segment, an arc-shaped segment and a second segment, the arc-shaped segment is connected between the first segment and the second segment, the second segment is connected with the first power terminal, and the arc-shaped segment is parallel to the arc-shaped edge.

18. The display panel of claim 17, wherein, The display panel further includes: The third power bus includes a third segment and a fourth segment, the third segment is connected between the fourth segment and a first power signal line of the display area, and the fourth segment is connected with a second power terminal of the display panel. The second segment includes a first sub-segment and a second sub-segment, the first sub-segment is connected between the arc-shaped segment and the second sub-segment, the first sub-segment and the third segment extend along a first direction, the second sub-segment and the fourth segment extend along a second direction, and the first direction intersects the second direction.

19. The display panel of claim 1, wherein, The display panel includes a substrate and an organic layer located on a side of the substrate, and the second power bus includes a plurality of sub-buses located in different film layers and connected with each other, and the sub-bus located on a side of the organic layer away from the substrate includes a hollow area.

20. The display panel of claim 1, wherein, The display area includes light emitting elements, the light emitting elements include a first electrode, a light emitting layer and a second electrode, the second electrode is located on a side of the light emitting layer away from the first electrode, the first power bus is connected with the second electrode through a second contact hole, and the second contact hole is located in the display area.

21. A display device comprising: The display panel includes a display panel as claimed in any one of claims 1 to 20. The display panel includes a display panel as claimed in any one of claims 1 to 20.

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