Computing unit, array and computing method

Abstract

The present invention discloses a computing unit, a computing unit array and a computing method for high parallel computing using the computing unit, which mainly solve the problem that the prior art is affected by the nonlinearity of the current-voltage relationship of the device and has low accuracy, and has high power consumption during parallel computing. The computing unit includes: a tree-like network, which includes a parent node and at least two child nodes, and the parent node and at least one child node have conduction capability; at least one forward current driving stage, connected to the parent node of the network; and multiple rear-end current sampling stages, which are connected to the child nodes of the network one by one. The present invention uses the current distribution method to realize the decoupling of multiplication operations at the device end in linear operations, and can be applied to large-scale analog computing systems with integrated storage and computing.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and more specifically, to the system architecture and working mode of integrated circuit computing chips. Background Art

[0002] With the development of the Internet of Things and cloud computing, the complexity of computing tasks is increasing day by day, which brings greater pressure to computing chips. Among them, the main performance indicators of computing chips can be divided into power consumption and computing power indicators. Whether in energy-constrained scenarios such as the Internet of Things or in scenarios that consume a lot of energy such as cloud computing, power consumption indicators are very critical. Therefore, how to further reduce chip power consumption while providing a given computing power is an important research direction for computing chips.

[0003] The power consumption of computing chips mainly comes from two operations: data reading and writing, and data computing. For specific calculations, such as the reasoning and training calculations involved in deep neural networks, a large number of data reading and writing operations will occur. The target memory for data reading and writing can be divided into on-chip storage and off-chip storage. Since static random access memory (SRAM) is widely used in on-chip storage, its density is low, so its storage capacity is often small. When encountering a large number of data reading and writing operations, it is necessary to access off-chip storage. In examining data reading and writing operations, the charging and discharging of parasitic capacitance around the interconnection wires is the main source of energy consumption. However, off-chip storage uses interconnection wires and pins with larger spacing for data access, which will generate much greater energy consumption than on-chip storage. In response to this phenomenon, deploying data in on-chip storage as much as possible and further reducing data access to on-chip storage are important strategies for optimizing the energy efficiency of computing chips.

[0004] The storage-computing integrated architecture is one of the specific implementations. This architecture can partially solidify the calculation data in the calculation unit by constructing a high-density calculation unit based on memristors, thereby reducing the access operations to the data. At the same time, due to the use of analog calculation, it has a certain robustness for storing data, so it can achieve larger-scale on-chip storage. A typical in-memory calculation method is to input a voltage vector V through a digital-to-analog converter (DAC) on one side of the memristor array with a conductance value of the matrix G, and by measuring the output current vector I on the other side of the orthogonal, the matrix-vector multiplication calculation of I=GV can be realized. Among them, in the calculation scenario of neural network reasoning, G corresponds to the network weight and is updated less frequently, and V corresponds to the feature map of the data and is updated more frequently.

[0005] The above typical calculation method puts forward a basic requirement for memristor devices, that is, they need to show a highly linear current-voltage relationship. Existing memory technologies only have a small linear region, so to meet this requirement, the input voltage range needs to be limited to a very small range, which in turn poses a greater challenge to the input circuit. Secondly, in the case of full parallelism, the lateral interconnection lines of the array all input signals, so the parasitic capacitance of the interconnection lines needs to be charged to the input voltage. This process will consume a lot of energy. Summary of the invention

[0006] The purpose of the present invention is to solve the above technical problems and to provide a computing unit, an array and a computing method.

[0007] The objective of the present invention is achieved through the following technical solutions:

[0008] In a first aspect, a computing unit is provided, comprising:

[0009] A tree-like network, the network comprising a parent node and at least two child nodes, the parent node and at least one child node having a conduction capability;

[0010] at least one forward current driving stage connected to a parent node of the network;

[0011] A plurality of back-end current sampling stages are connected to the sub-nodes of the network in a one-to-one correspondence.

[0012] Furthermore, the current driving stage includes a voltage digital-to-analog converter and a current limiting resistor connected in series.

[0013] Furthermore, the conduction capacity of the network can be adjusted, which may be done in the following ways but not limited to:

[0014] Mode 1: The computing unit includes a storage structure having at least two ports, denoted as port 1 and port 2, that meet the following conditions, that is, when storing different data, by giving different fixed inputs to the port 1 and the port 2, there is a difference in current between the two ports;

[0015] The child nodes are all connected to port 1 or port 2 of at least one of the storage structures, and the port 1 or port 2 of the storage structure that is not connected to the child node is connected to the parent node; the conduction capacity of the network is adjusted by writing data to the storage structure;

[0016] In this manner, the storage structure may use a memristor, and the conduction capacity of the network may be adjusted by adjusting the state of the memristor.

[0017] Method 2: The parent node and the child node include one or more of magnetoresistive memory, resistive random access memory, phase change memory, ferroelectric memory, static random access memory, dynamic random access memory, floating gate memory and charge capture memory, which are used to adjust the conduction capacity of the network.

[0018] In a second aspect, a calculation method of the calculation unit according to the first aspect is provided, comprising:

[0019] Step 1, setting the potential of the input terminal of the current sampling stage to be the same as the zero potential of the current driving stage;

[0020] Step 2, applying current to the current driving stage;

[0021] Step three, performing current sampling at the current sampling stage;

[0022] The order of precedence is satisfied: step 2 precedes step 3, and step 1 precedes step 3.

[0023] In a third aspect, a computing unit array for implementing parallel computing is provided, which can be implemented in the following manners but is not limited to:

[0024] Mode 1: comprising a plurality of computing units as described in the first aspect;

[0025] A back-end current sampling stage is connected to at least two sub-nodes in different computing units.

[0026] Mode 2: comprising a plurality of computing units as described in the first aspect;

[0027] A forward current driving stage is connected to at least two parent nodes in different computing units.

[0028] Mode 3: comprising a plurality of computing units as described in the first aspect;

[0029] A back-end current sampling stage is connected to at least two sub-nodes in different computing units;

[0030] A forward current driving stage is connected to at least two parent nodes in different computing units.

[0031] In a fourth aspect, a calculation method of the calculation unit array as described in the third aspect is provided, comprising:

[0032] Step 1, setting the potential of the input terminal of the current sampling stage to be the same as the zero potential of the current driving stage;

[0033] Step 2, applying current to the current driving stage;

[0034] Step three, performing current sampling at the current sampling stage;

[0035] The order of precedence is satisfied: step 2 precedes step 3, and step 1 precedes step 3.

[0036] The beneficial effects of the present invention are as follows: the present invention proposes a new computing principle, based on which the device can be operated in a low-voltage state by using a current input in a suitable range, and the current can be conveniently controlled during array calculation, thereby solving the nonlinear problem in the current-voltage relationship of the memristor device and the problem of high power consumption during array-scale parallel calculation.

[0037] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 The structure and calculation method of traditional in-memory computing are shown;

[0040] Figure 2 An implementation method of an analog computing unit and its corresponding peripheral circuit is shown;

[0041] Figure 3 The basic principle of realizing calculation by a simulation computing unit is shown;

[0042] Figure 4 A method for implementing a current driving stage is shown;

[0043] Figure 5 An implementation method of an analog computing unit and its corresponding peripheral circuit is shown;

[0044] Figure 6 The basic principle of realizing calculation by a simulation computing unit is shown;

[0045] Figure 7 An implementation method of an analog computing unit including a magnetic tunnel junction and its corresponding peripheral circuit is shown;

[0046] Figure 8 A charge storage based structure is shown;

[0047] Fig. 9 A structure based on static random access memory is shown;

[0048] Fig.10A structure based on dynamic random access memory is shown. DETAILED DESCRIPTION

[0049] In the following specific embodiments, reference is made to the accompanying drawings that form a part of the present invention, wherein the specific embodiments that can implement the present invention are shown by way of diagrams. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present invention. For example, the features shown or described for one embodiment can be used for or in combination with other embodiments to produce another embodiment. It is intended that the present invention includes these modifications and variations. Specific language (which should not be interpreted as limiting the scope of the appended claims) is used to describe the embodiments. The accompanying drawings are not drawn to scale and are for illustration purposes only.

[0050] The primary technical problem that the present invention is required to solve is: how to reduce the requirements of the traditional in-memory computing method on the linearity of the device.

[0051] refer to Figure 1 As shown, the current mainstream in-memory calculation method is to input a voltage vector V through a digital-to-analog converter (DAC) on one side of the memristor array whose conductivity value is the matrix G, and by measuring the output current vector I on the other side of the orthogonal, the matrix-vector multiplication calculation of I=GV can be realized. The above typical calculation method puts forward a basic requirement for memristor devices, that is, they need to show a highly linear current-voltage relationship. However, existing memory technologies only have a small linear region, so to meet this requirement, the input voltage range needs to be limited to a very small range, which in turn poses a greater challenge to the input circuit. For voltage input, when trying to fix the voltage at the millivolt level, it will be affected by circuit noise and circuit nonlinearity, which is quite difficult.

[0052] To solve this problem, the present invention proposes a new in-memory computing method, which realizes multiplication operation by current distribution. This method is based on a new analog computing unit, including:

[0053] A tree-like network, the network comprising a parent node and at least two child nodes, the parent node and at least one child node having a certain conduction capability;

[0054] at least one forward current driving stage connected to a parent node of the network;

[0055] A plurality of back-end current sampling stages are connected to the sub-nodes of the network in a one-to-one correspondence.

[0056] The basic idea is that, unlike voltage signals, current corresponds to the conserved quantity of charge, which makes it more robust to noise. At the same time, the current range corresponding to the parallel computing of existing memories is also more friendly to circuit design, so that the current can be linearly and stably regulated within the target range.

[0057] like Figure 2 What is shown is a network containing a parent node 210, three child nodes 231, 232 and 233. The parent node and the child nodes are connected by adjustable resistors 221, 222 and 223 respectively. By configuring the current input that matches the array conductivity, the voltage drop across the device can be maintained at a low level with a wide range of current changes, thereby ensuring that its conductivity is close to a constant. In this structure, the additional benefits introduced are as follows: First, as the voltage decreases, the energy consumption for charging and discharging the wire capacitance is reduced. Second, the current on the array storage device is maintained at a low level, and Joule heat is reduced. In summary, the power consumption of the calculation can be greatly reduced.

[0058] Figure 3 The principle of this calculation is further explained. We consider the following configuration, the input current of the parent node 310 is I0, the conductance of the adjustable on-resistor 321 is G1, the conductance of the adjustable on-resistor 322 is G2, the conductance of the adjustable on-resistor 323 is G3, the potential of the child node 331 is 0 relative to the parent node 310, the potential of the child node 332 is 0 relative to the parent node 310, and the potential of the child node 333 is 0 relative to the parent node 310. Under the above configuration, the current sampling level corresponding to the child node can be solved to obtain the following currents, that is, I1 = I0*G1 / (G1+G2+G3), I2 = I0*G2 / (G1+G2+G3), I3 = I0*G3 / (G1+G2+G3). It can be observed that subnode 331 corresponds to the multiplication of I0 and G1 / (G1+G2+G3), subnode 332 corresponds to the multiplication of I0 and G2 / (G1+G2+G3), and subnode 333 corresponds to the multiplication of I0 and G3 / (G1+G2+G3). As mentioned above, the requirement for array storage devices in storage and computing integration is to have a conduction capability with resistance characteristics. The structure proposed in the present application can weaken the above requirements to only have a certain conduction capability by decoupling the resistance characteristics and conduction capability, thereby greatly improving the applicability of storage devices to the storage and computing integration architecture.

[0059] like Figure 4 As shown, in at least one embodiment, the current driving stage 400 may include at least one voltage digital-to-analog converter 401 and at least one current limiting resistor 402, wherein the conductance of the current limiting resistor is much smaller than the driven sub-node load. Figure 4 In the structure, G0< <G 11 +G12 +G 13 . Considering that voltage digital-to-analog converters are more common than current digital-to-analog converters, it is easier to implement using the former as a basic unit in some cases. In traditional implementations, general voltage-to-current conversion needs to be implemented through complex analog circuits. By combining and utilizing the particularity of the tree network load resistance being small in this embodiment, the current driving stage 400 based on the current limiting resistor 402 can achieve this function with less power consumption, area, and parasitic capacitance, thereby improving the overall performance of the circuit.

[0060] In linear algebra, two basic vector calculations are scalar multiplication of vectors, C=aB, and addition of vectors, C=A+B. In the above embodiment, scalar multiplication of vectors is implemented, that is, I=I0G, where I=[I1,I2,I3], G=[G1,G2,G3]. Further, in Figure 5 In the embodiment shown, a structure capable of realizing scalar multiplication of vectors and addition combination between vectors is realized, including:

[0061] A plurality of said analog computing units, such as Figure 5 Shown are two analog computing units 511 and 512;

[0062] One of the back-end current sampling stages is connected to at least two sub-nodes in different analog computing units;

[0063] Specifically, the sub-nodes 520 and 521 are connected to the same current sampling stage 531 , the sub-nodes 522 and 523 are connected to the same current sampling stage 532 , and the sub-nodes 524 and 525 are connected to the same current sampling stage 533 .

[0064] Through Figure 5 A further development of the embodiment, that is, using a specific number of analog computing units containing a specific number of sub-nodes, can realize any linear combination between vectors, thereby realizing general linear algebra calculations.

[0065] Figure 6 The principle of this calculation is further explained. We consider the following configuration, where the input current of the parent node 601 is I 10 , the input current of the parent node 602 is I 20 The conductivity of the adjustable on-resistance 611 is G 11 , the conductivity of the adjustable on-resistance 612 is G 21 The conductivity of the adjustable on-resistance 613 is G 12 , the conductivity of the adjustable on-resistance 614 is G 22 The conductivity of the adjustable on-resistance 615 is G 13 , the conductivity of the adjustable on-resistance 616 is G23 , all child node potentials are placed at the common zero potential of the parent nodes 601 and 602. Under the above configuration, the current sampling level corresponding to the child node can be solved to obtain the following current, that is,

[0066] I1=I 10 *G 11 / (G 11 +G 12 +G 13 )+I 20 *G 21 / (G 21 +G 22 +G 23 ),

[0067] I2=I 10 *G 12 / (G 11 +G 12 +G 13 )+I 20 *G 22 / (G 21 +G 22 +G 23 ),

[0068] I3=I 10 *G 13 / (G 11 +G 12 +G 13 )+I 20 *G 23 / (G 21 +G 22 +G 23 ).

[0069] It can be observed that the above calculation structure and calculation method realize the multiplication of vector X and matrix G, and obtain vector Y, that is, Y = GX, where X = [I 10 ,I 20 ,I 30 ],G=[G 11 ,G 12 ,G 13 ; G 21 ,G 22 ,G 23 ] T ,Y=[I1,I2,I3].

[0070] In at least one embodiment, the memory may be a memristor. By performing analog adjustment of the conduction characteristics, the computing function may be implemented more efficiently.

[0071] In at least one embodiment, the memory may include at least one magnetic tunnel junction (MTJ). The MTJ can realize non-volatile storage of information, so that the network does not need to be reconfigured every time the power is turned off.

[0072] like Figure 7 As shown, in at least one embodiment, the memory can be composed of a gating device and a magnetic tunnel junction. For example, the memory 761 is composed of a magnetic tunnel junction 733 and a gating device 743 connected in series. Optionally, the gating device can be controlled by a signal line. For example, the gating device 741 is controlled by the signal line 711. The conduction capacity adjustment between the child node and the parent node is realized by writing different values ​​in the memory. Specifically, it is realized by writing data 0 to the magnetic tunnel junction and setting it to a high resistance state, or writing data 1 and setting it to a low resistance state. The gating device can be a transistor, a transmission gate, or a diode. During the calculation process, the gating device in the memory participating in the calculation process is set to an open state. The input port of the current analog-to-digital converter 751, 752, and 753 is electrically zeroed. The current digital-to-analog converter inputs a current signal, and samples the signal in the current analog-to-digital converter, and obtains a calculated value after certain signal processing. The embodiments of the phase change memory and the resistive memory are similar.

[0073] like Figure 8 As shown, in at least one embodiment, the storage structure can be a ferroelectric memory, a floating gate memory or a charge trapping memory. The parent node is connected to the interconnection line 802, and the child node is connected to the interconnection line 803. Through an isolated charge storage structure 811, information storage and corresponding conduction capacity adjustment can be achieved.

[0074] like Fig. 9 As shown, in at least one embodiment, the storage structure may be a static random access memory, wherein the parent node is connected to the interconnection line 902, and the child node is connected to the interconnection line 904. Information storage and corresponding conduction capacity adjustment may be achieved through a latch 911 similar to the static random access memory mechanism.

[0075] like Fig.10 As shown, in at least one embodiment, the storage structure can be a dynamic random access memory, wherein the parent node is connected to the interconnection line 1002, and the child node is connected to the interconnection line 1004. Through an isolable capacitor structure 1011, information storage and corresponding conduction capacity adjustment can be achieved.

[0076] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0077] The above is only a preferred embodiment of the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present invention by using the above disclosed methods and technical contents without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A calculation method, characterized in that: It is implemented by a computing unit, and the computing unit includes: A tree-like network, the network comprising a parent node and at least two child nodes, the parent node and at least one child node having a conduction capability; at least one forward current driving stage connected to a parent node of the network; A plurality of back-end current sampling stages are connected to the sub-nodes of the network in a one-to-one correspondence; The calculation method includes: Step 1, setting the potential of the input terminal of the current sampling stage to be the same as the zero potential of the current driving stage; Step 2, applying current to the current driving stage; Step three, performing current sampling at the current sampling stage; The order of precedence is satisfied: step 2 precedes step 3, and step 1 precedes step 3.

2. The calculation method according to claim 1, characterized in that: The current driving stage includes a voltage digital-to-analog converter and a current limiting resistor connected in series.

3. The calculation method according to claim 1, characterized in that: The conduction capacity of the network can be adjusted.

4. The calculation method according to claim 3, characterized in that: The computing unit includes a storage structure having at least two ports, denoted as port 1 and port 2, that meet the following conditions, that is, when storing different data, by giving different fixed inputs to the port 1 and the port 2, there is a difference in current between the two ports; The child nodes are all connected to port one or port two of at least one of the storage structures, and the port one or port two of the storage structure that is not connected to the child node is connected to the parent node; the conduction capacity of the network is adjusted by writing data to the storage structure.

5. The calculation method according to claim 4, characterized in that: The storage structure is a memristor, and the conduction capacity of the network is adjusted by adjusting the state of the memristor.

6. The calculation method according to claim 4, characterized in that: The parent node and the child node include one or more of magnetoresistive memory, resistive random access memory, phase change memory, ferroelectric memory, static random access memory, dynamic random access memory, floating gate memory and charge capture memory, which are used to realize the conduction capacity adjustment of the network.

7. A calculation method, characterized in that: It is implemented by a computing unit array, wherein the computing unit array includes a plurality of computing units; The computing unit comprises: A tree-like network, the network comprising a parent node and at least two child nodes, the parent node and at least one child node having a conduction capability; at least one forward current driving stage connected to a parent node of the network; A plurality of back-end current sampling stages are connected to the sub-nodes of the network in a one-to-one correspondence; A back-end current sampling stage is connected to at least two sub-nodes in different computing units; The calculation method includes: Step 1, setting the potential of the input terminal of the current sampling stage to be the same as the zero potential of the current driving stage; Step 2, applying current to the current driving stage; Step three, performing current sampling at the current sampling stage; The order of precedence is satisfied: step 2 precedes step 3, and step 1 precedes step 3.

8. A calculation method, characterized in that: It is implemented by a computing unit array, wherein the computing unit array includes a plurality of computing units; The computing unit comprises: A tree-like network, the network comprising a parent node and at least two child nodes, the parent node and at least one child node having a conduction capability; at least one forward current driving stage connected to a parent node of the network; A plurality of back-end current sampling stages are connected to the sub-nodes of the network in a one-to-one correspondence; A forward current driving stage is connected to at least two parent nodes in different computing units; The calculation method includes: Step 1, setting the potential of the input terminal of the current sampling stage to be the same as the zero potential of the current driving stage; Step 2, applying current to the current driving stage; Step three, performing current sampling at the current sampling stage; The order of precedence is satisfied: step 2 precedes step 3, and step 1 precedes step 3.

9. A calculation method, characterized in that: It is implemented by a computing unit array, wherein the computing unit array includes a plurality of computing units; The computing unit comprises: A tree-like network, the network comprising a parent node and at least two child nodes, the parent node and at least one child node having a conduction capability; at least one forward current driving stage connected to a parent node of the network; A plurality of back-end current sampling stages are connected to the sub-nodes of the network in a one-to-one correspondence; A back-end current sampling stage is connected to at least two sub-nodes in different computing units; A forward current driving stage is connected to at least two parent nodes in different computing units; The calculation method includes: Step 1, setting the potential of the input terminal of the current sampling stage to be the same as the zero potential of the current driving stage; Step 2, applying current to the current driving stage; Step three, performing current sampling at the current sampling stage; The order of precedence is satisfied: step 2 precedes step 3, and step 1 precedes step 3.

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