Semiconductor device with attached band and method

Abstract

Semiconductor devices and methods using an attached tape are disclosed. A semiconductor device has a first semiconductor package including a substrate and an encapsulant deposited on the substrate. An adhesive tape is disposed on the encapsulant. A conductive via is formed by trenching through the adhesive tape and the encapsulant to expose the substrate. A second semiconductor package is disposed on the adhesive tape opposite the first semiconductor package. The first semiconductor package and the second semiconductor package are joined together by the adhesive tape.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor devices, and more particularly, to semiconductor devices and methods using tape attachment. BACKGROUND

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a variety of functions such as signal processing, high speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, converting solar light to electricity, and creating visual images for television displays. Semiconductor devices are found in many areas of modern electronics, including communication, power conversion, networking, computing, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment. SUMMARY

[0003] Semiconductor packages are becoming more complex to meet the demands from electronic device manufacturers and consumers. Manufacturing processes continue to increase in difficulty for using the same old methods to form more complex structures. Various devices are added to improve warpage characteristics, but this also adds significant manufacturing complexity. Thus, there is a need for simplified packaging and manufacturing methods that can be used for complex packages.

[0004] One aspect of the present disclosure relates to a method of manufacturing a semiconductor device, the method comprising: providing a first semiconductor package comprising a substrate and an encapsulant deposited on the substrate; disposing an adhesive tape on the encapsulant; forming a conductive via by trenching through the adhesive tape and the encapsulant to expose the substrate; and disposing a second semiconductor package on the adhesive tape opposite the first semiconductor package, wherein the first semiconductor package and the second semiconductor package are joined together by the adhesive tape. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figures la to lc Illustrating a semiconductor wafer having multiple semiconductor dies separated by scribe lanes;

[0006] Figures 2a to 2i Illustrating a stacked package semiconductor device formed using tape attachment;

[0007] Figure 3a and Figure 3b Illustrating a stacked package top having a ball grid array;

[0008] Figures 4a to 4c Illustrating forming a dual side package having tape attachment;

[0009] Figure 5 Illustrating another dual side embodiment;

[0010] Figure 6 Illustrating a shielding embodiment; and

[0011] Figure 7a and Figure 7b FIGURE illustrates integrating shielded semiconductor packages into electronic devices. DETAILED DESCRIPTION

[0012] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various embodiments for practicing the present application. It is to be understood that other embodiments can be utilized and structural or

[0013] Semiconductor devices are generally manufactured using two complex processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of the semiconductor dies containing the active and passive electrical components on the surface of a semiconductor wafer. The active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. The passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current flow that a functional circuit requires.

[0014] Back-end manufacturing refers to the formation of packaged integrated circuit devices from the diced or singulated semiconductor dies. The wafer is cut or singulated into individual semiconductor dies after the formation of the active and passive electrical components. The individual semiconductor dies are then mounted to a packaging substrate, which includes pins or contact pads for interconnection to other system components. The contact pads formed on the semiconductor dies are then connected to the contact pads within the package. Electrical connections can be created by the use of soldering, welding, bonding, or other suitable methods. Encapsulants or other molding compounds are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system and the functionality of the semiconductor device is available to other system components.

[0015] Figure laA semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material. A plurality of semiconductor dies or components 104 are formed on the wafer 100 separated by non-active, inter-die wafer areas or streets 106 as described above. The streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0016] Figure lb A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a backside or non-active surface 108 and an active surface 110 that contains analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or above the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry can include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog circuitry or digital circuitry, such as a digital signal processor (DSP), ASIC, MEMS, memory, or other signal processing circuitry. The semiconductor die 104 can also contain integrated passive devices (IPD) for RF signal processing, such as inductors, capacitors, and resistors. The backside surface 108 of the semiconductor wafer 100 can undergo an optional backside grinding operation to remove a portion of the base material 102 and reduce the thickness of the semiconductor wafer 100 and semiconductor dies 104 using mechanical grinding or etching processes.

[0017] A conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive material. The conductive layer 112 operates as contact pads electrically connected to the circuitry on the active surface 110.

[0018] The conductive layer 112 can be formed as contact pads disposed side-by-side a first distance from the edges of the semiconductor dies 104, as shown in FIG. 2A, or as a continuous conductive layer 112 covering the entire active surface 110, as shown in FIG. 2B. Figure lbThe conductive layer 112 can be formed as contact pads offset in multiple rows, as shown in FIG. 1. Alternatively, the conductive layer 112 can be formed as contact pads offset in multiple rows, such that a first row of contact pads is disposed a first distance from an edge of the die, and a second row of contact pads, alternating with the first row, is disposed a second distance from the edge of the die. The conductive layer 112 represents the last conductive layer formed on the semiconductor die 104, with contact pads for subsequent electrical interconnection to a larger system. However, there can be one or more intervening conductive and insulating layers between the actual semiconductor devices formed on the active surface 110 and the contact pads 112 for signal routing.

[0019] A conductive bump material is deposited on the conductive layer 112 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. The material can be reflowed by heating the bump material above its melting point to form conductive balls or bumps 114. In one embodiment, the conductive bumps 114 are formed on a bump under metalization (UBM) having a wetting layer, barrier layer, and adhesion layer. The conductive bumps 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The conductive bumps 114 represent one type of interconnect structure that can be formed on the conductive layer 112 for electrical connection to a substrate. Interconnect structures can also use bond wires, conductive paste, columnar bumps, micro bumps, conductive pillars, or other electrical interconnections.

[0020] In Figure lc The semiconductor wafer 100 is singulated into individual semiconductor dies 104 through the scribe lanes 106 using a saw blade or laser cutting tool 118. The individual semiconductor dies 104 can be inspected and electrically tested for identification of KGD post-singulation.

[0021] Figures 2a to 2i Formation of a package-on-package (PoP) device with the semiconductor dies 104 is shown using tape attachment. In Figure 2a In

[0022] Substrate 152 includes one or more insulating layers 154 interleaved with one or more conductive layers 156. In one embodiment, insulating layers 154 are core insulating boards with conductive layers 156 patterned on the top and bottom surfaces, such as copper clad laminated substrates. Conductive layers 156 also include conductive vias electrically coupled through insulating layers 154. Substrate 152 can include any number of conductive and insulating layers interleaved on one another. A solder mask or passivation layer can be formed on either side of substrate 152. In other embodiments, any suitable type of substrate or lead frame is used for substrate 152.

[0023] Any components desired to implement the intended functionality of PoP b 150 are mounted or disposed on substrate 152 and electrically connected to conductive layers 156. Substrate 152 has two major surfaces: a top surface 157 and a bottom surface 159. Electrical components can be mounted to top and bottom surfaces 157 and 159 in any suitable configuration.

[0024] In Figure 2a Semiconductor die 104 is mounted to surface 157 of substrate 152 using pick and place or other suitable operations. Mold underfill (MUF) 160 is deposited between semiconductor die 104 and substrate 152. MUF 160 can be deposited on substrate 152 or semiconductor die 104 prior to mounting or injected between the two by capillary action after mounting. Additional electrical components 162 are mounted to bottom surface 159. Electrical components 162 can also be mounted to top surface 157 with semiconductor die 104. Any combination of electrical components, such as semiconductor dies or discrete active or passive components, can be mounted to surfaces 157 and 159 in any desired combination. Bumps 164 are formed on bottom surface 159 in a similar manner to bumps 114 formed on semiconductor die 104. Bumps 164 can be any suitable type of interconnect structure and can be formed at any stage of manufacture.

[0025] In Figure 2b Encapsulant 170 is deposited on substrate 152 and semiconductor die 104. Encapsulant 170 can be a polymer composite, such as an epoxy, epoxy acrylate, or a polymer with or without filler added. Encapsulant 170 is electrically non-conductive and environmentally protects the semiconductor device from external factors and contaminants. Encapsulant 170 also protects semiconductor die 104 from degradation due to exposure to light.

[0026] In Figure 2cIn this embodiment, adhesive tape 180 is deployed on encapsulation 170. Adhesive tape 180 comprises a tape or film material, such as polyimide (PI) or aluminum (Al), serving as a substrate, wherein an adhesive is coated onto the top and bottom surfaces of the tape. Polyimide is convenient as an insulating material that does not short-circuit electrical contacts. Aluminum has excellent thermal conductivity and can improve heating or cooling efficiency. Aluminum can protect plastic parts from heat and can increase light brightness by reflecting light from a light source. Aluminum protects the surface of encapsulation 170 from damage caused by heat or fire. Noise can be reduced because aluminum reduces vibration. Aluminum has high flexibility and can be applied to bending areas. High tensile strength and high tear resistance are also beneficial qualities of aluminum used for adhesive tape 180. Because aluminum is conductive, it can operate as an electromagnetic interference (EMI) shield between layers of a stacked package. In one embodiment, adhesive tape 180 is formed using high-purity aluminum. In another embodiment, adhesive tape 180 is a die attachment film (DAF).

[0027] Cover tape or backing tape 182 is deployed onto one surface of adhesive tape 180 to prevent the top adhesive surface of the tape from being exposed during processing. Figure 2c In this embodiment, adhesive tape 180 is adhered to encapsulant 170 by an adhesive on the bottom surface of tape 180, and tape 180 is adhered to cover tape 182 by an adhesive on the top surface of tape 180. In one embodiment, silicone is used as the adhesive.

[0028] exist Figure 2d In this process, a laser cutting tool 192 is used to trench-cut the via opening 190 through a cover tape 182, an adhesive tape 180, and an encapsulant 170. In some embodiments, the laser cutting tool 192 is an infrared or ultraviolet laser. The trenching process only drills through the adhesive tape 180, cover tape 182, and encapsulant 170 to expose the contact pads of the substrate 152. Trenching using the laser cutting tool 192 is faster than conventional TSV technology and allows for a higher aspect ratio for the via opening 190, i.e., a taller and finer opening can be formed. Trenching allows for the use of smaller conductive pads and a thicker encapsulant 170 on the substrate 152. In some embodiments, particularly when the adhesive tape 180 is conductive, portions of the tapes 180 and 182 surrounding the via opening 190 are also removed to create a physical separation between the adhesive tape 180 and the via opening 190.

[0029] Figure 2eA conductive via 196 is shown formed by depositing a conductive material into the via opening 190. The conductive via 196 can be formed by depositing a conductive epoxy, a conductive adhesive, or a solder paste. In other embodiments, the conductive material is sputtered, sprayed, or plated onto the cover tape 182 and into the via opening 190. The conductive material can be gold, silver, copper, aluminum, steel, or another suitable conductive material. In one embodiment, a product that can cure at less than 100°C is selected in order to reduce the heat required, thereby reducing warpage. One example of a suitable conductive adhesive for the conductive via 196 is ABP2032S by Henkel Adhesive Technologies. The conductive via 196 extends down into the via opening 190 to physically and electrically contact the conductive layer 156 of the substrate 152.

[0030] After the conductive via 196 is formed and cured (if needed), the cover tape 182 is removed to expose the top adhesive surface of the adhesive tape 180, as shown in Figure 2f The cover tape 182 is typically peeled off as shown, but can be chemically removed or removed using any other suitable means. In other embodiments, the cover tape 182 is not used, and the top surface of the adhesive tape 180 is not initially adhesive. An adhesive material is deposited onto the tape 182 during this step, rather than removing the tape 180 to expose a pre-applied adhesive.

[0031] The conductive via 196 is formed with a top surface that is co-planar with or slightly recessed from the adhesive tape 180. In other embodiments, the conductive via 196 is formed with a top surface that is approximately co-planar with or recessed in the encapsulant 170. The conductive via 196 can be formed to extend above the top surface of the tape 180.

[0032] In Figure 2g a solder paste 198 is printed onto the conductive via 196 using a nozzle 199. In some embodiments, a stencil controls the distribution of the solder paste 198. Any suitable solder paste printing or deposition method is used in other embodiments.

[0033] In Figure 2h and Figure 2iIn this case, a package-on-package top (PoPt) 200 is deployed on and mounted to PoPb 150. PoPt 200 has a similar structure to PoPb 150, including a substrate 202 with an encapsulated semiconductor die 204. In other embodiments, PoPt 200 can be any type of semiconductor package with any desired electrical components. Substrate 202 of PoPt 200 is pressed down onto adhesive tape 180, which mechanically joins PoPt 200 to PoPb 150. The bottom of substrate 202 has a land grid array for interconnection. Contact pads on the bottom of substrate 202 are aligned with the locations at which solder paste 198 is printed on conductive vias 196.

[0034] Both PoPb 150 and PoPt 200 can be held as un singulated unit panels, and then both are singulated together after mounting. In other embodiments, PoPt 200, PoPb 150, or both are singulated before mounting. Each of PoPt 200 and PoPb 150 can be considered separately as a semiconductor package. After they are combined, the combination can also be considered a semiconductor package. PoP 210 is a semiconductor package composed of two stacked semiconductor packages.

[0035] Figure 2i A completed PoP 210 is shown, with PoPt 200 mounted to PoPb 150 and electrically connected by conductive vias 196. Solder paste 198 is reflowed, if needed, to improve the reliability of the electrical connections. In other embodiments, conductive vias 196 are composed of conductive adhesive or epoxy that remains uncured or partially cured when PoPt 200 is pressed down onto tape 180. Then, conductive vias 196 are cured while in physical contact with both substrate 152 and substrate 202, without the need for separate solder paste 198.

[0036] Because of the use of adhesive tape 180 and conductive vias 196, PoP 210 is a complex package type formed using simple processes. Conductive vias 196 are significantly smaller than copper-core solder balls that would otherwise be embedded in encapsulant 170 in prior art. Also, no separate interposer is required between PoPt 200 and PoPb 150 as in some prior art PoP implementations. Forming via openings 190 with trench cuts allows significantly finer interconnection pitch than in prior art. The overall process is simpler, less expensive, and has improved warpage characteristics. Adhesive tape 180 is used to stack PoPt 200 and PoPb 150 to hold the packages together. Trench cuts and fill are used to electrically connect PoPt 200 and PoPb 150.

[0037] Figure 3a AndFigure 3b PoPt 220 is shown being used instead of PoPt 200 with a land grid array to form PoP 212. PoPt 220 has conductive bumps 224 formed on the bottom of substrate 202 for electrical interconnection. Bumps 224 can be formed as described above for bumps 114 on semiconductor die 104. PoPt 220 is pressed down onto tape 180 so that the tape adheres to substrate 202. Conductive vias 196 can be recessed to provide additional clearance for bumps 224, thus allowing tape 180 to physically contact substrate 202. An extra thick tape 180 can also be used to provide sufficient height to reach substrate 202 with additional offset from bumps 224. In some embodiments, a gap is maintained between substrate 202 and tape 180. Tape attachment is still helpful by holding PoPt 220 in place before the bumps are reflowed to mechanically couple to PoPb 150 adhering to bumps 224. Flux material can be printed onto conductive vias 196 to aid the solder reflow process, similar to the way solder paste 198 is printed above.

[0038] Figures 4a to 4c Dual-sided packaging is shown being formed with tape attachment. In Figure 4a bottom package 230 has a substrate 231. Adhesive tape 232 and cover tape 234 are disposed on substrate 231. Bottom package 230 further has solder bumps 236 formed on substrate 231 in an opening of encapsulant 238.

[0039] In Figure 4b opening 235 is formed through cover tape 234 and adhesive tape 232 to expose contact pads of substrate 231 underneath the tape. Opening 235 is formed by trench cutting as described above. Opening 235 is formed through only adhesive tape 232 and cover tape 234. There is no additional encapsulant as in the above embodiments because adhesive tape 232 is disposed directly on substrate 231.

[0040] In Figure 4c conductive vias 239 are formed by filling opening 235 with conductive material as described above for conductive vias 196. Dual-sided package 241 is completed by mounting top package 240 onto adhesive tape 232 with substrate 243 contacting the adhesive tape. Substrate 243 has a land grid array, but can also have a ball grid array. Top package 243 includes semiconductor die 104 and discrete active or passive components 242 that are molded in encapsulant 244. Any suitable combination of electrical components can be used as part of bottom package 230 and top package 240 in any desired configuration.

[0041] Bilateral package 241 has top package 240 and bottom package 230, which are deployed with their respective substrates oriented toward each other, unlike the previous embodiments in which both substrates are oriented in the same direction. Both bottom package 230 and top package 240 can remain as unit panels that are not singulated, and then both are singulated together after mounting. In other embodiments, top package 230, bottom package 240, or both are singulated before mounting.

[0042] Figure 5 Bilateral package 250 is shown, which adds conductive vias or bumps 252 relative to bilateral package 241. The via openings for conductive bumps 252 can be formed through bottom package 230 by mechanical, chemical, or laser etching or drilling before or after top package 240 is mounted to bottom package. Solder or another conductive material is deposited into the via openings to form conductive bumps 252. Conductive bumps 252 extend from substrate 243 of top package 240, all the way through bottom package 230, and beyond the bottommost surface of the bottom package.

[0043] Figure 6 Bilateral package 260 is shown with a shielding layer 262 formed on top package 240. Shielding layer 262 is formed using any suitable metal deposition technique, such as chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtered material can be copper, steel, aluminum, gold, titanium, combinations thereof, or any other suitable conductive material. In some embodiments, shielding layer 262 can be made by sputtering on multiple layers of different materials, such as stainless steel-copper-stainless steel or titanium-copper. Shielding layer 262 reduces electromagnetic interference (EMI) between components of package 260 and other nearby electronic devices.

[0044] Shielding layer 262 is formed on the side surfaces of encapsulant 244 and substrate 243. Shielding layer 262 is optionally connected to a ground voltage through a conductive layer of substrate 243 that can be exposed at the side surfaces of substrate 243. Shielding layer 262 is formed before top package 240 is mounted on bottom package 230, so that the shielding layer is formed only on top package 240. In other embodiments, shielding layer 262 is formed after package 260 is complete, so that the shielding layer extends down to bottom package 230. Any of the above embodiments can have a shielding layer formed in a similar manner.

[0045] Figure 7a and Figure 7b Figure illustrates integrating the semiconductor packages described above (e.g., PoP 210) into a larger electronic device 340. Figure 7aA partial cross-section of PoP 210 mounted to a printed circuit board (PCB) or other substrate 342 that is part of an electronic device 340 is illustrated. Bumps 164 are reflowed onto a conductive layer 344 of PCB 342 to physically attach and electrically connect PoP 210 to the PCB. In other embodiments, thermal compression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between PoP 210 and PCB 342. Semiconductor dies 104 and 204 are electrically coupled to conductive layer 344 through substrates 152 and 202.

[0046] Figure 7b Electronic device 340 is illustrated including PCB 342 with multiple semiconductor packages mounted on a surface of the PCB, including PoP 210. Electronic device 340 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Electronic device 340 can be a stand-alone system that uses semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 340 can be a sub-assembly of a larger system. For example, electronic device 340 can be part of a tablet computer, cellular telephone, digital camera, communication system, or other electronic device. Electronic device 340 can also be a graphics card, network interface card, or another signal processing card that is plugged into a computer. The semiconductor packages can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor dies or electrical components.

[0047] In Figure 7b , PCB 342 provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 344 are formed on a surface or within a layer of PCB 342 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 344 provide electrical communication between semiconductor packages, mounted components, and other external systems or components. Traces 344 also provide power and ground connections to semiconductor packages as needed.

[0048] In some embodiments, the semiconductor device has two package levels. The first level of packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to PCB 342. In other embodiments, the semiconductor device can have only the first level of packaging, in which the die is mechanically and electrically mounted directly to PCB 342.

[0049] For illustrative purposes, several types of first-level packages are shown on the PCB 342, including a wire bond package 346 and a flip chip 348. Additionally, several types of second-level packages are shown, including a ball grid array (BGA) 350, a bump chip carrier (BCC) 352, a land grid array (LGA) 356, a multi-chip module (MCM) 358, a quad flat no-lead package (QFN) 360, a quad flat package 362, and an embedded wafer level ball grid array (eWLB) 366, which are mounted on the PCB 342 along with the PoP 210. Conductive traces 344 electrically couple the various packages and components disposed on the PCB 342 to the PoP 210, giving the components within the PoP 210 the use of other components on the PCB.

[0050] Depending on system requirements, any combination of semiconductor packages configured with any combination of first-level packaging and second-level packaging, along with other electronic components, can be connected to the PCB 342. In some embodiments, the electronic device 340 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages include complex functionality, less expensive components and streamlined manufacturing processes can be used to manufacture electronic devices. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs to consumers.

[0051] While one or more embodiments of the present application have been illustrated and described, it will be appreciated that those skilled in the art can make modifications and adaptations to the described embodiments without departing from the spirit and scope of the application as set forth in the claims.

Claims

1. A method of manufacturing a semiconductor device, comprising: providing a first semiconductor package, including, a substrate, discrete components mounted on a bottom surface of the substrate, and an encapsulant deposited on a top surface of the substrate; disposing an adhesive tape over the encapsulant, wherein the adhesive tape includes, a polyimide film, an adhesive coated onto a top surface and a bottom surface of the polyimide film, and a cover tape disposed on the top surface of the polyimide film, wherein the adhesive tape is disposed with the bottom surface of the polyimide film on the encapsulant; forming a via through the adhesive tape by trench cutting through the adhesive tape and the encapsulant to expose a contact pad of the substrate, wherein the trench cutting forms an opening in both the polyimide film of the adhesive tape and the cover tape, and wherein the via remains free of conductive material through an entire thickness of the encapsulant above the contact pad; forming a conductive via by depositing a conductive material into the via after the trench cutting, wherein the conductive via completely fills the via including the opening in the adhesive tape; removing the cover tape after forming the conductive via by peeling the cover tape from the polyimide film, wherein a portion of the via through the cover tape is removed with the cover tape; disposing a solder paste over the conductive via, wherein the solder paste is printed using a nozzle; and disposing a second semiconductor package over the adhesive tape opposite the first semiconductor package after forming the conductive via that completely fills the opening in the adhesive tape and after disposing the solder paste over the conductive via, wherein the first semiconductor package and the second semiconductor package are joined together through the adhesive tape.

2. The method of claim 1, wherein the conductive material of the conductive via includes a conductive epoxy or an adhesive.

3. The method of claim 1, wherein each of the first semiconductor package and the second semiconductor package physically contacts the adhesive tape.

4. The method of claim 1, further comprising forming a shield layer on the second semiconductor package prior to disposing the second semiconductor package over the adhesive tape opposite the first semiconductor package.

5. A method of manufacturing a semiconductor device, comprising: providing a first semiconductor package; disposing an adhesive tape over the first semiconductor package, wherein the adhesive tape includes, a polyimide film, an adhesive coated onto a top surface and a bottom surface of the polyimide film, and a cover tape disposed on the top surface of the polyimide film, wherein the adhesive tape is disposed with the bottom surface of the polyimide film on the first semiconductor package; forming a conductive via through the adhesive tape by, trench cutting to form an opening in the first semiconductor package, wherein the opening is completely free of conductive material, and depositing a conductive material to completely fill the opening; removing the cover tape of the adhesive tape after forming the conductive via by peeling the cover tape from the polyimide film; and disposing a second semiconductor package over the first semiconductor package after the conductive material completely fills the opening, wherein the second semiconductor package is electrically coupled to the first semiconductor package through the conductive via.

6. The method of claim 5, further comprising forming the conductive via using a conductive epoxy or an adhesive for the conductive material.

7. The method of claim 6, further comprising curing the conductive epoxy or adhesive after the second semiconductor package is disposed on the first semiconductor package.

8. The method of claim 5, further comprising disposing an adhesive tape on the substrate of the first semiconductor package.

9. The method of claim 8, further comprising disposing a second semiconductor package, wherein the substrate of the second semiconductor package is in physical contact with the adhesive tape.

10. The method of claim 5, further comprising forming a conductive via through the encapsulant of the first semiconductor package.

11. A method of manufacturing a semiconductor device, comprising: providing a first semiconductor package, the first semiconductor package comprising a substrate and an encapsulant deposited on the substrate; disposing an adhesive tape on the first semiconductor package, wherein the adhesive tape comprises a conductive aluminum film and an adhesive coated onto top and bottom surfaces of the conductive aluminum film; forming a via opening through the adhesive tape and the encapsulant to expose the substrate; forming a conductive via by completely filling the via opening with a conductive material, wherein a top surface of the conductive material is coplanar with the adhesive tape; disposing a second semiconductor package over the first semiconductor package after forming the conductive via having a top surface that is coplanar with the adhesive tape, wherein the adhesive tape is between the first semiconductor package and the second semiconductor package; and pressing the second semiconductor package onto the adhesive tape, wherein the adhesive tape mechanically joins the second semiconductor package to the first semiconductor package.

12. The method of claim 11, further comprising forming a shield layer on the first semiconductor package.

13. The method of claim 11, wherein the first semiconductor package and the second semiconductor package are joined together by the adhesive tape.

14. The method of claim 11, further comprising forming the via opening using a trench cut.

15. A semiconductor device, comprising: a first semiconductor package; a second semiconductor package; an adhesive tape disposed between the first semiconductor package and the second semiconductor package, wherein a substrate of the second semiconductor package physically contacts the adhesive tape, and wherein the adhesive tape comprises a conductive aluminum film; a conductive via formed through the adhesive tape and an encapsulant of the first semiconductor package, wherein the conductive via comprises a conductive epoxy or adhesive that extends completely between a substrate of the first semiconductor package and a substrate of the second semiconductor package; and solder paste disposed on the conductive via between the first semiconductor package and the second semiconductor package.

16. The semiconductor device of claim 15, wherein the adhesive tape extends from the substrate of the first semiconductor package to the substrate of the second semiconductor package.

17. The semiconductor device of claim 15, further comprising a shield layer formed on the first semiconductor package. ​ ​

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