Hybrid Switching Architecture for SerDes Communication Channels in Reconfigurable Hardware Modeling Circuits

Abstract

Various aspects of the disclosed technology relate to hybrid static switching and dynamic switching in a reconfigurable hardware modeling circuit for flexible and low-latency communication. The reconfigurable hardware modeling circuit includes a serializer circuit and a deserializer circuit for one or more communication ports, wherein the serializer circuit has a first subchannel for receiving data sent from the reconfigurable hardware modeling circuit, and the deserializer circuit has a second subchannel for outputting data received by the reconfigurable hardware modeling circuit. The reconfigurable hardware modeling circuit also includes a static switching circuit and a dynamic switching circuit, the static switching circuit can be configured to couple each of the first zero or one or more subchannels in the first subchannel with one of the signal sources including the second subchannel, and the dynamic switching circuit can be configured to couple each of the second zero or one or more subchannels in the first subchannel with more than one of the signal sources in a time division multiplexing mode.

Description

Technical Field

[0001] The technology disclosed herein relates to the field of circuit design verification. Various embodiments of the disclosed technology are particularly useful for flexible and low-latency communication between reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device. Background Art

[0002] Electronic circuits, such as integrated circuits, are used in a variety of products, from automobiles to smartphones to personal computers. Designing and manufacturing these circuit devices typically involves many steps, which are referred to as a "design flow." The specific steps in the design flow typically depend on the type of integrated circuit being designed, its complexity, the design team, and the integrated circuit manufacturer or foundry that will manufacture the circuit. Typically, software and hardware "tools" will verify the design at various stages of the design flow by running software simulators and / or hardware emulators / prototyping devices. The verification process is then used to identify and correct errors in the design.

[0003] For most design flows, some steps are common. Typically, the specification for a new circuit is initially described as a logic design at a very abstract level. An example of this type of abstract description is a register transfer level (RTL) description of a circuit. With this type of description, the circuit is defined in terms of the exchange of signals between hardware registers and the logical operations performed on those signals. Register transfer level design typically employs a hardware description language (HDL) (sometimes also called a hardware design language or hardware definition language), such as a very high speed integrated circuit hardware description language (VHDL) or Verilog. The logic of the circuit is then analyzed to confirm that the logic incorporated into the design will accurately perform the functions required of the circuit. This analysis is sometimes referred to as "functional verification."

[0004] Logic simulation is a tool used for functional verification. Current design hardware involves writing a program in a hardware description language. The simulation can be performed by running the program on a computer. Such electronic design simulators can determine what the various states of the electronic design will be when certain input stimuli are presented. Simulators are commercially available, such as the Questa series of simulators from Mentor Graphics Corporations of Wilsonville, Oregon.

[0005] However, for large and complex designs such as SoC (system on chip) designs, software-based simulation may be too slow. The execution speed of the simulator is significantly reduced as the design size increases (which is caused by cache misses and memory swaps). The simulation and prototyping are significantly improved in verification productivity by adopting a reconfigurable hardware modeling device (which includes a simulator and a prototyping device). Simulators and prototyping devices based on field programmable gate arrays (FPGAs) rely on actual silicon implementations, and circuit verification is usually performed in parallel when the circuit design will be executed in actual devices. On the contrary, the simulator performs circuit verification by serially executing the hardware description code. Different types of execution will result in orders of magnitude differences in execution time. Examples of hardware simulators include the VELOCE series simulators available from Mentor, Inc. in Wilsonville, Oregon, the ZEBU series simulators available from Synopsys, Inc. in Mountain View, California, and the PALLADIUM series simulators available from Cadence Design Systems in San Jose, California.

[0006] Reconfigurable hardware modeling devices are usually constructed by connecting a large number of isomorphic or heterogeneous reconfigurable hardware modeling circuits. For example, Veloce StratoM contains 1024 analog computing devices and 256 non-computing switching devices. Larger systems may have 5000 or more devices. Each of these reconfigurable hardware modeling circuits can be programmed to model some elements of the integrated circuit design, some elements of the testbench, or both. The testbench is used to create stimuli or apply stimuli to the modeling design during the verification process, and to capture and estimate the response from the modeling design to evaluate whether the design meets expectations.

[0007] Although reconfigurable hardware modeling circuits are usually connected by high-speed links, most of the connections between them in large systems cannot be direct connections because each circuit does not have enough links to reach all other circuits. In addition, circuit designs usually exhibit a certain degree of locality, so the simulation system modeling these circuit designs has unevenness and locality in its interconnection network. Some groups in the reconfigurable hardware modeling circuits are more deeply connected with multiple direct physical links and paths, while other remote circuits / groups are more restrictedly connected through indirect paths that may involve multiple intermediate nodes. Due to these characteristics, it is not practical to make each of the physical communication channels connected to the reconfigurable hardware modeling circuits dedicated to the traffic between specific circuit pairs. On the other hand, sharing physical communication channels by multiple links will introduce delays. Other disadvantages include contention and resource control restrictions. Summary of the invention

[0008] Various aspects of the disclosed technology relate to techniques for employing hybrid static switching and dynamic switching in reconfigurable hardware modeled circuits for flexible and low-latency communications. In one aspect, a reconfigurable hardware modeling device includes: a plurality of reconfigurable hardware modeling circuits interconnected directly or indirectly, wherein each of the plurality of reconfigurable hardware modeling circuits includes: a serializer circuit and a deserializer circuit for one or more communication ports of each of the plurality of reconfigurable hardware modeling circuits, the serializer circuit having a first subchannel, the first subchannel being used to receive data sent from each of the plurality of reconfigurable hardware modeling circuits, and the deserializer circuit having a second subchannel, the second subchannel being used to output data received by each of the plurality of reconfigurable hardware modeling circuits; a static switching circuit, which can be configured to, when a hardware model of a circuit design is implemented in the reconfigurable hardware modeling device, couple each of first zero or one or more subchannels of the first subchannel with one of signal sources during a verification process for the circuit design, the signal source including the second subchannel; and a dynamic switching circuit, which can be configured to, when the hardware model of the circuit design is implemented in the reconfigurable hardware modeling device, in a time division multiplexing mode, couple each of second zero or one or more subchannels of the first subchannel with more than one of the signal sources during a verification process for the circuit design.

[0009] The static switching circuit and the dynamic switching circuit may be configured to operate using one or more identical sub-channels of the second sub-channels.

[0010] The static switching circuit may be configured to couple a subchannel in the second subchannels with more than one subchannel in the first zero or one or more subchannels in the first subchannels.

[0011] The signal source may also include a model computation subsystem in each of the plurality of reconfigurable hardware modeling circuits, the model computation subsystem coupled to the dynamic switching circuit.

[0012] The reconfigurable hardware modeling device may also include: a plurality of network circuits, which can be configured to assist communication between the plurality of reconfigurable hardware modeling circuits, wherein each of the plurality of network circuits includes: other serializer circuits and other deserializer circuits, which are used for other one or more communication ports of each of the plurality of network circuits, the other serializer circuit having a third subchannel, the third subchannel being used to receive data sent from each of the plurality of network circuits, the other deserializer circuit having a fourth subchannel, the fourth subchannel being used to output data received by each of the plurality of network circuits; other static switching circuits a circuit which can be configured to, when a hardware model of the circuit design is implemented in a reconfigurable hardware modeling device, couple each of a third zero or one or more sub-channels in the third sub-channel with one of the other signal sources during a verification process for the circuit design, the other signal sources including the fourth sub-channel; and other dynamic switching circuits which can be configured to, when a hardware model of the circuit design is implemented in the reconfigurable hardware modeling device, couple each of a fourth zero or one or more sub-channels in the third sub-channel with more than one of the signal sources in a time division multiplexing mode during a verification process for the circuit design.

[0013] The other static switching circuits and the other dynamic switching circuits may be configured to operate using one or more of the same sub-channels in the fourth sub-channel.

[0014] The other static switching circuit may be configured to couple a subchannel in the fourth subchannel with more than one subchannel in the third zero or one or more subchannels in the third subchannel.

[0015] The serializer circuit and the deserializer circuit may conform to the Common Electrical I / O (CEI) Interoperability Agreement (IA) promulgated by the Optical Interconnect Forum (OIF).

[0016] The static switching circuit is used to carry one or more links of timing-critical traffic during the verification process for the circuit design.

[0017] The reconfigurable hardware modeling device may be a processor-based simulator, and the plurality of reconfigurable hardware modeling circuits may be Boolean processor circuits.

[0018] The reconfigurable hardware modeling device may be an FPGA-based simulator or an FPGA-based prototyping device, and the plurality of reconfigurable hardware modeling circuits may be commercial FPGA chips or custom-designed FPGA chips.

[0019] On the other hand, a reconfigurable hardware modeling circuit includes: a model computing subsystem; a network subsystem having a connection to the model computing subsystem; and a plurality of communication ports, wherein the network subsystem includes: a serializer circuit and a deserializer circuit, which are used for one or more communication ports of the plurality of communication ports, wherein the serializer circuit has a first subchannel, the first subchannel is used to receive data sent from the reconfigurable hardware modeling circuit, and the deserializer circuit has a second subchannel, the second subchannel is used to output data received by the reconfigurable hardware modeling circuit. The reconfigurable hardware modeling circuit also includes: a static switching circuit, which can be configured to couple each of the first zero or one or more subchannels in the first subchannel with one of the signal sources including the second subchannel; and a dynamic switching circuit, which can be configured to couple each of the second zero or one or more subchannels in the first subchannel with more than one of the signal sources in a time division multiplexing mode.

[0020] The static switching circuit and the dynamic switching circuit may be configured to operate using one or more identical sub-channels of the second sub-channels.

[0021] The static switching circuit may be configured to couple a subchannel in the second subchannels with more than one subchannel in the first zero or one or more subchannels in the first subchannels.

[0022] The signal source may also include a model calculation subsystem coupled to the dynamic switching circuit.

[0023] The serializer circuit and the deserializer circuit may conform to the Common Electrical I / O (CEI) Interoperability Agreement (IA) promulgated by the Optical Interconnect Forum (OIF).

[0024] The reconfigurable hardware modeling circuit may be a reconfigurable hardware modeling circuit based on a Boolean processor, or a reconfigurable hardware modeling circuit based on an FPGA.

[0025] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features of the dependent claims may be combined with features of the independent claim as appropriate and with features of other dependent claims and not only as explicitly set out in the claims.

[0026] Certain objects and advantages of various inventive aspects have been described above. Of course, it should be understood that not all of these objects or advantages need be achieved according to any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology can be implemented or realized in a manner that implements or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1A An illustrative example of a simulation system having a simulator coupled to a target is shown.

[0028] Figure 1B An illustrative example of an analog circuit board is shown.

[0029] Figure 2 A programmable computer system is shown with which various embodiments of the disclosed technology may be employed.

[0030] Figure 3 An example of a reconfigurable hardware modeling circuit that employs dynamic switching techniques to process time-division multiplexed data streams configured for a specific design verification process is shown.

[0031] Figure 4 An example of a network subsystem in a reconfigurable hardware modeling circuit that employs dynamic switching technology and serializer / deserializer technology for communication links is shown.

[0032] Figure 5 An example of a network subsystem in a reconfigurable hardware modeling circuit that employs static switching technology and serializer / deserializer technology for communication links and is configured for a specific design verification process is shown.

[0033] Figure 6 An example of a reconfigurable hardware modeling circuit having a hybrid dynamic and static switching architecture in its network subsystem and configured for a specific design verification process according to various embodiments of the disclosed technology is shown.

[0034] Figure 7 An example of a node in an indirect communication network is shown. DETAILED DESCRIPTION

[0035] General considerations

[0036] Various aspects of the technology disclosed herein relate to techniques for employing hybrid static switching and dynamic switching in reconfigurable hardware modeling circuits for flexible and low-latency communications. In the following description, many details are set forth for the purpose of explanation. However, those of ordinary skill in the art will recognize that the disclosed technology can be practiced without using these specific details. In other cases, in order to avoid confusing the technology disclosed herein, known features are not described in detail.

[0037] Some of the techniques described herein may be implemented using software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of the two. For example, some of the disclosed techniques may be implemented as part of an electronic design automation (EDA) tool. These methods may be performed on a single computer or on a networked computer.

[0038] Although the operations of the disclosed methods are described in a particular order for ease of presentation, it should be understood that this description includes rearrangement unless the specific language described below requires a specific ordering. For example, in some cases, the operations described in sequence can be rearranged or performed simultaneously. In addition, for the sake of simplicity, the disclosed flowcharts and block diagrams generally do not show the various ways in which a particular method can be used in conjunction with other methods. In addition, the detailed description sometimes uses terms such as "operation" and "connection" to describe the disclosed method / system. These terms are high-level descriptions of the actual operations performed. The actual operations corresponding to these terms will vary depending on the specific implementation, and can be easily discerned by a person of ordinary skill in the art.

[0039] Furthermore, as used herein, the term "design" is intended to encompass data that describes an entire integrated circuit device. However, the term is also intended to encompass smaller sets of data that describe one or more components of the entire device (e.g., a portion of an integrated circuit device). Furthermore, the term "design" is also intended to encompass data that describes more than one microdevice, such as data for forming multiple microdevices on a single wafer.

[0040] Declarative Hardware Modeling Environment

[0041] Reconfigurable hardware modeling devices can be simulators or prototyping devices. Two types of simulators have been developed. The first type is based on FPGA. In an FPGA-based architecture, each FPGA chip (reconfigurable hardware modeling circuit) has a network of pre-wired blocks of lookup tables and coupled triggers. The lookup table can be programmed as a Boolean function, and each of the lookup tables can be programmed to connect or bypass associated one or more triggers. The lookup table with a connection trigger acts as a finite state machine, while the lookup table with a bypass trigger operates as a combinational logic. The lookup table can be programmed to mimic any combinational logic of a predetermined number of inputs and outputs. In order to simulate the circuit design, the circuit design is first compiled and mapped to an array of interconnected FPGA chips. The compiler usually needs to divide the circuit design into slices (sub-circuits) so that each slice is adapted to the FPGA chip. The sub-circuit is then synthesized into a lookup table (i.e., content is generated in the lookup table so that the lookup table generates the function of the sub-circuit together). Subsequently, placement and routing are performed on the FPGA chip in a manner that maintains the connectivity in the original circuit design.

[0042] The programmable logic chip (reconfigurable hardware modeling circuit) used by the simulator can be a commercial FPGA chip or a custom-designed analog chip containing programmable logic blocks. The simulator based on a custom FPGA can have a specially designed internal interconnect network of programmable elements within each custom FPGA, an external interconnect network and I / O structure of the custom FPGA, and a debug engine for the design being tested. Compared with its counterpart based on commercial FPGAs, this architecture enables fast and structurally correct compilation and high design visibility in the silicon structure, with 100% access without probe compilation and fast waveform tracking. Commercial FPGA chips can have a slightly larger capacity density than custom FPGA chips. For a given design, a simulator based on a custom FPGA may require more FPGAs than a simulator based on a commercial FPGA, resulting in a larger physical size and higher power consumption.

[0043] The second type of simulator is processor-based: an array of Boolean processors (reconfigurable hardware modeling circuits) that can share data with each other is used to map the circuit design, and Boolean operations are scheduled and executed accordingly. Similar to FPGA-based, the circuit design first needs to be divided into sub-circuits so that the code of each sub-circuit fits the instruction memory of the processor. However, the compilation speed of processor-based simulators is much faster than that of FPGA-based simulators. Compared with FPGA-based simulators, the disadvantages of processor-based simulators are limited execution speed in transaction-based mode, high power consumption, and large physical size.

[0044] The simulator can operate in various modes. In the in-circuit simulation mode, the simulator is connected to the user's target system to form a prototype of the system that the user is designing. The simulator is usually replaced with the circuit designed for the target system, allowing system-level and software testing before silicon availability. Although the simulator will run up to six orders of magnitude faster than the emulator, it is usually not enough to run at the same speed as the physical target system (a few megahertz vs. hundreds of megahertz). A rate adapter can be introduced between the target system and the simulator. The rate adapter behaves like a buffer. It caches signal activity from the design-under-test (DUT) at simulation speed and sends it to the target system at real-time speed. Conversely, it captures signal activity from the target system at full speed, caches it, and then sends it back to the DUT at simulation speed. Even when rate adapters are available, the continuous evolution of the speed and complexity of various I / O protocols may make timely rate adapter development difficult.

[0045] In the accelerated mode, the physical target system is replaced by a virtual target system modeled by one of the high-level languages ​​(e.g., SystemVerilog, SystemC, or C++). The accelerated mode leverages existing simulation test benches and eliminates the need for external rate adapters. The test bench creates test vectors and checks the corresponding responses of the circuit model. In addition to eliminating the rate adapter, the accelerated mode has advantages such as no hardware dependencies, the ability to use simulators remotely, and the ability to run verification corner cases.

[0046] The acceleration mode can be either cycle-based or transaction-based. The cycle-based acceleration mode employs a signal-level interface or a bit-level interface that connects the testbench processed by the host workstation to the design model on the simulator. Each transition on each interface signal must be transferred between the testbench and the design model at the slow speed of the testbench simulated in the workstation. As a result, the speed of the simulator is wasted by waiting for these signal transfers to be performed.

[0047] Transaction-based acceleration reduces the amount of communication between the workstation and the simulator by replacing bit-by-bit exchanges with transaction exchanges. Data exchange is carried out through a so-called transaction processor. The transaction processor converts high-level commands from the test platform on the host computer into signal-level bit sequences required by the tested design model on the simulator, and vice versa. The transaction processor includes a front-end agent interface on the workstation or host computer, a back-end bus functional model on the simulator, and a physical communication channel between the host computer and the simulator. This allows data to be streamed and buffered between the test platform on the host computer and the tested design on the simulator, thereby accelerating the execution of the test platform on the host computer. Therefore, the design team can access the full performance of the simulator. In addition to performance, transaction-based simulation eliminates the need for rate adapters. The tested design can be connected to a "virtual device" (software model of the device) running on the host computer through a transaction-level interface, or connected to a physical device through a transaction-level interface and a "virtual device" acting as a bridge device.

[0048] In addition to simulators, reconfigurable hardware modeling equipment also includes FPGA prototyping equipment. FPGA prototyping is often deployed near the end of the verification process to capture system-level issues. For designs that rely heavily on commercial intellectual property (IP), FPGA-based prototypes are ideal test platforms for ensuring that all IP components perform together. FPGA-based prototypes can also be used as a carrier for software development and verification. Embedded software has become a major part of modern system-on-chip (SoC) design. FPGA prototyping provides software developers with early access to fully functional hardware platforms before actual silicon. This enables the implementation of early software development tasks such as operating system (OS) integration and application testing. The improved productivity of software development and verification greatly accelerates the time to market for products.

[0049] FPGA prototypes are designed and built to achieve the highest possible execution speed, allowing the speed range to be extended to tens of megahertz, compared to FPGA-based simulators, which typically operate at 1 million to 2 million cycles per second. The disadvantages of FPGA prototyping are limited capacity, limited debugging capabilities, and long startup times. With the increasing complexity of FPGAs and advances in simulation and prototyping technology, the line between FPGA-based prototyping and simulation is blurring.

[0050] In some embodiments, the disclosed techniques may be implemented as part of a hardware simulation environment, e.g. Figure 1AAs shown in the figure, the hardware simulation environment includes a simulator 120 coupled to a host computer or workstation 110. The workstation 110 can be implemented by one or more computing systems. A computing system can include a single computer or multiple computers (e.g., a master computer and multiple slave computers). The workstation provides the ability to load a DUV (design-under-verification, also known as DUT-design under test) model into the simulator, control the execution of the DUV model on the simulator over time, and serve as a debugging interface for the DUV model on the simulator. As previously discussed, in some operating modes, the workstation can include a test platform and possibly other software models.

[0051] The simulator 120 includes a plurality of printed circuit boards (simulation boards) 130. These simulation boards 130 are networked (not shown). A circuit design can be partitioned by the workstation 110 and loaded into the simulation boards 130 for frequent simulation with test bench components.

[0052] In the in-circuit simulation mode, one or more targets 180 may be coupled to simulator 120, such as Figure 1A As shown. In some simplified environments, the target can be a piece of test equipment that generates and verifies test data, such as a network tester. In other environments, the target can be the actual circuit that the DUT model will interact with its final application (e.g., other hardware components of the system for which the DUT model is designed). The target can be a static target or a dynamic target, depending on whether the clock signal of the design running in the simulator can be suspended.

[0053] Figure 1B An example of an analog circuit board 130 is shown. The analog circuit board 130 includes an array of analog devices 140 (reconfigurable hardware modeling circuits). The analog devices 140 can be programmed to model, for example, combinational logic elements, sequential circuit elements, and memories. The analog devices 140 can be processor-based or FPGA-based.

[0054] Also included in the analog circuit board 130 is a configurable interconnect system 150, a programming system 160, and a debugging system 170. One portion of a circuit design on one analog device may require data calculated by another portion of the design on another analog device. The configurable interconnect system 150 allows data to be moved between analog devices 140. In some embodiments, the configurable interconnect system 150 may include a cross-bar device, a multiplexer, some other configurable network, or any combination thereof.

[0055] Programming system 160 can enable various other types of data to be brought to or from emulated device 140. Examples include programming data used to configure the emulated device to perform a particular function, visibility data collected from debug system 170 and brought to host workstation 110 for display, and content data read from or written to memory circuits in emulated device 140.

[0056] Debug system 170 enables the simulation system to monitor the behavior of the modeled circuit design. The required data for visibility viewing purposes can be stored in debug system 170. Debug system 170 can also provide resources for detecting specific conditions that occur in the circuit design. This condition detection is sometimes called a trigger.

[0057] The simulator 120 is coupled to the host workstation 110 via an interface system 190. The interface system 190 includes one or more interfaces. A particular interface is optimized to transfer large amounts of data, such as data containing a simulated circuit design model (e.g., an FPGA configuration bitstream), the initial contents of registers and design memory, and data for debugging purposes. The interface is independent of the design under test and may include dedicated logic or programmed logic in the simulator.

[0058] The interface system may also include one or more transaction level interfaces. These interfaces may be optimized for small packets and fast streaming speeds of data. For example, the speed may be in the order of 2-3 gigabits per second. As discussed previously, communication is performed by a transaction processor. The transaction processor includes a back-end bus functional model-aware logic in the simulator model, which requires the simulator infrastructure clock to remain operational, even if the design clock may be stopped.

[0059] It should also be understood that Figure 1A The simulation system and Figure 1B The analog circuit board 130 in the figure is shown only as an example and is not intended to be limiting. Various embodiments of the disclosed technology can be implemented using only a subset of the components shown in the figure, or including an alternative combination of components, including components not shown in the figure.

[0060] Exemplary Computer-Based Operating Environment

[0061] Figure 2An illustrative example of a computing device 201 is shown that can be used as a workstation 110 and / or implement various embodiments of some or all of the disclosed technology. As shown in the figure, the computing device 201 includes a computing unit 203 having a processing unit 205 and a system memory 207. The processing unit 205 can be any type of programmable electronic device for executing software instructions, but can typically be a microprocessor. The system memory 207 can include a read-only memory (ROM) 209 and a random access memory (RAM) 211. As will be understood by those of ordinary skill in the art, both the read-only memory (ROM) 209 and the random access memory (RAM) 211 can store software instructions executed by the processing unit 205.

[0062] The processing unit 205 and the system memory 207 are directly or indirectly connected to one or more peripheral devices via the bus 213 or an alternative communication structure. For example, the processing unit 205 or the system memory 207 can be directly or indirectly connected to one or more additional memory storage devices, such as a "hard disk" disk drive 215, a removable disk drive 217, an optical drive 219, or a flash memory card 221. The processing unit 205 and the system memory 207 can also be directly or indirectly connected to one or more input devices 223 and one or more output devices 225. The input devices 223 can include, for example, a keyboard, a pointing device (such as a mouse, a touch pad, a stylus, a trackball, or a joystick), a scanner, a camera, and a microphone. The output devices 225 can include, for example, a monitor display, a printer, and a speaker. For various examples of the computer 201, one or more peripheral devices 215-225 can be housed internally with the computing unit 203. Alternatively, one or more peripheral devices 215-225 can be external to the housing for the computing unit 203 and connected to the bus 213 via, for example, a universal serial bus (USB) connection.

[0063] In some embodiments, the computing unit 203 may be directly or indirectly connected to one or more network interfaces 227 for communicating with other devices constituting the network. The network interface 227 converts data and control signals from the computing unit 203 into network messages according to one or more communication protocols (e.g., Transmission Control Protocol (TCP) and Internet Protocol (IP)). In addition, the interface 227 may employ any suitable connection agent (or combination of agents) for connecting to the network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are known in the art, and therefore will not be discussed in more detail here.

[0064] It should be understood that computer 201 is shown only as an example and is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices, including Figure 2 The components of the computer 201 shown include only Figure 2 A subset of the components shown, or an alternative combination of components thereof, including Figure 2 For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, multiple single-processor and / or multi-processor computers arranged in a network, or some combination of the two.

[0065] Hybrid network based on a combination of dynamic switching and static switching

[0066] Reconfigurable hardware modeling devices typically include a large number of reconfigurable hardware modeling circuits. The reconfigurable hardware modeling circuit may include a subsystem for performing network switching functions (referred to as a network subsystem) and a subsystem for model calculation (referred to as a model calculation subsystem). The model calculation subsystem is configured to perform logical functions on signal data (including locally generated data, locally stored data, data obtained from other devices via the network subsystem, or any combination thereof), and to send some data to other devices via the network subsystem. The network subsystem is typically responsible for transmitting signal data with other circuits including other reconfigurable hardware modeling circuits, such as delivering the signal data into or out of the reconfigurable hardware modeling circuit. The network subsystem may also be configured to transmit data from input to output, acting as a bridge between reconfigurable hardware modeling circuits that are not directly connected via a physical channel.

[0067] The bridging function is important because a large number of reconfigurable hardware modeling circuits in the network cannot be completely connected to each other through direct physical links. Only a limited number of physical communication channels can be connected to the reconfigurable hardware modeling circuits. The collection of physical links that interconnect the modeling circuits in the simulator usually has unevenness and locality in its interconnection network, and some reconfigurable hardware modeling circuit groups are more closely connected to multiple direct physical links and paths than other remote circuits / groups. In this way, the network subsystem for some of these reconfigurable hardware modeling circuits needs to act as a switching element for non-direct paths between other reconfigurable hardware modeling circuits.

[0068] For the same reason, physical communication channels connected to reconfigurable hardware modeling circuits cannot typically be dedicated to traffic between specific pairs of circuits. Some physical communication channels that transmit data out of the reconfigurable hardware modeling circuit may need to transmit traffic to more than one destination, while some physical communication channels that transmit data into the reconfigurable hardware modeling circuit may need to transmit traffic from more than one source. For example, a reconfigurable hardware modeling circuit can typically be configured to receive input time-division multiplexed data from a communication channel and send data to different output communication channels according to different time slots on the time-division multiplexed communication channel. Similarly, a reconfigurable hardware modeling circuit can be configured to combine data from different time slots on multiple communication channels to form a time-division multiplexed data stream to be transmitted using a single output communication channel. This approach is sometimes referred to as time-division multiplexing. In addition to the types of traffic bridged by the reconfigurable hardware modeling circuit, there is also traffic that is initiated or terminated at the model computing subsystem of the reconfigurable hardware modeling circuit.

[0069] Figure 3 An example of a reconfigurable hardware modeling circuit 300 that uses dynamic switching technology to process a time-division multiplexed data stream configured for a specific design verification process is shown. The reconfigurable hardware modeling circuit 300 includes a model calculation subsystem 310 and a network subsystem 320. The network subsystem 320 includes a dynamic switching circuit 330. The figure also shows four communication channels 340, 350, 360 and 370, a subset of which are connected to the reconfigurable hardware modeling circuit 300. The dynamic switching circuit 330 is configured to receive data from the communication channel 340 and send the data to at least three different locations: the model calculation subsystem 310, the communication channel 360 and 370 according to different time slots. The dynamic switching circuit 330 is also configured to receive data from the communication channel 350 and send the data to the communication channels 360 and 370 according to different time slots. In addition to demultiplexing the received data, the dynamic switching circuit 330 is also configured to mix data from communication channels 340, 350 and possibly other communication channels (not shown) to generate traffic for output through communication channel 360, and to mix data from communication channels 340, 350, the model computing subsystem 310 and possibly other communication channels (not shown) to generate traffic for output through communication channel 370.

[0070] As shown in the example, the dynamic switching circuit can demultiplex, align, switch and re-multiplex data streams, so it is very flexible for routing. However, the dynamic switching circuit may also introduce delays. Because the data from the local computing subsystem is mixed with the data carried from the input link to the output link, the delay of the switching part will be large. The delay in the communication system will have a negative impact on the performance of the analog system. Competition and control resource limitations are two other disadvantages associated with dynamic switching. When the paths originating from different points may want to use the same communication channel in the same time slot, competition will occur. This cannot be done, and all candidates except one candidate must wait. The more obvious shared network links on the path, the higher the possibility of the impact of competition on the data carried by the communication channel. Control resources are information indicating the switching settings for a specific time slot. The storage of this information is limited, thereby limiting the amount of data carried by the resources controlled by dynamic switching.

[0071] Serializer / deserializer (SerDes) technology is another technology that can be used to compensate for limited input / output and increase the communication speed and capacity of reconfigurable hardware modeling circuits. Serializer / deserializer links are high-speed links that can typically run at several or tens of Gb / s. Serializer / deserializer circuits include serializer circuits and deserializer circuits. The serializer circuit converts the input parallel data bits into a serial data stream for transmission through a communication channel, and the deserializer circuit converts the data bits received from the serial data stream into a parallel form. Therefore, the serializer / deserializer circuit can present a parallel interface to the reconfigurable hardware modeling circuit for the connected communication channel. The communication channel for SerDes can be a single line or a differential pair. Differential signaling sends the same electrical signal as the differential signal pair, each signal in its own conductor. The conductor pair can be a wire (usually twisted together) or a trace on a circuit board. The Optical Internetworking Forum (OIF) has published the Common Electrical I / O (CEI) Interoperability Agreements (IAs), which define five generations of SerDes electrical interfaces at 3.125, 6, 10, 28, and 56 Gb / s.

[0072] The reconfigurable hardware modeling circuit can apply / receive a set of independent data streams on each bit of the SerDes parallel interface, which runs at a data rate of approximately 1 / P of the SerDes transmit clock, where P is the width of the parallel interface. In practice, the SerDes transmit clock can run slightly faster than the data rate of the input stream by P times because encoding and correction overhead data are also transmitted. P can be 2 to 16 or more.

[0073] Figure 4 An example of a network subsystem 400 in a reconfigurable hardware modeling circuit that employs dynamic switching technology and serializer / deserializer technology for communication links is shown. The network subsystem 400 includes a dynamic switching circuit 410, a deserializer circuit 420, and a serializer circuit 430. Only two communication channels 440 and 450 are shown in this figure. Communication channel 440 is configured to be coupled to deserializer circuit 420, while communication channel 450 is configured to be coupled to serializer circuit 430. Both deserializer circuit 420 and serializer circuit 430 are coupled to dynamic switching circuit 410. In this way, communication channels 440 and 450 are associated with a parallel input channel group and a parallel output channel group of dynamic switching circuit 410, respectively. Dynamic switching circuit 410 is configured to be coupled to Figure 3 The dynamic switching circuit 330 in the MCU operates in a similar manner, but treats each of the parallel input / output as a communication channel. This arrangement can increase bandwidth and communication speed, but latency is still a problem, especially for some timing-critical links.

[0074] Figure 5 An example of a network subsystem 500 in a reconfigurable hardware modeling circuit is shown, which uses static switching technology and serializer / deserializer technology for communication links and is configured for a specific design verification process. The network subsystem 500 includes a static switching circuit 510, a deserializer circuit 520, and a serializer circuit 530. Figure 4 Similarly, only two communication channels 540 and 550 are shown in the figure. Communication channel 540 is configured to be coupled to deserializer circuit 520, while communication channel 550 is configured to be coupled to serializer circuit 530. Deserializer circuit 520 and serializer circuit 530 are both coupled to static switching circuit 510. In this way, communication channels 540 and 550 are associated with a parallel input channel group and a parallel output channel group of static switching circuit 510, respectively.

[0075] The static switching circuit does not change the connection configuration of different clock cycles, but can maintain a fixed connection configuration for the entire design verification process. When the reconfigurable hardware modeling circuit is configured for different designs, this connection configuration can be changed to a different connection configuration. The static switching circuit 510 is shown as connecting two parallel input channels (560, 570) from the deserializer circuit 520 to the serializer circuit 530 through two parallel output channels (580, 590). This network used for these connections will not obtain input from the local model calculation subsystem, thereby significantly reducing the number of inputs to the switch. The combination of static switching reconfigurability plus significantly reduced input count allows the creation of switching circuits with significantly low latency. This network structure is also significantly smaller than a dynamic switching network. This type of switching system is sometimes referred to as an IVW (Indirect Virtual Wire) switch, because: using the switch in one or more continuous circuits to create an indirect virtual connection between a source and a non-adjacent endpoint, which is essentially similar to a direct connection, but with a longer delay.

[0076] Despite the advantage of low latency for indirect connections, static switching has some limitations. It is difficult to use static switching to manage locally generated data because local data connections have been omitted in order to have small and fast switches. Static switching also lacks flexibility because virtual channels on a physical link can only be assigned to a single source / destination path. Sending a single data value from a source to a specific destination requires a dedicated virtual channel group that is allocated from the source to the destination across intermediate resources. For a circuit with L physical communication channels and a P-width parallel interface to a SERDES link, it is impossible to build a fully interconnected system with more than L*P circuits because the circuit needs at least one dedicated output channel or input channel to / from each other circuit.

[0077] Various embodiments of the disclosed technology combine dynamic switching and static switching for SerDes communication channels to take advantage of the advantages of both technologies. The reconfigurable hardware modeling circuit includes a dynamic switching circuit and a static switching circuit. The sub-channels of the communication ports of the reconfigurable hardware modeling circuit created by the deserializer circuit can be configured to operate using one or both of the dynamic switching circuit and the static switching circuit. For timing-critical signals, static switching can be primarily or exclusively used to reduce latency. For non-timing-critical traffic, dynamic switching can be used to increase bandwidth and flexibility.

[0078] Figure 6An example of a reconfigurable hardware modeling circuit 600 according to various embodiments of the disclosed technology is shown, which has a hybrid dynamic switching and static switching architecture in its network subsystem and is configured for a specific design verification process. The reconfigurable hardware modeling circuit 600 includes a model calculation subsystem 610 and a network subsystem 620. The network subsystem 620 includes a serializer circuit 645, a deserializer circuit 635, a static switching circuit 640, and a dynamic switching circuit 630. The communication channels 630, 640, 650, and 660 shown in the figure are a subset of the communication channels connected to the reconfigurable hardware modeling circuit 600 through corresponding communication ports. Communication channels 630 and 650 are configured to be coupled to the deserializer circuit 635, while communication channels 640 and 660 are configured to be coupled to the serializer circuit 645. As a result, each of these communication channels is associated with the following subchannel groups: subchannels 631 and 632 for communication channel 630, subchannels 641 and 642 for communication channel 640, subchannels 651, 652 and 653 for communication channel 650, and subchannels 661 and 662 for communication channel 660.

[0079] Subchannels 642 and 652, 653 and 662 are connected by static switching circuit 640 to form indirect virtual lines, respectively. During the verification process for circuit design, these indirect virtual lines are used as part of the link between a specific pair of reconfigurable hardware modeling circuits. Subchannel 632 is also connected to model calculation subsystem 610 through static switching circuit 640 as part of the link with another circuit. Dynamic switching circuit 630 is configured to operate with the remaining subchannels. During the verification process for circuit design, each of these subchannels (631, 641, 651 and 661) can be shared by links between different reconfigurable hardware modeling circuit pairs. A specific link may have a part operated by a static switching circuit and another part operated by a dynamic switching circuit.

[0080] The configuration between subchannels and static / dynamic switching circuits is usually established when the design under test is compiled and mapped to the interconnected reconfigurable hardware modeling circuit array. Links for timing critical signals are usually formed using static switching. It should be noted that the subchannels for a specific communication channel can all be coupled to dynamic switching circuits or static switching circuits, or can be mixed with some subchannels coupled to one subchannel and other subchannels. However, each subchannel external (i.e., connected to the serializer circuit) can be coupled to a dynamic switching circuit or a static switching circuit, rather than connecting both at the same time. In addition, an input subchannel can be coupled to one or more output subchannels for the same communication channel and / or different communication channels through a static switching circuit, and coupled to one or more other output subchannels for the same communication channel and / or different communication channels through a dynamic switching circuit, or both.

[0081] The network used to connect the reconfigurable hardware modeling circuits can be a direct network or an indirect network. A direct network involves a direct connection between a subset of the reconfigurable hardware modeling circuits and a pure direct network, which means that all network nodes are reconfigurable hardware modeling circuits. In contrast, an indirect network involves the use of network circuits that are not reconfigurable hardware modeling circuits. These network circuits typically perform only switching, routing, or both functions. Figure 7 An example of a node in an indirect communication network is shown. In the figure, eight reconfigurable hardware modeling circuits 721-728 are not connected to each other, but are connected to a network circuit 710 used as a node. Analog devices often employ hybrid networks. In a hybrid network, there are some direct connections between reconfigurable hardware modeling circuits that include computational circuits, but there are also some pure network circuits that connect clusters of directly connected reconfigurable hardware modeling circuits together.

[0082] In one example of a hybrid network, reconfigurable hardware modeling circuits are directly connected to other reconfigurable hardware modeling circuits on the same printed circuit board, but are indirectly connected through network circuits when sending data between boards. Similarly, the same system has a collection of analog boards within a chassis that can be interconnected, and the connections between circuits on different chassis are through network circuits within each chassis, a first network circuit for an outbound path from a first chassis and a second network circuit for an inbound path from a second chassis to a final circuit. This use of indirect network elements to connect boards or chassis is conventional to allow all reconfigurable hardware modeling circuits in a system to symmetrically share the interconnect wiring inputs / outputs of a limited number of boards or the interconnect wiring inputs / outputs of the system. Interconnect resources are typically time-division multiplexed, and this sharing can allow data from and to multiple different circuits to be carried on scarce interconnect resources.

[0083] To reduce latency and increase bandwidth and flexibility, the network circuit can also combine static switching and dynamic switching for SerDes communication channels. This configuration can be similar to the network subsystem of the reconfigurable hardware modeling circuit, such as the example described above. According to various embodiments of the disclosed technology, the network circuit includes: a serializer / deserializer circuit for each communication channel connected to the network circuit; a static switching circuit, which can be configured to operate using one or more sub-channels of each of the one or more communication channels when implementing a part of the hardware model of the circuit design, and each of the one or more sub-channels is used as part of the link between two specific reconfigurable hardware modeling circuits during the verification process for the circuit design; and a dynamic switching circuit, which can be configured to operate using other sub-channels of each of the one or more communication channels when implementing a part of the hardware model of the circuit design, and each of the other sub-channels of each of the one or more other communication channels is shared by the link between different reconfigurable hardware modeling circuit pairs during the verification process for the circuit design.

[0084] in conclusion

[0085] Although the disclosed technology has been described with reference to specific examples including presently preferred modes of implementing the disclosed technology, those skilled in the art will appreciate that there are many variations and permutations of the above-described systems and technologies within the spirit and scope of the disclosed technology as set forth in the appended claims. For example, although specific terminology has been employed above to refer to electronic design automation processes, it should be understood that the various examples of the disclosed technology may be implemented using any desired combination of electronic design automation processes.

Claims

1. A reconfigurable hardware modeling device, comprising: Multiple reconfigurable hardware modeling circuits that are directly or indirectly interconnected, Wherein, each of the plurality of reconfigurable hardware modeling circuits comprises: a serializer circuit and a deserializer circuit for one or more communication ports of each of the plurality of reconfigurable hardware modeling circuits, the serializer circuit having a first subchannel for receiving data sent from each of the plurality of reconfigurable hardware modeling circuits, and the deserializer circuit having a second subchannel for outputting data received by each of the plurality of reconfigurable hardware modeling circuits; a static switching circuit configurable to, when a hardware model of a circuit design is implemented in the reconfigurable hardware modeling device, couple each of first zero or one or more of the first sub-channels to one of signal sources during a verification process for the circuit design, the signal source including the second sub-channel; and A dynamic switching circuit is configurable to, when a hardware model of the circuit design is implemented in the reconfigurable hardware modeling device, couple each of the second zero or one or more sub-channels of the first sub-channel to more than one of the signal sources in a time division multiplexing mode during a verification process for the circuit design.

2. The reconfigurable hardware modeling device according to claim 1, further comprising: a plurality of network circuits configurable to facilitate communication between the plurality of reconfigurable hardware modeling circuits, Wherein, each of the plurality of network circuits comprises: other serializer circuits and other deserializer circuits for other one or more communication ports of each of the plurality of network circuits, the other serializer circuits having a third subchannel for receiving data sent from each of the plurality of network circuits, the other deserializer circuits having a fourth subchannel for outputting data received by each of the plurality of network circuits; other static switching circuitry configurable to, when a hardware model of the circuit design is implemented in the reconfigurable hardware modeling device, couple each of the third zero or one or more of the third sub-channels with one of the other signal sources during a verification process for the circuit design, the other signal sources including the fourth sub-channel; and Other dynamic switching circuits may be configured to, when a hardware model of the circuit design is implemented in the reconfigurable hardware modeling device, couple each of the fourth zero or one or more sub-channels of the third sub-channel to more than one of the signal sources in a time division multiplexing mode during a verification process for the circuit design.

3. The reconfigurable hardware modeling device according to claim 2, wherein: The other static switching circuits and the other dynamic switching circuits may be configured to operate using one or more of the same sub-channels of the fourth sub-channels.

4. The reconfigurable hardware modeling device according to claim 2, wherein: The other static switching circuit may be configured to couple a subchannel of the fourth subchannel with more than one of the third zero or one or more subchannels of the third subchannel.

5. The reconfigurable hardware modeling device according to claim 1, wherein: The static switching circuit and the dynamic switching circuit may be configured to operate using one or more identical ones of the second sub-channels.

6. The reconfigurable hardware modeling device according to claim 1, wherein: The static switching circuit may be configured to couple a subchannel of the second subchannels with more than one of the first zero or one or more subchannels of the first subchannels.

7. The reconfigurable hardware modeling device according to claim 1, wherein: The signal source also includes a model computation subsystem in each of the plurality of reconfigurable hardware modeling circuits, the model computation subsystem coupled to the dynamic switching circuit.

8. The reconfigurable hardware modeling device according to claim 1, wherein: The serializer circuit and the deserializer circuit comply with the Common Electrical I / O (CEI) Interoperability Agreement (IA) promulgated by the Optical Interconnect Forum (OIF).

9. The reconfigurable hardware modeling device according to claim 1, wherein: The static switching circuit is used to carry one or more links of timing critical traffic during a verification process for the circuit design.

10. The reconfigurable hardware modeling device according to claim 1, wherein: The reconfigurable hardware modeling apparatus is a processor-based simulator, and the plurality of reconfigurable hardware modeling circuits are Boolean processor circuits.

11. The reconfigurable hardware modeling device according to claim 1, wherein: The reconfigurable hardware modeling device is an FPGA-based simulator or an FPGA-based prototyping device, and the plurality of reconfigurable hardware modeling circuits are commercial FPGA chips or custom-designed FPGA chips.

12. A reconfigurable hardware modeling circuit, comprising: Model calculation subsystem; a network subsystem having a connection to the model computing subsystem; and Multiple communication ports, Wherein, the network subsystem includes: a serializer circuit and a deserializer circuit, which are used for one or more communication ports of the plurality of communication ports, the serializer circuit having a first sub-channel, the first sub-channel being used to receive data sent from the reconfigurable hardware modeling circuit, and the deserializer circuit having a second sub-channel, the second sub-channel being used to output data received by the reconfigurable hardware modeling circuit; static switching circuitry configurable to couple each of first zero or one or more of the first subchannels to one of signal sources, the signal source including the second subchannel; and A dynamic switching circuit is configurable to couple each of the second zero or one or more of the first sub-channels to more than one of the signal sources in a time division multiplexing mode.

13. The reconfigurable hardware modeling circuit according to claim 12, wherein: The static switching circuit and the dynamic switching circuit may be configured to operate using one or more identical ones of the second sub-channels.

14. The reconfigurable hardware modeling circuit according to claim 12, wherein: The static switching circuit may be configured to couple a subchannel of the second subchannels with more than one of the first zero or one or more subchannels of the first subchannels.

15. The reconfigurable hardware modeling circuit according to claim 12, wherein: The signal source also includes the model calculation subsystem, which is coupled to the dynamic switching circuit.

16. The reconfigurable hardware modeling circuit according to claim 12, wherein: The serializer circuit and the deserializer circuit comply with the Common Electrical I / O (CEI) Interoperability Agreement (IA) promulgated by the Optical Interconnect Forum (OIF).

17. The reconfigurable hardware modeling circuit according to claim 12, wherein: The reconfigurable hardware modeling circuit is a reconfigurable hardware modeling circuit based on a Boolean processor.

18. The reconfigurable hardware modeling circuit according to claim 12, wherein: The reconfigurable hardware modeling circuit is a reconfigurable hardware modeling circuit based on FPGA.

Images