Control method and control device of display panel, display device

Abstract

A control method of a display panel, comprising: converting gray scale data of a display picture into gray scale voltage at a first refresh frequency; calculating average gray scale voltage of the display picture according to the gray scale voltage of the display picture; determining display parameters matched with the display picture according to the average gray scale voltage of the display picture; and outputting a control signal of the display picture to the display panel according to the display parameters matched with the display picture. The control signal comprises at least one of a data retention signal and an anode reset signal of a light emitting element of the display panel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display panel control method and device, and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) display device is considered to be an emerging application technology for next-generation flat panel displays because it has excellent characteristics such as self-emission, high contrast, thin thickness, wide viewing angle, fast response, use in flexible panels, wide temperature range, simple structure, and simple manufacturing process. SUMMARY

[0003] The following is an overview of subject matter of the detailed description herein. This overview is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display panel control method and device, and a display device.

[0005] In one aspect, the present disclosure provides a display panel control method, comprising: converting gray scale data of a display picture into gray scale voltages at a first refresh frequency; calculating an average gray scale voltage of the display picture according to the gray scale voltages of the display picture; determining display parameters matched with the display picture according to the average gray scale voltage of the display picture; and outputting a control signal of the display picture to a display panel according to the display parameters matched with the display picture. The control signal comprises at least one of the following: a data retention signal, and an anode reset signal of a light emitting element of the display panel.

[0006] In some example embodiments, the display stage of the display picture comprises a refresh stage and a retention stage. The display parameters comprise at least one of the following: a data retention voltage of the retention stage, a first anode reset voltage of the refresh stage, and a second anode reset voltage of the retention stage.

[0007] In some example embodiments, the converting the gray scale data of the display picture into the gray scale voltages comprises: for the gray scale data of each display unit of the display picture, searching for a gray scale voltage corresponding to the gray scale data in a stored gray scale conversion table.

[0008] In some example embodiments, the converting the gray scale data of the display picture into the gray scale voltages further comprises: if the gray scale voltage corresponding to the gray scale data of the display unit is not found in the gray scale conversion table, calculating the gray scale voltage corresponding to the gray scale data by using a preset gray scale mapping function.

[0009] In some example embodiments, the calculating the average gray scale voltage of the display frame according to the gray scale voltages of the display frame comprises: calculating the average value of the gray scale voltages of each display row of the display frame, and then calculating the average gray scale voltage of the display frame by using the average values of the gray scale voltages of all the display rows.

[0010] In some example embodiments, the determining the display parameter matched with the display frame according to the average gray scale voltage of the display frame comprises: searching for the display parameter matched with the average gray scale voltage of the display frame from a stored parameter reference table. The parameter reference table records at least one of the following: a mapping relationship between the average gray scale voltage and the data retention voltage, a mapping relationship between the average gray scale voltage and the first anode reset voltage and the second anode reset voltage.

[0011] In some example embodiments, the average gray scale voltage in the parameter reference table is in a positive correlation with the data retention voltage; and the average gray scale voltage in the parameter reference table is in an inverse correlation with the absolute value of the pressure difference between the first anode reset voltage and the second anode reset voltage.

[0012] In some example embodiments, the outputting the control signal of the display frame to the display panel according to the display parameter matched with the display frame comprises at least one of the following: outputting the data retention signal to the display panel in the retention stage, and the data retention signal maintains the data retention voltage; and outputting the anode reset signal to the display panel, and the anode reset signal maintains the first anode reset voltage in the refresh stage and maintains the second anode reset voltage in the retention stage.

[0013] In some example embodiments, the first refresh frequency is less than 60 Hz.

[0014] In another aspect, the embodiments of the present disclosure provide a control device of a display panel, which comprises a gray scale conversion module, a voltage calculation module, a parameter conversion module, and a signal output module. The gray scale conversion module is configured to convert gray scale data of a display frame into gray scale voltages at a first refresh frequency. The voltage calculation module is configured to calculate an average gray scale voltage of the display frame according to the gray scale voltages of the display frame. The parameter conversion module is configured to determine a display parameter matched with the display frame according to the average gray scale voltage of the display frame. The signal output module is configured to output a control signal of the display frame to the display panel according to the display parameter matched with the display frame. The control signal comprises at least one of a data retention signal and an anode reset signal of a light emitting element of the display panel.

[0015] In some example embodiments, the display stage of the display frame comprises a refresh stage and a hold stage. The display parameters comprise at least one of a data hold voltage of the hold stage, a first anode reset voltage of the refresh stage, and a second anode reset voltage of the hold stage.

[0016] In some example embodiments, the parameter conversion module comprises a first parameter conversion module, a second parameter conversion module, and a third parameter conversion module. The first parameter conversion module is configured to determine a first anode reset voltage matched with the display frame according to the average gray scale voltage of the display frame. The second parameter conversion module is configured to determine a second anode reset voltage matched with the display frame according to the average gray scale voltage of the display frame. The third parameter conversion module is configured to determine a data hold voltage matched with the display frame according to the average gray scale voltage of the display frame.

[0017] In some example embodiments, the signal output module comprises a first output module and a second output module. The first output module is configured to output an anode reset signal of the display frame to the display panel according to the display parameters matched with the display frame. The second output module is configured to output a data hold signal of the display frame to the display panel according to the display parameters matched with the display frame.

[0018] In another aspect, the embodiments of the present disclosure provide a display device, comprising a display panel and a control device as described above, the control device being configured to provide a control signal to the display panel.

[0019] In some example embodiments, the display panel comprises a pixel array, the pixel array comprising a plurality of sub-pixels, at least one sub-pixel comprising a light emitting element and a pixel circuit configured to drive the light emitting element to emit light, the pixel circuit comprising a plurality of transistors and at least one capacitor.

[0020] In another aspect, the embodiments of the present disclosure provide a control device, comprising a memory and a processor, the memory being configured to store a computer program, and the processor being configured to execute the computer program to implement the control method as described above.

[0021] In another aspect, the embodiments of the present disclosure provide a non-transitory computer readable storage medium storing a computer program, the computer program being executed to implement the control method as described above.

[0022] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shape and size of one or more components in the drawings do not reflect the actual proportion, and the purpose is only to schematically illustrate the present disclosure.

[0024] Figure 1 A flowchart of a control method of a display panel of at least one of the embodiments of the present disclosure;

[0025] Figure 2 A schematic diagram of a display device of at least one of the embodiments of the present disclosure;

[0026] Figure 3 An equivalent circuit diagram of a pixel circuit of at least one of the embodiments of the present disclosure;

[0027] Figure 4 For Figure 3 A working timing diagram of the pixel circuit provided;

[0028] Figure 5 A schematic diagram of a frame skipping driving mode of at least one of the embodiments of the present disclosure;

[0029] Figure 6 A waveform schematic diagram of a control signal of at least one of the embodiments of the present disclosure;

[0030] Figure 7 A schematic diagram of a control device of a display panel of at least one of the embodiments of the present disclosure;

[0031] Figure 8 Another schematic diagram of a control device of a display panel of at least one of the embodiments of the present disclosure;

[0032] Figure 9 Another schematic diagram of a control device of at least one of the embodiments of the present disclosure;

[0033] Figure 10 A schematic diagram of a display device of at least one of the embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] The embodiments of the present disclosure will be described in detail below with reference to the drawings. The embodiments can be implemented in various forms. One of ordinary skill in the art can easily understand that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other as long as there is no conflict.

[0035] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0036] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0037] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0038] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0039] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0040] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0041] In this disclosure, "about" or "approximately" means values ​​that are not strictly defined and are within the allowable range of process and measurement errors.

[0042] With the application of Low Temperature Polycrystalline Oxide (LTPO) technology, the refresh rate of OLED display panels can be reduced to 1 Hz or even lower. Since the human eye can perceive brightness changes at a frequency of approximately 24 Hz to 30 Hz, for LTPO-based display panels, when displaying at low frequencies (i.e., refresh rates lower than the conventional 60 Hz), the overall screen brightness needs to remain constant, and low-frequency brightness changes cannot be introduced during the display process.

[0043] This disclosure provides a control method and control device for a display panel, as well as a display device, which can improve the display effect of the display panel.

[0044] Figure 1 This is a flowchart illustrating a control method for a display panel according to at least one embodiment of the present disclosure. Figure 1 As shown, this disclosure provides a method for controlling a display panel, including:

[0045] Step S11: At the first refresh rate, the grayscale data of the display screen is converted into grayscale voltage.

[0046] Step S12: Calculate the average grayscale voltage of the displayed screen based on the grayscale voltage of the displayed screen;

[0047] Step S13: Determine the display parameters that match the display screen based on the average grayscale voltage of the display screen;

[0048] Step S14: Output control signals for the display screen to the display panel according to the display parameters matched by the display screen.

[0049] In some exemplary embodiments, the control method of this embodiment can be applied to a display driver integrated circuit (DDIC) chip. Taking a display device employing an application processor (AP), a DDIC chip, and a display panel architecture as an example, after the AP renders and generates image data, it sends the image data to the DDIC chip, which then controls the display panel to display the image based on the image data. In this example, the DDIC chip can output different control signals to the display panel according to different display screens, thereby improving the display effect of the display panel.

[0050] In some exemplary embodiments, the control signal output to the display panel may include at least one of the following: a data hold signal, and an anode reset signal for the light-emitting elements of the display panel. In this exemplary embodiment, different control signals can be provided to different display screens according to the display parameters, thereby achieving a better display effect.

[0051] In some exemplary embodiments, the display phase of the display screen may include a refresh phase and a hold phase. Display parameters may include at least one of the following: a data hold voltage during the hold phase; a first anode reset voltage during the refresh phase; and a second anode reset voltage during the hold phase. In some examples, only the data hold voltage matching the display screen can be determined based on the average grayscale voltage of the display screen; or, only the anode reset voltage matching the display screen (including the first and second anode reset voltages) can be determined based on the average grayscale voltage of the display screen; or, both the data hold voltage and the anode reset voltage matching the display screen can be determined based on the average grayscale voltage of the display screen. In this example, by selecting a superior display parameter or combination, the display effect of the display panel can be improved.

[0052] In some exemplary embodiments, step S14 may include at least one of the following: during the hold phase, outputting a data hold signal to the display panel, wherein the data hold signal maintains a data hold voltage; and outputting an anode reset signal to the display panel, wherein the anode reset signal maintains a first anode reset voltage during the refresh phase and a second anode reset voltage during the hold phase. In this example, the data hold signal can be generated based on the data hold voltage, and the anode reset signal can be generated based on the first anode reset voltage and the second anode reset voltage. In some examples, the data hold voltage may range from approximately 0.2V to 7.0V. The first anode reset voltage may range from approximately -0.5V to -6.0V, and the second anode reset voltage may range from approximately -0.5V to -6.0V. This embodiment is not limited in this respect.

[0053] In some exemplary embodiments, the first refresh rate may be less than 60Hz. The control method provided in this example is executed in a low-frequency drive state, thereby improving the low-frequency flicker effect of the display panel.

[0054] In some exemplary embodiments, the grayscale data conversion and average grayscale voltage calculation of the displayed image can be performed on a per-display-unit basis. That is, the grayscale data of each display unit is converted into a grayscale voltage, and the average grayscale voltage of all display units is calculated. In some examples, a display unit can be a pixel unit or a sub-pixel. However, this embodiment is not limited to this.

[0055] The following examples illustrate the solution of this embodiment.

[0056] Figure 2 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 2 As shown, the display device of this exemplary embodiment may include a display panel and a control device. The control device may include a DDIC chip 10. The display panel may include a pixel array 13, a plurality of first signal lines extending along a first direction (e.g., scan lines GL1 to GLm, light emission control lines EML1 to EMLo), and a plurality of second signal lines extending along a second direction (e.g., data lines DL1 to DLn). The first direction (e.g., horizontal direction) intersects the second direction (e.g., vertical direction), for example, the first direction and the second direction may be perpendicular to each other. Wherein, m, n, and o are all integers. The display panel is also provided with a gate driving circuit (e.g., including a first gate driving circuit 11 and a second gate driving circuit 12). The control device 10 and the gate driving circuit may be configured to drive the pixel array 13.

[0057] In some exemplary embodiments, the DDIC chip 10 can provide clock signals, start signals, etc., of specifications suitable for the first gate driving circuit 11 to the first gate driving circuit 11, and clock signals, start signals, etc., of specifications suitable for the second gate driving circuit 12 to the second gate driving circuit 12. The first gate driving circuit 11 can use the clock signals, start signals, etc., received from the DDIC chip 10 to generate scan signals provided to scan lines GL1 to GLm. The second gate driving circuit 12 can use the clock signals, start signals, etc., received from the DDIC chip 10 to generate light emission control signals provided to light emission control lines EML1 to EMLm. The DDIC chip 10 can also be adapted to generate data signals provided to data lines DL1 to DLn.

[0058] In some exemplary embodiments, the first gate driving circuit 11 can sequentially provide scan signals with on-level pulses to scan lines GL1 to GLm. For example, the first gate driving circuit 11 can be configured as a shift register and can generate scan signals by sequentially transmitting start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal. The second gate driving circuit 12 can sequentially provide light emission control signals with off-level pulses to light emission control lines EML1 to EMLo. For example, the second gate driving circuit 12 can be configured as a shift register and can generate light emission control signals by sequentially transmitting start signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. However, this embodiment is not limited in this respect.

[0059] In some exemplary embodiments, pixel array 13 may include a plurality of sub-pixels PX. A pixel unit may include three sub-pixels. The three sub-pixels are a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited thereto. In some examples, a pixel unit may include four sub-pixels, which are a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively. In some examples, the shape of the sub-pixels may be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally side by side, vertically side by side, or in a square arrangement. However, this embodiment is not limited thereto.

[0060] In some exemplary embodiments, at least one sub-pixel PX includes: a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The light-emitting element is electrically connected to the corresponding pixel circuit. The light-emitting element can be an OLED device, including an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. In some examples, the pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit can be a 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. However, this embodiment is not limited thereto.

[0061] Figure 3 This is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 3 As shown, the pixel circuit of this exemplary embodiment can be an 8T1C structure, that is, it includes a first transistor T1 to an eighth transistor T8 and a storage capacitor C1.

[0062] In some exemplary embodiments, the first transistor T1 to the seventh transistor T7 of the pixel circuit can be a first type of transistor, such as a P-type transistor, and the eighth transistor T8 can be a second type of transistor, such as an N-type transistor. However, this embodiment is not limited to this. For example, all transistors in the pixel circuit can be P-type transistors, or they can all be N-type transistors.

[0063] In some exemplary embodiments, the first type of transistors in the pixel circuit (e.g., first transistor T1 to seventh transistor T7) can be low-temperature polycrystalline silicon (LTPS) thin-film transistors, and the second type of transistors in the first pixel circuit (e.g., eighth transistor T8) can be oxide (O) thin-film transistors. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OX thin-film transistor is made of oxide (Oxide). LTPS thin-film transistors have advantages such as high mobility and fast charging, while OX thin-film transistors have advantages such as low leakage current. Integrating LTPS and OX thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate allows for the utilization of both advantages, enabling low-frequency driving, reducing power consumption, and improving display quality. However, this embodiment is not limited to this. For example, all transistors in the pixel circuit can be LTPS thin-film transistors, or all can be OX thin-film transistors.

[0064] In some exemplary implementations, such as Figure 3 As shown, the pixel circuit is electrically connected to the first scan line GLa, the second scan line GLb, the data line DL, the first power line PL1, the second power line PL2, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, and the reset control line RST. In some examples, the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GLa is configured to provide a first scan signal SCAN1 to the pixel circuit, the second scan line GLb is configured to provide a second scan signal SCAN2 to the pixel circuit, the data line DL is configured to provide a data signal DATA to the pixel circuit, the light emission control line EML is configured to provide a light emission control signal EM to the pixel circuit, and the reset control line RST is configured to provide a reset control signal RESET to the pixel circuit. The first initial signal line INIT1 is configured to provide a first initial signal for resetting the fifth node N5 and the first node N1, and the second initial signal line INIT2 is configured to provide a second initial signal (i.e., an anode reset signal) for resetting the fourth node N4 (i.e., the anode of the light-emitting element EL).

[0065] In some exemplary embodiments, in the nth row pixel circuit, the reset control line RST can be connected to the first scan line GLa of the (n-1)th row pixel circuit to be input with the first scan signal SCAN1(n-1), that is, the reset control signal RESET(n) is the same as the first scan signal SCAN1(n-1). In this way, the number of signal lines on the display substrate can be reduced, and a narrow bezel on the display substrate can be achieved.

[0066] In some exemplary implementations, such as Figure 3 As shown, the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the first scan line GLa, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The control electrode of the second transistor T2 is electrically connected to the first scan line GLa, the first electrode of the second transistor T2 is electrically connected to the fifth node N5, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The control electrode of the fifth transistor T5 is electrically connected to the light emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the light emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The control electrode of the first transistor T1 is electrically connected to the reset control line RST. The first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1. The second electrode of the first transistor T1 is electrically connected to the fifth node N5. The control electrode of the seventh transistor T7 is electrically connected to the reset control line RST. The first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2. The second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The control electrode of the eighth transistor T8 is electrically connected to the second scan line GL2. The first electrode of the eighth transistor T8 is electrically connected to the fifth node N5. The second electrode of the eighth transistor T8 is electrically connected to the first node N1. The first electrode of the storage capacitor C1 is electrically connected to the first node N1. The second electrode of the storage capacitor C1 is electrically connected to the first power supply line PL1.

[0067] In this example, the first node N1 is the connection point of storage capacitor C1, eighth transistor T8 and third transistor T3; the second node N2 is the connection point of fifth transistor T5, fourth transistor T4 and third transistor T3; the third node N3 is the connection point of third transistor T3, second transistor T2 and sixth transistor T6; the fourth node N4 is the connection point of sixth transistor T6, seventh transistor T7 and the anode of light-emitting element EL; and the fifth node N5 is the connection point of first transistor T1, second transistor T2 and eighth transistor T8.

[0068] Figure 4 for Figure 3 The provided timing diagram for the pixel circuit is shown below. Figure 4 right Figure 3 The operation of the pixel circuit shown is explained. The first transistor T1 to the seventh transistor T7 in the pixel circuit are P-type transistors, and the eighth transistor T8 is an N-type transistor.

[0069] In some exemplary implementations, such as Figure 3 and Figure 4 As shown, the operation of the pixel circuit within one frame can include: the first stage S1, the second stage S2, and the third stage S3.

[0070] The first stage, S1, is called the reset stage. The reset control signal RESET provided by the reset control line RST is low, turning on the first transistor T1 and the seventh transistor T7. The second scan signal SCAN2 provided by the second scan line GLb is high, turning on the eighth transistor T8. The first initial signal provided by the first initial signal line INIT1 is provided to the fifth node N5 and the first node N1 to initialize the first node N1 and clear the original data voltage in the storage capacitor C1. The first scan signal SCAN1 provided by the first scan line GLa is high, and the light emission control signal EM provided by the light emission control line EML is high, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, and the sixth transistor T6. The seventh transistor T7 turns on, causing the second initial signal provided by the second initial signal line INIT2 to be provided to the fourth node N4, initializing (resetting) the anode of the light-emitting element EL, clearing its internal pre-stored voltage, and completing the initialization. During this stage, the light-emitting element EL does not emit light.

[0071] The second stage, S2, is called the data writing stage or threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GLa is a low-level signal. The second scan signal SCAN2 provided by the second scan line GLb, the reset control signal RESET provided by the reset control line RST, and the light emission control signal EM provided by the light emission control line EML are all high-level signals. The data line DL outputs the data signal DATA. During this stage, because the first electrode of the storage capacitor C1 is low, the third transistor T3 is turned on. The low-level first scan signal SCAN1 turns on the second transistor T2 and the fourth transistor T4. The second transistor T2, the fourth transistor T4, and the eighth transistor T8 are turned on, causing the data voltage Vdata output from the data line DL to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fifth node N5, and the turned-on eighth transistor T8. The difference between the data voltage Vdata output from the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor C1. The voltage at the first electrode of the storage capacitor C1 (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from the data line DL, and Vth is the threshold voltage of the third transistor T3. The reset control signal RESET provided by the reset control line RST is a high-level signal, causing the first transistor T1 and the seventh transistor T7 to turn off. The light emission control signal EM provided by the light emission control line EML is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0072] The third stage, S3, is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 provided by the second scan line GLb is a low-level signal, turning off the eighth transistor T8. The first scan signal SCAN1 provided by the first scan line GLa and the reset control signal RESET provided by the reset control line RST are both high-level signals, turning off the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the first transistor T1. The first voltage signal VDD output by the first power supply line PLA provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0073] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 (i.e., the driving transistor) is determined by the voltage difference between its control electrode and its first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0074] I = K × (Vgs - Vth) 2=K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 ;

[0075] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0076] As can be seen from the above formula, the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3.

[0077] In display panels based on LTPO technology, a frame skipping driving method is introduced to achieve low-frequency driving. Figure 5 This is a schematic diagram illustrating a frame skipping driving method according to at least one embodiment of the present disclosure. Figure 5 As shown, the display phase of a screen can include a refresh phase and a hold phase. The refresh phase includes refresh frames, which are frames that require data updates. The hold phase includes multiple hold frames, which are frames that do not require data updates and emit light by holding previous screen data. The difference between refresh frames and hold frames is that hold frames retain the data voltage written in the previous refresh frame without writing new data voltage to the sub-pixels. In low-frequency driving mode, the driving frequency is low, for example, less than 60Hz. Taking a driving frequency of 1Hz as an example, one second can include one refresh frame and 59 hold frames. This reduces power consumption.

[0078] In some exemplary embodiments, within a refresh frame, the pixel circuit can be configured according to... Figure 4The working timing shown is written to the data signal provided by the data line. During the hold phase, since no data refresh is required, the data line provides a data hold signal, which can be maintained at a constant voltage (i.e., data hold voltage) to save power and reduce power consumption. The second initial signal line connected to the pixel circuit provides the second initial signal, which is the anode reset signal provided to the light-emitting element. By providing anode reset signals with different voltage values ​​during the refresh and hold phases, the second initial signal line can improve the low-frequency flicker effect, allowing the display to maintain a constant brightness. In this example, by applying an appropriate voltage to the source of the driving transistor, the state of the driving transistor during light emission is adjusted, making the state of the driving transistor basically consistent between the refresh frame and the hold frame. Furthermore, by directly adjusting the light emission start voltage of the light-emitting element through the anode reset signal, the brightness levels of the refresh frame and the hold frame are leveled, thereby improving the low-frequency flicker effect.

[0079] In some exemplary embodiments, the anode reset signal, data signal, and data hold signal are generated by the DDIC chip. The DDIC chip can provide the data signal and data hold signal to the sub-pixel via the data line, and provide the anode reset signal to the sub-pixel via the second initial signal line.

[0080] In some exemplary embodiments, the DDIC chip acquires externally input image data, processes the externally input image data, and obtains grayscale data of sub-pixels (or pixel units). For example, the DDIC chip can receive image data from an application processor. The DDIC chip can generate a tearing effect (TE) signal to prevent screen tearing during image display. The DDIC chip generates a TE signal when it is ready to refresh the next frame of the image. For example, the AP sends the next frame of image data to the DDIC chip after listening to the rising edge of the TE signal or detecting that the TE signal is in a high-level state.

[0081] In some exemplary embodiments, at a first refresh frequency (i.e., a refresh frequency less than 60Hz), the DDIC chip can convert the grayscale data of each sub-pixel (or pixel unit) of the display screen into grayscale voltage according to a pre-stored grayscale conversion lookup table. As shown in Table 1, the pre-stored grayscale conversion lookup table may include a column of grayscale data and a corresponding column of grayscale voltage, and there is a one-to-one correspondence between the grayscale data and grayscale voltage in the grayscale conversion lookup table.

[0082] Table 1 Grayscale Conversion Comparison Table

[0083] Gray scale data 1 Gray scale voltage 1 Gray scale data 2 Gray scale voltage 2 …… …… Gray scale data n Gray scale voltage n

[0084] In some examples, the grayscale data range can be 0 to 255, and the grayscale voltage range can be approximately 0.2V to 7.0V. For example, the grayscale voltage corresponding to grayscale data L0 is 7.0V, the grayscale voltage corresponding to grayscale data L8 is 6.0V, and the grayscale voltage corresponding to grayscale data L255 is 0.2V. However, this embodiment is not limited in this respect.

[0085] In some exemplary embodiments, the grayscale data and grayscale voltage between any two adjacent grayscale data in the grayscale conversion lookup table satisfy a grayscale mapping function. That is, Voltage = f(Graydata), where Voltage represents grayscale voltage and Graydata represents grayscale data. In some examples, the grayscale mapping function can be a linear relationship or an exponential relationship. For example, the grayscale mapping function can be y = a*X + b or y = X a Where X represents grayscale data, y represents grayscale voltage, and a and b are constants. However, this embodiment is not limited in this respect.

[0086] In some exemplary embodiments, the grayscale mapping functions satisfied by the grayscale data and grayscale voltage between any two adjacent grayscale data in the grayscale conversion lookup table can be the same or different. For example, the grayscale data and grayscale voltage between grayscale data 1 and grayscale data 2 in the grayscale conversion lookup table shown in Table 1 can satisfy a first grayscale mapping function, and the grayscale data and grayscale voltage between grayscale data 2 and grayscale data 3 can satisfy a second grayscale mapping function, and the first grayscale mapping function is different from the second grayscale mapping function. For example, the first grayscale mapping function can be a linear function, and the second grayscale mapping function can be an exponential function. However, this embodiment is not limited in this respect.

[0087] In some exemplary embodiments, for the grayscale data of any sub-pixel of the displayed image, the DDIC chip can look up the corresponding grayscale voltage in a grayscale conversion lookup table. If no corresponding grayscale voltage is found in the grayscale conversion lookup table, the grayscale data can be converted using interpolation. For example, the grayscale mapping function corresponding to the grayscale data to be converted can be determined through the grayscale conversion lookup table, and the corresponding grayscale voltage can be calculated using the grayscale mapping function.

[0088] In some exemplary embodiments, after the DDIC chip obtains the grayscale voltage of each sub-pixel of the displayed image, it can calculate the average grayscale voltage of the displayed image. The average grayscale voltage is the ratio of the sum of the grayscale voltages of all sub-pixels of the displayed image to the total number of sub-pixels.

[0089] In some exemplary embodiments, taking a display screen with a resolution of H*V as an example, the average grayscale voltage of each row of sub-pixels can be calculated first, and then the average grayscale voltage of the display screen can be calculated. For example, the average grayscale voltage of each row of sub-pixels can be calculated in the following way:

[0090]

[0091] Among them, Vh avg The average grayscale voltage of a row of sub-pixels; Voltage i is the grayscale voltage of the i-th sub-pixel in the sub-pixel row; W is the weighting factor. W can be set according to requirements, for example, it can be set to 1 by default. However, this embodiment does not limit this.

[0092] Subsequently, the average grayscale voltage of the displayed image was calculated using the following method:

[0093]

[0094] Among them, V avg The average grayscale voltage of the displayed image.

[0095] However, this embodiment does not limit the method for calculating the average grayscale voltage of the displayed image. For example, the sum of the grayscale voltages of all sub-pixels can be calculated directly, and then the average grayscale voltage can be obtained according to the ratio of the sum of the grayscale voltages to the total number of sub-pixels; or, the average grayscale voltage of each column of sub-pixels can be calculated first, and then the average grayscale voltage of the displayed image can be calculated using the average grayscale voltage of all columns of sub-pixels.

[0096] In some exemplary embodiments, after calculating the average grayscale voltage of the displayed image, the DDIC chip can determine the corresponding data hold voltage, first anode reset voltage, and second anode reset voltage according to a pre-stored parameter lookup table. As shown in Table 2, the pre-stored parameter lookup table may include a column for average grayscale voltage Vavg, a column for data hold voltage, a column for first anode reset voltage Vinit2-1, and a column for second anode reset voltage Vinit2-2. There is a one-to-one correspondence between the average grayscale voltage and the data hold voltage, a one-to-one correspondence between the average grayscale voltage and the first anode reset voltage, and a one-to-one correspondence between the average grayscale voltage and the second anode reset voltage. In some examples, the data hold voltage, first anode reset voltage, and second anode reset voltage corresponding to the average grayscale voltage between any two adjacent average grayscale voltages in the parameter lookup table can be calculated by interpolation.

[0097] Table 2 Parameter Comparison Table

[0098]

[0099] In some examples, the average grayscale voltage can range from approximately 0.2V to 7.0V, the data hold voltage can range from approximately 0.2V to 7.0V, the first anode reset voltage can range from approximately -0.5V to -0.6V, and the second anode reset voltage can range from approximately -0.5V to -0.6V. For example, if the average grayscale voltage is 7.0V, the corresponding data hold voltage can be 7.0V, the first anode reset voltage can be -3.5V, and the second anode reset voltage can be -4.0V; if the average grayscale voltage is 6.0V, the corresponding data hold voltage can be 6.2V, the first anode reset voltage can be -3.6V, and the second anode reset voltage can be -4.0V; if the average grayscale voltage is 0.2V, the corresponding data hold voltage can be 1.0V, the first anode reset voltage can be -3.7V, and the second anode reset voltage can be -4.0V. However, this embodiment is not limited in this respect.

[0100] In some exemplary embodiments, the average grayscale voltage in the parameter lookup table can be directly proportional to the data holding voltage. The average grayscale voltage in the parameter lookup table can be inversely proportional to the absolute value of the voltage difference between the first anode reset voltage and the second anode reset voltage. For example, the higher the average grayscale voltage, the higher the data holding voltage, and the smaller the voltage difference between the first anode reset voltage and the second anode reset voltage.

[0101] In some exemplary embodiments, a parameter lookup table can be obtained by collecting and organizing data from the output display screen. The parameter combination provided by the parameter lookup table can achieve the best low-frequency flicker effect. In some examples, the parameter lookup table shown in Table 2 can be divided into multiple parameter lookup sub-tables. For example, the first parameter lookup sub-table can record the correspondence between the average grayscale voltage and the data holding voltage, and the second parameter lookup sub-table can record the correspondence between the average grayscale voltage and the first anode reset voltage and the second anode reset voltage. Alternatively, the first parameter lookup sub-table can record the correspondence between the average grayscale voltage and the data holding voltage, the second parameter lookup sub-table can record the correspondence between the average grayscale voltage and the first anode reset voltage, and the third parameter lookup sub-table can record the correspondence between the average grayscale voltage and the second anode reset voltage. However, this embodiment is not limited to this.

[0102] In some exemplary embodiments, after calculating the average grayscale voltage for any given display screen, the DDIC chip can look up the display parameters corresponding to that average grayscale voltage from a parameter lookup table. After determining the display parameters of the display screen, the DDIC chip can dynamically output a data hold signal and an anode reset signal to the display panel according to the display parameters.

[0103] Figure 6This is a waveform diagram of a control signal according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 6 As shown, V-sync is the vertical synchronization signal, used to define frame periods (or vertical synchronization periods). The display panel includes... Figure 3 Taking the pixel circuit shown as an example, the first scan signal SCAN1 can be provided by the first scan line GLa, and the second scan signal SCAN2 can be provided by the second scan line GLb. In refresh frame Q1, the pixel circuit writes the data signal provided by the data line under the control of the first scan signal SCAN1 and the second scan signal SCAN2; in hold phase Q2, the pixel circuit does not write new data signals under the control of the first scan signal SCAN1 and the second scan signal SCAN2.

[0104] In some exemplary implementations, such as Figure 6 As shown, the following explanation uses a first display screen and a second display screen with different grayscale data as examples. Vinit2-a is the anode reset signal corresponding to the first display screen, and Vinit2-b is the anode reset signal corresponding to the second display screen. During the refresh phase Q1, the anode reset signal Vinit2-a maintains the first anode reset voltage V2-1, and during the hold phase Q2, it maintains the second anode reset voltage V2-2. During the refresh phase Q1, the anode reset signal Vinit2-b maintains the first anode reset voltage V2-1', and during the hold phase Q2, it maintains the second anode reset voltage V2-2'. The first anode reset voltage V2-1 is greater than the second anode reset voltage V2-2, and the first anode reset voltage V2-1' is greater than the second anode reset voltage V2-2'. The first anode reset voltages V2-1 and V2-1' can be different, and the second anode reset voltages V2-2 and V2-2' can be different. However, this embodiment is not limited to this.

[0105] In some exemplary implementations, such as Figure 6 As shown, KV-a is the data hold signal for the first display screen during the hold phase Q2, and the data hold signal KV-a is maintained at the first data hold voltage KV1 during the hold phase Q2. KV-b is the data hold signal for the second display screen during the hold phase Q2, and the data hold signal KV-b is maintained at the second data hold voltage KV2 during the hold phase Q2. The first data hold voltage KV1 may be different from the second data hold voltage KV2; for example, the first data hold voltage KV1 may be greater than the second data hold voltage KV2, or the second data hold voltage KV2 may be greater than the first data hold voltage KV1. However, this embodiment is not limited to this.

[0106] In this exemplary embodiment, under low-frequency driving mode, different display parameters are determined for display images with different grayscale data, and different control signals are provided to the display panel, thereby achieving the best low-frequency flicker effect under any image. Furthermore, in this embodiment, the grayscale data of the display image is converted into grayscale voltage before determining the matching display parameters, resulting in more accurate display parameters and improved display performance.

[0107] Figure 7 This is a schematic diagram of a control device for a display panel according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 7 As shown, the control device in this embodiment may include: a grayscale conversion module 301, a voltage calculation module 302, a parameter conversion module 303, and a signal output module 304. The grayscale conversion module 301 is configured to convert the grayscale data of the display screen into grayscale voltage at a first refresh rate. The voltage calculation module 302 is configured to calculate the average grayscale voltage of the display screen based on the grayscale voltage of the display screen. The parameter conversion module 303 is configured to determine the display parameters matching the display screen based on the average grayscale voltage of the display screen. The signal output module 304 is configured to output a control signal for the display screen to the display panel based on the display parameters matching the display screen. The control signal includes at least one of the following: a data hold signal and an anode reset signal for the light-emitting elements of the display panel.

[0108] In some exemplary embodiments, the display phase of the display screen may include a refresh phase and a hold phase. The display parameters may include at least one of the following: a data hold voltage during the hold phase; a first anode reset voltage during the refresh phase; and a second anode reset voltage during the hold phase.

[0109] Figure 8 This is another schematic diagram of a control device for a display panel according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 8 As shown, the parameter conversion module 303 may include: a first parameter conversion module 3031, a second parameter conversion module 3032, and a third parameter conversion module 3033. The first parameter conversion module 3031 is configured to determine a first anode reset voltage matching the display screen based on the average grayscale voltage of the display screen. The second parameter conversion module 3032 is configured to determine a second anode reset voltage matching the display screen based on the average grayscale voltage of the display screen. The third parameter conversion module 3033 is configured to determine a data holding voltage matching the display screen based on the average grayscale voltage of the display screen.

[0110] In some exemplary implementations, such as Figure 8As shown, the signal output module 304 may include a first output module 3041 and a second output module 3042. The first output module 3041 is configured to output an anode reset signal of the display screen to the display panel according to the display parameters matched by the display screen. The second output module 3042 is configured to output a data hold signal to the display panel according to the display parameters matched by the display screen.

[0111] The description of the control device for the display panel in this embodiment can be found in the description of the foregoing embodiment, and therefore will not be repeated here.

[0112] Figure 9 This is another schematic diagram of a control device according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 9 As shown, the control device in this embodiment may include a memory 401 and a processor 402. The memory 401 is configured to store a computer program, and the processor 402 is configured to execute the computer program to implement the control method described above.

[0113] In some exemplary embodiments, the processor 402 of the control device may include a processing device such as a microcontroller unit (MCU) or a field-programmable gate array (FPGA). The memory 401 of the control device may store grayscale conversion lookup tables, parameter lookup tables, and software programs and modules of application software, such as program instructions or modules corresponding to the methods in this embodiment. The processor 402 executes various functional applications and data processing by running the software programs and modules stored in the memory 401, such as implementing the methods provided in this embodiment. The memory 401 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory may include memory remotely located relative to the processor, and these remote memories can be connected to the control device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0114] Figure 10 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 10 As shown, the display device in this embodiment may include a display panel 502 and a control device 501. The control device 501 is configured to provide control signals to the display panel 502.

[0115] In some exemplary embodiments, the display panel 502 may include a pixel array. The pixel array includes a plurality of sub-pixels, and at least one sub-pixel includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The pixel circuit includes a plurality of transistors and at least one capacitor. Further descriptions of the display device according to this embodiment can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0116] Furthermore, at least one embodiment of this disclosure also provides a non-transient computer-readable storage medium storing a computer program that, when executed, implements the steps of the above-described control method.

[0117] It will be understood by those skilled in the art that all or some of the steps, functional modules, or units in the methods, systems, or apparatuses disclosed above can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules or units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0118] The foregoing has shown and described the basic principles, main features, and advantages of this disclosure. This disclosure is not limited to the above embodiments; the embodiments and descriptions in the specification are merely illustrative of the principles of this disclosure. Various changes and modifications can be made to this disclosure without departing from its spirit and scope, and all such changes and modifications fall within the scope of this disclosure as claimed.

Claims

1. A method for controlling a display panel, comprising: At the first refresh rate, the grayscale data of the display screen is converted into grayscale voltage. Calculate the average grayscale voltage of the displayed image based on the grayscale voltage of the displayed image; Based on the average grayscale voltage of the displayed image, determine the display parameters that match the displayed image; According to the display parameters matched by the display screen, a control signal for the display screen is output to the display panel. The control signal includes at least one of the following: a data hold signal and an anode reset signal for the light-emitting element of the display panel. The display phase of the displayed screen includes a refresh phase and a hold phase; The display parameters include at least one of the following: the data holding voltage during the holding phase; the first anode reset voltage during the refresh phase; and the second anode reset voltage during the holding phase.

2. The method according to claim 1, wherein, The process of converting the grayscale data of the display screen into grayscale voltage includes: For the grayscale data of each display unit of the display screen, the grayscale voltage corresponding to the grayscale data is looked up in the stored grayscale conversion lookup table.

3. The method according to claim 2, wherein, The process of converting the grayscale data of the display screen into grayscale voltage also includes: If the gray level voltage corresponding to the gray level data of the display unit is not found in the gray level conversion lookup table, the gray level voltage corresponding to the gray level data is calculated using a preset gray level mapping function.

4. The method according to any one of claims 1 to 3, wherein, The step of calculating the average grayscale voltage of the display screen based on the grayscale voltage of the display screen includes: Calculate the average grayscale voltage of each display row of the display screen, and then use the average grayscale voltage of all display rows to calculate the average grayscale voltage of the display screen.

5. The method according to claim 1, wherein, The step of determining the display parameters matching the display screen based on the average grayscale voltage of the display screen includes: Find the display parameters that match the average grayscale voltage of the displayed image from the stored parameter lookup table; The parameter lookup table records at least one of the following: the mapping relationship between average grayscale voltage and data holding voltage, and the mapping relationship between average grayscale voltage and first anode reset voltage and second anode reset voltage.

6. The method according to claim 5, wherein, The average grayscale voltage in the parameter lookup table is directly proportional to the data holding voltage; the average grayscale voltage in the parameter lookup table is inversely proportional to the absolute value of the voltage difference between the first anode reset voltage and the second anode reset voltage.

7. The method according to claim 1, wherein, The step of outputting a control signal for the display screen to the display panel based on the display parameters matched by the display screen includes at least one of the following: During the holding phase, the data holding signal is output to the display panel, and the data holding signal maintains the data holding voltage; An anode reset signal is output to the display panel, and the anode reset signal is maintained at the first anode reset voltage during the refresh phase and at the second anode reset voltage during the hold phase.

8. The method according to claim 1, wherein, The first refresh rate is less than 60Hz.

9. A control device for a display panel, comprising: The grayscale conversion module is configured to convert the grayscale data of the display screen into grayscale voltage at the first refresh rate. The voltage calculation module is configured to calculate the average grayscale voltage of the display screen based on the grayscale voltage of the display screen. The parameter conversion module is configured to determine the display parameters matching the display screen based on the average grayscale voltage of the display screen; The signal output module is configured to output a control signal for the display screen to the display panel according to the display parameters matched by the display screen. The control signal includes at least one of the following: a data hold signal and an anode reset signal for the light-emitting element of the display panel. The display phase of the displayed screen includes a refresh phase and a hold phase; The display parameters include at least one of the following: the data holding voltage during the holding phase; the first anode reset voltage during the refresh phase; and the second anode reset voltage during the holding phase.

10. The control device according to claim 9, wherein, The parameter conversion module includes: a first parameter conversion module, a second parameter conversion module, and a third parameter conversion module; The first parameter conversion module is configured to determine the first anode reset voltage matching the display screen based on the average grayscale voltage of the display screen; The second parameter conversion module is configured to determine the second anode reset voltage matching the display screen based on the average grayscale voltage of the display screen; The third parameter conversion module is configured to determine the data holding voltage matching the display screen based on the average grayscale voltage of the display screen.

11. The control device according to claim 9, wherein, The signal output module includes: a first output module and a second output module; The first output module is configured to output an anode reset signal of the display screen to the display panel according to the display parameters matched by the display screen; The second output module is configured to output a data hold signal of the display screen to the display panel according to the display parameters matched by the display screen.

12. A display device comprising a display panel and a control device as claimed in any one of claims 9 to 11, the control device being configured to provide a control signal to the display panel.

13. The display device according to claim 12, wherein, The display panel includes: a pixel array, the pixel array including multiple sub-pixels, at least one sub-pixel including a light-emitting element and a pixel circuit for driving the light-emitting element to emit light; the pixel circuit includes: multiple transistors and at least one capacitor.

14. A control device, comprising: Memory and processor; The memory is configured to store a computer program, and the processor is configured to execute the computer program to implement the control method as described in any one of claims 1 to 8.

15. A non-transient computer-readable storage medium storing a computer program that, when executed, implements the control method as described in any one of claims 1 to 8.

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