Method for accelerating chip layout OPC correction speed

Abstract

The application provides a method for accelerating the correction speed of a chip layout OPC, provides a design layout, the design layout is composed of multiple types of patterns, and a line segment composed of multiple sampling points is set according to the contour of the design layout; the features of different types of patterns are classified to form multiple sets, each set is provided with a corresponding pre-supplementary value; the sampling points are iterated according to the pre-supplementary values corresponding to different types of patterns to form a corrected layout, so that the error value between the developed pattern of the corrected layout and the design layout is less than or equal to a target value; the accuracy of the corrected layout is verified, and if there is no error, a mask is manufactured by using the corrected layout. According to the specific patterns of the design chip layout, pre-supplementary values are provided according to model data, the convergence speed of optical proximity correction is accelerated, the iteration number of sampling point calculation is reduced, the running time is reduced, and the correction speed of the mask is accelerated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a method for accelerating chip layout OPC correction speed. BACKGROUND

[0002] With the semiconductor chip node more and more advanced, the key size of the designed chip is smaller and smaller, and the minimum size is close to the resolution limit of the light source, and the light will have optical diffraction phenomenon through the mask pattern, and the pattern formed by the lithography will have distortion phenomenon, which will endanger the performance and yield of the chip. In order to reduce the diffraction effect of the mask, before the mask is made, the optical proximity correction (OPC) needs to be performed on the chip design layout.

[0003] The OPC corrected mask is based on the OPC model of the lithography process, the light intensity at each sampling point of the chip layout pattern is calculated, the threshold value is used to obtain the pattern of the mask imaging on the photoresist, and then the difference between the design requirement pattern (ADI Target) and the pattern is obtained. The offset of each sampling point, multiplied by the coefficient, is the mask translation amount of each sampling point along the vertical direction of the chip layout pattern segment edge, and through multiple rounds of calculation and translation iteration, the mask imaging pattern on the silicon wafer is made to conform to the design requirement pattern.

[0004] Therefore, the design pattern needs to be fully segmented and sampled during OPC correction, and the light intensity of the sampling point needs to be calculated and translated for multiple rounds. For advanced nodes, the key size of the designed chip is reduced, and the pattern density is increased. The number of sampling points of the layout during OPC correction is very large. And each sampling point needs to be calculated and iterated for multiple rounds to obtain the final mask correction result. This consumes a lot of computing resources and seriously increases the layout OPC correction time, affecting the product progress.

[0005] In order to solve the above problems, a new method for accelerating the chip layout OPC correction speed is needed. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method for accelerating the chip layout OPC correction speed, which is used to solve the problem that the design pattern needs to be fully segmented and sampled during OPC correction, and the light intensity of the sampling point needs to be calculated and translated for multiple rounds. For advanced nodes, the key size of the designed chip is reduced, and the pattern density is increased. The number of sampling points of the layout during OPC correction is very large. And each sampling point needs to be calculated and iterated for multiple rounds to obtain the final mask correction result. This consumes a lot of computing resources and seriously increases the layout OPC correction time, affecting the product progress.

[0007] To achieve the above object and other related objects, the present application provides a method for accelerating the OPC correction speed of chip layout, comprising:

[0008] Step one, providing a design layout, the design layout is composed of multiple types of patterns, and a line segment composed of multiple sampling points is set according to the contour of the design layout;

[0009] Step two, classifying the features of different types of patterns to form multiple sets, and each set is provided with a corresponding pre-supplementary value;

[0010] Step three, iterating the sampling points according to the pre-supplementary values corresponding to different types of patterns to form a corrected layout, so that the error value between the developed pattern of the corrected layout and the design layout is less than or equal to a target value;

[0011] Step four, verifying the accuracy of the corrected layout, and if there is no error, using the corrected layout to manufacture a mask.

[0012] Preferably, the types of patterns in the design layout in step one include line patterns, hole patterns, two-dimensional patterns with regular shapes, and two-dimensional patterns with irregular shapes.

[0013] Preferably, in step two, multiple sets are formed according to the different densities of the surrounding environment of the patterns.

[0014] Preferably, in step two, according to the different densities of the surrounding environment of the patterns, close patterns, semi-sparse patterns and sparse patterns are formed.

[0015] Preferably, in step two, the method for obtaining the pre-supplementary value includes an OPC model anchor, an OPC model simulation, and manufacturing data of a wafer.

[0016] Preferably, in step three, the sampling points are iterated N times, and the sampling points are used for any iteration.

[0017] Preferably, in step three, the method for iterating the sampling points according to the pre-supplementary values corresponding to different types of patterns includes: sequentially performing first to Nth iterations on the sampling points, and in the X-1th to Xth iterations, the correction value Y of the sampling points is [(Z1-Z2)+Z3]*K; wherein (Z1-Z2) is the error value between the developed pattern of the X-1th corrected layout and the design layout, Z3 is the pre-supplementary value, K is a correction coefficient, N is an integer greater than or equal to 2, X is an integer greater than or equal to 2 and less than or equal to N.

[0018] Preferably, the method of iterating the sampling points according to the pre-supplementary values of the different types of the patterns in step three comprises: sequentially iterating the sampling points for the first to N times, and from the X-1th to Xth iterations, the correction value Y of the sampling points is [(Z1-Z2)]*K; wherein (Z1-Z2) is the error value between the developed pattern of the X-1th corrected layout and the design layout, K is a correction coefficient, N is an integer greater than or equal to 2, and X is an integer greater than or equal to 3 and less than or equal to N.

[0019] Preferably, step three further comprises the method of forming the corrected layout by inserting a resolution auxiliary pattern.

[0020] As described above, the method of accelerating the OPC correction speed of the chip layout of the present application has the following beneficial effects:

[0021] The present application accelerates the convergence speed of the optical proximity correction by pre-supplementing the values of the specific patterns of the design chip layout according to the model data, reduces the iteration times of the sampling points, reduces the running time, and accelerates the correction speed of the mask layout. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 The figure shows the OPC correction flowchart of the present application;

[0023] Figure 2 The figure shows the selected pattern requiring pre-supplementing of an embodiment;

[0024] Figure 3 The figure shows the layout of an embodiment after pre-supplementing and SRAF adding;

[0025] Figure 4 The figure shows the relationship between the difference of the mask layout in the X direction of an embodiment of the two correction methods and the target mask layout and the iteration times;

[0026] Figure 5 The figure shows the relationship between the difference of the mask layout in the Y direction of an embodiment of the two correction methods and the target mask layout and the iteration times;

[0027] Figure 6 The figure shows the relationship between the difference of the square hole diameter of an embodiment of the two correction methods and the target and the iteration times. DETAILED DESCRIPTION

[0028] Following, the embodiments of the present application will be described in detail by specific examples. Other advantages and effects of the present application can be easily understood by those skilled in the art from this description. The present application can also be implemented or applied by other different embodiments, and the details in this description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0029] Please refer to Figure 1 The present application provides a method for accelerating the speed of OPC correction of chip layout, comprising:

[0030] Step one, providing a design layout, the design layout is composed of multiple types of patterns, setting a line segment composed of multiple sampling points according to the outline of the design layout, the line segment is usually formed by cutting the edge of the design layout;

[0031] Preferably, the types of patterns in the design layout in step one include line patterns, hole patterns, two-dimensional patterns with regular shapes, and two-dimensional patterns with irregular shapes.

[0032] Step two, classifying the features of different types of patterns to form multiple sets, each set is provided with a corresponding pre-supplementary value;

[0033] Preferably, in step two, multiple sets are classified according to the different densities of the surrounding environment of the patterns.

[0034] Preferably, in step two, according to the different densities of the surrounding environment of the patterns, the patterns are classified into close patterns, semi-sparse patterns, and sparse patterns.

[0035] Preferably, in step two, the method for obtaining the pre-supplementary value includes optical proximity correction model anchor, optical proximity correction model simulation, and wafer manufacturing data.

[0036] Step three, according to the pre-supplementary value corresponding to different types of patterns, iteratively adjusting the sampling points to form a corrected layout, so that the error value between the developed patterns of the corrected layout and the design layout is less than or equal to the target value;

[0037] Preferably, in step three, the sampling points are iterated N times, and the sampling points are used for any iteration.

[0038] Preferably, the method of iterating the sampling point according to the pre- compensation value corresponding to the different types of the patterns in step three comprises: sequentially iterating the sampling point for the first to Nth times, and the correction value Y of the sampling point in the Xth iteration is [(Z1-Z2)+Z3]*K; wherein (Z1-Z2) is the error value between the developed pattern of the corrected layout in the Xth-1th iteration and the design layout, Z3 is the pre-compensation value, K is a correction coefficient, N is an integer greater than or equal to 2, and X is an integer greater than or equal to 2 and less than or equal to N.

[0039] Illustratively, the present application classifies the design layout, sets a specific pre-compensation value for specific patterns in the first iteration cycle of OPC correction, thereby effectively reducing the iteration times of the sampling mask calculation and movement, accelerating the convergence speed of the mask correction, ultimately reducing the OPC correction time of the entire layout, reducing the mask manufacturing cycle, and accelerating the product development progress. It should be noted that the iteration value can also be used in the subsequent iteration process according to the size of the deviation, and is not only used in the first iteration.

[0040] Preferably, the method of iterating the sampling point according to the pre- compensation value corresponding to the different types of the patterns in step three comprises: sequentially iterating the sampling point for the first to Nth times, and the correction value Y of the sampling point in the Xth iteration is [(Z1-Z2)+Z3]*K; wherein (Z1-Z2) is the error value between the developed pattern of the corrected layout in the Xth-1th iteration and the design layout, Z3 is the pre-compensation value, K is a correction coefficient, N is an integer greater than or equal to 2, and X is an integer greater than or equal to 2 and less than or equal to N.

[0041] Preferably, step three further comprises forming the corrected layout by using the method of inserting a resolution auxiliary pattern.

[0042] Step four, checking the accuracy of the corrected layout, and if there is no error, manufacturing a photomask according to the corrected layout.

[0043] Illustratively, taking the advanced node product M0P layer as an example:

[0044] In the advanced node product, the M0P layer is used to connect the PO, M0A and V0 layers, and the pattern types are square holes and rectangular holes with a fixed length-width ratio. The square holes account for the majority of all patterns, and can be divided into Dense patterns, SEMI patterns and ISO patterns according to the density of the surrounding environment. Since the SEMI / ISO square holes are far away from other patterns and are less affected by the adjacent patterns, there is enough space for pre-compensation. In this embodiment, OPC correction based on model data value is performed on SEMI / ISO square holes, and the results of OPC correction without using the present application are provided for comparison.

[0045] OPC correction of pre-correction of specific patterns according to the present application:

[0046] 1. Determine the pre-correction of specific patterns, based on the Anchor of the OPC model of the lithography process, square hole array, side 58nm, X / Y direction Pitch (period) 108nm. After exposure, a hole with a diameter of 50nm is formed on the silicon wafer, i.e. the mask size of the square hole is 58nm, and the diameter of the hole on the silicon wafer is 50nm, i.e. the mask size is 8nm different from the exposure hole diameter, and each side is 4nm different. Set the pre-correction to 4nm per side.

[0047] 2. Read in the design layout of the chip, and select the SEMI / ISO square hole. Select all square holes with a side length of 50nm in the design layout of the current layer. Take the center of the 50nm square hole as the center, and draw a circle (circle 1) with a radius of 250nm. Figure 2 Select the square hole in the design layout that has no other pattern contact in the circle, such as Figure 1 square hole A.

[0048] 3. Refer to Figure 3 , pre-correct the layout and add SRAF (resolution assist pattern) to meet and increase the process window. The black solid pattern is the chip design layout, and the black hollow pattern is the SRAF.

[0049] 4. After step 3, the chip design layout is subjected to OPC correction, and the SEMI / ISO square holes selected in step 2 form set 1, and the remaining patterns form set 2. In order to ensure that the OPC correction meets the requirements, the OPC correction of all sets of patterns is iterated 16 times. In the first iteration, all patterns in set 1 are pre-corrected by 4nm on one side, and all patterns in set 2 are normally OPC corrected. In the 2nd-16th iteration, set 1 and set 2 are normally OPC corrected, and finally the OPC corrected mask is obtained. The mask and the corresponding simulation value of each iteration of the OPC correction are output.

[0050] 5. Check the correction result, and there is no error, and the OPC correction of the chip layout is completed.

[0051] OPC correction of specific patterns without pre-correction according to the present application:

[0052] 1. Pre-correct the design chip layout and add SRAF.

[0053] 2. Perform OPC correction on the chip design layout after step 1, and in order to ensure that the OPC correction meets the requirements, the OPC correction of all sets of patterns is iterated 16 times. The mask and the corresponding simulation value of each iteration of the OPC correction are output.

[0054] 3. Check the OPC correction result, no error, complete the OPC correction of the chip layout.

[0055] The comparison chart of the OPC correction result of the pre-complement value of the specific pattern by using the present patent and the OPC correction result of the pre-complement value of the specific pattern without using the present patent is shown in Figures 4 to 6 It can be seen from the chart that the OPC correction of the pre-complement value of the specific pattern by using the present patent reduces the iteration times and accelerates the correction speed of the mask.

[0056] It is to be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the diagrams, not the components number, shape and size when actually implemented. The type, number and proportion of the components when actually implemented can be arbitrarily changed, and the component layout type can be more complicated.

[0057] In summary, the present application accelerates the optical proximity correction convergence speed by pre-complementing the specific pattern of the design chip layout according to the model data, reduces the iteration times of the sampling point calculation, reduces the running time, and accelerates the correction speed of the mask. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0058] The above embodiments only illustratively explain the principle and effect of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method for accelerating the speed of OPC correction of a chip layout, characterized in that, At least comprising: Step one, providing a design layout, the design layout is composed of multiple types of patterns, according to the contour of the design layout, a line segment composed of multiple sampling points is set; Step two, classifying the features of different types of patterns to form multiple sets, each set is provided with a corresponding pre-supplementary value; Step three, according to the pre-supplementary value corresponding to the different types of patterns, the sampling points are iterated to form a corrected layout, so that the error value between the developed pattern of the corrected layout and the design layout is less than or equal to the target value, the method of iterating the sampling points according to the pre-supplementary value corresponding to the different types of patterns includes: sequentially iterating the sampling points for the first to N times, from the X-1 to X iterations, the correction value Y of the sampling point is [ (Z1-Z2) +Z3]*K; Wherein, (Z1-Z2) is the error value between the developed pattern of the X-1 times of the corrected layout and the design layout, Z3 is the pre-supplementary value, K is the correction coefficient, N is an integer greater than or equal to 2, X is an integer greater than or equal to 2 and X is less than or equal to N; Or, sequentially iterating the sampling points for the first to N times, from the X-1 to X iterations, the correction value Y of the sampling point is [ (Z1-Z2) ]*K; Wherein, (Z1-Z2) is the error value between the developed pattern of the X-1 times of the corrected layout and the design layout, K is the correction coefficient, N is an integer greater than or equal to 2, X is an integer greater than or equal to 3 and X is less than or equal to N; Step four, verifying the accuracy of the corrected layout, if there is no error, the mask is made with the corrected layout.

2. The method for accelerating the speed of OPC correction of chip layout according to claim 1, characterized in that: The types of patterns in the design layout in step one include line patterns, hole patterns and other regular or irregular two-dimensional patterns.

3. The method for accelerating the speed of OPC correction of chip layout according to claim 1, characterized in that: In step two, multiple sets are formed by classifying according to the density of the surrounding environment of the patterns.

4. The method for accelerating the speed of OPC correction of chip layout according to claim 3, characterized in that: In step two, according to the different density of the surrounding environment of the patterns, the tight patterns, semi-sparse patterns and sparse patterns are classified.

5. The method for accelerating the speed of OPC correction of chip layout according to claim 1, wherein: The method of obtaining the pre-supplementary value in step two includes: optical proximity correction model anchor, optical proximity correction model simulation, wafer manufacturing data.

6. The method for accelerating the speed of OPC correction of chip layout according to claim 1, wherein: In step three, the sampling points are iterated N times, and the sampling points are used for any iteration.

7. The method for accelerating the speed of OPC correction of chip layout according to claim 1, wherein: Step three also includes the method of forming the corrected layout by inserting resolution auxiliary patterns.

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