Method for improving overlay accuracy

Abstract

The application provides a method for improving overlay accuracy, and provides a wafer, a front layer structure and a current layer structure on the wafer, and a front layer overlay mark on the front layer structure; a photoresist layer is formed on the front layer structure, and a photoetching is performed to form an etching pattern and a current layer overlay mark, and then a post-etching detection is performed to obtain a first error according to the front layer overlay mark and the current layer overlay mark; the current layer structure is etched with the etching pattern as a mask to form an etching pattern, and then a post-etching detection is performed to obtain a second error according to the etching pattern, and the second error is an etching offset; a compensation value is obtained through the first and second errors, and an overlay accuracy correction system of a photoetching machine corrects the overlay accuracy of a current batch or a next batch of wafers. The application represents the overlay mark based on the difference modeling of the key size of the etching pattern, and compensates for the feedback of the current layer overlay mark, so that the layer overlay accuracy is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving overlay accuracy. Background Technology

[0002] Please see Figure 1 , Figure 1 This is a schematic diagram of an overlay marking technique, such as... Figure 1 As shown, the overlay accuracy measurement marks (hereinafter referred to as overlay marks) commonly used in photolithography processes are as follows: the overlay mark 100 of the front layer (aligned layer) is formed on the wafer after photolithography and etching processes, and the overlay mark 200 of the next layer (aligned layer) is formed on the wafer after photolithography. Overlay accuracy is divided into overlay accuracy ΔX in the X direction and overlay accuracy ΔY in the Y direction, as shown below. Figure 1 As shown, the overlay accuracy in the X direction is ΔX = (X2 - X1) / 2, and the overlay accuracy in the Y direction is ΔY = (Y2 - Y1) / 2. In actual production, in addition to measuring the overlay accuracy, there is also a lithography machine overlay accuracy correction system. The working principle of this system is: after measuring the overlay accuracy, the measured overlay error is fed back to the lithography machine to compensate for the overlay parameters of the lithography machine. The compensated overlay parameters are then used for the current batch of wafers or the next batch of wafers, so that the current batch of wafers or the next batch of wafers can obtain better overlay accuracy.

[0003] With the continuous improvement of IC chip manufacturing processes, the requirements for overlay accuracy are becoming increasingly stringent, especially for advanced processes below 28nm. Generally, overlay accuracy is measured on the wafer after photolithography to ensure that the overlay accuracy meets the production process requirements. This measurement is based on overlay accuracy markings to characterize the alignment of the actual pattern. However, in actual production, it has been found that the actual overlay accuracy between the final layers after etching differs somewhat from the overlay accuracy markings measured after photolithography, indicating a deviation.

[0004] To solve the above problems, a new method for improving overlay accuracy is needed. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method to improve overlay accuracy, which solves the problem in the prior art of measuring the overlay accuracy of wafers after photolithography to ensure that the overlay accuracy meets the production process. This measurement is based on the overlay accuracy mark to characterize the alignment of the actual pattern. After etching, the actual overlay accuracy between the final layers is somewhat different from the overlay accuracy mark measurement after photolithography, resulting in a deviation.

[0006] To achieve the above and other related objectives, the present invention provides a method for improving overlay accuracy, comprising:

[0007] Step one, providing a wafer, a front layer structure and a current layer structure formed on the wafer, a front layer overlay mark formed on the front layer structure;

[0008] Step two, forming a photoresist layer on the front layer structure, opening the photoresist layer to form an etching pattern and a current layer overlay mark, then performing post-development detection, obtaining a first error according to the difference between the positions of the front layer overlay mark and the current layer overlay mark;

[0009] Step three, etching the current layer structure with the etching pattern as a mask to form an etching pattern, then performing post-etching detection, obtaining a second error according to the etching pattern, the second error being an offset caused by etching;

[0010] Step four, obtaining the compensation value through the first and second errors, and the overlay accuracy correction system of the lithography machine uses the compensation value to correct the overlay accuracy of the current batch or the next batch of wafers.

[0011] Preferably, the front layer overlay mark in step one includes an X-direction overlay mark and a Y-direction overlay mark, which form a square area.

[0012] Preferably, the current layer overlay mark in step two includes an X-direction overlay mark and a Y-direction overlay mark, which form a square area with an area smaller than that of the rectangular area, the X-direction overlay accuracy ΔX = (X2-X1) / 2, and the Y-direction overlay accuracy ΔY = (Y2-Y1) / 2, X1 and X2 being the distances of the current layer overlay mark from the front layer overlay mark in the X-direction, and Y1 and Y2 being the distances of the current layer overlay mark from the front layer overlay mark in the Y-direction.

[0013] Preferably, the post-development detection or the post-etching detection in steps two and three is performed by an electron beam machine or a scanning electron microscope.

[0014] Preferably, the etching offset in step three includes X-direction and Y-direction offsets.

[0015] Preferably, the method for obtaining the compensation value through the first and second errors in step four further includes: obtaining critical dimension data of the etching pattern, establishing an etching pattern model according to the critical dimension data, judging the correlation degree of the etching pattern model and the critical data, and determining whether the correlation degree is within a preset range; if yes, calculating the compensation value.

[0016] Preferably, the overlay accuracy correction system in step four is an overlay accuracy measurement calculation model.

[0017] Preferably, the overlay correction system in step four is an advanced process control system.

[0018] As mentioned above, the method for improving overlay accuracy of the present application has the following beneficial effects:

[0019] The present application compensates for the overlay mark feedback of the same layer based on the modeling of the difference of the critical dimension of the measurement feature pattern after etching, and improves the overlay accuracy of the layer. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 An overlay accuracy mark schematic diagram of the prior art is shown;

[0021] Figure 2 A process flow schematic diagram of the present application is shown;

[0022] Figure 3 An etched same layer structure schematic diagram of the present application is shown;

[0023] Figure 4 A modeling correlation schematic diagram of the present application is shown;

[0024] Figure 5 An overlay accuracy vector schematic diagram after lithography of the prior art is shown;

[0025] Figure 6 An overlay accuracy vector schematic diagram after etching of the prior art is shown;

[0026] Figure 7 An overlay accuracy vector schematic diagram after etching of the present application is shown. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be described herein below with reference to specific drawings that were given by way of example and in a non-restrictive manner. Based upon the content disclosed in the present specification, those skilled in the art can easily understand other advantages and effects of the present application. The present application can also be implemented or applied in other different embodiments, and the details in the present specification can be modified or changed in various ways based upon different viewpoints and applications without departing from the spirit of the present application.

[0028] Please refer to Figure 2 The present application provides a method for improving overlay accuracy, comprising:

[0029] Step one, providing a wafer 301, the wafer 301 has a front layer structure 302 and a same layer structure 303 on the front layer structure 302, the front layer structure 302 has a front layer overlay mark 100;

[0030] In the embodiments of the present application, the front layer overlay mark 100 in step one includes an X-direction overlay mark and a Y-direction overlay mark, which enclose a square area.

[0031] Step two, forming a photoresist layer on the front layer structure 302, opening the photoresist layer to form an etching pattern 304 and a current layer overlay mark 200 by photoetching, then performing a post-etching detection, and obtaining a first error according to the difference between the position of the front layer overlay mark 100 and the current layer overlay mark 200;

[0032] In the embodiment of the present application, the current layer overlay mark 200 in step two includes an overlay mark in the X direction and an overlay mark in the Y direction, and the square area surrounded by the two overlay marks is smaller than the rectangular area, the overlay precision in the X direction is ΔX=(X2-X1) / 2, and the overlay precision in the Y direction is ΔY=(Y2-Y1) / 2, wherein X1 and X2 are the distance between the current layer overlay mark 200 and the front layer overlay mark 100 in the X direction, and Y1 and Y2 are the distance between the current layer overlay mark 200 and the front layer overlay mark 100 in the Y direction.

[0033] Step three, referring to Figure 3 , etching the current layer structure 303 using the etching pattern 304 as a mask to form an etched pattern, then performing a post-etching detection, and obtaining a second error according to the etched pattern, wherein the second error is the offset H caused by etching;

[0034] In the embodiment of the present application, the post-etching detection or the post-etching detection in steps two and three is performed by an electron beam machine or a scanning electron microscope.

[0035] In the embodiment of the present application, the etching offset in step three includes the offset in the X direction and the offset in the Y direction.

[0036] Step four, obtaining a compensation value according to the first and second errors, and using the compensation value by an overlay precision correction system of a photoetching machine to correct the overlay precision of the current batch or the next batch of wafers 301.

[0037] In the embodiment of the present application, referring to Figure 4 , the method for obtaining the compensation value according to the first and second errors in step four further includes: obtaining critical dimension data of the etched pattern, establishing an etched pattern model according to the critical dimension data, judging the correlation degree between the etched pattern model and the critical dimension data, and determining whether the correlation degree is within a preset range; if yes, the compensation value is calculated.

[0038] In the embodiment of the present application, the overlay precision correction system in step four is an overlay precision measurement calculation model.

[0039] In the embodiment of the present application, the overlay precision correction system in step four is an advanced process control system.

[0040] In the embodiment of the present application, referring to Figure 5The wafer 301 includes multiple exposure areas (shots), where vector arrows indicate the vector direction and magnitude, showing the offset direction and magnitude of the layer overlay mark 200. See also... Figure 6 The wafer 301 includes multiple exposure areas (shots), where vector arrows indicate the offset direction and magnitude, illustrating the offset direction and magnitude for post-etching development and inspection. Please refer to... Figure 7 The wafer 301 includes multiple exposure areas (shots). After correction by the compensation value of the present invention, the vector arrows therein indicate the offset direction and offset size, that is, they show the offset direction and offset size of the development detection after etching, which improves the overlay accuracy compared with the prior art.

[0041] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0042] In summary, this invention uses modeling to characterize overlay marks based on differences in key dimensions of etched feature patterns, and compensates for feedback on overlay marks in the current layer, thereby improving layer overlay accuracy. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0043] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of improving overlay accuracy, comprising: At least comprising: Step one, providing a wafer, a front layer structure and a current layer structure formed on the wafer, a front layer overlay mark formed on the front layer structure; Step two, forming a photoresist layer on the front layer structure, opening the photoresist layer to form an etching pattern and a current layer overlay mark, then performing post-development detection, obtaining a first error according to the difference between the positions of the front layer overlay mark and the current layer overlay mark; Step three, etching the current layer structure with the etching pattern as a mask to form an etched pattern, then performing post-etching detection, obtaining a second error according to the etched pattern, the second error being an offset caused by etching; Step four, obtaining a compensation value through the first error and the second error, an overlay accuracy correction system of a lithography machine using the compensation value to correct the overlay accuracy of the current batch or the next batch of wafers, including: obtaining critical dimension data of the etched pattern, establishing an etched pattern model according to the critical dimension data, judging the correlation degree of the etched pattern model and the critical dimension data, and when the correlation degree is within a preset range, the compensation value is calculated; the overlay accuracy correction system of the lithography machine uses the compensation value to correct the overlay accuracy of the current batch or the next batch of wafers; Based on the difference modeling of the critical dimension of the etched measurement feature pattern, the overlay error is fed back to compensate for the current layer overlay mark to improve the layer overlay accuracy.

2. The method of claim 1, wherein: The front layer overlay mark in step one includes X-direction overlay marks and Y-direction overlay marks, which form a square area.

3. The method of claim 2, wherein: The current layer overlay mark in step two includes X-direction overlay marks and Y-direction overlay marks, which form a square area with an area smaller than that of a rectangular area, the X-direction overlay accuracy ΔX=(X2-X1) / 2, and the Y-direction overlay accuracy ΔY=(Y2-Y1) / 2, X1 and X2 being the distances of the current layer overlay mark in the X-direction from the front layer overlay mark, and Y1 and Y2 being the distances of the current layer overlay mark in the Y-direction from the front layer overlay mark.

4. The method of claim 1, wherein: The post-development detection or post-etching detection in steps two and three is performed by an electron beam machine or a scanning electron microscope.

5. The method of claim 1, wherein: The etching offset in step three includes X-direction and Y-direction offsets.

6. The method of claim 1, wherein: The overlay accuracy correction system in step four is an overlay accuracy measurement calculation model.

7. The method of claim 1, wherein: The overlay correction system in step four is an advanced process control system.

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