A multi-channel time-to-digital converter with no mismatch and high precision

Abstract

The present invention discloses a multi-channel time-to-digital converter with no mismatch and high precision, which includes independent time signal measurement channels, a coarse counter, a measurement data processing module, and a data communication module; there are multiple independent time signal measurement channels, and each channel includes a tapped delay line (TDL), a fine counting sampling and judgment circuit, a transcoding module, a coarse counting sampling circuit, and a code density test circuit; the independent time measurement channels are used to quantize continuous time signals into digital signals, and the measurable range exceeds the system clock period. Together with the coarse counter, they form a two-step time-to-digital converter to achieve high-precision time signal measurement over a wide range. The structure of the present invention is simple, and it ensures no mismatch while maintaining the high-precision multi-channel measurement ability.

Description

Technical Field

[0001] The present invention belongs to the field of digital integrated circuit design, and particularly relates to a multi-channel time-to-digital converter with no mismatch and high precision. Background Art

[0002] A time-to-digital converter (TDC) is a device that quantizes a time signal into a digital signal and can be used to calculate parameters such as the phase difference and period between input signals. It is widely used in technical fields such as automated test equipment (ATE), time-of-flight measurement, positron emission tomography, lasers, radar, and oscilloscopes.

[0003] Common methods for digital time converters include multi-phase clock measurement method, tapped delay line (TDL) method, vernier method, and pulse shrinking method, etc. The tapped delay line method has a simple structure and a wide range of applications and is widely used. Generally, a TDC based on the tapped delay line method has three basic units: a fine counter cascaded by delay units, a coarse counter that counts by clock cycles, and a tapped sampling and conversion circuit. In a general TDL-TDC, since the delay of the measured signal arriving at the entrance of the delay line is not the same as the path delay to the coarse counter, when the measured signal arrives near the rising edge of the clock, there may be a mismatch between the fine and coarse counting results. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a multi-channel time-to-digital converter with no mismatch and high precision, and to solve the problem of mismatch between fine and coarse counting results by improving the counting trigger logic of the fine and coarse counters.

[0005] A multi-channel time-to-digital converter with no mismatch and high precision includes independent time signal measurement channels, a coarse counter, a measurement data processing module, and a data communication module; there are multiple independent time signal measurement channels, and each channel includes a tapped delay line (TDL), a fine counting sampling and judgment circuit, a transcoding module, a coarse counting sampling circuit, and a code density test circuit;

[0006] The independent time measurement channels are used to quantize continuous time signals into digital signals, and their measurable range exceeds the system clock cycle. They can jointly form a two-step time-to-digital converter with the coarse counter to achieve high-precision time signal measurement over a wide range;

[0007] The transcoding module is used to convert the sampling result in the TDL from thermometer code to binary code;

[0008] The coarse counter is used to count according to the system clock, incrementing the result by one per cycle, and the coarse counting result is connected to the coarse counting sampling circuit in the aforementioned independent time signal measurement channels;

[0009] The described code density test circuit is used to perform code density tests on each independent measurement channel before measurement to obtain the delay time corresponding to each tap of each channel and establish a corresponding lookup table. When measuring the time signal, the measured TDL result is converted into the corresponding fine count result by looking up the table;

[0010] The described measurement data processing module is located in each independent measurement channel, used to save and calculate the measurement data each time, and is controlled to provide the measurement data to the data communication module;

[0011] The described data communication module is used to send the delay time corresponding to each tap obtained after the code density test, the reference delay time of each chain obtained after the delay chain alignment operation, and the measurement result of the random time signal to the host computer.

[0012] The described tap delay chain is composed of two identical cascaded delay units, namely the first delay unit cascade chain and the second delay unit cascade chain. These two cascade chains are closely arranged in the physical layout. The output of each delay unit except the last one is connected to the input of the next delay unit and the data input terminal of a nearest D flip-flop respectively. The output of the last delay unit is only connected to the data input terminal of the nearest D flip-flop;

[0013] The D flip-flops connected to the output of each delay unit of the first delay unit cascade chain form the first flip-flop array, and the D flip-flops connected to the output of each delay unit of the second delay unit cascade chain form the second flip-flop array;

[0014] The output of each flip-flop of the first flip-flop array and the second flip-flop array is connected to the input terminal of another nearest D flip-flop. The D flip-flops connected to the output of each flip-flop of the first flip-flop array form the third flip-flop array, and the D flip-flops connected to the output of each flip-flop of the second flip-flop array form the fourth flip-flop array;

[0015] The output of the 8th flip-flop of the first to fourth flip-flop arrays is connected to the fine count sampling judgment circuit.

[0016] The output of the 8th flip-flop of the first to fourth flip-flop arrays is connected to the judgment circuit; among them, when the output of the 8th flip-flop of the first flip-flop array is high and the output of the 8th flip-flop of the third flip-flop is low, or the output of the 8th flip-flop of the second flip-flop array is high and the output of the 8th flip-flop of the fourth flip-flop is low, the fine count sampling valid signal Fine_samp_valid is set to high level, indicating that the sampling is valid.

[0017] The described coarse counter starts counting according to the system clock when the time-to-digital converter system enters the measurement state, incrementing the result by one per cycle, and the count value is fed into the coarse count sampling circuit of each measurement channel; when the fine count sampling valid signal Fine_samp_valid jumps to a high level, the coarse count value of this cycle is sampled and saved together with the fine count result.

[0018] The described measurement data processing module saves and calculates the measurement results of each chain each time during the multi-channel alignment process for multiple channels, obtaining the path delay differences of each chain from the signal source to the entrance of the delay chain.

[0019] The mismatch-free high-precision multi-channel time-to-digital converter for mismatch-free high-precision multi-channel time-to-digital conversion includes the following steps:

[0020] Step 1: Build the circuit of the mismatch-free high-precision multi-channel time-to-digital converter;

[0021] Step 2: Obtain the delay time corresponding to each tap of each chain through the method of code density testing and store it in the RAM;

[0022] Step 3: Send the same rising-edge pulse Hit_align_n to each chain simultaneously and record the results recorded by each chain, calculate the path delay differences from the signal source to each measurement channel, and use this data as a reference to correct all subsequent measurement results;

[0023] Step 4: Send a rising-edge pulse signal Hit_meas_n to the measurement channel to trigger the fine count sampling valid signal Fine_samp_valid, input the results sampled on the tap delay chain into the result lookup table obtained from the code density test, output the corresponding delay time, and finally save the delay time output by the lookup table as the fine count result together with the coarse count result saved when the fine count sampling valid signal is set high;

[0024] Step 5: Send the coarse and fine count results to the host computer, and calculate the rising-edge positions of each rising-edge pulse recorded by each channel to obtain various parameters to be measured.

[0025] The beneficial effects of the present invention are as follows:

[0026] In the thickness counting trigger, first detect whether the fine counting is triggered. Only when the fine counting trigger is effective, the coarse count value is saved, effectively avoiding the mismatch between the thickness and fine counters. Generally, a TDL-TDC uses one channel to record both the rising edge and the falling edge of the pulse signal simultaneously to calculate the pulse width. In the present invention, since one channel only records once, more than two channels are required to cooperate to measure the position of the rising edge of the signal to be measured, etc., and further calculate various parameters to be measured. In the present invention, multi-channel alignment operations are used to eliminate the influence of the path delay difference from the signal source to be measured to each channel, ensuring the high precision of multi-channel measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is the circuit structure of a general TDL-TDC.

[0028] Figure 2 It is the possible timing states when the Hit signal arrives near the rising edge of the clock in the general TDL-TDC circuit structure.

[0029] Figure 3 It is the system structure block diagram of the time-to-digital converter TDC in the present invention.

[0030] Figure 4 It is the schematic diagram of the tapped delay line part and the fine counting sampling and judgment circuit in the present invention.

[0031] Figure 5 It is the actual test result of the embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The present invention will be further described below in conjunction with the drawings and embodiments.

[0033] The time-to-digital converter adopts the structure of TDL-TDC, and its general form is as Figure 1 shown. The output of each delay unit is connected to the D terminal of the flip-flop, and the C terminal of the flip-flop is connected to the system clock. In this way, the state on the delay chain can be sampled at each rising edge of the clock. When a high level is collected, it indicates that the rising edge of the signal enters the delay chain and propagates in the chain. The delay time of each delay unit is fixed. By measuring the number of high levels in the chain, the time for the rising edge to propagate can be known, that is, the time interval t1 between the start of the rising edge propagation into the delay chain and the rising edge of the clock. Similarly, the time interval t2 between the falling edge and the rising edge of the clock can be measured. The time interval between the two measurements is counted by the coarse counter. If it is recorded that N clock cycles have elapsed between the rising edge and the falling edge of the signal to be measured, and the time of each cycle is T, the width of the pulse signal to be measured can be calculated as .

[0034] Such as Figure 2As shown, when the rising edge of the signal under test is very close to the rising edge of the system clock, the corresponding clock cycles of the coarse and fine counting may be misaligned, resulting in the counting result differing from the expected value by more than one cycle and causing counting errors. Figure 2 Figure 2 shows two typical mismatches that occur at the rising edge of the measurement. If the falling edge of the measurement is considered, there will also be two typical mismatch situations. These mismatches will greatly affect the measurement accuracy.

[0035] In addition, in a general delay chain structure, only a delay chain composed of one delay unit is used. However, by using multiple cascaded chains interpolated into one delay chain, that is, the same signal under test is input into multiple identical and physically closely parallel cascaded chains, the output of the delay units of the multiple chains can be misaligned on the time axis to achieve the effect of "interpolation", enabling the resolution of the delay chain to exceed the limitation of the inherent delay time of the delay unit. This part of the theory has been disclosed in the prior art, but the situation of the mismatch between the coarse and fine counters has not been considered in the paper by Y. Wang et al. (A 3.9-ps RMS Precision Time-to-Digital Converter Using Ones-Counter Encoding Scheme in a Kintex-7 FPGA, IEEE Transactions on Nuclear Science, October 2017). In addition, since the time when the signal under test arrives at the two cascaded chains must be in sequence, there must be the first few taps of a certain cascaded chain, that is, the delay times corresponding to the first few taps of the delay chain are essentially the delay times of a single cascaded chain, that is, the performance is equivalent to without interpolation.

[0036] In order to eliminate the problem of the mismatch between the coarse and fine counting results during the measurement process and improve the accuracy as much as possible, the present invention proposes an improved sampling judgment circuit and a supporting measurement method based on the TDL structure of cascaded chain interpolation.

[0037] The present invention proposes a multi-channel time-to-digital converter with mismatch-free high precision, including multiple independent time signal measurement channels, a measurement data processing module, and a data communication module; each of the multiple independent time signal measurement channels includes a tapped delay line (Time Delay Line, TDL), a fine counting sampling judgment circuit, a transcoding module, a coarse counter, and a code density test circuit.

[0038] The data communication module sends the delay times corresponding to each tap obtained after the code density test, the reference delay times of each chain obtained after the delay chain alignment operation, and the measurement results of the random time signal to the host computer.

[0039] The transcoding module converts the sampling result in the TDL from thermometer code to binary code.

[0040] The described coarse counter will count according to the system clock, and the result will be incremented by one per cycle.

[0041] The code density test circuit performs code density tests on each chain before measurement to obtain the delay time corresponding to each tap of each chain.

[0042] The described measurement data processing module saves and calculates the measurement results of each chain of the multiple channels in each multi-channel alignment session, obtains the path delay difference from the signal source to the delay chain entrance of each chain, and uses this as a reference value to eliminate the influence of this path delay difference.

[0043] The described tap delay chain is formed by cascading two identical delay units, namely the first delay unit cascade chain and the second delay unit cascade chain. These two cascade chains are closely arranged in the physical layout. The output of each delay unit except the last one is connected to the input of the next delay unit and the data input terminal of a nearest D flip-flop, and the output of the last delay unit is only connected to the data input terminal of the nearest D flip-flop.

[0044] The D flip-flops connected to the output of each delay unit of the first delay unit cascade chain form the first flip-flop array, and the D flip-flops connected to the output of each delay unit of the second delay unit cascade chain form the second flip-flop array.

[0045] The output of each flip-flop of the first flip-flop array and the second flip-flop array is connected to the input terminal of another nearest D flip-flop. The D flip-flops connected to the output of each flip-flop of the first flip-flop array form the third flip-flop array, and the D flip-flops connected to the output of each flip-flop of the second flip-flop array form the fourth flip-flop array;

[0046] The output of the 8th flip-flop of the first to fourth flip-flop arrays is connected to the fine counting sampling judgment circuit.

[0047] In the described fine counting sampling judgment circuit, when the output of the 8th flip-flop of the first flip-flop array is high and the output of the 8th flip-flop of the third flip-flop is low, or when the output of the 8th flip-flop of the second flip-flop array is high and the output of the 8th flip-flop of the fourth flip-flop is low, the fine counting sampling valid signal Fine_valid is set to high level, indicating that the sampling is valid.

[0048] In addition, the results of the second and fourth flip-flop arrays are respectively connected to the thermometer code to binary code module. After the transcoding is completed, the results of the second and fourth flip-flop arrays are Tdl_res0 and Tdl_res1 respectively. The two are added to obtain the sampling result Tdl_res of this tap delay chain module. The sampling result is input into the look-up table circuit obtained by the code density test to find the fine delay value t corresponding to the sampling result.fine , and this value is the fine count value.

[0049] For the described coarse counter, when the time-to-digital converter system enters the measurement state, it starts counting according to the system clock, incrementing the result by one per cycle. When the fine count sampling valid signal Fine_valid transitions to a high level, the coarse count result of that cycle is sampled. The sampled result multiplied by the cycle value in picoseconds gives the coarse count as t coar .

[0050] The workflow includes the following steps:

[0051] Step 1: Build the circuit of any one of the mismatch-free high-precision multi-channel time-to-digital converters;

[0052] Step 2: Obtain the delay time corresponding to each tap of each chain through the method of code density testing and store it in the RAM;

[0053] Step 3: Send the same rising edge pulse Hit_align_n to each chain simultaneously and record the results recorded by each chain, calculate the path delay difference from the signal source to each measurement channel, and use this data as a reference to correct all subsequent measurement results;

[0054] Step 4: Send a rising edge pulse signal Hit_meas_n to the measurement channel to trigger the fine count sampling valid signal Fine_valid. Input the result sampled on the tap delay chain into the result lookup table obtained from the code density test, output the corresponding delay time, and finally save the delay time output by the lookup table together with the coarse count result saved when the fine count sampling valid signal is set high as the fine count result;

[0055] Step 5: Send the coarse and fine count results to the host computer, and calculate the rising edge positions of each rising edge pulse recorded by each channel to obtain various parameters to be measured. Embodiment

[0056] The circuit structure schematic of the time measurement function part of this embodiment is as Figure 3 shown. This time-to-digital converter has a total of 8 measurement channels. Each channel is equipped with an independent tap delay chain, a fine count sampling judgment circuit, a transcoding module, a coarse count sampling circuit, and a code density test circuit. They independently complete the sampling of the coarse and fine count results and send them to the measurement data processing module, communication module, etc. in real time. The 8 channels share a common coarse counter. This coarse counter starts accumulating by cycle at the beginning of the measurement, and the count value is connected to the coarse count sampling circuit. Whenever the fine count sampling result is valid, the corresponding coarse count value of this clock cycle is sampled. Combining the coarse and fine count results gives the moment corresponding to each rising edge. Calculating these recorded rising edge moments and combining with the peripheral circuit can obtain waveform parameter measurement results such as period and rise time.

[0057] The improved tapped delay line structure is as Figure 4 shown. First, two cascaded delay cells are used to form a delay line, and the 8th tap outputs of the two cascaded chains enter the judgment circuit. Each delay line measures only the corresponding moment of one rising edge in one measurement. It should be noted that here, choosing the 8th tap output to enter the judgment circuit is a more appropriate result obtained through practice. Using the 9th, 7th, or other appropriate taps is also acceptable. All those using this structure should be protected by this patent.

[0058] In the judgment circuit, if a rising edge signal is detected in one of the cascaded chains, that is, when the 8th output of the third flip - flop array is low and the 8th output of the previous first flip - flop array is high, or when the 8th output of the fourth flip - flop array is low and the 8th output of the previous second flip - flop array is high, the sampling valid signal is set high, and the coarse count result is sampled in the next clock cycle.

[0059] Although this method will cause the sampling moment of the coarse count to be later than the sampling period of the fine count, if the jump edge is delayed by the same period in each measurement, the final result will not affect the measurement performance. If only the position of a certain jump edge is to be measured, the measurement result can be subtracted by this fixed system cycle time.

[0060] To solve the problem that the corresponding delays of the first few taps are relatively large, we change the trigger condition from the output of the general first tap entering the judgment circuit to the output of the 8th tap entering the judgment circuit. In this way, the corresponding tap of one clock cycle and the fine count changes from the original 1 - N to 8 - (N + 7), which is equivalent to the taps covering one coarse cycle being shifted backward by 7 as a whole. Since the fine counter using the tapped delay line structure reserves more than 8 taps at the end of the chain as redundancy, the required taps after improvement are still within the range of the taps that the double - cascaded chain can provide.

[0061] To cooperate with the improved trigger method and enable the time - to - digital converter to meet various measurement requirements, the described time - to - digital converter uses a multi - channel cooperative measurement method, and aligns each channel before the measurement starts to adapt to the change that each delay line only measures one rising edge as described above, so that it can continue to measure the width of the pulse to be measured normally. Although this requires more delay lines than the traditional method, in actual application scenarios, this method is more flexible and can expand more parameter measurement functions. Especially in complex parameter measurement applications, sometimes it requires fewer delay lines than the traditional time - to - digital converter.

[0062] In the present invention, during the coarse and fine counting trigger, it first detects whether the fine counting is triggered. Only when the fine counting trigger is effective will the coarse count value be saved, effectively avoiding the mismatch between the coarse and fine counters. Generally, a TDL-TDC uses one channel to record both the rising edge and the falling edge of a pulse signal simultaneously to calculate the pulse width. In the present invention, since one channel only records once, more than two channels are required to cooperate in measuring the positions of the rising edge, etc. of the signal to be measured, and further calculate various parameters to be measured. In the present invention, multi-channel alignment operations are used to eliminate the influence of the path delay difference from the signal source to be measured to each channel, ensuring the high precision of multi-channel measurement.

[0063] This solution can be implemented based on the Xilinx ZYNQ-7 ZC706 development board. Since the performances of different FPGAs and underlying devices are different, the performances of the time-to-digital converters implemented with them will also be different. The performance of the 8-channel time-to-digital converter implemented on the ZYNQ-7 ZC706 development board is as Figure 5 shown. The resolution of a single chain is (5.46, 5.53) ps, the integral nonlinearity is (-3.55, 21.82) LSB, the differential nonlinearity is (-1.00, 1.55) LSB, and the range of the measurement accuracy when each chain cooperates is (13.19, 20.20) ps. The figure shows the resolution of each tap, the integral nonlinearity INL, the differential nonlinearity DNL of Line0, which is one of the 8 channels, and the measurement accuracy between Line1-Line0, Line2-Line0, Line3-Line0, Line5-Line4, Line6-Line4, Line7-Line4.

[0064] The implementation schemes described above can be further combined or replaced. Moreover, the implementation schemes only describe the preferred embodiments of the present invention, and do not limit the concept and scope of the present invention. Without departing from the design concept of the present invention, various changes and improvements made by those of ordinary skill in the art to the technical solutions of the present invention all fall within the protection scope of the present invention. The protection scope of the present invention is given by the appended claims and any equivalents thereof.

Claims

1. A multi-channel time-to-digital converter with no mismatch and high precision, characterized in that: It includes independent time signal measurement channels, a coarse counter, a measurement data processing module, and a data communication module; there are multiple independent time signal measurement channels, and each channel includes a tapped delay line (TDL), a fine count sampling and judgment circuit, a transcoding module, a coarse count sampling circuit, and a code density test circuit; The independent time measurement channels are used to quantize continuous time signals into digital signals, with a measurable range exceeding the system clock cycle. Together with the coarse counter, they form a two-step time-to-digital converter to achieve high-precision time signal measurement over a wide range; The transcoding module is used to convert the sampling results in the TDL from thermometer code to binary code; The coarse counter is used to count according to the system clock, incrementing the result by one per cycle. The coarse count result is input to the coarse count sampling circuit in the aforementioned independent time signal measurement channels; The code density test circuit is used to perform code density tests on each independent measurement channel before measurement to obtain the delay time corresponding to each tap of each channel and establish a corresponding lookup table. When measuring the time signal, the measured TDL results are converted into corresponding fine count results by looking up the table; The measurement data processing module is located in each independent measurement channel, used to save and calculate the measurement data each time, and is controlled to provide the measurement data to the data communication module; The data communication module is used to send the delay time corresponding to each tap obtained after code density testing, the reference delay time of each chain obtained after delay chain alignment operation, and the measurement results of random time signals to the host computer.

2. The multi-channel time-to-digital converter with no mismatch and high precision according to claim 1, characterized in that: The tapped delay line is composed of two identical cascaded delay units, namely the first delay unit cascaded chain and the second delay unit cascaded chain. These two cascaded chains are closely arranged in physical layout. The output of each delay unit except the last one is connected to the input of the next delay unit and the data input terminal of a nearest D flip-flop, and the output of the last delay unit is only connected to the data input terminal of the nearest D flip-flop; The D flip-flops connected to the output of each delay unit of the first delay unit cascaded chain form the first flip-flop array, and the D flip-flops connected to the output of each delay unit of the second delay unit cascaded chain form the second flip-flop array; The outputs of each flip-flop of the first flip-flop array and the second flip-flop array are connected to the input terminals of another nearest D flip-flop. The D flip-flops connected to the output of each flip-flop of the first flip-flop array form the third flip-flop array, and the D flip-flops connected to the output of each flip-flop of the second flip-flop array form the fourth flip-flop array; The outputs of the 8th flip-flops of the first to fourth flip-flop arrays are connected to the fine count sampling and judgment circuit.

3. The multi-channel time-to-digital converter with no mismatch and high precision according to claim 2, wherein: The outputs of the 8th flip-flops of the first to fourth flip-flop arrays are connected to the judgment circuit. Among them, when the output of the 8th flip-flop of the first flip-flop array is high and the output of the 8th flip-flop of the third flip-flop is low, or the output of the 8th flip-flop of the second flip-flop array is high and the output of the 8th flip-flop of the fourth flip-flop is low, the fine count sampling valid signal Fine_samp_valid is set to high level, indicating that sampling is valid.

4. The multi-channel time-to-digital converter with no mismatch and high precision according to claim 1, characterized in that: For the described coarse counter, when the time-to-digital converter system enters the measurement state, it starts counting according to the system clock, adding one to the result in each cycle, and the count value is connected to the coarse count sampling circuit of each measurement channel. When the fine count sampling valid signal Fine_samp_valid jumps to high level, the coarse count value of this cycle is sampled and saved together with the fine count result.

5. The multi-channel time-to-digital converter with no mismatch and high precision according to claim 1, characterized in that: For the described measurement data processing module, multiple channels save and calculate the measurement results of each chain in the multi-channel alignment step, and obtain the path delay differences of each chain from the signal source to the entrance of the delay chain.

6. The multi-channel time-to-digital converter with no mismatch and high precision according to claim 1, characterized in that: Mismatch-free high-precision multi-channel time-to-digital conversion includes the following steps: Step 1, build the circuit of a mismatch-free high-precision multi-channel time-to-digital converter; Step 2, obtain the delay time corresponding to each tap of each chain through the method of code density test and store it in the RAM; Step 3, by simultaneously sending the same rising edge pulse Hit_align_n to each chain and recording the results recorded by each chain, calculate the path delay differences from the signal source to each measurement channel, and use this data as a reference to correct all subsequent measurement results; Step 4, send a rising edge pulse signal Hit_meas_n to the measurement channel to trigger the fine count sampling valid signal Fine_samp_valid, input the results sampled on the tap delay chain into the result lookup table obtained by the code density test, output the corresponding delay time, and finally save the delay time output by the lookup table as the fine count result together with the coarse count result saved when the fine count sampling valid signal is set high; Step 5, send the coarse and fine count results to the host computer, and calculate the rising edge positions of the rising edge pulses recorded by each channel to obtain various parameters to be measured.

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