An extension method, device and medium of a standard serial bus device

Abstract

The application relates to the communication field and discloses an expansion method and device of a standard serial bus equipment, a medium, and application of the standard serial bus equipment including a bus adapter, the method comprising the following steps: obtaining design instructions and performing analysis to obtain equipment design information; obtaining a to-be-acquired function circuit and a direct memory access module corresponding to the to-be-acquired function circuit according to the equipment design information; determining pin information of the direct memory access module and the to-be-acquired function circuit; and updating configuration information of the bus adapter according to the pin information to realize communication connection of a core circuit and the to-be-acquired function circuit. According to the application, the to-be-acquired function circuit and the direct memory access module corresponding to the to-be-acquired function circuit are connected with the core circuit, the to-be-acquired function circuit does not need to be adaptively modified, the PCIe equipment can quickly and efficiently integrate various function circuits, the waste of manpower and material resources in the design process is reduced, and the PCIe equipment expansion efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of bus communication, and in particular to a method, apparatus, and medium for extending a standard serial bus device. Background Technology

[0002] The Peripheral Component Interconnect Express (PCIe) standard is a high-speed, point-to-point, dual-channel, high-bandwidth bus transmission standard widely used in computers and servers. Common PCIe devices include network interface cards (NICs), storage devices, and computing devices. With the rapid growth of computing power and increasing user demands, PCIe devices often need to integrate different functions. For example, smart NICs require added storage functionality, while high-speed storage devices require added NIC functionality within ordinary storage devices. Figure 1 For an existing PCIe device architecture, such as Figure 1 As shown, the hardware intellectual property (HIP) of a PCIe device is connected to each IP core (NIC, RDMA, NVME, and Kernel) through a multi-channel direct memory access (DMA) link core.

[0003] In order to shorten the development cycle and reduce development costs during the equipment development process, most manufacturers choose to add mature intellectual property (IP) cores to existing equipment. Figure 2 For example, an existing method for porting IP cores, such as Figure 2 As shown, manufacturers connect the NVME IP core to the multi-channel DMA IP core of the PCIe device to enable the PCIe device to have NVME functionality. However, when using this method, due to the large number of user interface signals and complex timing of the multi-channel DMA controller, in order to prevent incompatibility caused by inconsistent user interface signal definitions between the NVME IP core and the multi-channel DMA core, adaptive modifications to the DMA IP core and NVME IP core are required, which consumes a lot of manpower and resources.

[0004] Therefore, it is evident that providing a new method for expanding standard serial bus devices to enable PCIe devices to quickly and efficiently integrate multiple functional modules (IP cores) and reduce the waste of human and material resources during the design process is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a method, apparatus, and medium for expanding a standard serial bus device, so that PCIe devices can quickly and efficiently integrate multiple functional modules (IP cores) and reduce the waste of manpower and resources in the design process.

[0006] To address the aforementioned technical problems, this application provides a method for expanding a standard serial bus device, applicable to a standard serial bus device including a bus adapter. A first end of the bus adapter is connected to pins of the core circuitry of the standard serial bus device, and a second end of the bus adapter is connected to pins of the direct memory access modules of each functional module, thereby enabling data interaction between the core circuitry and the direct memory access modules. The method for expanding the standard serial bus device includes:

[0007] Obtain and parse design instructions to obtain device design information;

[0008] Based on the device design information, obtain the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired;

[0009] Determine the pin information of the direct memory access module and the functional circuit to be acquired;

[0010] The configuration information of the bus adapter is updated based on the pin information to establish a communication connection between the core circuit and the functional circuit to be acquired.

[0011] Preferably, the bus adapter includes a merging unit, a splitting unit, a flow control interface unit, and a bus configuration unit;

[0012] The first end of the splitting unit is connected to the transmit pin of the core circuit, and the second end of the splitting unit is connected to each of the direct memory access modules as a transmit pin, so as to split the data packets sent by the core circuit to the corresponding direct memory access modules.

[0013] The first end of the merging unit is connected to each of the direct memory access modules, and the second end of the merging unit is connected to the receiving pin of the core circuit, so as to merge the data packets sent by each of the direct memory access modules and send them to the core circuit.

[0014] The first end of the flow control interface unit and the bus configuration unit are both connected to the core circuit, and the second end of the flow control interface unit and the bus configuration unit are both connected to each direct memory access module.

[0015] Preferably, the data packet includes metadata information and data information;

[0016] The metadata information includes message type and data keywords.

[0017] Preferably, the merging unit merges the data packets sent by each of the direct memory access modules and sends them to the core circuit, including:

[0018] Obtain the data packets sent by each of the direct memory access modules via the transmit bus;

[0019] Determine whether the data packet is a memory read / write message based on the metadata information of the data packet;

[0020] If it is a memory read / write message, then the metadata information of each memory read / write message is updated according to the pin multiplexing relationship table of the core circuit, and the memory read / write messages are merged to generate a merged message, and the merged message is sent to the core circuit.

[0021] If not, the memory read / write messages are merged to generate a merged message, and the merged message is sent to the core circuit.

[0022] Preferably, the diversion unit diverts the data packets sent by the core circuit to the corresponding direct memory access module, including:

[0023] The data packets sent by the core circuit via the receive bus are acquired.

[0024] Determine whether the data packet is a memory read / write message based on the metadata information of the data packet;

[0025] If it is a memory read / write message, then the direct memory access module corresponding to the data packet is determined according to the data keywords of the memory read / write message;

[0026] If not, the direct memory access module corresponding to the data packet is determined based on the feature value of the metadata information of the data packet.

[0027] Preferably, the flow control interface unit is used to obtain the standard serial bus device credit limit of the core circuit to enable each of the direct memory access modules.

[0028] Preferably, the bus configuration unit is used to obtain the configuration information sent by the configuration bus of the core circuit, and send the configuration information to each of the direct memory access modules.

[0029] To address the aforementioned technical problems, this application also provides an expansion device for a standard serial bus device, applied to a standard serial bus device including a bus adapter. A first end of the bus adapter is connected to pins of the core circuit of the standard serial bus device, and a second end of the bus adapter is connected to pins of the direct memory access modules of each functional module, thereby enabling data interaction between the core circuit and the direct memory access modules. The expansion device for the standard serial bus device includes:

[0030] The first acquisition module is used to acquire and parse design instructions in order to obtain device design information;

[0031] The second acquisition module is used to acquire the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired based on the device design information.

[0032] A determination module is used to determine the pin information of the direct memory access module and the functional circuit to be acquired;

[0033] The update module is used to update the configuration information of the bus adapter according to the pin information, so as to realize the communication connection between the core circuit and the functional circuit to be acquired.

[0034] To address the aforementioned technical problems, this application also provides an extension device for a standard serial bus device, including a memory for storing computer programs;

[0035] A processor, used to implement the steps of the method for extending the standard serial bus device when executing the computer program.

[0036] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method for extending a standard serial bus device.

[0037] This application provides a method for expanding a standard serial bus device, applicable to a standard serial bus device including a bus adapter. The first end of the bus adapter is connected to pins of the core circuit of the standard serial bus device, and the second end of the adapter is connected to pins of the direct memory access modules (DMIs) of each functional module, to achieve data interaction between the core circuit and the DMIs. The method includes: acquiring and parsing design instructions to obtain device design information; acquiring the functional circuit to be acquired and the corresponding DMI based on the device design information; determining the pin information of the DMI and the functional circuit to be acquired; and updating the configuration information of the bus adapter based on the pin information to achieve communication connection between the core circuit and the functional circuit to be acquired, thereby enabling the core circuit to connect to the functional circuit to be acquired through its DMI. Therefore, the technical solution provided in this application, by connecting the functional circuit to be acquired and its corresponding DMI to the core circuit, eliminates the need for adaptive modifications to the functional circuit, enabling PCIe devices to quickly and efficiently integrate multiple functional circuits, reducing the waste of manpower and resources during the design process, and improving the expansion efficiency of PCIe devices.

[0038] Furthermore, this application also provides an expansion device and medium for a standard serial bus device, applied to a standard serial bus device including a bus adapter. The first end of the bus adapter is connected to each pin of the core circuit of the standard serial bus device, and the second end of the adapter is connected to each pin of the direct memory access module of each functional module to realize data interaction between the core circuit and the direct memory access module. The expansion device for the standard serial bus device includes: acquiring and parsing design instructions to obtain device design information; acquiring the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired based on the device design information; determining the pin information of the direct memory access module and the functional circuit to be acquired; and updating the configuration information of the bus adapter based on the pin information to realize data interaction between the core circuit and the functional circuit to be acquired.

[0039] The communication connection of the core circuit enables the core circuit to connect with the functional circuit to be acquired via the direct memory access module of the functional circuit to be acquired. Therefore, the technical solution provided in this application, by connecting the functional circuit to be acquired and its corresponding direct memory access module to the core circuit, eliminates the need for adaptive modifications to the functional circuit to be acquired. This allows PCIe devices to quickly and efficiently integrate multiple functional circuits, reducing the waste of manpower and resources during the design process and improving the expansion efficiency of PCIe devices. Attached Figure Description

[0040] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is an existing PCIe device architecture;

[0042] Figure 2 This is an existing method for porting IP cores;

[0043] Figure 3 An application scenario diagram illustrating a method for expanding a standard serial bus device provided in an embodiment of this application;

[0044] Figure 4 A flowchart illustrating an extension method for a standard serial bus device provided in this application embodiment;

[0045] Figure 5 A user interface definition diagram for the core circuit of a PCIe device;

[0046] Figure 6 This is a schematic diagram of the core circuit data bus format of a PCIe device.

[0047] Figure 7 A flowchart illustrating the merging unit provided in the embodiments of this application;

[0048] Figure 8 A flowchart illustrating the workflow of the shunt unit provided in an embodiment of this application;

[0049] Figure 9 A structural diagram of an expansion device for a standard serial bus device provided in an embodiment of this application;

[0050] Figure 10 This is a structural diagram of an expansion device for another standard serial bus device provided in an embodiment of this application. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and

[0052] This is not an exhaustive list of embodiments. All other embodiments obtained by those skilled in the art based on the embodiments described in this application without inventive effort are within the scope of protection of this application.

[0053] The core of this application is to provide a method, device, and medium for expanding a standard serial bus device, so that PCIe devices can quickly and efficiently integrate multiple functional modules (IP cores), reduce the waste of manpower and resources in the design process, and improve the expansion efficiency of PCIe devices.

[0054] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] In the application scenarios of the standard serial bus device expansion method provided in this application, the design instructions involved can be chip design instructions or design instructions for other PCIe devices, and are not limited here. Figure 2 For example, an existing method for porting IP cores, such as Figure 2 As shown, when PCIe device manufacturers add new network or storage functions, traditionally, they rely on their own multi-channel DMA and reserve one path for implementing the new function. However, PCIe device manufacturers often lack sufficient technical reserves for new functions. In this case, manufacturers will add new functions by purchasing mature IP or porting mature open-source projects, adapting the new functions to their own multi-channel DMA controllers. Acceleration IPs (such as NVMe IPs) provided by IP providers are usually provided in conjunction with PCIe DMA. For example, NVMe-IP (NVMe-IP for PCIe Gen3 / Gen4 Hard IP) is a PCIe-based IP core, and PCIe device manufacturers will extract the NVMe IP and integrate it into existing PCIe acceleration projects. However, the user interfaces of DMA controllers from different manufacturers are usually inconsistent. This method of adding new third-party functions based on an existing multi-channel DMA controller requires modifying the IP code of the new function based on the existing multi-channel DMA controller. Moreover, the corresponding function IP code must be modified for each function added. In this process, not only is it necessary to be familiar with the IP code of the new function, but also the DMA controller has many user interface signals with complex timing. Furthermore, the inconsistent definition of user interface signals of DMA controllers from different manufacturers leads to difficulties in adaptation or debugging, which invisibly increases the porting time and the probability of failure.

[0056] Figure 3 This application scenario diagram illustrates an extension method for a standard serial bus device provided in an embodiment of this application. Figure 3As shown, this application connects the functional circuit to be acquired and its corresponding direct memory access module to the core circuit, eliminating the need for adaptive modifications to the functional circuit. This enables PCIe devices to quickly and efficiently integrate multiple functional circuits, reducing waste of manpower and resources during the design process and improving the expansion efficiency of PCIe devices. Specifically, the expansion method for standard serial bus devices provided in this application is applied to standard serial bus devices including a bus adapter. The first end of the bus adapter is connected to each pin of the core circuit of the standard serial bus device, and the second end of the adapter is connected to each pin of the direct memory access module of each functional module, thereby realizing the connection between the core circuit and the direct memory access module.

[0057] Accessing data interaction between modules; the extension method for standard serial bus devices includes: obtaining and parsing design instructions to obtain device design information; obtaining the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired based on the device design information; determining the pin information of the direct memory access module and the functional circuit to be acquired; updating the configuration information of the bus adapter based on the pin information to realize the communication connection between the core circuit and the functional circuit to be acquired, so that the core circuit can connect to the functional circuit to be acquired through the direct memory access module of the functional circuit to be acquired.

[0058] Figure 4 The flowchart illustrates an expansion method for a standard serial bus device provided in this application embodiment. This method is applied to a standard serial bus device including a bus adapter. The first end of the bus adapter is connected to each pin of the core circuit of the standard serial bus device, and the second end of the adapter is connected to each pin of the direct memory access module of each functional module, thereby enabling data interaction between the core circuit and the direct memory access module. Figure 4 As shown, the expansion method for this standard serial bus device includes:

[0059] S10: Obtain and parse design instructions to obtain device design information;

[0060] S11: Obtain the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired based on the equipment design information;

[0061] S12: Determine the pin information of the direct memory access module and the functional circuit to be acquired;

[0062] S13: Update the configuration information of the bus adapter according to the pin information to realize the communication connection between the core circuit and the functional circuit to be acquired.

[0063] Figure 5 A user interface definition diagram for the core circuit of a PCIe device, such as Figure 5As shown, the rx_st bus is the user data receiving bus, and the tx_st bus is the user data sending bus. Both meet the timing requirements of the avalon_stream bus. The data bus transmits hdr and data. hdr contains PCIe protocol related information, such as TLP message type, TAG tag, etc., and data is the data information.

[0064] Figure 6 This is a schematic diagram of the core circuit data bus format of a PCIe device. The bus data format diagrams for rx_st and tx_st are shown below. Figure 6 As shown, the metadata information HDR includes the TAG field and FMT. The Tx_cred bus is the flow control signal bus, and the user enables transmission based on the credit value output by the bus signal. The tl_cfg bus is the configuration bus, used for configuring the PCIe interface.

[0065] This embodiment provides an expansion method for a standard serial bus device, applied to a standard serial bus device including a bus adapter. The first end of the bus adapter is connected to each pin of the core circuit of the standard serial bus device, and the second end of the adapter is connected to each pin of the direct memory access module (DMI) of each functional module, to realize data interaction between the core circuit and the DMI. The expansion method for the standard serial bus device includes: acquiring and parsing design instructions to obtain device design information; acquiring the functional circuit to be acquired and the corresponding DMI module based on the device design information; determining the pin information of the DMI module and the functional circuit to be acquired; and updating the configuration information of the bus adapter based on the pin information to realize the communication connection between the core circuit and the functional circuit to be acquired, thereby enabling the core circuit to connect to the functional circuit to be acquired through the DMI module of the functional circuit to be acquired. Therefore, the technical solution provided in this application, by connecting the functional circuit to be acquired and its corresponding DMI module to the core circuit, eliminates the need for adaptive modifications to the functional circuit to be acquired, enabling PCIe devices to quickly and efficiently integrate multiple functional circuits, reducing the waste of manpower and resources during the design process, and improving the expansion efficiency of PCIe devices.

[0066] In practical implementation, the bus adapter is mainly used to realize data interaction between the core circuit and the functional circuit to be acquired, and to send the working instructions of the core circuit to the functional circuit to be acquired, as well as to send the working status of the functional circuit to be acquired to the core circuit, so as to ensure that the PCIe device can operate normally.

[0067] Based on the above embodiments, the bus adapter includes a merging unit, a splitting unit, a flow control interface unit, and a bus configuration unit; wherein, the first end of the splitting unit is connected to the transmit pin of the core circuit, and the second end of the splitting unit is connected to each direct memory access module as a transmit pin, so as to split the data packets sent by the core circuit to the corresponding direct memory access modules;

[0068] The first end of the merging unit is connected to each direct memory access module, and the second end of the merging unit is connected to the receiving pin of the core circuit to merge the data packets sent by each direct memory access module and send them to the core circuit.

[0069] The first end of the flow control interface unit and the bus configuration unit are both connected to the core circuit, and the second end of the flow control interface unit and the bus configuration unit are both connected to each direct memory access module.

[0070] Furthermore, the data packet includes metadata information and data information; among which, the metadata information includes message type and data keywords.

[0071] Figure 7 A flowchart of the merging unit provided in the embodiments of this application is shown below. Figure 7 As shown, the merging unit merges the data packets sent by each direct memory access module and sends them to the core circuit, including:

[0072] S20: Obtain the data packets sent by each direct memory access module through the transmit bus;

[0073] S21: Determine whether the data packet is a memory read / write message based on the data packet's metadata information;

[0074] S22: If it is a memory read / write message, update the metadata information of each memory read / write message according to the pin multiplexing relationship table of the core circuit, merge each memory read / write message to generate a merged message, and send the merged message to the core circuit.

[0075] S23: If not, merge the memory read / write messages to generate a merged message and send the merged message to the core circuit.

[0076] In practical implementation, the PCIe HIP interface user data bus transmits TLP messages, which mainly include MWr / MRd memory read / write messages, Msg messages, and Cpl completion messages. The rx_st bus transmits MWr / MRd messages and Cpl completion messages, while the tx_st bus transmits MWr / MRd messages, Msg messages, and Cpl completion messages. Different types of messages can be distinguished by the type field of the data bus hdr.

[0077] The merging unit's processing flow is as follows: The multi-DMA engine sends data packets to the core circuit via the tx_st bus. If the data packet is a Mrd / MRd message, the PCIe bus adapter updates the tag label of the hdr field of the corresponding tx_st, the multi-DMA engine divides the tag value equally, and then merges and outputs it to the PCIe core circuit. If the sent data packet is a Cpl message or a Msg message, the PCIe bus adapter directly merges and outputs it.

[0078] Figure 8 The flowchart of the shunt unit provided in the embodiments of this application is as follows: Figure 8 As shown, the data packet distribution unit distributes the data packets sent by the core circuit to the corresponding direct memory access modules, including:

[0079] S31: Obtain the data packets sent by the core circuit through the receive bus;

[0080] S32: Determine whether the data packet is a memory read / write message based on the data packet's metadata information;

[0081] S33: If it is a memory read / write message, determine the direct memory access module corresponding to the data packet based on the data keywords of the memory read / write message;

[0082] S34: If not, determine the direct memory access module corresponding to the data packet based on the feature value of the data packet's metadata information.

[0083] In practice, the processing flow of the traffic splitting unit is as follows: detect the hdr field of rx_st to determine the data type of the packet. If it is a MWr / Mrd packet output by PCIe HIP, it is distributed to different DMA engines according to the tag value. If it is a Cfg packet output, it is distinguished by the bar id of the hdr field and sent to different DMA engines.

[0084] Furthermore, the flow control interface unit is used to obtain the PCIe interface credit limit of the core circuit to enable each direct memory access module. In specific implementation, the flow control interface unit subtracts the credit value consumed by a single DMA engine from the PCIe interface credit limit contained in the tx_cred bus, and transmits the difference to the DMA engine.

[0085] The bus configuration unit is used to obtain the configuration information sent by the configuration bus of the core circuit and send the configuration information to each direct memory access module.

[0086] In the above embodiments, the expansion method for a standard serial bus device has been described in detail. This application also provides embodiments corresponding to the expansion device for a standard serial bus device. It should be noted that this application describes the embodiments of the device part from two perspectives: one is based on the functional module, and the other is based on the hardware.

[0087] Figure 9 This application provides a structural diagram of an expansion device for a standard serial bus device, applicable to a standard serial bus device including a bus adapter. The first end of the bus adapter is connected to each pin of the core circuit of the standard serial bus device, and the second end of the adapter is connected to each pin of the direct memory access module of each functional module to realize data interaction between the core circuit and the direct memory access module. Figure 9 As shown, the expansion device of this standard serial bus device includes:

[0088] Module 10 is used to acquire and parse design instructions to obtain device design information;

[0089] The second acquisition module 11 is used to acquire the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired based on the device design information.

[0090] Module 12 is used to determine the pin information of the direct memory access module and the functional circuit to be acquired;

[0091] The update module 13 is used to update the configuration information of the bus adapter according to the pin information, so as to realize the communication connection between the core circuit and the functional circuit to be acquired.

[0092] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0093] This embodiment provides an expansion device for a standard serial bus device, applied to a standard serial bus device including a bus adapter. The first end of the bus adapter is connected to each pin of the core circuit of the standard serial bus device, and the second end of the adapter is connected to each pin of the direct memory access module of each functional module to realize data interaction between the core circuit and the direct memory access module. The expansion device for the standard serial bus device includes: acquiring and parsing design instructions to obtain device design information; acquiring the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired based on the device design information; determining the pin information of the direct memory access module and the functional circuit to be acquired; and updating the configuration information of the bus adapter based on the pin information to realize the communication connection between the core circuit and the functional circuit to be acquired, thereby enabling the core circuit to connect to the functional circuit to be acquired through the direct memory access module of the functional circuit to be acquired. Therefore, the technical solution provided in this application, by connecting the functional circuit to be acquired and its corresponding direct memory access module to the core circuit, eliminates the need for the functional circuit to be acquired to be connected.

[0094] Adaptive modifications are made to enable PCIe devices to quickly and efficiently integrate multiple functional circuits, reducing the waste of manpower and resources during the design process and improving the expansion efficiency of PCIe devices.

[0095] Figure 10 A structural diagram of an expansion device for another standard serial bus device provided in an embodiment of this application is shown below. Figure 10 As shown, the expansion device of the standard serial bus device includes: a memory 20 for storing computer programs;

[0096] The processor 21 is configured to implement the steps of the extended method for a standard serial bus device as described in the above embodiments when executing a computer program.

[0097] The application areas of the expansion device for the standard serial bus device provided in this embodiment may include, but are not limited to, smartphones, tablets, laptops, or desktop computers.

[0098] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0099] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the expansion method for the standard serial bus device disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, design instructions, device design information, etc.

[0100] In some embodiments, the expansion device of the standard serial bus device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0101] Those skilled in the art will understand that Figure 10 The structure shown does not constitute a limitation on the expansion device of a standard serial bus device and may include more or fewer components than illustrated.

[0102] The extension device for a standard serial bus device provided in this application includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method:

[0103] Obtain and parse design instructions to obtain device design information;

[0104] Based on the equipment design information, obtain the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired;

[0105] Determine the pin information of the direct memory access module and the functional circuit to be acquired;

[0106] The configuration information of the bus adapter is updated based on the pin information to achieve communication connection between the core circuit and the functional circuit to be acquired.

[0107] This embodiment provides an expansion device for a standard serial bus device, applied to a standard serial bus device including a bus adapter. The first end of the bus adapter is connected to each pin of the core circuit of the standard serial bus device, and the second end of the adapter is connected to each pin of the direct memory access module of each functional module to realize data interaction between the core circuit and the direct memory access module. The expansion device for the standard serial bus device includes: acquiring and parsing design instructions to obtain device design information; acquiring the functional circuit to be acquired and the corresponding direct memory access module based on the device design information; determining the pin information of the direct memory access module and the functional circuit to be acquired; and updating the configuration information of the bus adapter based on the pin information to realize the communication connection between the core circuit and the functional circuit to be acquired, thereby enabling the core circuit to connect to the functional circuit to be acquired through the direct memory access module of the functional circuit to be acquired. Therefore, the technical solution provided in this application, by connecting the functional circuit to be acquired and its corresponding direct memory access module to the core circuit, eliminates the need for adaptive modifications to the functional circuit to be acquired, enabling PCIe devices to quickly and efficiently integrate multiple functional circuits, reducing the waste of manpower and resources during the design process, and improving the expansion efficiency of PCIe devices.

[0108] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above method embodiments.

[0109] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.

[0110] Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0111] The above provides a detailed description of the methods, apparatus, and media for expanding the standard serial bus device provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0112] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for expanding a standard serial bus device, characterized in that, It is applied to a standard serial bus device including a bus adapter, wherein the first end of the bus adapter is connected to each pin of the core circuit of the standard serial bus device, and the second end of the bus adapter is connected to each pin of the direct memory access module of each functional module, so as to realize data interaction between the core circuit and the direct memory access module; The method for extending the standard serial bus device includes: Obtain and parse design instructions to obtain device design information; Based on the device design information, obtain the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired; Determine the pin information of the direct memory access module and the functional circuit to be acquired; The configuration information of the bus adapter is updated based on the pin information to establish a communication connection between the core circuit and the functional circuit to be acquired.

2. The method for expanding a standard serial bus device according to claim 1, characterized in that, The bus adapter includes a merging unit, a splitting unit, a flow control interface unit, and a bus configuration unit; The first end of the splitting unit is connected to the transmit pin of the core circuit, and the second end of the splitting unit is connected to each of the direct memory access modules as a transmit pin, so as to split the data packets sent by the core circuit to the corresponding direct memory access modules. The first end of the merging unit is connected to each of the direct memory access modules, and the second end of the merging unit is connected to the receiving pin of the core circuit, so as to merge the data packets sent by each of the direct memory access modules and send them to the core circuit. The first end of the flow control interface unit and the bus configuration unit are both connected to the core circuit, and the second end of the flow control interface unit and the bus configuration unit are both connected to each direct memory access module.

3. The method for expanding a standard serial bus device according to claim 2, characterized in that, The data packet includes metadata information and data information; The metadata information includes message type and data keywords.

4. The method for expanding a standard serial bus device according to claim 3, characterized in that, The merging unit merges the data packets sent by each of the direct memory access modules and sends them to the core circuit, including: Obtain the data packets sent by each of the direct memory access modules via the transmit bus; Based on the metadata information of the data packet, determine whether the data packet is a memory read / write message; a memory read / write message is an MWr / MRd memory read / write message; If it is a memory read / write message, the metadata information of each memory read / write message is updated through the PCIe bus adapter, and the memory read / write messages are merged to generate a merged message, which is then sent to the core circuit. If not, the data packets are merged to generate a merged message, and the merged message is sent to the core circuit.

5. The method for expanding a standard serial bus device according to claim 3, characterized in that, The diversion unit diverts the data packets sent by the core circuit to the corresponding direct memory access modules, including: Acquire the data packet sent by the core circuit through the transmit pin; Based on the metadata information of the data packet, determine whether the data packet is a memory read / write message; a memory read / write message is an MWr / MRd memory read / write message; If it is a memory read / write message, then the direct memory access module corresponding to the data packet is determined according to the data keywords of the memory read / write message; If not, the direct memory access module corresponding to the data packet is determined based on the feature value of the metadata information of the data packet.

6. The method for expanding a standard serial bus device according to any one of claims 1 to 5, characterized in that, The flow control interface unit is used to obtain the standard serial bus device credit limit of the core circuit in order to control the enabling of each of the direct memory access modules.

7. The method for expanding a standard serial bus device according to claim 6, characterized in that, The bus configuration unit is used to obtain the configuration information sent by the configuration bus of the core circuit and send the configuration information to each of the direct memory access modules.

8. An expansion device for a standard serial bus device, characterized in that, It is applied to a standard serial bus device including a bus adapter, wherein the first end of the bus adapter is connected to each pin of the core circuit of the standard serial bus device, and the second end of the bus adapter is connected to each pin of the direct memory access module of each functional module, so as to realize data interaction between the core circuit and the direct memory access module; The expansion device of the standard serial bus device includes: The first acquisition module is used to acquire and parse design instructions in order to obtain device design information; The second acquisition module is used to acquire the functional circuit to be acquired and the direct memory access module corresponding to the functional circuit to be acquired based on the device design information. A determination module is used to determine the pin information of the direct memory access module and the functional circuit to be acquired; The update module is used to update the configuration information of the bus adapter according to the pin information, so as to realize the communication connection between the core circuit and the functional circuit to be acquired.

9. An expansion device for a standard serial bus device, characterized in that, Includes memory used to store computer programs; A processor, configured to implement the steps of the method for extending a standard serial bus device as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for extending a standard serial bus device as described in any one of claims 1 to 7.

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