Data migration method and computing device

Abstract

The embodiment of the application provides a data migration method and a computing device, relates to the technical field of computing devices, and can improve the memory access performance of an application. The method is applied to a first processor, the first processor is one of a plurality of processors included in a computing device, each processor in the plurality of processors is connected with at least one memory; a first memory accessed by the first processor includes to-be-migrated data; and the method comprises the following steps: in response to a data migration instruction, determining a second memory from a data migration mapping table; the data migration mapping table comprises a memory set corresponding to the first memory, the memory set corresponding to the first memory is obtained based on comprehensive access delays of each memory, and the comprehensive access delay of each memory is determined according to an actual access delay of the first processor to the memory and an equivalent access delay of the first processor to the memory; and migrating the to-be-migrated data from the first memory to the second memory. The embodiment of the application can be used in the process of server optimization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computing devices, and particularly relates to a data migration upgrading method and a computing device. BACKGROUND

[0002] In a computing device, the running of an application program often occupies a certain memory space. With the continuous promotion of enterprise digitalization and informatization transformation, various diversified application programs emerge in an endless stream, and higher requirements are put forward for the content capacity of the computing device. Compute express link (CXL) is a bus architecture based on an industry standard protocol, which is used for memory expansion of the computing device to improve the memory bandwidth and capacity of the computing device. Since the CXL protocol and the link itself have a certain time delay, there are memories with different access time delays in the computing device after CXL expansion.

[0003] In the process of running the application program, the computing device needs to transfer the access data in the high-time-delay memory to the low-time-delay memory to improve the running performance of the application program. However, the current data migration scheme has the problem of causing the performance of the application program to decrease in the actual operation process. SUMMARY

[0004] The embodiments of the present application provide a data migration method and a computing device, which can effectively improve the performance of the application program during data migration.

[0005] In a first aspect, the embodiments of the present application provide a data migration method applied to a first processor, the first processor being one of a plurality of processors included in a computing device, each processor in the plurality of processors being connected to at least one memory; a first memory accessed by the first processor including to-be-migrated data; the method comprising: determining a second memory from a data migration mapping table in response to a data migration instruction; the data migration mapping table including a memory set corresponding to the first memory, the second memory being one of the memory set, the memory set corresponding to the first memory being obtained based on comprehensive access time delays of each memory, the comprehensive access time delay of each memory being determined according to an actual access time delay of the first processor to the memory and an equivalent access time delay of the first processor to the memory, the equivalent access time delay being used to indicate a performance loss of the first processor when accessing the memory; and migrating the to-be-migrated data from the first memory to the second memory.

[0006] The data migration method provided in the embodiments of the present application determines the second memory from the data migration mapping table determined based on the comprehensive access latency of each memory after receiving the data migration instruction, and migrates the to-be-migrated data to the second memory. The comprehensive access latency takes into account not only the real access latency of the processor accessing the memory, but also the performance loss caused by the processor accessing the memory. Compared with the conventional method of determining the second memory only by considering the real access latency, the data migration method provided in the embodiments of the present application is more in line with the performance loss that may exist in the cross-processor access to the memory in the actual scenario, and the data migration based on this method can give full play to the hardware performance and effectively improve the memory access performance of the application program.

[0007] In a possible implementation manner, the data migration mapping table is stored in the memory of the computing device; and the second memory is determined from the data migration mapping table in response to the data migration instruction, including: the data migration mapping table is acquired from the memory in response to the data migration instruction; and the second memory is determined from the data migration mapping table. It should be understood that the data migration mapping table is previously established and saved in the memory, and the processor can directly call and use the data migration mapping table when performing data migration, without the need to additionally spend time and computing power to create the data migration mapping table, thereby improving the data migration efficiency and reducing the waste of computing power resources.

[0008] In another possible implementation manner, after the data migration instruction is responded to, the method further includes: acquiring a memory latency table, the memory latency table including the comprehensive access latency of each memory to the first processor; and acquiring the data migration mapping table based on the memory latency table and the size ordering of the comprehensive access latency of the memory.

[0009] In yet another possible implementation manner, after the data migration instruction is responded to, the method further includes: acquiring the memory latency table based on the memory relationship mapping table; the memory relationship mapping table including the connection mode between each processor in the plurality of processors and the memory connected thereto; the memory relationship mapping table being determined based on the memory information of each memory; the memory latency table including the comprehensive access latency of each memory to the first processor; and acquiring the data migration mapping table based on the memory latency table and the size ordering of the comprehensive access latency of the memory.

[0010] In yet another possible implementation manner, after the data migration instruction is responded to, the method further includes: acquiring the memory information of each memory; acquiring the memory relationship mapping table based on the memory information; the memory relationship mapping table including the connection mode between each processor in the plurality of processors and the memory connected thereto; acquiring the memory latency table based on the memory relationship mapping table; the memory latency table including the comprehensive access latency of each memory to the first processor; and acquiring the data migration mapping table based on the memory latency table and the size ordering of the comprehensive access latency of the memory.

[0011] In another possible implementation, the comprehensive access latency of each memory in the data migration mapping table satisfies:

[0012] T_total = T_equal + T_real

[0013] wherein T_total represents the comprehensive access latency, T_real represents the real access latency, and T_equal represents the equivalent access latency.

[0014] In another possible implementation, the equivalent access latency satisfies:

[0015] T_equal = a x T_remote

[0016] wherein a is a first value when the memory is connected to the first processor, and a is a second value when the memory is connected to a second processor, the second processor being one of the plurality of processors other than the first processor, the second value being greater than the first value, and T_remote represents a latency conversion coefficient corresponding to a performance loss of the first processor when accessing the memory.

[0017] In another possible implementation, the data migration instruction includes a first data migration direction, the first data migration direction being used to indicate a migration direction of the hot data, and determining the second memory from the data migration mapping table includes: determining, from the data migration mapping table, a first memory set corresponding to the first memory in the first data migration direction, the comprehensive access latency of each memory in the first memory set being less than the comprehensive access latency of the first memory, and taking a target memory in the first memory set as the second memory, the comprehensive access latency of the target memory being less than the comprehensive access latency of other memories in the first memory set. It should be understood that, for hot data migration, the hot data can be placed in a memory with a lower latency, the time spent by the processor in accessing the hot data can be shortened, and thus the memory access performance of the application program can be ensured.

[0018] In another possible implementation, after the to-be-migrated data is migrated from the first memory to the second memory, the method further includes: in the case of migration failure, taking a next memory of the target memory in the first memory set as the second memory in the order of the comprehensive access latency from small to large. It should be understood that, in the case of hot data migration failure, a new memory is sequentially selected for retry, the low-latency memory capacity can be fully utilized while meeting the data migration requirement, and the memory access performance of the application program can be further ensured.

[0019] In another possible implementation manner, the data migration instruction comprises: a second data migration direction; the second data migration direction is used to indicate a migration direction of the cold data; the determining the second memory from the data migration mapping table comprises: determining, from the data migration mapping table, a second memory set corresponding to the first memory in the second data migration direction; a comprehensive access latency of each memory in the second memory set is greater than the comprehensive access latency of the first memory; and one memory in the second memory set is selected as the second memory. It should be understood that, by migrating the cold data, more low-latency memory capacity can be released, so that more hot data can be migrated to the low-latency memory, and the memory access performance of the application program is further ensured.

[0020] In another possible implementation manner, after the data to be migrated is migrated from the first memory to the second memory, the method further comprises: in the case of migration failure, selecting one memory from the second memory set as the second memory according to the comprehensive access latency.

[0021] In another possible implementation manner, the connection mode of the at least one memory and the processor comprises one or more of the following modes: direct connection, connection through CXL, and connection through a CXL switching chip.

[0022] In a second aspect, an embodiment of the present application provides a data migration apparatus applied to a first processor, the first processor being one of a plurality of processors included in a computing device, each processor in the plurality of processors being connected to at least one memory; a first memory accessed by the first processor comprising data to be migrated; and the apparatus comprising: a determining module and a migration module. The determining module is configured to determine a second memory from a data migration mapping table; the data migration mapping table comprising a memory set corresponding to the first memory, the second memory being one of the memory set, the memory set corresponding to the first memory being obtained based on comprehensive access latencies of the memories, the comprehensive access latency of each memory being determined according to an actual access latency of the first processor to the memory and an equivalent access latency of the first processor to the memory, the equivalent access latency being used to indicate a performance loss of the first processor when accessing the memory; and the migration module is configured to migrate the data to be migrated from the first memory to the second memory.

[0023] In a possible implementation manner, the data migration mapping table is stored in a memory of the computing device; and the determining module is specifically configured to acquire the data migration mapping table from the memory in response to the data migration instruction; and determine the second memory from the data migration mapping table.

[0024] In another possible implementation manner, the apparatus further comprises an acquisition module. The acquisition module is configured to acquire a memory latency table, the memory latency table comprising the comprehensive access latencies of the first processor to the memories; and acquire the data migration mapping table based on the memory latency table and the comprehensive access latencies of the memories in size order.

[0025] In a further possible implementation form of the data migration method, the memory relationship mapping table comprises a connection mode between each processor of the plurality of processors and the memory connected thereto, and the memory relationship mapping table is determined based on memory information of the memory.

[0026] In a further possible implementation form of the data migration method, the memory information of the memory is obtained, the memory relationship mapping table is obtained based on the memory information, the memory relationship mapping table comprises a connection mode between each processor of the plurality of processors and the memory connected thereto, the memory latency table is obtained based on the memory relationship mapping table, the memory latency table comprises the comprehensive access latency of the first processor to the memory, and the data migration mapping table is obtained based on the memory latency table and the comprehensive access latency of the memory.

[0027] In a further possible implementation form of the data migration method, the comprehensive access latency of each memory in the data migration mapping table satisfies:

[0028] T_total=T_equal+T_real

[0029] wherein T_total represents the comprehensive access latency, T_real represents the real access latency, and T_equal represents the equivalent access latency.

[0030] In a further possible implementation form of the data migration method, the equivalent access latency satisfies:

[0031] T_equal=α×T_remote

[0032] wherein α is a first value when the memory is connected to the first processor, α is a second value when the memory is connected to a second processor, the second processor is one of the plurality of processors other than the first processor, the second value is greater than the first value, and T_remote represents a latency conversion coefficient corresponding to a performance loss of the first processor when accessing the memory in the case that the memory is connected to the second processor.

[0033] In a further possible implementation form of the data migration method, the first data migration direction is used to indicate a migration direction of the hot data, and the determining comprises: determining, from the data migration mapping table, a first memory set corresponding to the first memory in the first data migration direction, wherein the comprehensive access latency of each memory in the first memory set is less than the comprehensive access latency of the first memory, and a target memory in the first memory set is taken as the second memory, wherein the comprehensive access latency of the target memory is less than the comprehensive access latency of the other memories in the first memory set.

[0034] In a further possible implementation form of the data migration method, the migration module is further configured to, in case of a migration failure, select a next memory of the target memory in the first memory set as the second memory according to an order of the comprehensive access latency from small to large.

[0035] In a further possible implementation form of the data migration method, the data migration instruction comprises a second data migration direction, the second data migration direction is used to indicate a migration direction of the cold data, the determining module is specifically configured to determine, from the data migration mapping table, a second memory set corresponding to the first memory in the second data migration direction, each memory in the second memory set has a comprehensive access latency greater than the comprehensive access latency of the first memory, and one memory in the second memory set is selected as the second memory.

[0036] In a further possible implementation form of the data migration method, the migration module is further configured to, in case of a migration failure, reselect a memory from the second memory set as the second memory according to the comprehensive access latency.

[0037] In a further possible implementation form of the data migration method, the connection mode of the at least one memory and the processor comprises one or more of the following modes: direct connection, connection through a compute express link (CXL), and connection through a CXL switch chip.

[0038] In a third aspect, an embodiment of the present application provides a computing device, which comprises a processor and a memory, the memory stores instructions executable by the processor, and the processor is configured to execute the instructions to enable the computing device to implement the method in the first aspect.

[0039] In a fourth aspect, an embodiment of the present application provides a computing device, which comprises a plurality of processors, each processor in the plurality of processors is connected to at least one memory, and a first processor is one of the plurality of processors, the first processor is configured to: in response to a data migration instruction, determine a second memory from a data migration mapping table, the data migration mapping table comprises a memory set corresponding to a first memory, the second memory is one of the memory set, the memory set corresponding to the first memory is obtained based on comprehensive access latencies of the memories, the comprehensive access latency of each memory is determined according to an actual access latency from the first processor to the memory and an equivalent access latency from the first processor to the memory, and the equivalent access latency is used to indicate a performance loss of the first processor when accessing the memory; and migrate to-be-migrated data from the first memory to the second memory.

[0040] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which comprises computer software instructions, and when the computer software instructions run in a computing device, enable the computing device to implement the method in the first aspect.

[0041] In a sixth aspect, an embodiment of the present application provides a computer program product, which, when running on a computer, causes the computer to execute the steps of the method described in the first aspect to implement the method of the first aspect.

[0042] The advantages of the second aspect to the sixth aspect can refer to the corresponding description of the first aspect, and will not be repeated. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 A composition schematic diagram of a computing device provided by an embodiment of the present application is shown in FIG. 1.

[0044] Figure 2 A connection schematic diagram of a local memory and a remote memory provided by an embodiment of the present application is shown in FIG. 2.

[0045] Figure 3 A relationship schematic diagram of a multi-level latency memory provided by an embodiment of the present application is shown in FIG. 3.

[0046] Figure 4 A flowchart of a data migration method provided by an embodiment of the present application is shown in FIG. 4.

[0047] Figure 5 A flowchart of another data migration method provided by an embodiment of the present application is shown in FIG. 5.

[0048] Figure 6 A flowchart of still another data migration method provided by an embodiment of the present application is shown in FIG. 6.

[0049] Figure 7 A flowchart of a data migration method provided by an embodiment of the present application is shown in FIG. 7.

[0050] Figure 8 A flowchart of a data migration method provided by an embodiment of the present application is shown in FIG. 8.

[0051] Figure 9 A flowchart of a data migration method provided by an embodiment of the present application is shown in FIG. 9.

[0052] Figure 10 A system architecture schematic diagram provided by an embodiment of the present application is shown in FIG. 10.

[0053] Figure 11 A composition schematic diagram of a data migration device provided by an embodiment of the present application is shown in FIG. 11.

[0054] Figure 12 A composition schematic diagram of another computing device provided by an embodiment of the present application is shown in FIG. 12. DETAILED DESCRIPTION

[0055] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0056] It should be noted that in the embodiments of the present application, the words such as “exemplarily” or “for example” are used to represent an example, illustration or description. Any embodiment or design scheme described as “exemplarily” or “for example” in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words such as “exemplarily” or “for example” are intended to present the related concept in a specific manner.

[0057] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words “first”, “second” and the like are used to distinguish the same or similar items with basically the same function and role, and those skilled in the art can understand that the words “first”, “second” and the like are not used to limit the number and execution order.

[0058] In order to understand the technical solutions of the embodiments of the present application, the terms involved in the present application will be briefly introduced.

[0059] 1. Data migration: a technical means for improving the access speed of data and the performance of an application program, and transferring commonly used data to low-latency memory and transferring infrequently used data to high-latency memory.

[0060] 2. Compute Express Link (CXL): an open industry standard bus architecture that provides high-bandwidth, low-latency connections between dedicated compute, memory, input / output interfaces and storage elements within a data center. By extending the memory of a computing device through CXL, the memory bandwidth and capacity of the computing device can be improved to better adapt to memory-intensive application scenarios.

[0061] As described in the background section, to meet the diverse memory capacity and bandwidth requirements of applications, related technologies often employ Connected Memory Arrays (CXLs) to allow computing devices to connect more memory, thereby expanding the memory capacity and bandwidth of the computing device. Because CXLs themselves have a certain latency, memory connected via CXLs has a higher read / write access latency compared to traditionally directly connected memory. Therefore, after connecting memory via CXLs, the computing device has memory with varying access latencies. When applications indiscriminately access memory with different latencies, it can lead to performance degradation. Therefore, current methods generally involve data migration to move data used by applications from high-latency memory to low-latency memory, ensuring that applications can read data quickly and thus improving application performance.

[0062] The computing device mentioned here can be a tower server, a rack server, or a blade server. This application does not limit the specific form of the computing device.

[0063] Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application, such as... Figure 1 As shown, the hardware portion of this computing device may include a motherboard, multiple processors (two are shown as an example in the figure), and a basic input / output system (BIOS) chip. The BIOS chip and the multiple processors are mounted on the motherboard, with the BIOS chip connected to each of the processors. Each processor is connected to at least one memory module. It should be noted that the multiple processors can be interconnected in pairs or connected sequentially in a ring, depending on the specific scenario; this embodiment does not impose specific limitations in this regard. Furthermore, the software portion of this computing device may include an operating system (OS) kernel (also known as an OS management unit) and a BIOS. The OS kernel may reside within one or more processors, and the BIOS is located within a BIOS chip.

[0064] In this embodiment, the processor can be based on an x86 architecture or an ARM (advanced RISC machines) architecture. For example, the processor can be a central processing unit (CPU).

[0065] Taking a CPU as an example, in a multi-CPU computing device, there is a case that the CPU idle state is indefinite when an application is executed, and thus an application process can be executed on different CPUs, which changes dynamically. In addition, each CPU is connected with a memory, and thus, when an application running on a certain CPU (referred to as a first CPU) applies for a memory, if the memory capacity connected with the first CPU meets the application, the memory connected with the first CPU is allocated to the application, which is local memory for the application. If the memory capacity connected with the first CPU is insufficient, the memory connected with another CPU (referred to as a second CPU) can be allocated to the application, which is not the memory connected with the first CPU, and is non-local memory or remote memory for the application. Generally, the access latency of the remote memory is greater than that of the local memory, and thus, in the multi-CPU computing device, the application can directly access the local memory with a smaller access latency, or access the non-local memory with a greater access latency, and there is a certain optimization space for memory access.

[0066] Figure 2 A connection diagram of local memory and remote memory is provided for an embodiment of the present application. As shown in the figure, Figure 1 CPU0 is connected with memory0, CPU1 is connected with memory1, and CPU0 is connected with CPU1. For example, the memory0 and the memory1 herein can be dual-inline-memory-modules (DIMM). Taking the CPU0 as the first CPU, the CPU0 directly accesses the memory0, which is local memory. The CPU0 needs to access the memory1 across the CPU1, which is non-local memory or remote memory. Thus, when the application accesses data in the non-local memory, the data in the non-local memory can be migrated to the local memory under the premise that the local memory capacity is sufficient, so that the application running in the CPU0 can read and write data from the local memory with a smaller latency, to improve the memory access performance of the application.

[0067] For different processors, after the CXL extended memory, each processor in the computing device has memory with different access latencies, for example, Figure 3A relationship diagram of a multi-level latency memory is provided for an embodiment of the present application. The computing device can include two processors, CPU0 and CPU1. CPU0 is directly connected to memory 1, connected to memory 3 and memory 4 through CXL, and connected to memory 7 and memory 8 through a CXL switch. CPU1 is directly connected to memory 2, connected to memory 5 and memory 6 through CXL, and connected to memory 9 and memory 10 through a CXL switch. The direct connection refers to the connection between the memory and the pins provided by the CPU. The CXL switch is a switch chip based on the CXL protocol, which can be used to expand the connection of multiple memories, and configure the processors corresponding to the expanded connected memories according to the actual needs. For example, Figure 3 The CXL switch is connected to memories 7-10, in which memories 7 and 8 are configured as memories connected to CPU0, and memories 9 and 10 are configured as memories connected to CPU1.

[0068] At present, in the data migration process, the way to select the memory to be migrated (such as the second memory) is generally to select the target memory according to the real access latency of the memory. The real access latency refers to the time waiting for the memory response before the processor performs the read-write operation state ready. For example, it is illustrated in combination with Figure 3 Take CPU0 as an example. The real access latency of CPU0 accessing the local memory (memory 1) is about 100 nanoseconds, the real access latency of CPU0 accessing the remote memory (memory 2) is about 180 nanoseconds, the real access latency of CPU0 accessing the local CXL memory (memory 3 or memory 4) is about 260 nanoseconds, the real access latency of CPU0 accessing the remote CXL memory (memory 5 or memory 6) is about 440 nanoseconds, the real access latency of CPU0 accessing the local CXL switch memory (memory 7 or memory 8) is about 500 nanoseconds, and the real access latency of CPU0 accessing the remote CXL switch memory (memory 9 or memory 10) is about 600 nanoseconds.

[0069] If the data being accessed by CPU0 is located on memory 7, when it is necessary to migrate the data to a memory with low latency, memory 3 or memory 2 can be selected as the target for migration. As can be seen, although the real access latency of memory 2 is less than that of memory 3, for CPU0, memory 2 is a remote access memory, and if memory 2 is selected as the second memory for data migration, it will cause the frequently migration of frequently used data in the local memory to the remote memory (for example, memory 2 connected to CPU1) when the local memory is tight. In this case, for CPU1, since memory 2 is occupied, when CPU1 performs data migration, there is also a problem of local memory tightness, which causes the data to be migrated to the memory connected to CPU0, and thus the application running on CPU0 or CPU1 frequently accesses the data in the remote memory, thereby causing the performance of the application to decrease.

[0070] That is, the current data migration scheme only considers the real access latency of the memory, without considering the factor of cross-processor access to the memory. Especially in the case where the real access latency of the remote memory (path 1 in the middle) and the real access latency of the local CXL memory (path 2 in the middle) are close to each other, the cross-processor factor has a greater impact on the performance of the application. Figure 3 Figure 3

[0071] Based on this, the embodiment of the present application provides a data migration method, which comprehensively considers the real access latency and the performance loss when accessing the memory to determine the second memory to be migrated into, optimizes the deficiencies of the data migration scheme in the related art, and thus effectively improves the performance of the application.

[0072] The data migration method provided by the embodiment of the present application can be applied to the scenarios shown in Figure 1 or Figure 3 It should be noted that for each processor, the specific execution steps of the data migration method provided by the embodiment of the present application are similar, and the following will be described by taking any processor (for example, referred to as a first processor) as an example. The first memory accessed by the first processor includes to-be-migrated data, and it should be noted that the first memory herein is any memory in the computing device.

[0073] Embodiment one

[0074] Figure 4 A flowchart of a data migration method provided by the embodiment one of the present application. For example, as shown in Figure 4 The data migration method provided by the embodiment one of the present application can specifically include the following steps:

[0075] S401, in response to a data migration instruction, the first processor determines a second memory from a data migration mapping table.​​

[0076] The data migration instruction is used to indicate that the first processor needs to perform a migration operation on the to-be-migrated data. The data migration instruction can come from an operating system kernel. Embodiments of the present application do not limit the specific timing of the operating system kernel sending the data migration instruction. For example, a user manually issues a data migration instruction to the first processor through the operating system, or the operating system kernel itself supports the function of memory management, and the operating system kernel can periodically scan the attribute information (such as utilization, remaining space, etc.) of each memory and issue a data migration instruction when the attribute information meets a preset condition.

[0077] In the embodiments of the present application, when an application program running on the first processor is accessing the first memory, if the first processor receives the data migration instruction, the second memory (i.e., the target of migration) can be determined from the data migration mapping table in response to the data migration instruction.

[0078] The data migration mapping table described above includes a memory set corresponding to the first memory, the second memory is one of the memory set, and the memory set corresponding to the first memory is obtained based on the comprehensive access latency of each memory. The comprehensive access latency of each memory is determined according to the real access latency of the first processor to the memory and the equivalent access latency of the first processor to the memory. Here, each memory refers to a plurality of memories connected to a plurality of processors in a computing device. The equivalent access latency is used to indicate the performance loss of the first processor when accessing the memory; or the performance loss caused by the first processor accessing the memory across processors.

[0079] It should be noted that in the embodiments of the present application, the data migration mapping table described above can be constructed by any processor in the computing device in advance and stored in the memory of the computing device. For example, the memory can be a random access memory, a dynamic storage device, a disk storage medium, or any other form of storage device in the computing device. Specifically, S401 can be implemented to obtain the data migration mapping table from the memory in response to the data migration instruction, and then determine the second memory from the data migration mapping table. It should be understood that the data migration mapping table is previously established and saved in the memory, and the processor can directly call and use it when performing data migration, without the need to spend additional time and computing power to create the data migration mapping table, thereby improving the data migration efficiency and reducing the waste of computing resources.

[0080] The comprehensive access latency of each memory in the data migration mapping table satisfies the following expression:

[0081] T_total = T_equal + T_real

[0082] Wherein, T_total represents the comprehensive access latency, T_real represents the real access latency, and T_equal represents the equivalent access latency. The equivalent access latency satisfies the following expression:

[0083] T_equal = a x T_remote

[0084] Wherein, a represents whether the memory belongs to the first processor. When the memory is connected with the first processor, a is a first value; when the memory is connected with the second processor, a is a second value; the second processor is one of the processors except the first processor, and the second value is greater than the first value. The above T_remote represents a latency conversion coefficient corresponding to the performance loss of the first processor when accessing the memory in the case that the memory is connected with the second processor. Wherein, the value of T_remote can be determined according to experiments. In addition, the size of T_remote is related to the number of cross-processors, for example, when accessing the memory across one processor, the value of T_remote can be 100 nanoseconds, when accessing the memory across two processors, the value of T_remote can be 200 nanoseconds, and so on.

[0085] It should be noted that the data in the computing device includes hot data and cold data, and accordingly, the data migration is divided into hot data migration and cold data migration. If it is hot data migration, it means that the data needs to be frequently used, and then the hot data needs to be migrated from the memory with large latency to the memory with small latency to improve the access efficiency. If it is cold data migration, it means that the data is used less frequently, and then the cold data needs to be migrated from the memory with small latency to the memory with large latency to ensure that the memory with small latency has larger capacity.

[0086] The embodiment of the present application does not limit the specific distinguishing method of hot data and cold data, as an example, the operating system kernel can use a special statistical counter to count, if the data access frequency is greater than a certain threshold, it is determined as hot data, if the data access frequency is less than or equal to a certain threshold, it is determined as cold data. As another example, the least recently used (LRU) algorithm used in the current industry memory management can also be used to divide hot data and cold data, for details, please refer to the related technology, and the embodiment of the present application does not make detailed description. According to the difference between hot and cold data, the data migration direction can be included in the data migration instruction issued by the operating system kernel, and the data migration direction is used to indicate the migration direction of hot data or the migration direction of cold data. The detailed steps of determining the second memory for hot and cold data in the embodiment of the present application are described as follows:

[0087] In an embodiment, the data migration direction comprises a first data migration direction. The first data migration direction is used to indicate the migration direction of hot data, and the data to be migrated in the first memory is hot data. Based on this, as shown in Figure 5 S401a-S401b.

[0088] S401a, the first processor determines a first memory set corresponding to the first memory in the first data migration direction from the data migration mapping table.

[0089] Wherein, the comprehensive access latency of each memory in the first memory set is less than that of the first memory.

[0090] S401b, the first processor selects a target memory in the first memory set as the second memory.

[0091] Wherein, the comprehensive access latency of the target memory is less than that of other memories in the first memory set.

[0092] As described above, the data migration table includes a memory set corresponding to the first memory. After receiving the data migration instruction, the first processor determines a first memory set corresponding to the first memory in the first data migration direction from the data migration mapping table, and then selects a memory with the smallest comprehensive access latency (i.e. candidate memory) from the first memory set as the second memory to which the hot data needs to be migrated.

[0093] It should be understood that for hot data migration, the hot data can be placed in a memory with lower latency, which shortens the time spent by the processor accessing the hot data, thereby ensuring the memory access performance of the application program.

[0094] In another embodiment, the data migration direction comprises a second data migration direction. The second data migration direction is used to indicate the migration direction of cold data, and the data to be migrated in the first memory is cold data. As shown in Figure 6 S401c-S401d.

[0095] S401c, the first processor determines a second memory set corresponding to the first memory in the second data migration direction from the data migration mapping table.

[0096] Wherein, the comprehensive access latency of each memory in the second memory set is greater than that of the first memory.

[0097] S401d, the first processor selects a memory in the second memory set as the second memory.

[0098] As described previously, the first memory corresponds to a memory set in the data migration table. After receiving the data migration instruction, the first processor determines the first memory set corresponding to the first memory in the second data migration direction from the data migration mapping table according to the second data migration direction, and then selects one memory from the first memory set as the second memory that needs to be migrated as cold data. It should be noted that the manner of selecting the memory can be to select the memory with the minimum comprehensive access latency, or to select the memory with the maximum comprehensive access latency, or to randomly select, which can be determined according to the actual scene, and the embodiments of the present application do not make specific limitations.

[0099] It should be understood that the migration of cold data can release more capacity of lower latency memory, so that more hot data can be migrated to lower latency memory, further ensuring the memory access performance of the application program.

[0100] The above two embodiments will be described in detail below in combination with specific examples.

[0101] In combination with the schematic diagram shown in the foregoing Figure 3 The first value of a is 0, the second value of a is 1, and the value of T_remote is 100 nanoseconds. Taking CPU0 as an example of the first processor, memory 1 is connected to CPU0, so the value of a is 0, and the comprehensive access latency of memory 1 is 0*100+100=100 nanoseconds, that is, the comprehensive access latency of memory 1 is equal to the real access latency. Memory 2 is not connected to CPU0, so the value of a is 1, and the comprehensive access latency of memory 2 is 1*100+180=280 nanoseconds. Similarly, the comprehensive access latencies of memory 3 and memory 4 are both 260 nanoseconds, the comprehensive access latencies of memory 5 and memory 6 are both 540 nanoseconds, the comprehensive access latencies of memory 7 and memory 8 are both 500 nanoseconds, and the comprehensive access latencies of memory 9 and memory 10 are both 600 nanoseconds.

[0102] Further, based on the comprehensive access latency size comparison, for memory 1, no other memory has a comprehensive access latency smaller than that of memory 1, and the comprehensive access latencies of memory 2-memory 10 are all greater than that of memory 1. Therefore, it is determined that the first memory set of memory 1 in the hot data migration direction is empty (NA), and the second memory set of memory 2 in the cold data migration direction includes: memory 3, memory 4, memory 2, memory 7, memory 8, memory 5, memory 6, memory 9 and memory 10 (sorted in ascending order of comprehensive access latency). Based on the analysis principle described above, the determined data migration mapping table is shown in Table 1.

[0103] Table 1

[0104]

[0105]

[0106] In Table 1, for CPU0, each memory corresponds to a first memory set in the hot data migration direction, and a second memory set in the cold data migration direction. When CPU0 receives a data migration instruction, the second memory can be selected based on Table 1 for migration.

[0107] For example, in combination with Table 1, when the data accessed by the application running in CPU0 is located in memory 5, memory 5 is the first memory. After receiving the hot data migration instruction, the CPU can determine from Table 1 that the integrated access latency of memory 1, memory 3, memory 4, memory 2, memory 7, and memory 8 is less than that of memory 5. Among them, the integrated access latency of memory 1 (i.e., the target memory) is the smallest, so memory 1 is selected as the second memory to which the hot data in memory 5 needs to be migrated.

[0108] Similarly, after receiving the cold data migration instruction, CPU0 can determine from Table 1 that the integrated access latency of memory 9 and memory 10 is greater than that of memory 5. Then, memory 9 and memory 10 form a second memory subset. Among them, the integrated access latency of memory 9 and memory 10 is consistent, so one of them can be randomly selected as the second memory to which the cold data in memory 5 needs to be migrated.

[0109] It should be noted that the data migration mapping table shown in Table 1 is for CPU0. If it is for CPU1, the data migration mapping table established is shown in Table 2.

[0110] Table 2

[0111]

[0112]

[0113] In Table 2, for CPU1, each memory corresponds to a first memory set in the hot data migration direction, and a second memory set in the cold data migration direction. When CPU1 receives a data migration instruction, the second memory can be selected based on Table 2 for migration.

[0114] S402, the first processor migrates the to-be-migrated data from the first memory to the second memory.

[0115] In the embodiments of the present application, after determining the target position, i.e., the second memory, to which the to-be-migrated data is to be migrated, the first processor can migrate the to-be-migrated data from the first memory to the second memory. The embodiments of the present application do not limit the specific migration process. As an example, a function of data migration (page migration) is provided in the CPU, and the CPU can call the function to implement data migration. As another example, the CPU can establish a process to implement page copying to achieve the purpose of data migration.

[0116] It should be noted that, in the process of data migration, a situation of insufficient memory capacity can be encountered, which can result in migration failure. In this case, a memory needs to be determined again for data migration, which is described as follows:

[0117] In one embodiment, in the case of hot data migration, after S402, the data migration method provided by the embodiments of the present application can further include the following S403a.

[0118] S403a, in the case of migration failure, the next memory of the target memory in the first memory set is selected as the second memory in the order of the comprehensive access latency from small to large.

[0119] The next memory refers to a memory in the first memory set, which has a larger comprehensive access latency than the target memory, but has a smaller comprehensive access latency than other memories.

[0120] It should be understood that, in the case of hot data migration failure, it indicates that the capacity of the currently determined second memory is insufficient to accommodate the to-be-migrated data. Therefore, the first processor can determine the next memory from the first memory subset as a new second memory in the order of the comprehensive access latency from small to large, and perform the data migration operation.

[0121] In other embodiments, in the case of cold data migration, after S402, the data migration method provided by the embodiments of the present application further includes the following S403b.

[0122] S403b, in the case of migration failure, a memory is selected from the second memory set as the second memory according to the size of the comprehensive access latency.

[0123] Similarly, in the case of cold data migration failure, the first processor can determine the next memory from the second memory subset as a new second memory according to the size of the comprehensive access latency, and perform the data migration operation. The selection method can be to select in the order of the comprehensive access latency from small to large, or to select in the order of the comprehensive access latency from large to small, which can be determined according to the actual scene, and the embodiments of the present application do not limit the specific selection method.

[0124] It should be understood that, in the case of migration failure, reselecting the second memory node for migration retry according to the size of the comprehensive access latency can guarantee the full use of memory capacity and further guarantee the performance of the application program under the condition of meeting the data migration requirement.

[0125] The process of data migration is illustrated in detail in combination with the above Table 1 or Table 2.

[0126] Taking hot data migration as an example, when CPU0 receives a data migration instruction and needs to migrate the data on memory 5, according to the first memory set corresponding to memory 5 in the hot data migration direction in Table 1, the first memory set is memory 1, memory 3, memory 4, memory 2, memory 7 and memory 8 from left to right. Therefore, when migrating data, CPU0 first migrates to memory 1 with the smallest comprehensive access latency, and if the migration fails, it tries to migrate to memory 3, memory 4, memory 2, memory 7 and memory 8 in turn. It should be understood that when the migration of a certain memory is successful, the process of trying to migrate the following memory is ended. When all the migration attempts fail, the migration of the data in memory 5 is cancelled.

[0127] Taking cold data migration as an example, when CPU1 receives a data migration instruction and needs to migrate memory 10, CPU1 determines the second memory set corresponding to memory 10 in the cold data migration direction according to Table 2, which is memory 3, memory 4, memory 7 and memory 8 from left to right. Therefore, when migrating data, CPU1 can select the second memory to try to migrate in the order of the comprehensive access latency from small to large (i.e. from left to right in the table). It can also select the second memory to try to migrate in the order of the comprehensive access latency from large to small (i.e. from right to left in the table). Similarly, when the migration of a certain memory is successful, the process of trying to migrate the following memory is ended. When all the migration attempts fail, the migration of the data in memory 10 is cancelled.

[0128] The data migration method provided by the embodiments of the present application determines the second memory from the data migration mapping table determined based on the comprehensive access latency of each memory after receiving a data migration instruction, and migrates the to-be-migrated data to the second memory. The comprehensive access latency not only considers the real access latency of the processor accessing the memory, but also considers the performance loss caused by the processor accessing the memory. Compared with the conventional method of determining the second memory for migration only considering the real access latency, the data migration method provided by the embodiments of the present application is more consistent with the performance loss that may exist in the actual scenario of cross-processor accessing the memory. Based on this method, the hardware performance can be fully utilized, and the memory access performance of the application program can be effectively improved.

[0129] Further, in the case of data migration failure, a new memory can be selected in sequence for retry based on the size of the comprehensive access latency, to ensure sufficient utilization of memory capacity and further ensure the memory access performance of the application program while meeting the data migration requirements.

[0130] It should be noted that the above embodiment one is that the data migration mapping table is established in advance, and is directly used in the data migration. In other embodiments, the data migration mapping table can be acquired after the first processor receives the data migration instruction. The specific description is shown in the following embodiments two to four.

[0131] Embodiment two

[0132] Figure 7 A flowchart of a data migration method provided by the embodiment two of the present application is shown. As shown in the example of Figure 7 The data migration method provided by the embodiment two of the present application can specifically include the following steps:

[0133] S701, in response to a data migration instruction, acquiring memory information of each memory; based on the memory information, acquiring a memory relationship mapping table; based on the memory relationship mapping table, acquiring a memory latency table; based on the memory latency table and the size of the comprehensive access latency of the memory, sorting to acquire a data migration mapping table.

[0134] The memory relationship mapping table includes the connection mode between each processor in the plurality of processors and the memory connected thereto. The memory latency table includes the comprehensive access latency of the first processor to each memory.

[0135] In the embodiment of the present application, when the computing device is started, the plurality of processors perform a self-checking process to select a processor (referred to as a main processor) from the plurality of processors, and the main processor is responsible for calling the BIOS to start the process of performing the power-on self-test. Further, the BIOS can scan the memory in the computing device and acquire the related information of the memory during the power-on self-test process, including the identification of the memory, the memory timing, the connection mode between the memory and the processor, etc. The memory timing is a parameter describing the performance of the memory, which can determine the real access latency of the memory. In some implementations, the BIOS can also scan the memory in the computing device to acquire the memory size and the distance between the memory and the processor.

[0136] Further, after the operating system is started, the operating system kernel can call an advanced configuration and power management interface (ACPI) to obtain information such as memory identification, memory timing, and connection mode between the memory and the processor from the BIOS. The ACPI is a standard interface that defines a communication interface between the operating system, firmware, and hardware. The ACPI is usually implemented in the BIOS and controlled by an operating system driver. After the operating system kernel obtains the memory timing of each memory, the real access latency of each processor accessing the memory can be measured based on the memory timing. For details, refer to related technologies, which are not described in detail here.

[0137] After receiving the data migration instruction, the first processor can obtain memory information such as memory identification, real access latency of the memory, and connection mode between the memory and the processor issued by the operating system kernel, to obtain a memory relationship mapping table based on the memory information. The table can be stored in the memory. The table is mainly used to reflect different connection modes between the processor and the memory in the computing device.

[0138] For example, Table 3 is a memory mapping relationship table provided by an embodiment of the present application.

[0139] Table 3

[0140]

[0141]

[0142] Table 3 includes two processors (CPU0 and CPU1) and a plurality of memories connected to each processor. The plurality of memories are divided into three groups, and the connection mode of the memory in different groups to the corresponding processor is different, for example, the connection mode includes: direct connection, connection through CXL, and connection through CXL switch chip.

[0143] Further, in combination with Table 3 described above, based on the expression for determining the comprehensive access latency, a memory latency table is obtained, which can be stored in the memory.

[0144] Taking CPU0 as the first processor as an example, it can be known from Table 3 that the memory 1, the memory 3, the memory 4, the memory 7 and the memory 8 are memories connected with the CPU0, and according to the foregoing analysis, the comprehensive access latency of these memories is the real access latency. The other memories are not connected with the CPU, and the value of a is 1. For example, taking the value of T_remote as 100 nanoseconds as an example, the comprehensive access latency of the memory 2 is 1*100+180=280 nanoseconds, the comprehensive access latency of the memory 5 and the memory 6 is 1*100+440=540 nanoseconds, and the comprehensive access latency of the memory 9 and the memory 10 is 1*100+500=600 nanoseconds. Based on the foregoing analysis, the memory latency table obtained by the first processor is shown in Table 4.

[0145] Table 4

[0146]

[0147] Similarly, taking CPU1 as the first processor as an example, the memory latency table obtained by the first processor is shown in Table 5.

[0148] Table 5

[0149]

[0150]

[0151] Finally, based on the memory latency table and the size of the comprehensive access latency of the memory, the first processor can obtain a data migration table. For example, taking CPU0 as the first processor as an example, the data migration table obtained by the first processor according to Table 4 is shown in Table 1. Taking CPU1 as the first processor as an example, the data migration table obtained by the first processor according to Table 5 is shown in Table 2.

[0152] S702, the first processor determines the second memory from the data migration mapping table.

[0153] S703, the first processor migrates the to-be-migrated data from the first memory to the second memory.

[0154] The related description of S702 and S703 can refer to the related description in the foregoing embodiment one, which will not be repeated here.

[0155] Embodiment three

[0156] Figure 8 A flowchart of a data migration method provided by the embodiment three of the application is shown in Fig. 3. For example, as shown in Fig. 3, the data migration method provided by the embodiment three of the application can specifically include the following steps: Figure 8

[0157] ​S801, in response to the data migration instruction, obtaining a memory latency table based on the memory relationship mapping table; obtaining a data migration mapping table based on the memory latency table and the memory access latency size ordering.

[0158] In the embodiment of the present application, the BIOS can obtain the identification of each memory and the connection relationship between the memory and the processor in the power-on self-test process, and construct the memory relationship mapping table as described in Table 3 above according to these information, or report these information to the operating system kernel, and instruct any processor to construct the memory relationship mapping table and store it in the memory. When the first processor receives the data migration instruction, the memory relationship mapping table can be obtained from the memory, and the memory latency table shown in Table 4 or Table 5 can be obtained based on the memory relationship mapping table and the real access latency of the memory. Further, the data migration mapping table shown in Table 1 or Table 2 can be obtained based on the memory latency table and the memory access latency size ordering.

[0159] S802, the first processor determines the second memory from the data migration mapping table.

[0160] S803, the first processor migrates the to-be-migrated data from the first memory to the second memory.

[0161] The related description of S802 and S803 above can refer to the related description in the aforementioned embodiment one, which will not be repeated here.

[0162] Embodiment four

[0163] Figure 9 The flowchart of a data migration method provided by the fourth embodiment of the present application is shown. As an example, as shown in the figure, Figure 9 The data migration method provided by the fourth embodiment of the present application can specifically include the following steps:

[0164] S901, in response to the data migration instruction, obtaining a memory latency table; obtaining a data migration table based on the memory latency table and the memory access latency size ordering.

[0165] In the embodiment of the present application, the operating system kernel can combine the memory related information reported by the BIOS to instruct any one or more processors to construct the memory latency table corresponding to each processor in advance and store it in the memory. After receiving the data migration instruction, the first processor can obtain the corresponding memory latency table from the memory, and then obtain the data migration table shown in Table 1 or Table 2 based on the memory latency table and the memory access latency size ordering.

[0166] S902, determining the second memory from the data migration mapping table.

[0167] S903, migrating the to-be-migrated data from the first memory to the second memory.

[0168] The relevant descriptions of S902 and S903 above can be found in the relevant descriptions in the aforementioned Embodiment 1, and will not be repeated here.

[0169] The beneficial effects of Embodiments 2 to 4 described above can be found in the relevant description of Embodiment 1.

[0170] Figure 10 A system architecture diagram provided for an embodiment of this application, such as Figure 10 As shown in the diagram, from top to bottom, the components are the application (APP), user mode, and kernel mode. User mode and kernel mode are two runtime levels of the operating system. Most applications (APPs) that users directly use, such as Redis databases or HANA in-memory databases, run in user mode. When an application involves hardware operations (e.g., data migration in memory in this embodiment), the user mode runtime level cannot support the execution of hardware operation-related instructions, so it is necessary to switch to kernel mode to execute these instructions. The glibc library is a C runtime library that can run in user mode. The glibc library provides the operating system's lowest-level application programming interface (API), allowing users to configure the data migration strategy provided in this embodiment based on the glibc library's API. The kernel mode includes a memory relationship mapping table creation module, a cold / hot data migration target memory calculation module, and a page migration module. These modules are implemented by users through code written via the API interface. The memory mapping table creation module is used to establish a memory mapping table (Table 3 above) according to the user-configured strategy. The hot and cold data migration target memory computing module further establishes a hot data migration target memory list and a cold data migration target memory list for different computing nodes based on the mapping table (Table 1 or Table 2 above). The page migration module performs page migration scheduling (data migration).

[0171] As can be seen, the above mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, the embodiments of this application provide corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the modules and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0172] In an example embodiment, the present application also provides a data migration apparatus. The data migration apparatus can include one or more functional modules for implementing the data migration method of the above method embodiments. For example, Figure 11 A composition diagram of a data migration apparatus provided by the present application is shown. The data migration apparatus can be applied to a first processor, which is one of a plurality of processors included in a computing device, each of the plurality of processors being connected to at least one memory; the first memory accessed by the first processor including to-be-migrated data. As shown in the figure, the apparatus includes a determination module 1101 and a migration module 1102. Figure 11 The determination module 1101 is configured to determine a second memory from a data migration mapping table; the data migration mapping table including a memory set corresponding to the first memory, the second memory being one of the memory set, the memory set corresponding to the first memory being obtained based on comprehensive access latencies of the memories, the comprehensive access latency of each memory being determined according to an actual access latency of the first processor to the memory and an equivalent access latency of the first processor to the memory, the equivalent access latency being used to indicate a performance loss of the first processor when accessing the memory.

[0173] The migration module 1102 is configured to migrate the to-be-migrated data from the first memory to the second memory.

[0174] In some embodiments, the data migration mapping table is stored in a memory of the computing device; the determination module 1101 is specifically configured to, in response to a data migration instruction, obtain the data migration mapping table from the memory; and determine the second memory from the data migration mapping table.

[0175] In some embodiments, the above apparatus further includes an obtaining module 1103. The obtaining module 1103 is configured to obtain a memory latency table, the memory latency table including the comprehensive access latencies of the first processor to the memories; and obtain the data migration mapping table based on the memory latency table and the comprehensive access latencies of the memories in size order.

[0176] In some embodiments, the obtaining module 1103 is further configured to obtain the memory latency table based on a memory relationship mapping table; the memory relationship mapping table including connection modes between each processor of the plurality of processors and the memory connected thereto; the memory relationship mapping table being determined by memory information of the memories; the memory latency table including the comprehensive access latencies of the first processor to the memories; and obtain the data migration mapping table based on the memory latency table and the comprehensive access latencies of the memories in size order.

[0177] In some embodiments, the obtaining module 1103 is further configured to obtain the memory latency table based on a memory relationship mapping table; the memory relationship mapping table including connection modes between each processor of the plurality of processors and the memory connected thereto; the memory relationship mapping table being determined by memory information of the memories; the memory latency table including the comprehensive access latencies of the first processor to the memories; and obtain the data migration mapping table based on the memory latency table and the comprehensive access latencies of the memories in size order.

[0178] In some embodiments, the obtaining module 1103 is further configured to: obtain memory information of each memory; obtain a memory relationship mapping table based on the memory information, the memory relationship mapping table comprising a connection mode between each processor of the plurality of processors and a memory connected thereto; obtain a memory latency table based on the memory relationship mapping table, the memory latency table comprising a comprehensive access latency of the first processor to each memory; and obtain a data migration mapping table based on the memory latency table and a size ordering of the comprehensive access latency of the memory.

[0179] In some embodiments, the comprehensive access latency of each memory in the data migration mapping table satisfies:

[0180] T_total=T_equal+T_real

[0181] wherein T_total represents the comprehensive access latency, T_real represents a real access latency, and T_equal represents an equivalent access latency.

[0182] In some embodiments, the equivalent access latency satisfies:

[0183] T_equal=α×T_remote

[0184] wherein α is a first value when the memory is connected to the first processor, and α is a second value when the memory is connected to a second processor, the second processor being one of the plurality of processors other than the first processor, the second value being greater than the first value, and T_remote representing a latency conversion coefficient corresponding to a performance loss of the first processor when accessing the memory in the case where the memory is connected to the second processor.

[0185] In some embodiments, the first data migration direction is used to indicate a migration direction of the hot data, and the determining module 1101 is specifically configured to: determine, from the data migration mapping table, a first memory set corresponding to the first memory in the first data migration direction, the comprehensive access latency of each memory in the first memory set being less than the comprehensive access latency of the first memory; and take a target memory in the first memory set as the second memory, the comprehensive access latency of the target memory being less than the comprehensive access latency of other memories in the first memory set.

[0186] In some embodiments, the migrating module 1102 is further configured to, in the case where the migration fails, take a next memory of the target memory in the first memory set as the second memory in order from small to large according to the comprehensive access latency.

[0187] In some embodiments, the data migration instruction comprises: a second data migration direction; the second data migration direction is used to indicate the migration direction of the cold data; the determining module 1101 is specifically configured to determine, from the data migration mapping table, a second memory set corresponding to the first memory in the second data migration direction; the integrated access latency of each memory in the second memory set is greater than the integrated access latency of the first memory; and one memory in the second memory set is selected as the second memory.

[0188] In some embodiments, the migration module 1102 is further configured to, in the case of migration failure, select one memory from the second memory set as the second memory according to the integrated access latency.

[0189] In some embodiments, the connection mode of the at least one memory and the processor comprises one or more of the following modes: direct connection, connection through a compute express link (CXL), and connection through a CXL switch chip.

[0190] In the case of implementing the functions of the above integrated modules in the form of hardware, the embodiments of the present application provide a structural diagram of a computing device, which can be the above data migration apparatus. As shown in the figure, the computing device 1200 comprises a processor 1202, a communication interface 1203, and a bus 1204. Optionally, the computing device can further comprise a memory 1201. Figure 12

[0191] The processor 1202 can be various exemplary logical blocks, modules and circuits described in combination with the disclosure of the embodiments of the present application. The processor 1202 can be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in combination with the disclosure of the embodiments of the present application. The processor 1202 can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0192] The communication interface 1203 is used to connect with other devices through a communication network. The communication network can be an Ethernet, a wireless access network, a wireless local area network (WLAN), etc.

[0193] ​The memory 1201 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to this.

[0194] As a possible implementation, the memory 1201 can exist independently of the processor 1202, and the memory 1201 can be connected to the processor 1202 through the bus 1204 for storing instructions or program codes. When the processor 1202 invokes and executes the instructions or program codes stored in the memory 1201, the data migration method provided by the embodiments of the present application can be implemented.

[0195] In another possible implementation, the memory 1201 can also be integrated with the processor 1202.

[0196] The bus 1204 can be an extended industry standard architecture (EISA) bus or the like. The bus 1204 can be divided into an address bus, a data bus, a control bus, and the like. For the sake of brevity and conciseness, Figure 12 In the above description, only one thick line is used to represent the bus, but it does not mean that there is only one bus or only one type of bus.

[0197] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the above division of functional modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the data migration device is divided into different functional modules to complete all or part of the above described functions.

[0198] The embodiments of the present application further provide a computer readable storage medium. All or part of the processes in the above method embodiments can be directed by computer instructions to complete by relevant hardware, and the program can be stored in the computer readable storage medium. When the program is executed, the program can include the processes of the above method embodiments. The computer readable storage medium can be the memory of any of the above embodiments. The computer readable storage medium can also be an external storage device of the data migration device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. Further, the computer readable storage medium can include both the internal storage unit of the data migration device and the external storage device. The computer readable storage medium is used to store the computer program and other programs and data required by the data migration device. The computer readable storage medium can also be used to temporarily store data that has been output or will be output.

[0199] The embodiments of the present application further provide a computer program product, which contains a computer program, and when the computer program product runs on a computer, the computer executes any one of the data migration methods provided in the above embodiments.

[0200] Although the present application is described herein in conjunction with various embodiments, it is understood that other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from an inspection of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and the indefinite articles "a" or "an" do not exclude a plurality. A single processor or other unit can fulfill the functions of several means recited in the claims. Means-plus-function claims are expressed by the functions that they perform. Means-plus-function claims are synonymous with "step-plus-function" claims.

[0201] Although the present application is described herein in conjunction with specific features and embodiments thereof, it is understood that modifications and combinations can occur to those skilled in the art to which the present application pertains, within its spirit and scope. Accordingly, the description and drawings are to be regarded as illustrative in nature and are to be construed only as exemplary of the application as defined by the appended claims. Obviously, many modifications and changes are possible in the practice of the present application, which are intended to be subsumed under the scope of the application. Moreover, it should be noted that the use of the word only in the claims gives rise to a specific claim depending from an independent claim to which the word only appears. Therefore, the application is not to be limited to the specific details of the embodiments shown and described.

[0202] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical scope disclosed by the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data migration method, characterized by, The application is applied to a first processor, the first processor is one of a plurality of processors included in a computing device, each processor in the plurality of processors is connected to at least one memory; The first memory accessed by the first processor includes to-be-migrated data; the method comprises: In response to a data migration instruction, determining a second memory from a data migration mapping table; the data migration mapping table includes a memory set corresponding to the first memory, the second memory is one of the memory set, the memory set corresponding to the first memory is obtained based on comprehensive access latencies of each memory, the comprehensive access latency of each memory is determined according to a real access latency of the first processor to the memory and an equivalent access latency of the first processor to the memory, and the equivalent access latency is used to indicate a performance loss when the first processor accesses the memory; Migrating the to-be-migrated data from the first memory to the second memory.

2. The method of claim 1, wherein, The data migration mapping table is stored in a memory of the computing device; In response to the data migration instruction, determining a second memory from a data migration mapping table comprises: In response to the data migration instruction, obtaining the data migration mapping table from the memory; Determining the second memory from the data migration mapping table.

3. The method of claim 1, wherein, After responding to the data migration instruction, the method further comprises: Obtaining a memory latency table, the memory latency table including the comprehensive access latencies of the first processor to the memories; Based on the memory latency table and the size ordering of the comprehensive access latencies of the memories, obtaining the data migration mapping table.

4. The method of claim 1, wherein, After responding to the data migration instruction, the method further comprises: Based on a memory relationship mapping table, obtaining a memory latency table; the memory relationship mapping table including connection modes between each processor in the plurality of processors and the memory connected thereto; the memory relationship mapping table being determined based on memory information of the memories; the memory latency table including the comprehensive access latencies of the first processor to the memories; Based on the memory latency table and the size ordering of the comprehensive access latencies of the memories, obtaining the data migration mapping table.

5. The method of claim 1, wherein, After responding to the data migration instruction, the method further comprises: Obtaining memory information of the memories; Based on the memory information, obtaining a memory relationship mapping table; the memory relationship mapping table including connection modes between each processor in the plurality of processors and the memory connected thereto; Based on the memory relationship mapping table, obtaining a memory latency table; the memory latency table including the comprehensive access latencies of the first processor to the memories; Based on the memory latency table and the size ordering of the comprehensive access latencies of the memories, obtaining the data migration mapping table.

6. The method of claim 1, wherein, The comprehensive access latency of each memory in the data migration mapping table satisfies: T_total = T_equal + T_real Wherein, T_total represents the comprehensive access latency, T_real represents the real access latency, and T_equal represents the equivalent access latency.

7. The method of claim 6, wherein, The equivalent access latency satisfies: T_equal = α × T_remote When the memory is connected to the first processor, the alpha is a first value; when the memory is connected to a second processor, the alpha is a second value; the second processor is one of the plurality of processors other than the first processor; the second value is greater than the first value; the T_remote represents a delay conversion coefficient corresponding to a performance loss of the first processor when accessing the memory in the case that the memory is connected to the second processor.

8. The method according to any one of claims 1 to 7, characterized in that, The data migration instruction includes a first data migration direction; the first data migration direction is used to indicate a migration direction of hot data. The second memory is determined from the data migration mapping table, including: A first memory set corresponding to the first memory in the first data migration direction is determined from the data migration mapping table; the comprehensive access latency of each memory in the first memory set is less than the comprehensive access latency of the first memory; A target memory in the first memory set is taken as the second memory, and the comprehensive access latency of the target memory is less than the comprehensive access latency of other memories in the first memory set.

9. The method of claim 8, wherein, After the to-be-migrated data is migrated from the first memory to the second memory, the method further includes: In the case of migration failure, a next memory of the target memory in the first memory set is taken as the second memory in the order of comprehensive access latency from small to large.

10. The method according to any one of claims 1 to 7, characterized in that, The data migration instruction includes a second data migration direction; the second data migration direction is used to indicate a migration direction of cold data. The second memory is determined from the data migration mapping table, including: A second memory set corresponding to the first memory in the second data migration direction is determined from the data migration mapping table; the comprehensive access latency of each memory in the second memory set is greater than the comprehensive access latency of the first memory; One memory in the second memory set is taken as the second memory.

11. The method of claim 1, wherein The connection mode of the at least one memory and the processor includes one or more of the following modes: direct connection, connection through a compute express link (CXL), and connection through a CXL switch chip.

12. A computing device, comprising: A computing device includes a plurality of processors, each of which is connected to at least one memory, a first processor is one of the plurality of processors, and a first memory accessed by the first processor includes to-be-migrated data; the first processor is configured to: In response to a data migration instruction, a second memory is determined from a data migration mapping table; the data migration mapping table includes a memory set corresponding to the first memory, the second memory is one of the memory set, the memory set corresponding to the first memory is obtained based on comprehensive access latencies of the memories, the comprehensive access latency of each memory is determined according to a real access latency of the first processor to the memory and an equivalent access latency of the first processor to the memory, and the equivalent access latency is used to indicate a performance loss of the first processor when accessing the memory; The to-be-migrated data is migrated from the first memory to the second memory.

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