Optimization method of micro-nano optoelectronic devices and on-chip mode division multiplexing / demultiplexing device

Abstract

The present invention discloses an optimization method for micro-nano optoelectronic devices and an on-chip mode division multiplexer / demultiplexer, comprising the following steps: establishing an initial simulation model of the device and calculating the quality factor value of the entire simulation model at that time; selecting a movable vertex of the initial polygon as a search point, and calculating the quality factor value each time the position of the search point is changed; searching for the position of the search point that optimizes the quality factor value; maintaining the position of the search point at the position that optimizes the quality factor value, searching for the next search point, and searching all search points once until the optimal position is reached as one iteration; repeating the iteration until the set performance index is achieved. This optimization method has a high optimization speed, can save a large amount of computing time and computing resources; has shape search capability, does not require a detailed initial structure, and can optimize the size of existing mode division multiplexers / demultiplexers.

Description

Technical Field

[0001] The present invention relates to the technical field of micro-nano optoelectronic devices, and in particular to an optimization method for micro-nano optoelectronic devices and an on-chip mode division multiplexer / demultiplexer. Background Art

[0002] With the development of human society, the amount of information generated and needed by people in their daily lives and production is growing exponentially. How to efficiently transmit and process this information has become a pressing issue for humanity. Due to the advantages of photonic communication such as low latency, large bandwidth, and low loss, "optical interconnection" technology is considered a very promising high-speed communication solution, and it can apply advanced photon multiplexing technology to further increase capacity. At the same time, technologies such as "optical communication" and "optical computing" are also widely used in the fields of front-end transmission and reception and back-end processing of human information. In order to meet the needs of low energy consumption, small footprint, and high mobility, optical interconnection, optical communication, and optical computing systems are gradually moving towards miniaturization (ultimately reaching chip-level size) and large-scale integration.

[0003] The realization of large-scale integrated optical interconnection, optical communication, and optical computing technologies on a chip cannot be achieved without various optoelectronic devices, especially micro-nano optoelectronic devices. At present, a large number of academic studies have reported on many micro-nano optoelectronic devices designed based on traditional methods. Since these devices, especially multifunctional or systematic devices, usually require tens or hundreds of μm 2 Although they can achieve certain results, they are difficult to use for large-scale on-chip integration and are therefore less adaptable to future trends in optical interconnect technology. Besides requiring a small footprint, each device must also have the lowest possible insertion loss and crosstalk, which are also essential for dense on-chip integration of micro- and nano-optoelectronic devices.

[0004] The large size of micro-nano optoelectronic devices designed using traditional methods stems from the fact that, when designing such devices, traditional methods often begin by designing an initial structure based on a regular waveguide based on experience and relevant theoretical knowledge. The design is then refined by sweeping certain parameters or analyzing semi-analytical models. Because physical processes suitable for analytical analysis often require a large-scale operating space, these devices are generally large. Furthermore, devices designed using this approach have a very small variable parameter space, significantly limiting their design freedom. As mentioned earlier, this is a serious drawback for large-scale on-chip integration.

[0005] A multitude of intelligent design algorithms have emerged, many of which have been applied to the design of micro-nano optoelectronic devices. Compared with traditional methods, intelligent algorithm design offers advantages such as a simple and intuitive design process, a large degree of parameter freedom, and a low theoretical threshold. Commonly used algorithms for designing micro-nano optoelectronic devices include genetic algorithms (GAs), particle swarm optimization (PSOs), direct binary search (DBS), and adjoint methods (AMs). However, these algorithms also have some shortcomings. For example, when optimizing a device, GAs and PSOs often require an initial structure and parameters to be optimized (typically shape parameters such as length, width, height, angles, and spacing). These parameters are then optimized using algorithms to find the parameter value combination that satisfies the optimization objective. This means that the optimization process of genetic algorithms and particle swarm optimization algorithms is actually searching for the best among a series of devices with "similar but different shapes (such as rectangles with different aspect ratios)", so their freedom of choice is relatively small. In addition, since the optimization process of genetic algorithms is not very targeted, the time and computational cost of optimization are relatively high. The direct binary search algorithm does not need to give an initial structure when designing a device, but only needs to give an optimization area. It can find the optimal structure by "flipping" each "pixel" in the optimization area. Its optimization process is actually searching for the best in a large "device shape set" (which can be compared to a photo set). However, it also faces problems such as the huge shape set leading to high computational cost of optimization, easy local convergence, and difficulty in training neural networks.

[0006] Because a large-scale integrated chip may require a large number of devices, the time and computational cost of designing each device must be carefully considered. Both design time and computational cost must be kept within reasonable limits, otherwise many integration goals will be unattainable.

[0007] Furthermore, as a high-speed communication solution, the bandwidth of optical interconnect technology is a highly sought-after parameter. In recent decades, various multiplexing technologies, such as wavelength division multiplexing (WDM) and space division multiplexing (SDM), have emerged. These technologies have significantly expanded the bandwidth of optical interconnects to support the rapidly growing demand for optically transmitted information. Furthermore, optical mode division multiplexing (MDM) has also gained increasing attention in recent years. Mode division multiplexing involves multiplexing different modes of light onto a single multimode fiber, few-mode fiber, or bus waveguide for transmission, and demultiplexing the modes into their respective signals at the receiving end. This technology leverages the principle that different modes of light do not interfere with each other, allowing multiple signals to be transmitted simultaneously within the same information channel. In recent years, silicon-based integrated mode division multiplexing (MDM) systems based on silicon-on-insulator (SOI) have attracted widespread attention due to their small size, compatibility with CMOS manufacturing processes, and scalability to established wavelength division multiplexing (WDM) systems. Summary of the Invention

[0008] The present invention provides an optimization method for micro-nano optoelectronic devices and an on-chip mode division multiplexer / demultiplexer to solve the following technical problems: 1. The optimization algorithms currently used for designing micro-nano optoelectronic devices generally have high computational costs and long optimization times; 2. The algorithms are prone to local convergence; 3. The optimization degrees of freedom of the algorithms are inappropriate, being either too large or too small; and 4. The existing mode division multiplexers are too large, making them unsuitable for large-scale on-chip integration.

[0009] According to one aspect of the present invention, a method for optimizing a micro-nano optoelectronic device is provided, comprising the following steps:

[0010] S1. Establish basic simulation elements such as a substrate and other non-designed components such as an optical communication waveguide in the simulation software. Set a design region on the xy plane with the bottom plane of the optical communication waveguide as the xy plane, and set an initial polygon with N vertices in the design region.

[0011] S2. Using the initial polygon as the base and the designed height as the height, a polygonal prism is defined in the simulation software. The polygonal prism is connected to the optical communication waveguide and filled with the material of the device to be optimized. The quality factor of the entire simulation model is calculated at this time.

[0012] S3. Select a movable vertex of the initial polygon as a search point, change the position of the search point in the xy plane, generate a new polygon shape each time the position of the search point is changed, and calculate the quality factor value once;

[0013] S4. Searching for the position of the search point that makes the quality factor value optimal, and determining the shape of the polygon that makes the quality factor value optimal at this time;

[0014] S5. Keep the search point at the position that makes the quality factor value optimal, and repeat S3 and S4 for the next search point until all search points have been searched and the optimal position is reached, which is one iteration.

[0015] S6. Repeat the iteration until the set number of iterations is reached or the quality factor value of the entire simulation model reaches the target indicator.

[0016] Furthermore, step S4 specifically includes the steps of:

[0017] S41, record the quality factor values ​​corresponding to the search point in S3 at W different search positions;

[0018] S42, fitting a variation pattern of the quality factor values ​​on the straight line connected by the search positions;

[0019] S43, finding the search position A that maximizes the quality factor value, then finding the function that has the fastest quality factor change at search position A among all functions passing through search position A, then moving the search point from search position A in a direction where the quality factor becomes better, and then randomly moving forward a distance to search position B, and calculating the quality factor value corresponding to B;

[0020] S44, comparing the quality factor values ​​corresponding to the search position A and the search position B, and determining the search point position as the position with the better quality factor value;

[0021] S45. Determine the shape of the polygon that optimizes the quality factor value at this time.

[0022] Furthermore, step S42 specifically includes the following steps: when a straight line is formed by connecting M search positions, the variation pattern of the quality factor values ​​between the M positions on the straight line is represented by an M-1 function, where M≤W.

[0023] Furthermore, step S45 specifically includes the steps of connecting all vertices of the polygon in sequence, and then connecting them end to end, and the polygons generated by the intersection of the connecting lines and other polygons are regarded as different parts of the same polygon.

[0024] Furthermore, the optical communication waveguide includes a communication bus and a plurality of single-mode channels; the quality factor value is the sum of the transmittance of each single-mode channel.

[0025] Furthermore, the height of the optical communication waveguide is 220nm, and there are four single-mode channels; the size of the design area is 4.5μm×4.5μm, the initial polygon is a seventy-eight-gon, the design height of the polygonal prism is 220nm, and the filling material of the polygonal prism is silicon; the initial polygon includes ten fixed vertices and sixty-eight movable vertices, the ten fixed vertices are divided into five groups, two in each group, which are used to connect the communication bus and four single-mode channels respectively, and each search point changes position four times, and each position change moves 50nm.

[0026] The present invention has the following beneficial effects:

[0027] 1. Fast optimization speed, which can save a lot of computing time and computing resources;

[0028] 2. It has the ability to search for shapes without the need for a detailed initial structure;

[0029] 3. The degree of freedom of optimization is moderate, smaller than that of DBS algorithm, but larger than that of genetic algorithm and particle swarm optimization;

[0030] 4. Compared with the DBS algorithm, it is less likely to converge locally;

[0031] 5. It has a wide range of applications and is not affected by the device material, dimension, function, and surrounding materials. It is only responsible for optimizing the shape of the polygon. Therefore, any other material that can be used in micro-nano optical devices can use this algorithm to design functional devices.

[0032] 6. The on-chip mode division multiplexer / demultiplexer designed by the optimization method of this embodiment is smaller than the smallest TE0~TE3 fourth-order mode division multiplexer / demultiplexer reported so far, which largely solves the disadvantage of being too large in size that devices designed by traditional design methods generally have.

[0033] According to another aspect of the present invention, an on-chip mode division multiplexer / demultiplexer is also provided, which is obtained by the above-mentioned optimization method of micro-nano optoelectronic devices. The on-chip mode division multiplexer / demultiplexer includes a substrate and a top silicon structure arranged on the substrate, the top silicon structure includes an optical communication waveguide and a polygonal prism device for mode beam splitting multiplexing / demultiplexing, the optical communication waveguide includes a communication bus and multiple single-mode channels, the TE0 mode input by each of the single-mode channels is converted into one of TE0 mode, TE1 mode, TE2 mode or TE3 mode by the polygonal prism device, and output from the communication bus; each of the TE0 mode, TE1 mode, TE2 mode or TE3 mode input by the communication bus is converted into TE0 mode by the polygonal prism device, and output from different single-mode channels.

[0034] Furthermore, the communication bus and the single-mode channel are respectively provided at both ends of the polygonal prism device, there are four single-mode channels, and the communication bus transmits four modes: TE0 mode, TE1 mode, TE2 mode and TE3 mode.

[0035] Furthermore, the width of the optical communication waveguide is 0.5 μm to 2 μm.

[0036] Furthermore, the width of the communication bus is 2 μm, and the width of the single-mode channel is 0.5 μm.

[0037] The present invention has the following beneficial effects:

[0038] The on-chip mode division multiplexer / demultiplexer provided by the present invention has a compact structure and is smaller than the currently reported smallest TE0-TE3 fourth-order mode division multiplexer / demultiplexer, which is conducive to large-scale intensive integration of on-chip micro-nano optoelectronic devices.

[0039] In addition to the above-described objects, features and advantages, the present invention has other objects, features and advantages. The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0041] Figure 1 It is a flowchart of a preferred embodiment of the present invention;

[0042] Figure 2 is a schematic structural diagram of an initial polygon according to a preferred embodiment of the present invention;

[0043] Figure 3 Schematic diagram of the fitting principle of the quality factor value change law on a certain straight line in a preferred embodiment of the present invention;

[0044] Figure 4 is a global schematic diagram of the principle of searching for the maximum position of a search point according to a preferred embodiment of the present invention;

[0045] Figure 5 It is a partial schematic diagram of the principle of searching for the maximum position of a search point according to a preferred embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of a structure in which a polygon is generated due to the intersection of connecting lines in a preferred embodiment of the present invention;

[0047] Figure 7 This is the initial structural intention of the on-chip mode demultiplexer of the preferred embodiment of the present invention;

[0048] Figure 8 Schematic diagram of the original position, search position, three straight lines and their relative positions in a preferred embodiment of the present invention;

[0049] Figure 9 1 is a schematic structural diagram of an analog-to-analog demultiplexer according to a preferred embodiment of the present invention;

[0050] Figure 10 Schematic diagram of the control principle of the polygonal prism device according to the preferred embodiment of the present invention;

[0051] Figure 11 1 is a schematic structural diagram of the internal structure of a polygonal prism device according to a preferred embodiment of the present invention;

[0052] Figure 12 These are simulation results of the four modes TE0 to TE3 passing through the analog demultiplexer according to the preferred embodiment of the present invention. DETAILED DESCRIPTION

[0053] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in many different ways as defined and covered below.

[0054] like Figure 1 As shown, the optimization method for micro-nano optoelectronic devices provided in this embodiment is named "polygon search algorithm" herein, and specifically includes the following steps:

[0055] S1. First, establish a basic simulation model and the initial polygon corresponding to the device to be optimized in the simulation software. Figure 2 As shown, the initial polygon is the blank area surrounded by black dots and the solid lines connecting them; the design area is the black dotted rectangle; and the fixed structure is the black filled area, including the communication bus and the single-mode channel.

[0056] A simulation model typically includes a substrate, an optical communication waveguide, a design region, and other elements required for running the simulation. In this embodiment, the simulation software establishes an SOI structure and its associated optical communication waveguide. A design region is defined on the xy plane, with the top silicon bottom plane of the SOI as the xy plane. The initial polygon corresponding to the device to be optimized is an N-vertex polygon set within the design region. Other elements required for running the simulation include a light source, a monitor, and a computation region.

[0057] Optionally, to ensure light transmittance, several sides of the polygon may be selected to coincide with the optical communication waveguide, and the positions of the vertices that coincide with the optical communication waveguide are fixed.

[0058] S2. Determine a polygonal prism in the simulation software with the polygon as the base and the design height as the height; fill the polygonal prism with the material of the device to be designed, and calculate the figure of merit (FOM) value of the entire simulation model through the software.

[0059] When designing silicon-based optoelectronic devices based on silicon on insulators, the height of the polygonal prism is the thickness of the standard SOI wafer top silicon, that is, 220nm, and the filling material of the polygonal prism is silicon; when the polygonal prism is set, the polygonal prism and the set substrate, optical communication waveguide, and other elements required for running the simulation together constitute a simulation model. After that, no matter how the corresponding polygonal shape changes, the height of the polygonal prism remains unchanged and is always filled with this material. Similarly, for micro-nano optical devices based on other materials, the design height and filling material are adjusted accordingly. Other materials can be lithium niobate, germanium antimony telluride (Ge2Sb2Te5, GST), germanium antimony selenide telluride (Ge2Sb2Se4Te, GSST) and other materials used in micro-nano optical devices.

[0060] FOM is a parameter that measures the degree to which a designed device achieves its target indicators and is set by the designer based on the design goals.

[0061] S3. Select the first movable vertex of the polygon as the search point, change the position of this search point in the "xy" plane, and change it W times; each time the position of the search point is changed, calculate the FOM value using the simulation software.

[0062] When changing the position, the changed position should be kept very close to the initial position of the point at the beginning of this step.

[0063] Optionally, the search point changes position along the X-axis or Y-axis. For example, it moves 50nm in the positive / negative direction of the x-axis and 50nm in the positive / negative direction of the y-axis. The moving distance can also be 20nm, 30nm, 40nm, 60nm, 70nm, or a length value randomly generated by the computer, as long as the search point is within the design area to meet the size requirements of the device to be designed. Every time the point moves to a new position, it will cause the polygon to produce a new shape, that is, a device with a new shape will be generated. The new FOM value corresponding to this device with a new shape can be calculated using simulation software. Therefore, each position of the point in the "xy" plane has a corresponding FOM value.

[0064] Alternatively, each vertex of the polygon can be completely transplanted into a one-dimensional or three-dimensional parameter space.

[0065] S4. For the search point, the position of the vertex that makes the FOM value optimal is searched by a set method, and the shape of the polygon that makes the FOM value optimal at this time can be determined.

[0066] S5. Maintain the search point at the position that optimizes the FOM value, and repeat S3 and S4 for the next search point until all search points have been searched and the optimal position is reached, which is one iteration.

[0067] S6. Repeat the iteration until the set number of iterations X is reached or the FOM value of the entire simulation model reaches the target indicator.

[0068] like Figure 3 、 Figure 4 and Figure 5 As shown, in this embodiment, the method of searching for the position of the vertex that makes the FOM value optimal in S4 includes the following steps:

[0069] S41. First, record the FOM values ​​corresponding to the search point in S3 at W different search positions.

[0070] S42. Use a polynomial function to fit the variation pattern of the FOM value on the straight line connected by these search positions.

[0071] After searching W different positions of the search point, a total of W+1 FOM values ​​(including the initial FOM when it is not moved) can be obtained through simulation. These W+1 FOM values ​​can be used to fit the change pattern of the FOM values ​​on at least one straight line, and can be used to fit the change pattern of the FOM values ​​on at most (W+1)*W / 2 straight lines.

[0072] Since these search positions are close to each other, the variation of FOM between these search positions can be approximated by a low-order polynomial function. That is, if a straight line is formed by connecting two search positions, then the variation of the FOM value between the two positions on the straight line can be approximated by a linear function; if a straight line is formed by connecting three search positions, then the variation of the FOM value between the three positions on the straight line can be approximated by a quadratic function. Since an n-order function requires at least n+1 non-overlapping points to determine (for example, the expression of a linear function requires at least 2 non-overlapping points to determine, a quadratic function requires at least 3, a cubic function requires at least 4, and so on), if a straight line is formed by connecting M search positions, the variation of the quality factor value between these M positions on the straight line is represented by an M-1-order function, where M≤W.

[0073] Schematic diagram of the principle Figure 3As shown in the figure, the horizontal axis of the black dot (state X) represents the coordinate of the search point on a certain straight line before and after it moves on the straight line (here the straight line is taken as the x-axis, that is, the search point moves on the x-axis), and the vertical axis represents the value of the FOM function obtained by simulation when the search point is at the coordinate; the black solid line in the figure represents the FOM value (corresponding to the vertical axis in the figure) obtained by simulation of the overall model when the search point is at a certain position on the straight line (corresponding to the horizontal axis in the figure), that is, the actual change of the FOM value on the straight line, and the black dotted line is the fitting of the change of the FOM value on the straight line (that is, the black solid line); Figure 3 (a) The left side is a linear function fitting, Figure 3 (b) is the quadratic function fitting.

[0074] S43. Find the search position A that maximizes the FOM value. Then find the function that has the fastest FOM change (the largest absolute slope) at A among all functions passing through A. Then, start the search point from A and move it a random distance in the direction of increasing FOM to the search position B. Calculate the FOM value corresponding to B and compare it with the FOM value corresponding to A.

[0075] Figure 4 Schematic diagram of the principles of S41, S42, and S43, where the undulating surface represents the FOM value corresponding to the device of the new shape generated by the search point at each position in the "xy plane" when the positions of other vertices remain unchanged. Figure 5 for Figure 4 A partial enlarged view, in which the horizontal, vertical and vertical coordinates are Figure 4 Consistent, P1, P2, P3, and P4 are four search positions.

[0076] In this embodiment, the optimization goal is set to increase FOM, so the search point starts from A and moves in the direction of increasing FOM; it can be understood that if the optimization goal is to reduce FOM, the search point starts from the search position that minimizes FOM and moves in the direction of reducing FOM.

[0077] S44. If the FOM value corresponding to B is greater than the FOM value corresponding to A, the search point position is determined to be B; otherwise, the search point position is determined to be position A.

[0078] Optionally, the values ​​of the number of vertices N of the polygon, the number of moves W of the search point, and the number of iterations X are manually selected by the designer.

[0079] like Figure 6As shown, set N vertices within the design area, connect these vertices sequentially, and then connect them end to end. The polygons enclosed by these lines have one and only one case: the polygons generated by the intersection of the lines and the other polygons are considered different parts of the same polygon. For example, the sum of the three parts Z1, Z2, and Z3 in the figure is considered to be a single polygon. It can be understood that whether the sum of the three parts Z1, Z2, and Z3 is considered to be a single polygon or three polygons is irrelevant to the algorithm itself.

[0080] Optionally, FOM is the figure of merit of the designed device, which is determined based on the specific optimization goal. In this embodiment, FOM is set to be the sum of the transmittances of different optical communication waveguides. A larger FOM value indicates a higher proportion of the four modes of light output from the four corresponding channels, which means lower insertion loss and better mode separation.

[0081] The polygon search algorithm, an optimization method for designing micro-nano optoelectronic devices proposed in this embodiment, has the following advantages:

[0082] 1. Fast optimization speed, which can save a lot of computing time and computing resources;

[0083] 2. It has the ability to search for shapes without the need for a detailed initial structure;

[0084] 3. The degree of freedom of optimization is moderate, smaller than that of DBS algorithm, but larger than that of genetic algorithm and particle swarm optimization;

[0085] 4. Compared with the DBS algorithm, it is less likely to converge locally;

[0086] 5. It has a wide range of applications and is not affected by the device material, dimension, function, and surrounding materials. It is only responsible for optimizing the shape of the polygon. Therefore, any other material that can be used in micro-nano optical devices can use this algorithm to design functional devices.

[0087] 6. The on-chip mode division multiplexer / demultiplexer designed by the optimization method of this embodiment is smaller than the smallest TE0~TE3 fourth-order mode division multiplexer / demultiplexer reported so far, which largely solves the disadvantage of being too large in size that devices designed by traditional design methods generally have.

[0088] The present invention also provides an on-chip mode division multiplexer / demultiplexer, which is obtained by the above-mentioned optimization method of micro-nano optoelectronic devices. This device is a two-dimensional on-chip micro-nano optoelectronic device based on silicon on insulator - TE0~TE3 fourth-order mode division multiplexer / demultiplexer.

[0089] like Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 12 As shown, the on-chip mode division multiplexing / demultiplexing device provided by the present invention includes a substrate and a top silicon structure provided on the substrate, the top silicon structure includes an optical communication waveguide and a polygonal prism device for mode division multiplexing / demultiplexing, the optical communication waveguide includes a communication bus and multiple single-mode channels,

[0090] When the polygonal prism is used for mode demultiplexing, the TE0 mode inputted by each single-mode channel is converted into one of the TE0 mode, TE1 mode, TE2 mode or TE3 mode by the polygonal prism device and outputted from the communication bus;

[0091] When the polygonal prism is used for mode demultiplexing, each of the TE0, TE1, TE2, or TE3 modes input from the communication bus is converted to TE0 mode by the polygonal prism device and output from different single-mode channels. In this embodiment, single-mode channels 1-4 are arranged sequentially from top to bottom. The basic principle is that when the TE0 mode enters the device from the communication bus, it will be emitted from single-mode channel 4 as the TE0 mode. When the TE1 mode enters the device from the communication bus, it will be emitted from single-mode channel 3 as the TE0 mode. When the TE2 mode enters the device from the communication bus, it will be emitted from single-mode channel 2 as the TE0 mode. When the TE3 mode enters the device from the communication bus, it will be emitted from single-mode channel 1 as the TE0 mode. Based on the principle of "optical path reversibility," when the TE0 mode enters single-mode channels 1-4, it will be converted into TE3-TE0 modes within the device and output from the communication bus, at this point, the device becomes a fourth-order mode division multiplexer.

[0092] The on-chip mode demultiplexer provided by the present invention is obtained by the following steps:

[0093] 1. Create a standard SOI structure and an optical communication waveguide in conjunction with an on-chip mode demultiplexer in the simulation software. The optical communication waveguide height is the standard SOI top silicon height of 220nm. A 4.5μm x 4.5μm square design region is defined within the "xy plane," with the SOI top silicon bottom plane as the "xy plane." A 78-vertex polygon is created within the design region. To optimize light transmission efficiency, five sides of this polygon are chosen to coincide with the optical communication waveguide (10 vertices are fixed). Different light modes have different requirements for the transmission waveguide width. Higher-order modes require a larger minimum supported width. The minimum supported width for TE0 is approximately 0.4μm, and for TE3 is approximately 2μm. To ensure ultra-compactness, the optical communication waveguide width is chosen to be close to the minimum supported width for the corresponding mode. The communication bus width is 2μm, and the single-mode channel width is 0.5μm. This completes the basic simulation model and the initial polygon corresponding to the device to be optimized.

[0094] like Figure 7As shown, the initial seventy-eight-gon is a blank area surrounded by seventy-eight black dots and solid lines connecting them. The seventy-eight black dots include ten fixed vertices and sixty-eight movable vertices. The ten fixed vertices are divided into five groups, two in each group, which are used to connect the right end of the communication bus and the left ends of the four single-mode channels respectively; the design area is a black dotted rectangle; the optical communication waveguide is a black filled area, including the communication bus, single-mode channel 1, single-mode channel 2, single-mode channel 3 and single-mode channel 4.

[0095] 2. Using the 78-gon as the base and a height of 220 nm, create a 78-gon prism in the simulation software. Fill the 78-gon prism with silicon. The simulation software is set to ensure that the height of the 78-gon prism remains constant and the silicon material remains constant, regardless of how the 78-gon changes shape. The software then calculates the FOM value for the entire simulation model.

[0096] 3. Select the first search point Q of the 78-gon ( Figure 7 (The point in the dotted circle) changes the position of Q in the xy plane four times. It moves 50 nm to the left of its original position (negative x-axis), then 50 nm to the right (positive x-axis), then 50 nm above its original position (positive y-axis), and finally 50 nm below its original position (negative y-axis). Each time the vertex changes position, the corresponding FOM value is calculated using simulation software.

[0097] 4. The position of Q that optimizes the FOM value is searched by the aforementioned polygon search algorithm, thereby determining the shape of the 78-gon that optimizes the FOM value under the condition of "only Q moving".

[0098] Here, an example is used to illustrate the implementation process of the search method.

[0099] set up:

[0100]

[0101] in Indicates that when TE0 mode is incident, single-mode channel 4 ( Figure 7 (described in), It represents the light transmittance of single-mode channel 3 when TE1 mode is incident. It represents the light transmittance of single-mode channel 2 when TE2 mode is incident. Indicates the light transmittance of single-mode channel 1 when the TE3 mode is incident. A larger FOM value indicates a higher proportion of the four modes of light output from the four corresponding channels, indicating lower insertion loss and better mode separation.

[0102] like Figure 8 As shown in the figure, if the maximum FOM value is obtained when Q is moved to a position 50 nm above the original position, then this search position is set to A. There are three straight lines passing through A: L1, which connects A and a position 50 nm to the left of the original position; L2, which connects A and a position 50 nm to the right of the original position; and L3, which connects A and a position 50 nm below the original position.

[0103] Perform function fitting on the changes in the FOM values ​​between the search positions on these three lines. Perform a linear function fit on the FOM values ​​on the L1 and L2 paths (to obtain a straight line), and perform a quadratic function fit on the FOM value on the L3 path (to obtain a quadratic function curve). Calculate the slopes of these three lines at A and find the line with the largest slope at A.

[0104] Next, let Q start at A and move randomly along the line with the highest slope, moving a certain distance in the direction of increasing slope, to reach B. At this point, a new 78-gon is obtained. The FOM value corresponding to B is calculated using simulation software. If the FOM value corresponding to B is greater than that corresponding to A, Q's position is determined to be B; otherwise, Q's position is determined to be A.

[0105] Optionally, let Q take A as the starting point and move randomly a certain distance in the direction of increasing slope along the straight line with the largest slope to reach B. The random movement method here does not affect the basic idea and specific implementation of this algorithm. The distance can be set to the same as the previous movement distance, that is, 50nm; it can also be set to be different from the previous movement distance, such as 20nm, 30nm, 40nm, 60nm, 70nm, or a length randomly generated by the computer to ensure that the search point is within the design area to meet the size requirements of the device to be designed.

[0106] 5. Keep Q at the position that maximizes the FOM value, and repeat steps 3 and 4 for the next vertex Q+1 until all vertices have been searched for the optimal position.

[0107] 6. Select the first search point Q again and repeat steps 3, 4, and 5 until each vertex has been searched several times or the FOM value converges.

[0108] The final polygon structure is as follows Figure 9 As shown in (a), the final polygonal structure is the gray polygon within the design area frame; the optical communication waveguide is the black rectangle outside the design area frame, including the communication bus and four single-mode channels. The structure of the on-chip mode demultiplexer is shown in Figure 9 As shown in (b), the design area in the figure is a black dotted rectangle; the structure of the polyhedral device is the black polygon within the design area box; the optical communication waveguide is the black rectangle outside the design area box, including the communication bus and four single-mode channels.

[0109] like Figure 10 、 Figure 11 As shown in Figure 1, each mode in a waveguide corresponds to a light propagation mode. Taking the mode division multiplexer / demultiplexer as an example, when a mode (TE n When light is transmitted through a communication bus, it propagates in a fixed manner to the entrance of the mode demultiplexer. Once this light enters the mode demultiplexer's polygonal prism device, its propagation pattern undergoes a dramatic change due to a sudden change in the width of the waveguide cross-section perpendicular to the light's propagation direction. Due to the internal structure (the internal structure refers to the air region completely surrounded by silicon material) and the edge structure (the edge region of the polygonal prism device), different portions of this light beam undergo multiple reflections and refractions at different locations within the device. Simultaneously, the internal and external structures of the polygonal prism device guide the propagation direction of the light. Within the polygonal prism device, different portions of this light beam overlap and influence each other, ultimately emitting from the pre-set exit as the TE0 mode. This complex process is accomplished in a remarkably short time within the device's compact design. The TE0 light beams emitted from different ports then continue propagating along subsequent TE0 mode channels.

[0110] The simulation results of the four modes TE0 to TE3 through the on-chip mode division multiplexing / demultiplexing device are as follows Figure 12 As shown, Figure 12 (a) shows the ratio of the transmittance of the output light of the four single-mode channels (all output light is TE0 mode light) after the TE0 mode passes through the bus and enters the mode demultiplexer. The transmittance of the light in single-mode channel 4 is much greater than the transmittance of the light in single-mode channels 1, 2, and 3. Figure 12 (b) shows the ratio of the transmittance of the output light of the four single-mode channels after the TE1 mode passes through the bus and enters the mode demultiplexer. The transmittance of the light in single-mode channel 3 is much greater than the transmittance of the light in single-mode channel 1, single-mode channel 2, and single-mode channel 4. Figure 12 (c) shows the ratio of the transmittance of the output light of the four single-mode channels after the TE2 mode passes through the bus and enters the mode demultiplexer. The transmittance of the light in single-mode channel 2 is much greater than the transmittance of the light in single-mode channel 1, single-mode channel 3, and single-mode channel 4. Figure 12 (d) shows the ratio of the transmittance of the output light of the four single-mode channels after the TE3 mode passes through the bus and enters the mode demultiplexer. The transmittance of the light in single-mode channel 1 is much greater than the transmittance of the light in single-mode channels 2, 3, and 4.

[0111] Figure 12The simulation results of the TE0-TE3 fourth-order mode division multiplexer / demultiplexer designed using the "polygon search algorithm" are shown. The FOM is set as the sum of the transmittances of the corresponding single-mode channels after TE0, TE1, TE2, and TE3 enter the device at the 1550nm band. From the results, it can be seen that the TE0-TE3 fourth-order mode division multiplexer / demultiplexer of this embodiment is applicable to the 1530nm-1560nm band and can achieve a very efficient mode division multiplexing effect.

[0112] The latest similar results Zhou H, Wang Y, Gao X, et al. Dielectric Metasurfaces Enabled Ultradensely Integrated Multidimensional Optical System[J]. Laser&PhotonicsReviews, 2022(16-4) are devices designed using the DBS algorithm. It is the smallest TE0~TE3 fourth-order mode division multiplexer / demultiplexer reported so far.

[0113] The comparison of several key indicators of this embodiment with the latest similar results is as follows:

[0114] Table 1 Comparison of several main indicators of this embodiment and the latest similar results

[0115]

[0116] As can be seen from the comparison in Table 1, when the performance of the two devices is similar, the polygon search algorithm requires far fewer calculations than the DBS algorithm, indicating that the polygon search algorithm has a very obvious speed advantage in designing this device. The polygonal prism device used for mode beam splitting multiplexing / demultiplexing of the TE0-TE3 fourth-order mode division multiplexer / demultiplexer of this embodiment has dimensions of 3.83 μm × 4.5 μm. The smallest reported quadrangular prism used for mode division multiplexing / demultiplexing of the TE0-TE3 fourth-order mode division multiplexer / demultiplexer has dimensions of 4.8 μm × 4.8 μm. When using optical communication waveguides of the same size, the on-chip ultra-compact TE0-TE3 fourth-order mode division multiplexer / demultiplexer provided by this embodiment has a smaller size and a more compact structure, which is conducive to the large-scale and dense integration of on-chip micro-nano optoelectronic devices.

[0117] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for optimizing micro-nano optoelectronic devices, characterized in that: The following steps are involved: S1. Establish a substrate and an optical communication waveguide for use in the simulation software, use the bottom plane of the optical communication waveguide as the xy plane, set a design area on the xy plane, and set an initial polygon with N vertices in the design area; S2. Using the initial polygon as the base and the designed height as the height, a polygonal prism is defined in the simulation software. The polygonal prism is connected to the optical communication waveguide and filled with the material of the device to be optimized. The quality factor of the entire simulation model is calculated at this time. S3. Select a movable vertex of the initial polygon as a search point, change the position of the search point in the xy plane, generate a new polygon shape each time the position of the search point is changed, and calculate the quality factor value once; S4. Searching for the position of the search point that makes the quality factor value optimal, and determining the shape of the polygon that makes the quality factor value optimal at this time; S5. Keep the search point at the position that makes the quality factor value optimal, repeat S3 and S4 for the next search point, and all search points are searched once for the optimal position, which is considered one iteration; S6. Repeat the iteration until the set number of iterations is reached or the quality factor value of the entire simulation model reaches the target indicator.

2. The method for optimizing micro-nano optoelectronic devices according to claim 1, characterized in that: The step S4 specifically includes the following steps: S41, record the quality factor values ​​corresponding to the search point in S3 at W different search positions; S42, fitting a variation pattern of the quality factor values ​​on the straight line connected by the search positions; S43, finding the search position A that maximizes the quality factor value, then finding the function that has the fastest quality factor change at search position A among all functions that pass through search position A, then moving the search point from search position A in a direction where the quality factor becomes better, and then randomly moving forward a distance to search position B, and calculating the quality factor value corresponding to B; S44, comparing the quality factor values ​​corresponding to the search position A and the search position B, and determining the search point position as the position with the better quality factor value; S45. Determine the shape of the polygon that optimizes the quality factor value at this time.

3. The method for optimizing micro-nano optoelectronic devices according to claim 2, characterized in that: The step S42 specifically includes the following steps: A straight line is formed by connecting M search positions, and the variation pattern of the quality factor values ​​between the M positions on the straight line is represented by an M-1 function, where M≤W.

4. The method for optimizing micro-nano optoelectronic devices according to claim 2, wherein: The step S45 specifically includes the following steps: Connect all the vertices of the polygon in sequence, and then connect them end to end. The polygons generated by the intersection of the connecting lines are regarded as different parts of the same polygon as other polygons.

5. The method for optimizing a micro-nano optoelectronic device according to any one of claims 1 to 4, characterized in that: The optical communication waveguide includes a communication bus and multiple single-mode channels; the quality factor value is the sum of the transmittance of each single-mode channel.

6. The method for optimizing micro-nano optoelectronic devices according to claim 5, characterized in that: The height of the optical communication waveguide is 220 nm, and there are four single-mode channels; The size of the designed area is 4.5 μm×4.5 μm, the initial polygon is a 78-gon, the designed height of the polygonal prism is 220 nm, and the filling material of the polygonal prism is silicon; The initial polygon includes ten fixed vertices and sixty-eight movable vertices. The ten fixed vertices are divided into five groups, two in each group, which are used to connect the communication bus and four single-mode channels respectively. Each search point changes its position four times, and each time the position changes, it moves 50nm.

7. An on-chip mode division multiplexer / demultiplexer, characterized in that: Obtained by the optimization method of the micro-nano optoelectronic device according to any one of claims 1 to 6, The on-chip mode division multiplexing / demultiplexing device includes a substrate and a top silicon structure provided on the substrate, wherein the top silicon structure includes an optical communication waveguide and a polygonal prism device for mode division multiplexing / demultiplexing, wherein the optical communication waveguide includes a communication bus and a plurality of single-mode channels. The TE0 mode input by each of the single-mode channels is converted into one of the TE0 mode, TE1 mode, TE2 mode or TE3 mode by the polygonal prism device and output from the communication bus; Each of the TE0 mode, TE1 mode, TE2 mode or TE3 mode input by the communication bus is converted into the TE0 mode by the polygonal prism device and output from different single-mode channels respectively.

8. The on-chip mode division multiplexer / demultiplexer according to claim 7, characterized in that: The communication bus and the single-mode channels are respectively arranged at two ends of the polygonal prism device. There are four single-mode channels. The communication bus transmits four modes: TE0 mode, TE1 mode, TE2 mode and TE3 mode.

9. The on-chip mode division multiplexer / demultiplexer according to claim 7, characterized in that: The width of the optical communication waveguide is 0.5 μm to 2 μm.

10. The on-chip mode division multiplexer / demultiplexer according to claim 9, characterized in that: The width of the communication bus is 2 μm, and the width of the single-mode channel is 0.5 μm.

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