Buried power rail for scaling vertical transport field effect transistor

Abstract

A semiconductor structure can include a buried power rail below a bottom source drain of a vertical transistor and a dielectric bilayer below the bottom source drain. The dielectric bilayer can be between the buried power rail and the bottom source drain. The semiconductor structure can include a silicon germanium bilayer below the bottom source drain, which can be adjacent to the buried power rail. The semiconductor structure can include a buried power rail contact. The buried power rail contact can connect the bottom source drain to the buried power rail. The dielectric bilayer can include a first dielectric layer and a dielectric liner. The first dielectric layer can be in direct contact with the bottom source drain. The dielectric liner can surround the buried power rail. The silicon germanium bilayer can include a first semiconductor layer and a second semiconductor layer below the first semiconductor layer.

Description

Technical Field

[0001] This invention generally relates to semiconductor structures and methods of forming them. More specifically, this invention relates to a semiconductor structure including a buried power rail for an extremely miniaturized vertical transfer field-effect transistor (VTFET). Background Technology

[0002] The ongoing goal of building semiconductor devices is to create smaller, more densely packed devices with significant computing power. When designing semiconductor devices, each cell requires a power input (Vdd) and a ground (Vss) connection. To power the various components, each cell is also coupled to a power rail, which is electrically connected to the cell's active layer to provide the input power (Vdd). In some instances, multiple power rails may be provided for each cell to provide the input power (Vdd) and ground (Vss) separately. Summary of the Invention

[0003] According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a buried power rail below the bottom source and drain of a vertical transistor and a dielectric double layer below the bottom source and drain. The dielectric double layer may be located between the buried power rail and the bottom source and drain. The semiconductor structure may include a silicon-germanium double layer below the bottom source and drain, which may be adjacent to the buried power rail. The buried power rail may be made of tungsten or ruthenium. The semiconductor structure may include buried power rail contacts. The buried power rail contacts may connect the bottom source and drain to the buried power rail. The dielectric double layer may include a first dielectric layer and a dielectric pad. The first dielectric layer may be in direct contact with the bottom source and drain. The dielectric pad may surround the buried power rail. The dielectric pad may isolate the buried power rail from the dielectric double layer. The silicon-germanium double layer may include a first semiconductor layer and a second semiconductor layer below the first semiconductor layer. The second semiconductor layer may be in direct contact with the first semiconductor layer. The first semiconductor layer may include 30% germanium, and the second semiconductor layer may include 60% germanium. The semiconductor structure may include a third semiconductor layer. The third semiconductor layer may be located directly below the bottom source and drain. The third semiconductor layer may be made of silicon. The semiconductor structure may also include a top source and drain, fins, and a metal gate. The fins may be located between the top and bottom source and drain. The metal gate may be adjacent to and in direct contact with the fins.

[0004] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include a buried power rail below the bottom source / drain of a vertical transistor, a dielectric double layer below the bottom source / drain, and buried power rail contacts. The dielectric double layer may be located between the buried power rail and the bottom source / drain. The buried power rail contacts may connect the bottom source / drain to the buried power rail. The buried power rail may be made of tungsten or ruthenium. The dielectric double layer may include a first dielectric layer and a dielectric pad. The first dielectric layer may be in direct contact with the bottom source / drain. The dielectric pad may surround the buried power rail. The semiconductor structure may include a top source / drain, a fin, and a metal gate. The fin may be located between the top source / drain and the bottom source / drain. The metal gate may be adjacent to and in direct contact with the fin. The semiconductor structure may include a semiconductor layer. The semiconductor layer may be located directly below the bottom source / drain. The semiconductor layer may be made of silicon.

[0005] According to another embodiment of the present invention, a method is provided. The method may include epitaxially growing a silicon-germanium bilayer on a substrate, epitaxially growing a third semiconductor layer on the silicon-germanium bilayer, and forming one or more vertical fins and one or more bottom source / drain electrodes within the third semiconductor layer. The one or more bottom source / drain electrodes may be located below the one or more vertical fins. The method may include laterally etching a portion of the silicon-germanium bilayer and the third semiconductor layer to form one or more first recesses, and forming a first dielectric layer within the one or more recesses. The first dielectric layer may be located directly below the one or more bottom source / drain electrodes. The method may include laterally etching a portion of the first semiconductor layer to form one or more second recesses, depositing a dielectric pad within the one or more second recesses, and forming one or more buried power rails within the one or more second recesses. The one or more buried power rails may be located directly below the one or more bottom source / drain electrodes. The dielectric pad may separate the one or more buried power rails from the first dielectric layer. The silicon-germanium bilayer may include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer may include 30% germanium, and the second semiconductor layer may include 60% germanium. The third semiconductor layer may be made of silicon. The method may include forming shallow trench isolation between one or more vertical fins and forming one or more bottom source-drain contacts. The one or more bottom source-drain contacts can connect the one or more bottom source-drains to one or more buried power rails. The shallow trench isolation may extend through a third semiconductor layer, a silicon-germanium bilayer, and a portion of the substrate. The method may also include forming one or more top source-drains on top of one or more fins, forming a metal gate between one or more fins, forming one or more top source-drain contacts, and forming one or more gate contacts. Attached Figure Description

[0006] The following detailed description will be best understood in conjunction with the accompanying drawings, which are given by way of example and are not intended to limit the invention thereto, in which:

[0007] Figure 1 This is a cross-sectional view showing a first semiconductor layer and a second semiconductor layer arranged on a substrate according to an embodiment;

[0008] Figure 2 This is a cross-sectional view showing a vertical fin with a bottom source and drain according to an embodiment;

[0009] Figure 3 This is a cross-sectional view showing the organic planarization layer and sidewall spacers according to an embodiment;

[0010] Figure 4 This is a cross-sectional view showing a first recess formed by recessing a first semiconductor layer and a second semiconductor layer according to an embodiment;

[0011] Figure 5 This is a cross-sectional view showing the first dielectric layer below the bottom source and drain according to an embodiment;

[0012] Figure 6 This is a cross-sectional view showing the recessed first semiconductor layer according to an embodiment;

[0013] Figure 7 This is a cross-sectional view showing a dielectric pad conformally deposited on the top surface of the structure according to an embodiment;

[0014] Figure 8 This is a cross-sectional view showing the second embedded power rail directly below the bottom source and drain according to an embodiment;

[0015] Figure 9 This is a cross-sectional view showing the grooves between the vertical fins according to an embodiment;

[0016] Figure 10 This is a cross-sectional view showing shallow groove isolation between vertical fins according to an embodiment;

[0017] Figure 11 This is a cross-sectional view showing the top source / drain and metal gate according to an embodiment;

[0018] Figure 12 This is a cross-sectional view showing the bottom source-drain contact, top source-drain contact, and gate contact according to an embodiment;

[0019] Figure 13 This is a cross-sectional view showing the grooves between the vertical fins according to an embodiment;

[0020] Figure 14 This is a cross-sectional view showing the pad along the sidewall of the bottom source and drain according to an embodiment;

[0021] Figure 15 This is a cross-sectional view showing a structure according to an embodiment with the first semiconductor layer and the second semiconductor layer removed; and

[0022] Figure 16 This is a cross-sectional view showing a structure according to an embodiment having a buried power rail, bottom source-drain contacts, top source-drain contacts, and gate contacts; and

[0023] Figure 17 This is a top view showing a vertical transmission field-effect transistor with its corresponding embedded power rail according to an embodiment.

[0024] The accompanying drawings are not necessarily to scale. They are merely schematic representations and not intended to depict specific parameters of the invention. The drawings are intended to illustrate only typical embodiments of the invention. In the drawings, the same reference numerals denote the same elements. Detailed Implementation

[0025] This document discloses detailed embodiments of the claimed structures and methods; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which can be implemented in various forms. The invention can be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0026] For the purposes described below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall apply to the disclosed structures and methods, as oriented as shown in the accompanying drawings. The terms “cover,” “on top,” “on…,” or “on top” indicate that a first element (e.g., a first structure) is present on a second element (e.g., a second structure), wherein an intermediate element (e.g., an interface structure) may be present between the first and second elements. The term “direct contact” refers to the connection of the first element (e.g., the first structure) and the second element (e.g., the second structure) at the interface between the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0027] To avoid obscuring the presentation of embodiments of the invention, some processing steps or operations known in the art may be combined for presentation and illustrative purposes in the following detailed description, and may not be described in detail in some instances. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses more on the distinguishing features or elements of various embodiments of the invention.

[0028] Embodiments of the present invention generally relate to semiconductor structures and methods of forming thereof. More specifically, the present invention relates to a semiconductor structure including a buried power rail for an extremely miniaturized vertical transfer field-effect transistor (VTFET).

[0029] Power rails are used in circuits to supply current to devices. Traditionally, power rails can be stacked on top of devices or buried between devices. Buried power rails are typically formed in shallow trench isolation (STI) regions between transistors. Currently, with the rapid shrinking of cell sizes, more transistors are being manufactured on the same or even smaller footprint. As a result, the space for STIs is also shrinking. Burying power rails in STI regions does not allow the buried power to have sufficient size to carry current. Therefore, there is a need for a method of constructing and manufacturing power rails that not only supplies current to an increasing number of transistors but also fits within a reduced footprint.

[0030] Embodiments of the present invention provide a structure and method for manufacturing a power rail that is embedded directly beneath the active region of a transistor, thus eliminating limitations on the scaling of the occupied area. Furthermore, the position of the resulting embedded power rail allows the bottom source and drain electrodes to contact the embedded power rail within the active region, thereby saving space within the occupied area.

[0031] Figures 1-17 A method for fabricating an embedded power rail directly below the active region of a transistor is shown. Figure 13 and Figure 16 The resulting structure of a vertical transistor with embedded power rails is shown.

[0032] Now for reference Figure 1 The diagram illustrates a structure 100 according to an embodiment. Structure 100 may include a substrate 102, a first semiconductor layer 104, a second semiconductor layer 106, a third semiconductor layer 108, and a hard mask layer 110. Non-limiting examples of suitable substrate 102 materials may include Si (silicon), strained Si, Ge (germanium), SiGe (silicon-germanium), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)) or any combination thereof.

[0033] A first semiconductor layer 104 is epitaxially grown on a substrate 102. Then, a second semiconductor layer 106 is epitaxially grown on the top surface of the first semiconductor layer 104. The first semiconductor layer 104 and the second semiconductor layer 106 are epitaxially grown using an epitaxial growth process (e.g., molecular beam epitaxy (MBE)). Other methods can also be used to grow the first semiconductor layer 104 and the second semiconductor layer 106, such as rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), and atmospheric pressure chemical vapor deposition (APCVD). The first semiconductor layer 104 can be grown to a thickness between 30 nm and 200 nm. The second semiconductor layer 106 can be grown to a thickness between 5 nm and 20 nm. The first semiconductor layer 104 and the second semiconductor layer 106 can be made of silicon-germanium. The percentage of germanium in the first semiconductor layer 104 can be approximately 30%. The percentage of germanium in the second semiconductor layer 106 can be approximately 60%. The first semiconductor layer 104 and the second semiconductor layer 106 can be collectively referred to as a silicon-germanium bilayer or a semiconductor bilayer.

[0034] The third semiconductor layer 108 is epitaxially grown on the top surface of the second semiconductor layer 106. The third semiconductor layer 108 can be grown using similar techniques used to grow the first semiconductor layer 104 or the second semiconductor layer 106. The third semiconductor layer 108 can be epitaxially grown to a thickness between 60 nm and 150 nm. The third semiconductor layer 108 can be made of silicon.

[0035] A hard mask layer 110 is deposited on the top surface of the third semiconductor layer 108. The hard mask layer 110 may comprise any dielectric material, such as silicon dioxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the hard mask layer 110 may be formed using conventional deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In other embodiments, the hard mask layer 110 may be formed using a thermal growth process, such as thermal oxidation. In other embodiments, the hard mask layer 110 may be formed using a combination of deposition and thermal growth processes. The hard mask layer 110 may have a thickness ranging from about 10 nm to about 150 nm. Other thicknesses of the hard mask layer 110 are possible and can be used in this application.

[0036] Now for reference Figure 2The diagram illustrates a structure 100 with vertical fins 112 and bottom source / drain electrodes 116 according to an embodiment. After a hard mask layer 110 is formed on the top surface of a third semiconductor layer 108, the hard mask layer 110 and the third semiconductor layer 108 are patterned (not shown). Patterning can be performed by photolithography and etching. The patterning of the hard mask layer 110 and the third semiconductor layer 108 results in the formation of a hard mask cap 114 and fins 112. Each fin 112 includes a pair of vertical sidewalls that are parallel or substantially parallel to each other. While two fins 112 are described and illustrated, a single fin 112 or multiple fins 112 can be formed. Each fin 112 can have a vertical height ranging from about 20 nm to about 150 nm, a width ranging from 5 nm to 30 nm, and a length ranging from 20 nm to 300 nm. Other vertical heights and / or widths and / or lengths smaller or larger than the ranges mentioned herein may also be used in this application.

[0037] Once the fin 112 is patterned, the bottom source / drain 116 can be epitaxially grown using known techniques, so that the bottom source / drain 116 is formed directly below the fin 112. The bottom source / drain 116 can be in-situ doped with p-type or n-type dopant to form a p-type or n-type bottom source / drain for a VTFET. For example, the bottom source / drain 116 can be made of silicon-germanium and in-situ doped with a p-type dopant (e.g., boron) to form a p-type bottom source / drain 116a. The bottom source / drain 116 can be made of silicon and in-situ doped with an n-type dopant (e.g., phosphorus) to form an n-type bottom source / drain 116b.

[0038] Now for reference Figure 3 The embodiment illustrates a structure 100 having a first organic planarization layer (OPL) 118 and sidewall spacers 120. The first OPL 118 is first deposited on the top surface of the structure 100 such that the top surface of the first OPL 118 extends above the top surface of the hard mask cap 114. The first OPL 118 can be deposited using known deposition techniques (e.g., spin coating).

[0039] After the first OPL 118 is deposited, it can be etched using photolithographic patterning and dry etching processes (e.g., reactive ion etching) to expose the top of the third semiconductor layer 108. The top portion of the third semiconductor layer 108 lies below the bottom surface of the bottom source / drain 116. A spacer layer (not shown) is then conformally deposited on the top surface of the structure 100. The spacer layer may include an insulating material, such as silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of materials for the spacer layer may include dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxide nitrides, or any combination thereof. The spacer layer can be deposited using deposition processes such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The thickness of the spacer layer can range from about 3 to about 15 nm, or from about 5 to about 8 nm.

[0040] Once conformally deposited, the spacer layer is then etched back to form sidewall spacers 120. To form the sidewall spacers 120, the spacer layer can be etched using a dry etching process (e.g., reactive ion etching), such that portions of the spacer layer remain on the sidewalls of the bottom source / drain 116 and the first OPL 118. The sidewall spacers 120 protect the sidewalls of the bottom source / drain 116 and the first OPL 118 from damage during subsequent manufacturing processes.

[0041] After forming the sidewall spacers 120, another etching process that selectively (without substantially removing) the sidewall spacers 120 or the first OPL 118 can be used to further recess portions of the third semiconductor layer 108, the second semiconductor layer 106, and the first semiconductor layer 104. For example, the etching process could be a reactive ion etching process. Recessing portions of the third semiconductor layer 108, the second semiconductor layer 106, and the first semiconductor layer 104 exposes the sidewalls of the three layers directly beneath the sidewall spacers 120.

[0042] Now for reference Figure 4The diagram illustrates a structure 100 with a first recess 122 according to an embodiment. The first recess 122 is formed first using an etching process that selectively (without substantially removing) removes a second semiconductor layer 106 relative to the first semiconductor layer 104 and the third semiconductor layer 108. A portion of the second semiconductor layer 106 can be laterally removed at an appropriate temperature using an etching process such as dry etching with HCl vapor. As a result, a portion of the second semiconductor layer 106 located directly below the bottom source / drain electrode 116 is removed. Furthermore, another etching process (e.g., an isotropic etching process) is used to laterally etch the top of the first semiconductor layer 104 and a portion of the third semiconductor layer 108, such that the recess 122 is very close to the bottom source / drain electrode 116. The formed first recess 122 extends vertically from the bottom surface of the bottom source / drain electrode 116 to the exposed top portion of the first semiconductor layer 104.

[0043] Now for reference Figure 5 This illustrates a structure 100 according to an embodiment, having a first dielectric layer 124 below the bottom source / drain electrodes 116. Dielectric material can be deposited onto the top surface of the structure 100 using plasma-enhanced atomic layer deposition. During deposition, Figure 4 The recess 122 described herein is filled with a dielectric material. The dielectric material may be silicon nitride. The dielectric material is then etched using an isotropic etching process to form a first dielectric layer 124. The first dielectric layer 124 is below and in direct contact with the bottom source / drain electrode 116.

[0044] Now for reference Figure 6 The diagram illustrates a structure 100 in which a portion of the first semiconductor layer 104 is removed according to an embodiment. Once the first dielectric layer 124 is formed, a selective silicon-germanium 30% etching process is performed to laterally remove a portion of the first semiconductor layer 104, thereby forming a second recess 126. The exposed sidewalls of the first semiconductor layer 104 are substantially flush with the sidewalls of the second conductor layer 106 and the third semiconductor layer 108. As a result, the bottom surface of the first dielectric layer 124 is exposed. The second recess 126 extends laterally for approximately the same length as the first dielectric layer 124.

[0045] Now for reference Figure 7The diagram illustrates a structure 100 with a dielectric pad 128 according to an embodiment. After the second recess 126 is formed, the first OPL 118 is removed, thereby exposing the fin 112 and the hard mask cap 114. The first OPL 118 can be removed from the structure 100 using any material removal process (e.g., ashing). Once the first OPL 118 is removed, the dielectric pad 128 is conformally deposited on the top surface of the structure 100. Any deposition technique (e.g., atomic layer deposition) can be used to deposit the dielectric pad 128. The dielectric pad 128 can be made of an insulating material, such as silicon oxide. The dielectric pad 128 can be thin enough not to pinch the second recess 126. For example, the dielectric pad 128 can have a thickness ranging from about 3 nm to about 8 nm. The dielectric pad 128 and the first dielectric layer 124 can be collectively referred to as a dielectric bilayer.

[0046] Now for reference Figure 8 This illustrates a structure 100 according to an embodiment, having a buried power rail 130 directly below the bottom source / drain 116. Once the dielectric pad 128 is conformally deposited onto the top surface of the structure 100, a metal layer (not shown) is deposited onto the structure 100. The metal layer may fill the vertical fins 112 and the second recess 126 below the first dielectric layer 124. Figures 6-7 All spaces between (shown in the image). The metal layer can be a tungsten metal layer, a ruthenium metal layer, or a cobalt metal layer.

[0047] Then, CMP and etching processes (e.g., reactive ion etching) are used to planarize and recess the metal layer to form the buried power rail 130. The buried power rail 130 is formed in the second recess 126 (e.g., Figure 7 The embedded power rail 130 extends within and above the top surface of the first dielectric layer 124. The embedded power rail 130 is surrounded by a dielectric pad 128. The dielectric pad 128 separates the embedded power rail 130 from the adjacent silicon-germanium bilayer.

[0048] Now for reference Figure 9 The diagram illustrates a structure 100 with grooves 134 between vertical fins 112 according to an embodiment. A second organic planarization layer (OPL) 132 is deposited on the top surface of the structure 100. The second OPL 132 may be made of substantially the same material as the first OPL 118. The second OPL 132 protects the structure 100 from damage during subsequent manufacturing processes.

[0049] After the second OPL 132 is deposited, an etching process (such as reactive ion etching) can be used to remove the portion of the OPL 132 between the two vertical fins 112. Furthermore, the etching process removes portions of the dielectric pad 128, the bottom source / drain 116, the third semiconductor layer 108, the second semiconductor layer 106, and the first semiconductor layer 104 between the two vertical fins, thereby forming a trench 134. The trench 134 extends vertically from the top surface of the dielectric pad 128 to the exposed top surface of the substrate 102.

[0050] Now for reference Figure 10 The diagram illustrates a structure 100 with shallow trench isolation (STI) 136 between vertical fins 112 according to an embodiment. Trench 134 is filled with a dielectric material to form the STI 136. The STI 136 may be made of an oxide material, such as silicon oxide. The STI 136 is in the form of a dielectric plug that separates the two fins 112 such that a current applied to one fin has no effect on the second fin. The top surface of the STI 136 may be substantially flush with the top surface of the bottom source / drain 116. Typically, the STI 136 extends through a third semiconductor layer 108, a second semiconductor layer 106, and a first semiconductor layer 104. The STI 136 also extends through a portion of the substrate 102 to a depth that allows for electrical separation of the two fins.

[0051] Oxide material is also deposited on the sides of fin 112, above the embedded power rail 130, thereby forming a second dielectric layer 138. After STI 136 is formed, the second OPL 132 is removed, thereby exposing fin 112 and hard mask cap 114. The second OPL 132 can be removed from structure 100 using any material removal process (e.g., ashing).

[0052] Now for reference Figure 11 A structure 100 having a metal gate 142, a top source / drain 146, and an interlayer dielectric (ILD) 148 is shown according to an embodiment. Once the STI 136 is formed between the two fins 112, the structure 100 undergoes additional fabrication processes known in the art to form the bottom spacer 140, the metal gate 142, the top spacer 144, the top source / drain 146, and the ILD 148. The bottom spacer 140 and the top spacer 144 may comprise dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxide nitrides, or any combination thereof. The bottom spacer 140 and the top spacer 144 are formed by a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The bottom spacer 140 and the top spacer 144 may have a thickness of about 3 to about 15 nm or about 5 to about 10 nm.

[0053] The metal gate 142 may include a gate dielectric material, a work function metal, and a metal gate. The gate dielectric material may include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, high-k dielectrics (such as hafnium oxide), or any combination thereof. The work function metal includes p-type and n-type work function metal materials. P-type work function materials include components such as ruthenium, palladium, platinum, cobalt, nickel, titanium nitride, titanium aluminum carbide, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminum compounds, titanium nitride, titanium aluminum carbide, or any combination thereof. The metal gate may be made of a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The metal gate 142 can be deposited by appropriate deposition processes, such as atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, electroplating, thermal or electron beam evaporation, and sputtering.

[0054] After the metal gate 142 is formed, an ILD 148 is deposited on structure 100. The ILD 148 can be formed from, for example, a low-k dielectric material (k < 4.0), including but not limited to silicon oxide, spin-coated glass, flowable oxide, high-density plasma oxide, borosilicate glass (BPSG), or any combination thereof. The ILD 148 is deposited using deposition processes, including but not limited to chemical vapor deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, evaporation, chemical solution deposition, or similar processes. To form the top source / drain 146, the hard mask cap 114 is first removed. The hard mask cap 114 can be removed using any material removal process, such as chemical mechanical polishing followed by selective SiN removal. Once the hard mask cap 114 is removed, exposing the top surface of the third semiconductor layer 108, the top source / drain 146 is epitaxially grown from the exposed top surface of the third semiconductor layer 108. The top source / drain 146 can be doped with the same type of dopant as the bottom source / drain 116.

[0055] Now for reference Figure 12The diagram illustrates a structure 100 according to an embodiment, having a bottom source / drain contact 150, a top source / drain contact 152, and a gate contact 154. The bottom source / drain contact 150 extends from the bottom portion of the ILD 148, through the bottom source / drain 116, the first dielectric layer, and the dielectric pad 128 to reach the buried power rail 130. The bottom source / drain contact 150 is formed within a contact trench. To form the contact trench, a resist, such as a photoresist, can be deposited and patterned. The patterned resist can be used as an etching mask to perform an etching process (e.g., reactive ion etching) to remove portions of the ILD 148, the bottom source / drain 116, the first dielectric layer, and the dielectric pad 128 until the buried power rail 130 is exposed. The contact trenches are then filled with a conductive material, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), cobalt (Co), ruthenium (Ru), or any combination thereof. The conductive material can be deposited using a suitable deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, electroplating, thermal or electron beam evaporation, or sputtering. An etching process is then used to recess the conductive material to form the bottom source-drain contacts 150. The recessed portions of the contact trenches are then filled with ILD 148 using known deposition techniques.

[0056] In addition to the bottom source-drain contact 150, structure 100 undergoes further manufacturing processes to form the top source-drain contact 152 and the gate contact 154. The top source-drain contact 152 and the gate contact 154 are formed in substantially the same manner as the bottom source-drain contact 150. The top source-drain contact 152 extends through ILD 148 to reach the top source-drain 146. The gate contact 154 extends through ILD 148 to reach the metal gate 142.

[0057] like Figure 12 As shown, the resulting structure 100 includes two VTFETs separated by an STI 136. The VTFET on the left is a p-type FET, while the VTFET on the right is an n-type FET. Furthermore, each VTFET includes a buried power rail 130. The buried power rail 130 is located directly below the VTFET. Additionally, the buried power rail 130 is connected to the bottom source / drain 116 via bottom source / drain contacts 150.

[0058] The following is a reference appendix. Figures 13-17 Another embodiment of a VTFET with a buried power line directly beneath it is described in detail. In this embodiment, the first semiconductor layer 104 and the second semiconductor layer 106 are completely removed, and the STI 136 spans the region between the two buried power lines 130.

[0059] Now for reference Figure 13This illustrates the deposition of a second OPL 132 (as described above regarding) according to an embodiment of the invention. Figure 9 Structure 200 is the intermediate manufacturing step following the (described above). Structure 200 is substantially similar in all respects to the above-mentioned reference. Figure 9 Structure 100 is described in detail; however, in this embodiment, structure 200 includes a trench 134 that does not extend into the substrate 102. From Figure 9 Starting with structure 100, a reactive ion etching process is performed to form a trench 134 between the two fins 112. The reactive ion etching process ends when the top surface of the third semiconductor layer 108 is exposed. As a result, the trench 134 extends from the top surface of the dielectric pad 128 to the top surface of the third semiconductor layer 108.

[0060] Now for reference Figure 14 The diagram illustrates a structure 200 with a second pad 156 on the sidewalls of a trench 134 according to an embodiment. By forming the trench 134, the sidewalls of the bottom source / drain 116 are exposed. The second pad 156 is then deposited onto the exposed sidewalls of the bottom source / drain 116. The second pad 156 may be made of substantially the same material as the material constituting the dielectric pad 128. The second pad 156 protects the bottom source / drain 116 from damage during subsequent manufacturing steps. The second pad 156 extends the entire length of the sidewalls of the trench 134.

[0061] Now for reference Figure 15 The diagram illustrates a structure 200 in which the first semiconductor layer 104 and the second semiconductor layer 106 are removed according to an embodiment. After the second pad 156 is deposited onto the sidewalls of the trench 134, a selective silicon-germanium etching process (e.g., vapor-phase HCl dry etching) is used to remove the first semiconductor layer 104 and the second semiconductor layer 106, thereby creating an opening 158 and exposing the top surface of the substrate 102. The etching process is selective for the substrate 102 (it is essentially not removed). The etching process does not remove or damage the bottom source / drain electrodes 116 because they are protected by the second pad 156.

[0062] After the first semiconductor layer 104 and the second semiconductor layer 106 are removed, the resulting opening 158 is then filled with an oxide material (e.g., silicon oxide) to create an STI 136. The STI 136 separates the two fins 112 and the two bottom source / drain electrodes 116 such that a current applied to one fin has no effect on the second fin. Typically, the STI 136 extends through a portion of the substrate 102 to a depth that allows for electrical separation of the two fins.

[0063] Now for reference Figure 16The diagram illustrates a structure 200 according to an embodiment, having an embedded power rail 130, a bottom source-drain contact 150, a top source-drain contact 152, and a gate contact 154. Once the STI 136 is formed, structure 200 undergoes the process described herein. Figures 10-12 The additional manufacturing process described.

[0064] like Figure 16 As shown, the resulting structure 200 includes two VTFETs spaced apart by an STI 136. In one embodiment, the two VTFETs may be of the same type, such as a p-type VTFET or an n-type VTFET. In an alternative embodiment, the VTFETs are of different types. For example, one VTFET is p-type and the other is n-type. Furthermore, the STI 136 extends vertically from the bottom surface of the bottom spacer 140 to the top surface of the substrate 102. The STI 136 extends laterally between the two buried power rails 130. Structure 200 is substantially similar to structure 100 because both structures include buried power rails 130 directly beneath the VTFETs. However, structure 100 includes portions of a first semiconductor layer 104 and a second semiconductor layer 106 located directly beneath the STI 136 and the bottom source / drain 116. It should be understood that even though two VTFETs and two buried power rails 130 are shown, embodiments of the invention contemplate forming multiple VTFETs and multiple buried power rails 130 on a single substrate wafer.

[0065] Now for reference Figure 17 The diagram illustrates a plurality of VTFETs and their corresponding buried power rails 130 according to an embodiment. The top two VTFETs are p-type VTFETs, while the bottom two VTFETs are n-type VTFETs. Furthermore, Figures 1-16 The diagram shows a cross-sectional view of fin 112 taken along section line XX, with the element boundaries represented by dashed lines. Figures 1-16 The boundary between structure 100 and structure 200 shown.

[0066] like Figure 17 As shown, the buried power rail 130 is formed directly beneath the VTFET. Unlike either the top of the VTFET or the STI 136 region between VTFETs, having a buried power rail 130 directly beneath the VTFET allows for the fabrication of more VTFETs within the same footprint. Furthermore, since the buried power rail 130 forms direct contact with the bottom source / drain 116, there is no need to form additional bottom source / drain contacts. This is advantageous because it does not increase the footprint.

[0067] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: Embedded power rails below the bottom source and drain of the vertical transistor; A dielectric double layer below the bottom source and drain, the dielectric double layer being between the embedded power rail and the bottom source and drain; The silicon-germanium double layer is located below the bottom source and drain electrodes, and the silicon-germanium double layer is adjacent to the embedded power rail; as well as Embedded power rail contacts connect the bottom source and drain terminals to the embedded power rail.

2. The semiconductor structure according to claim 1, wherein the dielectric double layer comprises: A first dielectric layer is in direct contact with the bottom source and drain electrodes. as well as A dielectric pad surrounding the embedded power rail.

3. The semiconductor structure according to claim 2, wherein the dielectric pad isolates the embedded power rail from the silicon-germanium double layer.

4. The semiconductor structure according to claim 1, wherein the silicon-germanium bilayer comprises: First semiconductor layer; as well as A second semiconductor layer is disposed above the first semiconductor layer, and the second semiconductor layer is in direct contact with the first semiconductor layer.

5. The semiconductor structure according to claim 4, wherein the first semiconductor layer comprises 30% germanium, and the second semiconductor layer comprises 60% germanium.

6. The semiconductor structure according to claim 1, further comprising: A third semiconductor layer, made of silicon, is located directly below the bottom source and drain electrodes.

7. The semiconductor structure according to claim 1, further comprising: Top source and drain; A fin, wherein the fin is located between the top source / drain and the bottom source / drain; as well as A metal gate, which is adjacent to and in direct contact with the fin.

8. The semiconductor structure according to claim 1, wherein the embedded power rail is made of tungsten or ruthenium.

9. A semiconductor structure, comprising: Embedded power rails below the bottom source and drain of the vertical transistor; A dielectric double layer below the bottom source and drain, the dielectric double layer being between the embedded power rail and the bottom source and drain; as well as Embedded power rail contacts connect the bottom source and drain terminals to the embedded power rail.

10. The semiconductor structure according to claim 9, wherein the dielectric double layer comprises: A first dielectric layer is in direct contact with the bottom source and drain electrodes. as well as A dielectric pad surrounding the embedded power rail.

11. The semiconductor structure according to claim 9, further comprising: Top source and drain; A fin, wherein the fin is located between the top source / drain and the bottom source / drain; as well as A metal gate, which is adjacent to and in direct contact with the fin.

12. The semiconductor structure according to claim 9, further comprising: A semiconductor layer, located directly below the bottom source and drain electrodes, is made of silicon.

13. The semiconductor structure of claim 9, wherein the embedded power rail is made of tungsten or ruthenium.

14. A method comprising: A silicon-germanium bilayer is epitaxially grown on a substrate, the silicon-germanium bilayer comprising a first semiconductor layer and a second semiconductor layer; A third semiconductor layer is epitaxially grown on the silicon-germanium bilayer; One or more vertical fins and one or more bottom source / drain electrodes are formed within the third semiconductor layer, the one or more bottom source / drain electrodes being below the one or more vertical fins; Laterally etch portions of the silicon-germanium bilayer and the third semiconductor layer to form one or more first recesses; A first dielectric layer is formed within the one or more recesses, the first dielectric layer being directly below the one or more bottom source and drain electrodes; A portion of the first semiconductor layer is etched laterally to form one or more second recesses; Deposit a dielectric liner within one or more of the second recesses; as well as One or more embedded power rails are formed within the one or more second recesses, the one or more embedded power rails being directly below the one or more bottom source and drain terminals.

15. The method of claim 14, wherein the dielectric pad separates the one or more embedded power rails from the first dielectric layer.

16. The method of claim 14, further comprising: Shallow grooves are formed between the one or more vertical fins for isolation; as well as One or more bottom source-drain contacts are formed, which connect the one or more bottom source-drain terminals to the one or more embedded power rails.

17. The method of claim 16, wherein the shallow trench isolation extends through a portion of the third semiconductor layer, the silicon-germanium bilayer, and the substrate.

18. The method of claim 14, further comprising: One or more top source / drain electrodes are formed on the top of the one or more fins; A metal gate is formed between the one or more fins; Form one or more top source-drain contacts; as well as Form one or more gate contacts.

19. The method of claim 14, wherein the first semiconductor layer comprises 30% germanium and the second semiconductor layer comprises 60% germanium.

20. The method of claim 14, wherein the third semiconductor layer is made of silicon.

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