A Schottky diode
By setting a cap layer and a second semiconductor layer in the Schottky diode and optimizing the electrode contact method, the problem of poor leakage current characteristics of traditional Schottky diodes in high-temperature environments is solved, and the reverse leakage current and conduction loss are reduced.
Patent Information
- Application Number
- CN202080107495.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-11-27
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2040-11-27
AI Technical Summary
Traditional Schottky diodes have poor leakage characteristics at high temperatures and it is difficult to balance the contradiction between forward turn-on voltage and reverse leakage current, resulting in insufficient performance.
A cap layer is set between the electrode and the heterostructure layer, and an activation region is formed by doping. Combined with a second semiconductor layer and a barrier layer, the electrode contact method is optimized, reducing the direct contact area and leakage current.
It effectively reduces the reverse leakage current of Schottky diodes, improves reverse withstand voltage, reduces conduction losses, and maintains good performance in high-temperature environments.
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Figure CN116529892B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and in particular to a Schottky diode. BACKGROUND
[0002] The Schottky diode is widely used due to its high switching frequency and low forward voltage drop, and gradually replaces silicon in high-power semiconductor devices. However, the performance of the traditional Schottky diode has obvious drawbacks: on the one hand, although the low work function Schottky anode can reduce the opening voltage, the reverse leakage current is large; on the other hand, although the high work function anode can reduce the off-state leakage current and increase the reverse voltage, it significantly increases the opening voltage and conduction loss. The anode layer of the current Schottky diode is directly formed on the heterostructure layer, which increases the leakage characteristics of the heterostructure layer in a high-temperature environment, and does not meet the actual demand.
[0003] In view of the above-mentioned drawbacks, it is urgent to provide a Schottky diode with low forward conduction loss and effective reverse cutoff. SUMMARY
[0004] The present application provides a Schottky diode to improve the reverse leakage and reduce the conduction loss.
[0005] According to a first aspect of the embodiments of the present application, a Schottky diode is provided, comprising:
[0006] a first semiconductor layer;
[0007] a heterostructure layer located on the first semiconductor layer;
[0008] a layer located on the heterostructure layer, the layer comprising at least a first region and a second region;
[0009] a passivation layer located on the layer, the passivation layer comprising a first recess and a second recess, the first recess and the second recess at least penetrating the passivation layer, the first recess corresponding to the first region;
[0010] a first electrode formed at the first recess, the first electrode being in contact with the first region and / or the first electrode being in contact with the heterostructure layer;
[0011] a second electrode located at the second recess.
[0012] Optionally, the layer comprises:
[0013] the layer is an intrinsic semiconductor layer; or
[0014] the layer is a P-type semiconductor layer, and the doping element is magnesium element; or
[0015] The overlayer is a co-doped semiconductor layer, wherein the co-doped elements include magnesium elements, silicon elements and / or germanium elements and / or oxygen elements.
[0016] Optionally, the Schottky diode further comprises a second semiconductor layer, which is located at the first recess and simultaneously on the first region and under the first electrode, and the second semiconductor layer does not fill the first recess in the horizontal direction.
[0017] Optionally, the second semiconductor layer is a p-type semiconductor layer, and the doping element is a magnesium element, and the doping concentration of the magnesium element is between 1E16 cm 3 -5E20 / cm 3 .
[0018] Optionally, the sidewall of the second semiconductor layer is not flush with the sidewall of the first electrode.
[0019] Optionally, the overlayer has a doping element, wherein the doping element content of the first region is higher than that of the second region.
[0020] Optionally, when the overlayer is a p-type semiconductor layer or a co-doped semiconductor layer, the doping concentration of the doping element of the overlayer is less than the doping element concentration of the second semiconductor layer.
[0021] Optionally, the first region of the overlayer is an active region.
[0022] Optionally, the first region comprises a third recess, the third recess penetrates through the overlayer and exposes the heterostructure layer, and the third recess is in communication with the first recess.
[0023] Optionally, a barrier layer can be further provided between the heterostructure layer and the overlayer.
[0024] Optionally, the Schottky diode further comprises a dielectric layer, which is at least located on the passivation layer and / or the sidewall of the first recess.
[0025] Optionally, the heterostructure layer at least comprises a channel layer and a barrier layer, and the heterostructure layer is composed of the channel layer and the barrier layer which are stacked one or more times in sequence.
[0026] Optionally, the first semiconductor layer is a nucleation layer and / or a buffer layer.
[0027] Optionally, the first semiconductor layer material and the second semiconductor layer material are group III nitrides.
[0028] Optionally, the Schottky diode further comprises a substrate, which is located below the first semiconductor layer.
[0029] The technical solutions provided by the embodiments of the present application can include the following beneficial effects:
[0030] (1) As known from one of the embodiments, the present application sets a bump layer between the electrode and the heterostructure layer, so that the electrode and the bump layer form a Schottky contact, avoiding the direct contact of the electrode and the heterostructure layer, thereby greatly reducing the reverse leakage of the device. Further, the bump layer is doped with a single element or multiple elements, and the doped element in the bump layer region under the electrode is activated, so that the hole concentration of the activated region is high, which is conducive to reducing the forward opening voltage of the device, thereby improving the performance of the device.
[0031] (2) As known from another embodiment, a second semiconductor layer is arranged below the electrode, and the second semiconductor layer is a P-type semiconductor layer, so that the first electrode and the second semiconductor layer form a Schottky contact, which can balance the reverse leakage. Further, when the bump layer has a third groove penetrating through the bump layer and exposing the heterostructure layer, the first electrode and the second semiconductor layer form a Schottky contact, and the first electrode also directly contacts the heterostructure layer to form an Ohmic contact. Such a structure is conducive to reducing the area of the direct contact of the first electrode and the heterostructure layer, and also reduces the reverse leakage caused by the Ohmic contact to the minimum. In this way, the contradiction between the forward opening voltage and the reverse leakage characteristics of the Schottky diode can be balanced, and the leakage characteristics of the heterostructure layer in a high-temperature environment can be suppressed. Through the mixed contact mode of the first electrode, the effect of significantly reducing the off-state leakage current and increasing the reverse withstand voltage is achieved, and the conduction loss is not increased.
[0032] (3) As known from other embodiments, by setting a barrier layer, in the subsequent process of growing other epitaxial layers at high temperature, the barrier layer is not easy to decompose at high temperature, so that the groove does not penetrate through the barrier layer, so that the depth of the groove is not lower than the barrier layer, and the etching depth of the groove is accurately controlled.
[0033] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS
[0034] The accompanying drawings, which are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application.
[0035] FIG. 1(a) is a structural schematic diagram of a Schottky diode according to Embodiment 1.
[0036] FIG. 1(b) is a structural schematic diagram of a Schottky diode according to Embodiment 4.
[0037] Fig. 2(a) is a structural schematic diagram of a Schottky diode according to Embodiment 5.
[0038] Fig. 2(b) is a structural schematic diagram of a Schottky diode according to Embodiment 6.
[0039] Figure 3 Fig. 2(c) is a structural schematic diagram of a Schottky diode according to Embodiment 7.
[0040] Figure 4 Fig. 2(d) is a structural schematic diagram of a Schottky diode according to Embodiment 8.
[0041] Figure 5 Fig. 2(e) is a structural schematic diagram of a Schottky diode according to Embodiment 9.
[0042] Figure 6 Fig. 3 is a flow chart of a manufacturing process of a Schottky diode according to an exemplary embodiment.
[0043] Figures 7(a) to 7(j) Fig. 4 is a corresponding intermediate structural schematic diagram of the flow according to Figure 6 Fig. 5 is a corresponding intermediate structural schematic diagram of the flow according to
[0044] For the convenience of understanding the present application, all the reference signs appearing in the present application are listed as follows:
[0045] Substrate 100 First semiconductor layer 200
[0046] Heterostructure layer 300 Overlayer 400
[0047] First region 401 Second region 402
[0048] Passivation layer 500 Second semiconductor layer 600
[0049] First electrode 700 Second electrode 800
[0050] Barrier layer 900 Dielectric layer 910
[0051] Channel layer 310 Barrier layer 320
[0052] First recess 10 Second recess 20
[0053] Third recess 30 DETAILED DESCRIPTION
[0054] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description herein refers to the accompanying drawings, which show by way of example specific exemplary embodiments. The description herein, in reference to the accompanying drawings, is intended to be illustrative of examples rather than restrictive of the application. The following description of exemplary embodiments is not representative of all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.
[0055] Embodiment 1
[0056] Figure 1(a) is a schematic diagram showing a structure of a Schottky diode 1 according to Embodiment 1. As shown in Figure 1(a), the Schottky diode 1 can include a substrate 100, a first semiconductor layer 200, a heterostructure layer 300, a mesa layer 400, a passivation layer 500, a first electrode 700 and a second electrode 800. The first semiconductor layer 200 is formed on the substrate 100, which can be made of one or more of silicon, silicon carbide, gallium nitride, sapphire. The first semiconductor layer 200 can be a nucleation layer and / or a buffer layer, which can be made of one or more of AlN, GaN, AlGaN and InN, without being limited thereto.
[0057] Further, the heterostructure layer 300 is formed on the first semiconductor layer 200, which can include a multi-layer structure made of a group III nitride. Preferably, the heterostructure layer 300 includes at least a channel layer and a barrier layer.
[0058] Further, the mesa layer 400 is formed on the heterostructure layer 300, which includes an active region 401 and an inactive region 402. The passivation layer 500 is formed on the mesa layer 400, which has a passivation and protection effect, reduces the surface state of the device, and effectively reduces the current collapse effect. The passivation layer 500 can be one or a combination of silicon nitride, silicon aluminum nitride and silicon dioxide. The passivation layer 500 can be formed on the mesa layer 400 by a deposition process, which can be one or a combination of PECVD, LPCVD, ALD and MOCVD.
[0059] In this embodiment, the mesa layer 400 is an intrinsic semiconductor layer. For example, the mesa layer 400 is an intrinsic group III nitride semiconductor layer. Further, the first region 401 and the second region 402 of the mesa layer 400 are not distinguished in material and function. They only serve to protect the heterostructure layer 300 and prevent carrier scattering.
[0060] Figure 7(d) is a schematic diagram of the intermediate structure of an example Schottky diode manufacturing process. As shown in Figure 7(d), the passivation layer 500 includes a first groove 10 and a second groove 20, wherein the first groove 10 is formed corresponding to the active region 401. The first groove 10 and the second groove 20 penetrate the passivation layer 500 and expose the cap layer 400. The number of the first groove 10 and the second groove 20 is not limited, but the number is at least one, provided that the device fabrication conditions are met. Optionally, the Schottky diode 1 shown in Figure 1(a) has one first groove 10 and one second groove 20.
[0061] like Figure 1(a) and 7(d) As shown, the Schottky diode 1 further includes a first electrode 700 and a second electrode 800. The first electrode 700 is located at least on the cap layer 400 corresponding to the first groove 10; the second electrode 800 is formed at the second groove 20. It should be noted that since the first groove 10 exposes the cap layer 400, the first electrode 700 and the exposed cap layer 400 of the first groove 10 form a Schottky contact. The first electrode 700 can be made of a metal with a high work function to realize the Schottky metal, such as Ni, Au, or Pt metal, to form the Schottky contact.
[0062] As can be seen from the above embodiments, a Schottky contact is formed between the first electrode 700 and the cap layer 400, which can avoid direct contact between the first electrode 700 and the heterostructure layer 300, balance the contradiction between the forward turn-on voltage and the reverse leakage current characteristics of the Schottky diode 1, and suppress the leakage current characteristics of the heterostructure layer 300 under high temperature environment to improve device performance.
[0063] Example 2
[0064] The fabrication method and structure of this embodiment are basically the same as those of Embodiment 1, except that the cap layer 400 can also be a P-type semiconductor layer. Optionally, magnesium can be used as a dopant element, and the doping concentration of magnesium can be 1E16cm. 3 -5E20 / cm 3It is important to note that when the cap layer 400 is a P-type semiconductor layer, the difference between the first region 401 and the second region 402 is that the first region 401 is activated, while the second region 402 is an inactive region. Furthermore, by annealing the first region 401 of the cap layer 400, an activated region is formed. In the specific process steps, a heterogeneous structure layer 300, a capping layer 400, and a passivation layer 500 can be stacked to form a heterogeneous structure layer 300. Then, a first groove 10 extending through the capping layer 400 is formed on the passivation layer 500. The structure after the first groove 10 is formed is then placed in a hydrogen-free atmosphere for annealing, such as in nitrogen, nitric oxide, air, or a mixture of nitrogen and oxygen. Since the capping layer 400 corresponding to the first groove 10 is not blocked by the passivation layer 500, hydrogen atoms overflow and other atoms are activated, thus forming the first region 401, which becomes an activated region. Meanwhile, the other regions blocked by the passivation layer 500 remain in a semi-insulated state because hydrogen atoms have no channel to overflow, thus forming an inactive state.
[0065] In this embodiment, not only can the contradiction between the forward turn-on voltage and the reverse leakage current characteristics of the Schottky diode 1 be balanced, and the leakage current characteristics of the heterostructure layer 300 under high temperature environment be suppressed, but the first electrode 700 is in contact with the activation region 401 of the cap layer 400, and the carrier concentration of the activation region 401 is high, which is beneficial to improving the device performance.
[0066] Example 3
[0067] This embodiment is basically the same as Embodiments 1 and 2 in terms of fabrication method and structure, the only difference being that the cap layer 400 can also be a co-doped semiconductor layer. Optionally, the co-doping elements include magnesium, silicon, and / or germanium. It should be noted that when the cap layer 400 is a co-doped semiconductor layer, the difference between the first region 401 and the second region 402 is that the first region 401 is activated, while the second region 402 is an inactive region. Compared to Embodiment 2, due to the use of multiple elements for co-doping, the self-compensation effect of magnesium impurities is reduced through co-doping, greatly increasing the hole concentration, thereby reducing the forward turn-on voltage.
[0068] Example 4
[0069] Figure 1(b) is a schematic diagram of a structure of a Schottky diode 2 according to Embodiment 4, and Figure 7(d) is a schematic diagram of an intermediate structure in a manufacturing process of an example Schottky diode. As shown in Figure 1(b) and Figure 7(d), the manufacturing method and structure of this embodiment are basically the same as those of Embodiment 1, except that the Schottky diode further comprises a second semiconductor layer 600, which is located at the first recess 10 and on the first region 401 and under the first electrode 700, and does not fill the first recess 10 in the horizontal direction, i.e. exposing part of the epi-layer 400. The thickness of the second semiconductor layer 600 is not limited, and optionally, the thickness of the second semiconductor layer 600 is less than the thickness of the passivation layer 500.
[0070] The second semiconductor layer 600 is a P-type semiconductor layer, and is preferably a P-type nitride layer, and the doping element is magnesium element, wherein the doping concentration of the magnesium element can be between 1E16 cm 3 and 5E20 / cm 3 . The manufacturing method is selective growth. Meanwhile, the P-type semiconductor layer is formed by doping an intrinsic semiconductor layer, for example, a P-type semiconductor layer formed by doping magnesium element, and the doping method uses ion implantation of magnesium element. Optionally, the P-type semiconductor layer is obtained after doping of magnesium element based on a group III nitride. Further, the second semiconductor layer 600 can be activated by annealing. For example, annealing can be performed in nitrogen, nitric oxide, air or a mixture of nitrogen and oxygen, and during the annealing process, hydrogen atoms in the second semiconductor layer 600 overflow and magnesium atoms are activated, so that the second semiconductor layer 600 is activated.
[0071] In this embodiment, the first electrode 700 is located on the epi-layer 400 and the second semiconductor layer 600 corresponding to the first recess 10, and the second electrode 800 is formed at the second recess 20. Preferably, the sidewall of the second semiconductor layer 600 is not flush with the sidewall of the first electrode 700, so as to weaken the electric field peak generated by the sidewall of the first electrode 700. It should be noted that, since the first recess 10 exposes part of the epi-layer 400, the first electrode 700 forms a Schottky contact with the epi-layer 400 exposed by the first recess 10, and forms a Schottky contact with the second semiconductor layer 600. The second semiconductor layer 600 further improves the reverse breakdown voltage to a certain extent.
[0072] Embodiment 5
[0073] Figure 2(a) is a schematic diagram of a structure of a Schottky diode 3 according to embodiment 5. Figure 7(h) is a schematic diagram of an intermediate structure of a manufacturing process flow of an example Schottky diode. As shown in Figure 2(a) and Figure 7(h), the Schottky diode 3 is similar to the Schottky diode 1 in Figure 1, except that the first region 401 of the overlayer 400 further comprises a third recess 30. Preferably, the third recess 30 penetrates through the overlayer 400 and exposes the heterostructure layer 300, and the third recess 30 is in communication with the first recess 10. The first electrode 700 is formed at the first recess 10, while covering the first region 401 and being located within the third recess 30, and the first electrode 700 is in contact with the heterostructure layer 300. In a specific process step, a pre-processed structure of the heterostructure layer 300 and the overlayer 400 can be formed by layering, and the pre-processed structure is etched by protection of a mask plate, and optionally the third recess 30 can be etched to the first region 402 by a selective etching method until the heterostructure layer 300 is exposed, and the selective etching method can use one or more of boric acid, phosphoric acid hydrogen fluoride, nitric acid and acetic acid.
[0074] In this embodiment, the Schottky contact is formed between the first electrode 700 and the overlayer 400, which can reduce the area of direct contact between the first electrode 700 and the heterostructure layer 300, and the first electrode 700 is also in contact with the heterostructure layer 300 to form an Ohmic contact, forming a hybrid electrode contact mode, which can balance the contradiction between the forward opening voltage and the reverse leakage current characteristics of the Schottky diode, and is conducive to improving the performance of the device.
[0075] Embodiment 6
[0076] Figure 2(b) is a schematic diagram of a structure of a Schottky diode 4 according to embodiment 6. Figure 7(h) is a schematic diagram of an intermediate structure of a manufacturing process flow of an example Schottky diode. As shown in Figure 2(b) and Figure 7(h), the manufacturing method and structure of this embodiment are basically the same as those of embodiment 5, except that the overlayer 400 with the third recess 30 further comprises a second semiconductor layer 600 above the overlayer 400, and the second semiconductor layer 600 corresponds to the first recess. Preferably, the doping concentration of the doping element in the overlayer 400 is less than the doping concentration of the doping element in the second semiconductor layer 600. For example, the doping concentration of magnesium in the overlayer 400 is less than 1E17 cm 3 , and the doping concentration of magnesium in the second semiconductor layer 600 is greater than 1E17 cm 3 . By forming the second semiconductor layer 600 with a gradual doping concentration below the first electrode 700, the doping concentration gradually increases from the heterostructure layer 300 to the first electrode 700, which is conducive to reducing the interface transition energy between the first electrode 700 and the second semiconductor layer 600 and reducing the on-state voltage, while ensuring that the contact area with the heterostructure layer 300 maintains a low doping element concentration, thereby achieving the effect of controlling the reverse breakdown.
[0077] Embodiment 7
[0078] Figure 3 is a structural schematic diagram of a Schottky diode 5 according to Embodiment 7. As shown, the manufacturing method and structure of this embodiment are basically the same as those of Embodiment 1, and the only difference is that the Schottky diode 3 further includes a barrier layer 900 located between the heterostructure layer 300 and the barrier layer 400. The barrier layer 900 can be used to control the depth of etching. Optionally, the barrier layer 900 can include an aluminum gallium nitride layer. By providing the barrier layer 10, the depth of the third recess 30 can be accurately controlled. Figure 3 Embodiment 8
[0079]
[0080] Figure 4 is a structural schematic diagram of a Schottky diode 6 according to Embodiment 8. As shown, the manufacturing method and structure of this embodiment are basically the same as those of Embodiment 1, and the only difference is that the Schottky diode 6 further includes a dielectric layer 910, which is optionally formed on the passivation layer 500 and the sidewalls of the first recess 10 and the second recess 20. By providing the dielectric layer 910, the leakage of the device can be reduced and the Schottky diode 4 can have a higher voltage resistance value. The dielectric layer 910 can include one or a combination of aluminum nitride, silicon nitride, aluminum oxide, aluminum oxynitride, and silicon dioxide, which is not limited in the present application. Figure 4 Embodiment 9
[0081]
[0082] Figure 5 is a structural schematic diagram of a Schottky diode 7 according to Embodiment 9. As shown, the manufacturing method and structure of this embodiment are basically the same as those of Embodiment 1, and the only difference is that the heterostructure layer 300 of the Schottky diode 7 includes a channel layer 310 and a barrier layer 320 stacked in sequence. The heterostructure layer 300 can be formed by single stacking of the channel layer 310 and the barrier layer 320, or multiple stacking of the channel layer 310 and the barrier layer 320 as units. Optionally, both the channel layer 310 and the barrier layer 320 are a group III nitride, wherein the barrier layer 320 is formed on the channel layer 310. The channel layer 310 can be made of one or more materials selected from GaN and AlN, and the barrier layer 320 can be made of one or more materials selected from AlN, GaN, AlInGaN, AlGaN, InGaN, and InN, which is not limited in the present application. On the basis of the formation of two-dimensional electron gas by the channel layer 310 and the barrier layer 320, multiple stacking of the channel layer 310 and the barrier layer 320 as units can increase the number of carriers, thereby improving the efficiency of the device. Figure 5
[0083] Based on the above technical solutions, the application further provides a process flow of a manufacturing method of the Schottky diode 1, Figure 6 is a manufacturing process flow of a Schottky diode according to an example embodiment, Figures 7(a)-7(g) is a manufacturing process flow of a Schottky diode according to an example embodiment, Figure 6 The manufacturing process flow of the Schottky diode corresponds to an intermediate structure schematic diagram, and the manufacturing method can include the following steps:
[0084] In step 601, as shown in Figure 6 and Fig. 7(a), a first semiconductor layer 200 is formed on a substrate 100. The first semiconductor layer 200 is a nucleation layer and / or a buffer layer. Preferably, the material of the first semiconductor layer 200 is a group III nitride, for example, when the first semiconductor layer 200 is a nucleation layer, the material can be made of one or more of AlN, GaN, AlGaN and InN.
[0085] In step 602, as shown in Figure 6 and Fig. 7(b), a heterostructure layer 300 is formed on the first semiconductor layer 200.
[0086] In step 603, as shown in Figure 6 and Fig. 7(c), a mesa layer 400 is formed on the heterostructure layer 300, the mesa layer 400 includes a first region (401) and a second region (402).
[0087] In step 604, as shown in Figure 6 and Fig. 7(d), a passivation layer 500 with a first recess 10 and a second recess 20 is formed on the mesa layer 400. The passivation layer 500 can be one or a combination of silicon nitride, silicon aluminum nitride and silicon dioxide. In actual operation, the passivation layer 500 is formed on the mesa layer 400 by means of a mask using a deposition process. The process of depositing the passivation layer 500 can be one or a combination of PECVD, LPCVD, ALD and MOCVD.
[0088] In step 605, the structure with the first recess 10 is annealed to activate the first region 401, and the mesa layer 400 covered by the passivation layer 500 forms an inactive region. Further, the first region 401 can be doped with magnesium elements, wherein the doping concentration of the magnesium elements can be 1E16 cm 3 -5E20 / cm 3The first region 401 doped with magnesium element is then placed in a hydrogen-free atmosphere for annealing, for example, in nitrogen, nitric oxide, air or a mixture of nitrogen and oxygen. Since the first recess 10 region is not covered by the passivation layer 500, hydrogen atoms overflow and magnesium atoms are activated, thus activating the first region 401. The other regions covered by the passivation layer 500 are still in a semi-insulating state, and the second region 402 forms a non-activated region.
[0089] In step 606, as shown in Figure 6 A second semiconductor layer 600 is formed in the first recess 10, and the second semiconductor layer 600 does not fill the first recess 10 in the horizontal direction, and the thickness of the second semiconductor layer 600 is not limited, and preferably, the thickness of the second semiconductor layer is less than the thickness of the passivation layer 500. The growth method of the second semiconductor layer 600 can use selective growth to reduce the cost and increase the growth accuracy. The process of forming the second semiconductor layer 600 can also include forming an intrinsic semiconductor layer in the first recess 10, and then doping the intrinsic semiconductor layer by ion implantation. Preferably, the doping element is Mg, and the doping concentration can be 1E16cm 3 -5E20 / cm 3 The structure is annealed to activate the doped intrinsic semiconductor layer, thereby forming the second semiconductor layer 500. The annealing should be placed in a hydrogen-free atmosphere, for example, in nitrogen, nitric oxide, air or a mixture of nitrogen and oxygen.
[0090] Further, in the ion implantation process, the depth of ion implantation is not limited, and the first region 401 below the second semiconductor layer 600 is also ion implanted, so that the doping element concentration of the first region 401 is higher than that of the second region 402.
[0091] In step 607, as shown in Figure 6 A first electrode 700 is formed at the first recess 10, covering the second semiconductor layer 600 and the first region 401 in the first recess 10 not covered by the second semiconductor layer 600, and the first electrode 700 is in contact with the first region 401. The first electrode 700 can use a metal with a high work function to form a Schottky contact, for example, Ni, Au or Pt metal.
[0092] In step 608, as shown in Figure 6As shown in Figure 7(f), a second electrode 800 is formed, which is located at the second groove (20).
[0093] In another embodiment, such as Figures 7(g)-Figure 7(j) As shown, the first region 401 of the cap layer 400 also includes a third groove 30. This third groove 30 penetrates the cap layer 400 and exposes the heterostructure layer 300, and is conductive to the first groove 10. A first electrode 700 is formed at the first groove 10, simultaneously covering the second semiconductor layer 600, and located within the portion of the first groove 10 not covered by the second semiconductor layer 600 and within the third groove 30. The first electrode 700 is in contact with the heterostructure layer 300. In this embodiment, a Schottky contact is formed between the first electrode 700 and the second semiconductor layer 600, which reduces the area of direct contact between the first electrode 700 and the heterostructure layer 300, balancing the contradiction between the forward turn-on voltage and reverse leakage characteristics of the Schottky diode, and suppressing the leakage characteristics of the heterostructure layer 300 under high-temperature environments. Furthermore, the first electrode 700 also contacts the heterostructure layer 300, forming an ohmic contact, which is beneficial for improving device performance.
[0094] It should be noted that this application does not restrict the manufacturing order of the first electrode 700 and the second electrode 800.
[0095] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0096] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A Schottky diode, characterized by, Comprise: a first semiconductor layer; a heterostructure layer on the first semiconductor layer; a mesa layer on the heterostructure layer, the mesa layer comprising at least a first region and a second region; a passivation layer on the mesa layer, the passivation layer comprising a first recess and a second recess, the first recess and the second recess at least penetrating the passivation layer, the first recess corresponding to the first region; a first electrode formed at the first recess, the first electrode in contact with the first region and / or the first electrode in contact with the heterostructure layer; a second electrode at the second recess; a second semiconductor layer at the first recess and at the same time on the first region and under the first electrode, a side wall of the second semiconductor layer close to the second electrode not being flush with a side wall of the first electrode close to the second electrode to expose part of the second semiconductor layer.
2. The Schottky diode according to claim 1, wherein: the mesa layer is an intrinsic semiconductor layer; or the mesa layer is a P-type semiconductor layer, and the doping element is magnesium element; or the mesa layer is a co-doped semiconductor layer, wherein the co-doping elements include magnesium element, silicon element and / or germanium element and / or oxygen element.
3. The Schottky diode of claim 1, wherein the second semiconductor layer does not fill the first recess in the horizontal direction.
4. The Schottky diode of claim 3, wherein The second semiconductor layer is a p-type semiconductor layer, and the doping element is magnesium element, and the doping concentration of the magnesium element is between 1E16 cm 3 -5E20 / cm 3 .
5. The Schottky diode of claim 1, wherein the mesa layer has a doping element, wherein the content of the doping element in the first region is higher than that in the second region.
6. The Schottky diode according to claim 2 or 4, wherein when the mesa layer is a P-type semiconductor layer or a co-doped semiconductor layer, the doping concentration of the doping element in the mesa layer is less than the doping element concentration of the second semiconductor layer.
7. The Schottky diode of claim 1, wherein the first region is an active region.
8. The Schottky diode of claim 1, wherein, the first region comprises a third recess, the third recess penetrating the mesa layer and exposing the heterostructure layer, and the third recess is in communication with the first recess.
9. The Schottky diode of claim 1, wherein, a barrier layer is provided between the heterostructure layer and the mesa layer.
10. The Schottky diode of claim 1, wherein the Schottky diode further comprises a dielectric layer, the dielectric layer being at least on the passivation layer and / or on the side wall of the first recess.
11. The Schottky diode of claim 1, wherein the heterostructure layer comprises at least a channel layer and a barrier layer, the heterostructure layer being formed by stacking the channel layer and the barrier layer one or more times in sequence.
12. The Schottky diode of claim 1, wherein the first semiconductor layer is a nucleation layer and / or a buffer layer.
13. The Schottky diode of claim 1, wherein the first semiconductor layer material and the second semiconductor layer material are III-nitride.
14. The Schottky diode of claim 1, wherein the Schottky diode further comprises a substrate, the substrate being below the first semiconductor layer.
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