Reference voltage calibration method, chip and electronic device

Abstract

The embodiment of the present invention provides a reference voltage calibration method, chip and electronic device, which relate to the field of electronic technology. The chip includes a main circuit, a comparator and a trigger. In the process of outputting a reference voltage, the main circuit receives a test sequence, and the trigger obtains and sends a sampling value of a level signal to the main circuit. When the sampling sequence matches the test sequence, the main circuit uses the reference voltage as an alternative reference voltage and selects a target reference voltage from all alternative reference voltages. During the reference voltage calibration process, the main circuit controls the trigger to perform multiple sampling within the transmission period of each bit of data in the test sequence, and determines whether the reference voltage is an alternative reference voltage based on the multiple sampling values ​​corresponding to each bit of data. This can more accurately determine whether the reference voltage is an alternative reference voltage, and then determine the accurate target reference voltage from at least one alternative reference voltage.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a reference voltage calibration method, a chip and an electronic device. Background Art

[0002] Chips typically have input pins that can receive data from external circuits, enabling communication with the external circuit. During communication with the external circuit through the input pins, the analog signal from the external circuit is received through the input pins and compared with an internal reference voltage. If the analog signal is greater than the reference voltage, a high-level signal is generated; if the analog signal is less than the reference voltage, a low-level signal is generated. A high-level signal corresponds to a digital signal of 1, and a low-level signal corresponds to a digital signal of 0, thereby enabling communication between the chip and the external circuit.

[0003] An inaccurate reference voltage can generate erroneous signal levels, leading to communication anomalies. Therefore, during the chip initialization phase, reference voltage calibration (Vref calibration) is required to determine the correct reference voltage. During this calibration process, factors such as signal interference and timing errors often prevent accurate reference voltage calibration. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a reference voltage calibration method, chip, and electronic device that overcome the above problems or at least partially solve the above problems.

[0005] A first aspect of an embodiment of the present invention discloses a chip, comprising: a main circuit, a comparator, and a trigger;

[0006] The main circuit is connected to the first input terminal of the comparator and to the clock input terminal of the trigger, and is configured to sequentially output reference voltages of different levels to the first input terminal. During the process of outputting the reference voltages, the main circuit receives a test sequence including multi-bit data through an input pin of the main circuit, and receives a plurality of sampling time points within a transmission period of the data, and sends trigger signals to the trigger respectively.

[0007] The second input terminal of the comparator is connected to the input pin, and is configured to output different level signals when the voltage at the second input terminal is greater than or less than the reference voltage, respectively;

[0008] The data input terminal of the trigger is connected to the output terminal of the comparator, and the output terminal is connected to the main circuit, and is used to obtain and send the sampled value of the level signal to the main circuit when receiving the trigger signal;

[0009] The main circuit is further configured to use the reference voltage as an alternative reference voltage when a sampling sequence matches the test sequence, and to select a target reference voltage from at least one obtained alternative reference voltage as a reference voltage during a communication process; the sampling sequence is composed of a plurality of sampling values ​​corresponding to the test sequence.

[0010] Optionally, it also includes a clock adjustment circuit; the main circuit is connected to the clock adjustment circuit, and the output end of the clock adjustment circuit is connected to the clock input end; the main circuit is used to send the delay time and the clock signal of the main circuit to the clock adjustment circuit; the clock adjustment circuit is used to determine the sampling time point based on the clock edge of the clock signal and the delay time, and send the trigger signal to the trigger at the sampling time point.

[0011] Optionally, the main circuit is configured to receive the test sequence multiple times continuously through the input pin during the process of outputting each reference voltage, and send a delay time to the clock adjustment circuit each time during the process of receiving the test sequence; the delay time sent each time corresponds to a sampling time point within a transmission period of one of the data;

[0012] The clock adjustment circuit is used to delay the clock signal based on the delay time, so as to send a trigger signal to the trigger at a corresponding sampling time point during each reception of the test sequence.

[0013] Optionally, the main circuit is configured to receive the test sequence once through the input pin during the process of outputting each reference voltage;

[0014] The clock adjustment circuit is used to determine the input time of the test sequence based on the delay time, and perform frequency multiplication processing on the clock signal to send a trigger signal to the trigger at each sampling time point after the input time.

[0015] Optionally, the main circuit is further configured to receive a plurality of different test sequences through the input pin during the process of outputting the reference voltage.

[0016] Optionally, the main circuit is specifically configured to obtain a preset first characteristic sequence from the test sequence; the first characteristic sequence includes a plurality of consecutive first data bits located after the first data bit in the test sequence;

[0017] The main circuit is further configured to obtain a target characteristic sequence corresponding to the first characteristic sequence from the sampling sequence, and to obtain second data corresponding to the first data from the target characteristic sequence, and to use the currently output reference voltage as an alternative reference voltage when a proportion of the second data in the second characteristic sequence is consistent with a proportion of the corresponding first data in the first characteristic sequence; the target characteristic sequence has the same data change trend as the first characteristic sequence, and the second characteristic sequence is a data sequence in the sampling sequence corresponding to the first characteristic sequence.

[0018] A second aspect of an embodiment of the present invention discloses a reference voltage calibration method, which is applied to a main circuit in the chip according to the first aspect. The method includes:

[0019] outputting reference voltages of different levels to the first input terminal of the comparator in sequence;

[0020] In the process of outputting the reference voltage, a test sequence including multi-bit data is received through an input pin in the main circuit, so that the comparator outputs different level signals when the voltage at the second input terminal is greater than or less than the reference voltage, respectively; the second input terminal is connected to the input pin;

[0021] At multiple sampling time points within the data transmission period, trigger signals are respectively sent to the trigger, so that the trigger obtains and sends the sampled value of the level signal to the main circuit when receiving the trigger signal; the data input terminal of the trigger is connected to the output terminal of the comparator, and the output terminal of the trigger is connected to the main circuit;

[0022] When the sampling sequence matches the test sequence, the reference voltage is used as an alternative reference voltage, and a target reference voltage is selected from at least one obtained alternative reference voltage as a reference voltage during the communication process; the sampling sequence is composed of multiple sampling values ​​corresponding to the test sequence.

[0023] Optionally, sending a trigger signal to a trigger at each of the plurality of sampling time points within the data transmission period includes:

[0024] The delay time and the clock signal of the main circuit are sent to the clock adjustment circuit, so that the clock adjustment circuit determines the sampling time point based on the clock edge of the clock signal and the delay time, and sends the trigger signal to the trigger at the sampling time point.

[0025] Optionally, receiving a test sequence including multi-bit data through an input pin in the main circuit includes: receiving the test sequence multiple times continuously through the input pin during the process of outputting each reference voltage,

[0026] The sending of the delay time and the clock signal of the main circuit to the clock adjustment circuit includes: sending the clock signal and the delay time to the clock adjustment circuit once each time the test sequence is received, so that the clock adjustment circuit delays the clock signal based on the delay time, and sends a trigger signal to the trigger at a corresponding sampling time point each time the test sequence is received; the delay time sent each time corresponds to a sampling time point within a transmission period of one of the data.

[0027] Optionally, the receiving of a test sequence including multi-bit data through an input pin in the main circuit includes: receiving the test sequence once through the input pin during the process of outputting each reference voltage, and enabling the clock adjustment circuit to determine the input time of the test sequence based on the delay time, and performing frequency multiplication processing on the clock signal so as to send a trigger signal to the trigger at each sampling time point after the input time.

[0028] Optionally, in the process of outputting the reference voltage, receiving a test sequence including multi-bit data through an input pin in the main circuit includes:

[0029] During the process of outputting the reference voltage, a plurality of different test sequences are received through the input pin.

[0030] Optionally, when the sampling sequence matches the test sequence, using the reference voltage as an alternative reference voltage, and selecting a target reference voltage from at least one obtained alternative reference voltage as a reference voltage in a communication process, includes:

[0031] Acquire a preset first characteristic sequence from the test sequence; the first characteristic sequence includes a plurality of consecutive first data bits located after the first data bit in the test sequence;

[0032] A target feature sequence corresponding to the first feature sequence is obtained from the sampling sequence, and second data corresponding to the first data is obtained from the target feature sequence. When the proportion of the second data in the second feature sequence is consistent with the proportion of the corresponding first data in the first feature sequence, the currently output reference voltage is used as an alternative reference voltage; the target feature sequence has the same data change trend as the first feature sequence, and the second feature sequence is a data sequence in the sampling sequence corresponding to the first feature sequence.

[0033] A third aspect of an embodiment of the present invention discloses an electronic device, comprising the chip as described in the first aspect.

[0034] In an embodiment of the present invention, a chip includes a main circuit, a comparator, and a trigger. The main circuit is connected to a first input terminal of the comparator and to a clock input terminal of the trigger, and is configured to sequentially output reference voltages of different levels to the first input terminal. In the process of outputting the reference voltage, the main circuit receives a test sequence including multi-bit data through an input pin of the main circuit, and sends a trigger signal to the trigger at multiple sampling time points within a data transmission cycle. The second input terminal of the comparator is connected to the input pin, and is configured to output different level signals when the voltage at the second input terminal is greater than or less than the reference voltage. The data input terminal of the trigger is connected to the output terminal of the comparator, and the output terminal is connected to the main circuit, and is configured to obtain and send a sampled value of the level signal to the main circuit upon receiving the trigger signal. The main circuit is further configured to use the reference voltage as an alternative reference voltage when the sampling sequence matches the test sequence, and to select a target reference voltage from at least one obtained alternative reference voltage as the reference voltage during the communication process. During the reference voltage calibration process, the main circuit controls the trigger to perform multiple sampling within the transmission period of each bit of data in the test sequence, and determines whether the reference voltage is an alternative reference voltage based on the multiple sampling values ​​corresponding to each bit of data. This can more accurately determine whether the reference voltage is an alternative reference voltage, and further determine the accurate target reference voltage from at least one alternative reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a DDR data read timing diagram according to an embodiment of the present invention;

[0036] Figure 2 An eye diagram of a DQ pin in a DDR according to an embodiment of the present invention;

[0037] Figure 3 is a schematic diagram of using a reference voltage in an embodiment of the present invention;

[0038] Figure 4 This is another eye diagram of a DQ pin in a DDR according to an embodiment of the present invention;

[0039] Figure 5 A schematic structural diagram of a chip according to an embodiment of the present invention is shown;

[0040] Figure 6 Shows a main circuit structure diagram of a DDR chip in an embodiment of the present invention;

[0041] Figure 7 Shows a main circuit structure diagram of a CPU chip in an embodiment of the present invention;

[0042] Figure 8 A schematic structural diagram of another chip in an embodiment of the present invention is shown;

[0043] Figure 9 A flow chart showing the steps of reference voltage calibration in an embodiment of the present invention is shown;

[0044] Figure 10 A structural block diagram of an electronic device in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0045] To facilitate understanding of the present invention, the reference voltage calibration process in the prior art is briefly introduced by taking the reference voltage calibration of a double data rate synchronous dynamic random access memory (DDR) as an example.

[0046] Among them, the DDR chip, which can also be called a memory chip, includes data input / output (DQ) pins. The DQ pins can also be called data input / output channels and have data input and output functions. The DDR is internally provided with a voltage generation unit and an input buffer corresponding to the DQ pin. The input buffer can also be called a receiver. The input buffer is provided with a comparator. The output end of the voltage generation unit is connected to the first input end of the comparator and can output a reference voltage to the first input end of the comparator. The DQ pin is connected to the second input end of the comparator. The DDR is connected to the processor (Central Processing Unit, CPU) through the DQ pin. The CPU can read data from the DDR or write data to the DDR through the DQ pin. When the CPU writes a binary 1-bit data (0 or 1) to the DDR, the CPU inputs a low-level or high-level analog signal corresponding to the data to the DDR's DQ pin. 0 corresponds to a low-level signal and 1 corresponds to a high-level signal. The comparator in the input buffer compares the analog signal with the reference voltage. If the analog signal is greater than the reference voltage, a high-level signal is output. If the analog signal is less than the reference voltage, a low-level signal is output. The high-level signal corresponds to the digital signal 1, and the low-level signal corresponds to the digital signal 0. DDR can determine whether the data written by the CPU to the DDR is 1 or 0 based on the high and low-level signals.

[0047] like Figure 1 As shown, Figure 1 This is a DDR read data timing diagram in an embodiment of the present invention. DDR and CPU communicate using the DDR protocol. During the communication process, not only data transmission is required, but also the transmission of clock signals and data selection pulses is required. The clock signal is a differential clock signal, including Figure 1 The clock signal CK_t and the clock signal CK_c shown in FIG. 1 are differential signals, including Figure 1The data selection pulse DQS_c and data selection pulse DQS_t are shown. The data selection pulse is used to determine the sampling time point. The intersection of the clock edge of the data selection pulse DQS_c and the falling clock edge of the data selection pulse DQS_t corresponds to the sampling time point. The clock edge refers to the rising and falling edges of the clock signal. At the sampling time point, DDR samples the level signal output by the comparator and determines whether the level signal is a high-level signal or a low-level signal to determine whether the input data is a 0 or a 1.

[0048] like Figure 2 and Figure 3 As shown, Figure 2 : is an eye diagram of a DQ pin in a DDR in an embodiment of the present invention, Figure 3 FIG. 1 is a schematic diagram of a reference voltage used in an embodiment of the present invention. Figure 2 The eye diagram shown is the eye diagram of the DQ pin in an ideal state. The reference voltage has a maximum reference voltage (largest Vref level) and a minimum reference voltage (smallest Vref level), that is, Figure 2 The reference voltage Vref_H and reference voltage Vref_L shown in the figure have a voltage range between them that is a suitable reference voltage range. During the reference voltage calibration phase, the sampling time point needs to be within the time range TdIVW, and the reference voltage needs to be within the voltage range VdIVW, that is, within the mask area Rx_mask. After determining the highest reference voltage and the lowest reference voltage, the midpoint Vref level between the two is selected as the target reference voltage, that is, Figure 2 The target reference voltage Vcent is shown by the dotted line. During the communication process between the CPU and the DDR, the voltage generation unit outputs the target reference voltage Vcent to the comparator in the input buffer. Figure 3 As shown, during the communication process, the digital signal input to the DQ pin can only be determined to be 1 or 0 when the analog signal input to the DQ pin is between the highest reference voltage Vref_H and the lowest reference voltage Vref_L. When the analog signal input to the DQ pin is lower than the lowest reference voltage Vref_L or higher than the highest reference voltage Vref_H, the comparator will output an erroneous level signal, resulting in DDR receiving erroneous data.

[0049] During the reference voltage calibration process, the common practice is to sequentially output multiple levels of reference voltage to the first input of the comparator. During each reference voltage output process, a test sequence (pattern) consisting of multi-bit binary data is written into the DDR through the DQ pin. The sampling time point is determined based on the intersection of the clock edges of the data selection pulse DQS_c and the data selection pulse DQS_t. The level signal output by the comparator is sampled to obtain a sampling sequence corresponding to the test sequence. If the test sequence matches the sampling sequence, it indicates that communication is normal and the currently output reference voltage can be used as an alternative reference voltage. After outputting multiple reference voltages, at least one alternative reference voltage can be obtained, and then one of the at least one alternative reference voltages is selected as the target reference voltage.

[0050] like Figure 4 As shown, Figure 4 This is another eye diagram of the DQ pin in a DDR in an embodiment of the present invention. During the reference voltage calibration process, in some cases, due to interference in the circuit, the reference voltage may fluctuate. For example, when sampling at the first sampling time point T1, the highest reference voltage Vref_H obtained is correct, but the lowest reference voltage Vref_L obtained is an incorrect reference voltage Vref_L_wrong, which is lower than the correct lowest reference voltage Vref_L. In this case, an incorrect target reference voltage Vcent_wrong is determined based on the highest and lowest reference voltages. In other cases, due to timing fluctuations, DQS may fluctuate, resulting in fluctuations in the sampling time point. For example, due to timing fluctuations, the sampling time point may move from the first sampling time point T1 to the second sampling time point T2. When sampling at the second sampling time point T2, the target reference voltage ultimately determined may be incorrect due to the incorrect highest reference voltage Vref_H.

[0051] One of the core concepts of an embodiment of the present invention is that, during the calibration process of the reference voltage, multiple samples are taken within the transmission period of each bit of data in the test sequence to obtain an accurate sampling sequence. This can avoid sampling time point errors due to interference, as well as reference voltage fluctuations during the sampling process, which may lead to errors in the obtained test sequence. Furthermore, it is possible to accurately determine whether the currently output reference voltage is an alternative reference voltage based on the sampling sequence and the test sequence, thereby obtaining an accurate target reference voltage.

[0052] It should be noted that while the reference voltage calibration process is described using the DQ pins of a DDR chip as an example, the chip in the present invention is not limited to a DDR chip and can be any other chip with input pins, such as a CPU. Input pins are not limited to DQ pins with both input and output functions; they can also be input pins with only an input function. Furthermore, input pins can be used to input data, commands, or addresses.

[0053] In order to solve the above technical problems, embodiments of the present invention provide a chip, a reference voltage calibration method, and an electronic device. The present invention is described in detail below with reference to the accompanying drawings of the embodiments of the present invention.

[0054] Reference Figure 5 , Figure 5 1 shows a schematic structural diagram of a chip in an embodiment of the present invention. The chip includes a main circuit 501, a comparator 502 and a trigger 503.

[0055] The main circuit is connected to a first input terminal of a comparator, which is an inverting input terminal of the comparator and a clock input terminal of a trigger, and is configured to sequentially output reference voltages of different levels to the first input terminal. During the process of outputting the reference voltage, a test sequence including multi-bit data is received through an input pin of the main circuit, and a trigger signal is sent to the trigger at multiple sampling time points within a data transmission cycle. The second input terminal of the comparator is connected to the input pin, which is a non-inverting input terminal of the comparator, and is configured to output different level signals when the voltage at the second input terminal is greater than or less than the reference voltage, respectively. The data input terminal of the trigger is connected to the output terminal of the comparator, and the output terminal is connected to the main circuit, and is configured to obtain and send a sampled value of the level signal to the main circuit upon receiving the trigger signal. The main circuit is further configured to use the reference voltage as an alternative reference voltage when the sampling sequence matches the test sequence, and to select a target reference voltage from at least one obtained alternative reference voltage as the reference voltage during the communication process. The sampling sequence is composed of multiple sampling values ​​corresponding to the test sequence.

[0056] In this embodiment, a comparator 502 and a trigger 503 form a sampling module. During reference voltage calibration, a test sequence is input to the DQ pin. Comparator 502 compares the test sequence input to the DQ pin with the reference voltage, that is, compares the analog signal corresponding to the test sequence with the reference voltage, and outputs a level signal. Trigger 503 samples the level signal output by comparator 502 at multiple sampling points within the transmission cycle of each bit of data to obtain a sampling sequence. The voltage output of main circuit 501 is connected to the first input of comparator 502, the clock output of main circuit 501 is connected to the clock input of trigger 503, the second input of comparator 502 is connected to the DQ pin of the main circuit, the output of comparator 502 is connected to the data input of trigger 503, and the output of trigger 503 is connected to the input of main circuit 501. Comparator 502 can be a comparator provided in the input buffer included in main circuit 501, or a comparator provided outside the input buffer. During reference voltage calibration, main circuit 501 can sequentially input multiple reference voltages of different levels to the first input. During the process of outputting each reference voltage, the main circuit 501 can control the reception of a test sequence via the DQ pin. The test sequence includes multiple bits of binary data. The main circuit 501 can determine the transmission period of each bit of binary data and input a trigger signal, which can be a rising edge signal, to the clock input of the flip-flop 503 at multiple sampling time points within the transmission period. Under the control of the trigger signal, the flip-flop 503 can sample the level signal at the output of the comparator 502 multiple times, obtain and transmit the sampled values ​​to the main circuit 501, and the main circuit 501 can obtain a sampling sequence consisting of multiple sampled values.

[0057] For example, refer to Figure 6 When the chip is a DDR chip, the main circuit includes the logic control unit, voltage generation unit, delay locked loop (DLL), storage array, input buffer and output buffer, DQ pin connected to the input buffer and output buffer, and other components in the DDR chip. The voltage output end of the main circuit can be the output end of the voltage generation unit, connected to the first input end of the comparator; the clock output end of the main circuit can be the output end of the delay locked loop, connected to the clock input end of the trigger; the logic control unit is connected to the voltage generation unit and the phase-locked loop respectively, and can control the voltage generation unit to output different levels of reference voltage in sequence, and control the delay locked loop to send a trigger signal to the trigger at each sampling time point. At the same time, the input end of the main circuit can be the input end of the logic control unit, connected to the output end of the trigger, and can receive the sampled value obtained by the trigger sampling. In the DDR chip, each DQ pin in the DDR chip can be set separately. Figure 5When the chip is a CPU, refer to Figure 7 The main circuit includes a control unit, a computing unit, a storage unit, an input buffer, an output buffer, and DQ pins connected to the input buffer and the output buffer. The above is merely an example. The specific composition of the main circuit is determined by the specific type of chip and is not limited in this embodiment.

[0058] During the reference voltage calibration process, the DDR can interact with the connected CPU, causing the CPU to send a test sequence to the DDR's DQ pin. During communication with the CPU, the DDR requires half a clock cycle to transmit each bit of binary data, meaning the transmission cycle for each bit of data is half a clock cycle. For example, if the voltage generation unit in the DDR can output five levels of reference voltage in descending or ascending order, during the reference voltage calibration process, the logic control unit can first send a control instruction to the voltage generation unit, controlling the voltage generation unit to output the first reference voltage. It can then interact with the CPU, causing the CPU to send a write instruction to the DDR and a test sequence to the DDR, such as an 8-bit binary data sequence. In this case, the test sequence input time can be determined based on the write command reception time and the CPU's latency. The latency is the time between the first time the CPU issues the write instruction and the second time the first bit of data in the test sequence is transmitted to the DQ pin. The test sequence input time is the time it takes for the first bit of data in the test sequence to be transmitted to the DQ pin. Because the transmission period for each bit of data is half a clock cycle, the input time of each bit of data in the test sequence can be determined based on the input time of the test sequence. The half clock cycle after the input time is the transmission period of the binary data. The clock signal can be adjusted by delaying the clock signal so that the DLL in the DDR sends a rising edge to the trigger at each sampling time point, that is, sends a trigger signal.

[0059] For example, if the clock cycle is 2 microseconds, the transmission period for each data bit is 1 microsecond. Taking the input time of the first bit of data as the first sampling time point, if the input time of the first binary data bit in the test sequence is 0 microseconds, the DLL can send four rising edges to the trigger at 0.2 microseconds, 0.4 microseconds, 0.6 microseconds, and 0.8 microseconds, respectively. Accordingly, triggered by these four rising edges, the trigger samples the comparator output signal four times at the four sampling time points, obtaining four sampled values ​​and sending them to the logic control unit. The logic control unit then obtains the four sampled values ​​corresponding to the first data bit in the test sequence. Similarly, if the input time of the second data bit is 1 microsecond, five trigger signals can be sent to the trigger at the four sampling time points between 1.2 microseconds and 2 microseconds, causing the trigger to sample the comparator output signal four times, obtaining the four sampled values ​​corresponding to the second data bit. By analogy, we can obtain four sample values ​​corresponding to each bit of binary data in the test sequence, for a total of 32 sample values ​​corresponding to the test sequence, namely the sampling sequence. Each sample value output by the trigger is a low-level or high-level signal, so the 32 sample values ​​obtained by the main circuit are a 32-bit binary sequence.

[0060] After obtaining the sampling sequence, the logic control unit can compare the sampling sequence with the test sequence to determine whether the two match. For example, if the test sequence is the binary sequence 01010011, the first bit in the test sequence corresponds to bits 1-4 in the sampling sequence, and the second bit in the test sequence corresponds to bits 5-8 in the sampling sequence. Similarly, each bit of data in the test sequence corresponds to four bits of data in the sampling sequence. Ideally, the first bit in the test sequence is the same as bits 1-4 in the sampling sequence, and the second bit is the same as bits 5-8 in the sampling sequence. Similarly, each bit in the test sequence is the same as the corresponding four bits in the sampling sequence. The logic control unit can first obtain a pre-stored test sequence 01010011, and then use the 4-bit data in the sampling sequence as a unit to determine whether the data in the sampling sequence changes according to 01010011, that is, the 1st to 4th bits are 0, and the 5th to 8th bits are 1. It then sequentially determines whether each bit in the test sequence is identical to the corresponding 4-bit data in the sampling sequence. If each bit in the test sequence is identical to the corresponding 4-bit data in the sampling sequence, it is determined that the test sequence matches the sampling sequence, and the first reference voltage currently output can be used as an alternative reference voltage. Conversely, if any bit in the test sequence is different from the corresponding 4-bit data in the sampling sequence, it is determined that the sampling sequence does not match the test sequence, and the first reference voltage currently output is not used as an alternative reference voltage.

[0061] In this embodiment, after outputting the first reference voltage, the logic control unit can send a control instruction to the voltage generation unit, causing it to output a second reference voltage. Simultaneously, the logic control unit can interact with the CPU, causing the CPU to write a second test sequence to the DDR. Similarly, the logic control unit can send a control instruction to the DLL, causing the DLL to send a trigger signal to the trigger at each sampling time point. At this point, the logic control unit can obtain a second sampling sequence corresponding to the second reference voltage. Furthermore, after obtaining the second sampling sequence, the logic control unit determines that the second sampling sequence matches the test sequence and uses the second reference voltage as an alternative reference voltage. Similarly, at least one alternative reference voltage can be determined from the five reference voltages. After determining one or more alternative reference voltages, one of the at least one alternative reference voltages can be selected as the target reference voltage. In conjunction with the above example, when determining multiple alternative reference voltages, the highest and lowest reference voltages can first be determined from the multiple alternative reference voltages. Then, an intermediate reference voltage between the highest and lowest reference voltages can be determined and used as the target reference voltage. The method for determining the target reference voltage from the at least one alternative reference voltage can be customized as needed and is not limited in this embodiment.

[0062] Optionally, the main circuit is specifically used to obtain a pre-set first characteristic sequence from the test sequence; the first characteristic sequence includes multiple consecutive first data located after the first data in the test sequence; the main circuit is also used to obtain a target characteristic sequence corresponding to the first characteristic sequence from the sampling sequence, and obtain second data corresponding to the first data from the target characteristic sequence, and when the proportion of the second data in the second characteristic sequence is consistent with the proportion of the corresponding first data in the first characteristic sequence, use the currently output reference voltage as an alternative reference voltage; the target characteristic sequence has the same data change trend as the first characteristic sequence, and the second characteristic sequence is a data sequence in the sampling sequence corresponding to the first characteristic sequence.

[0063] In one embodiment, a first feature sequence can be pre-set in a test sequence. After acquiring a sampling sequence, a target feature sequence with the same data change trend as the first feature sequence can be determined from the sampling sequence. Based on the proportion of second data in the target feature sequence in the second feature sequence, a determination is made as to whether the test sequence matches the sampling sequence. Table 1 shows an exemplary test sequence.

[0064]

[0065] Table 1

[0066] As shown in Table 1, the test sequence includes five signature bits. The data of these five signature bits constitute a first signature sequence. The first signature sequence consists of the five first data bits following bit 0, i.e., 10100. The first data is the data in the test sequence. The first signature sequence can also be a series of first data bits following bit 1 or bit 2, or other bits. The data of the first signature bit can be set to be different from the data before the first signature bit, i.e., the data of bit 0 in Table 1 can be set to be different from the data of bit 1, i.e., bit 0 is 0 and bit 1 is 1. In the first signature sequence, the data change trend is 10100. Based on the above example, by performing four samplings within the transmission period of each bit of data, a sampling sequence consisting of 32 sample values ​​can be obtained, e.g., 0011 / 1111 / 0000 / 1111 / 0000 / 0000 / 1111 / 1111. The second signature sequence corresponds to the first signature sequence and consists of bits 5 to 24 in the sampling sequence. After obtaining a sampling sequence consisting of 32 sample values, a target signature sequence with a data variation trend of 10100 can be determined from the sampling sequence. The target signature sequence can then be determined to consist of data bits 3 to 24 in the sampling sequence. Bits 3 to 8 in the target signature sequence correspond to the first first data 1 in the first signature sequence, bits 9 to 12 correspond to the first first data 0 in the first signature sequence, bits 13 to 16 correspond to the second first data 1 in the first signature sequence, bits 17 to 20 correspond to the second first data 0 in the first signature sequence, and bits 21 to 24 correspond to the third first data 0 in the first signature sequence. The data variation trend of the entire target signature sequence is 10100. Furthermore, the second data corresponding to each first data point can be obtained from the target signature sequence to determine the proportion of the second data point in the second signature sequence. The second data point is the data in the sampling sequence. As described above, if the second data point corresponding to the first data point 1 in the first signature sequence is 111111, then the proportion of the second data point 111111 in the second signature sequence is greater than 20% as shown in Table 1. In this case, it can be determined that the test sequence does not match the sampling sequence. On the contrary, when the proportion of the second data corresponding to each first data in the second characteristic sequence is consistent with the proportion of the first data in the first characteristic sequence, it is determined that the test sequence matches the sampling sequence.

[0067] In practical applications, due to timing fluctuations, multiple sampling within each transmission cycle may result in the inability to identify the first bit of data in the test sequence, as well as inconsistencies between the first bit of data in the test sequence and the corresponding multiple bits of second data. By setting a first feature sequence in the test sequence and, during calibration, determining the target feature sequence from the sampling sequence based on the data change trend in the first feature sequence, and then determining whether the sampling sequence and the test sequence match based on the target feature sequence and the ratio of the second data to the first data in the first feature sequence, this method can accurately determine whether the test sequence and the sampling sequence match.

[0068] It should be noted that, during the sampling process, the time difference between two adjacent sampling time points may be set to be no less than a preset time difference, so as to avoid sampling the level signal at two relatively close sampling time points.

[0069] Optionally, the chip also includes a clock adjustment circuit; the main circuit is connected to the clock adjustment circuit, and the output end of the clock adjustment circuit is connected to the clock input end; the main circuit is used to send the delay time and the clock signal of the main circuit to the clock adjustment circuit; the clock adjustment circuit is used to determine the sampling time point based on the clock edge and delay time of the clock signal, and send a trigger signal to the trigger at the sampling time point.

[0070] In one embodiment, a clock adjustment circuit may be provided in the chip, and the clock adjustment circuit, the comparator, and the trigger form a sampling module. The clock adjustment circuit may adjust the clock signal of the main circuit to generate and send a corresponding trigger signal to the trigger at each sampling time point. Figure 8 As shown, Figure 8 A schematic diagram of the structure of another chip in an embodiment of the present invention is shown. The clock adjustment circuit 504 can be a DLL circuit. The input of the clock adjustment circuit is connected to the clock port of the main circuit, and can obtain the clock signal CLK from the main circuit. The clock signal CLK and the differential clock signal in the DDR are clock signals of the same frequency. During the process of receiving a test sequence through the DQ pin, the clock edge of the clock signal is used as a reference to determine the input time of each bit of data in the test sequence. Furthermore, by setting a delay time, each sampling time point within the transmission cycle of each bit of data can be determined, and a trigger signal is sent to the trigger at each sampling time point.

[0071] Optionally, the main circuit is used to continuously receive a test sequence through the input pin multiple times during the process of outputting each reference voltage, and send a delay time to the clock adjustment circuit each time the test sequence is received; the delay time sent each time corresponds to a sampling time point within the transmission cycle of one of the data; the clock adjustment circuit is used to delay the clock signal based on the delay time, so as to send a trigger signal to the trigger at a corresponding sampling time point each time the test sequence is received.

[0072] In one embodiment, the clock signal can be delayed by a clock adjustment circuit to obtain a trigger signal. The clock adjustment circuit can be a DLL. The DLL can delay the clock signal and send a trigger signal with the same frequency as the clock signal to the trigger. The delay time is between the rising edge of the trigger signal and the rising edge of the clock signal. In combination with the above example, the test sequence is an 8-bit binary sequence. There are 5 sampling time points in the transmission cycle of each bit of data, a total of 32 sampling time points, and 32 samples are required. In the process of controlling the voltage generation unit to output the first reference voltage, the logic control unit can interact with the CPU to enable the CPU to continuously send 32 test sequences. Each time the test sequence is input, the logic control unit can send a new delay time to the DLL, so that the DLL sends a trigger signal to the trigger at one of the sampling time points. For example, in the process of receiving the test sequence for the first time, the logic control unit can set the delay time of the DLL to X, where the delay time X is the length of the latency period. When receiving a test sequence for the first time, the delay time X is set between the rising edge of the clock signal and the rising edge of the trigger signal. The DLL can send the first rising edge to the trigger when the first bit of data in the test sequence is input to the DQ pin, allowing the trigger to perform the first sampling at the first sampling time point within the transmission cycle of the first bit of data in the test sequence. When receiving the test sequence for the second time, the logic control unit can adjust the DLL's delay time to X+Y, where Y is the time difference between the first sampling time point and the second sampling time point within the transmission cycle of the first bit of data in the test sequence. Therefore, during the second test sequence reception, the delay time X+Y is set between the rising edge of the clock signal and the rising edge of the trigger signal, allowing the trigger to perform the second sampling at the second sampling time point. Similarly, during the third test sequence reception, the main circuit can set the delay time to X+2Y, during the fourth test sequence reception, to X+3Y, and during the fifth test sequence reception, to X+4Y. The sampling time point corresponding to the delay time X+4Y is the first sampling time point within the transmission cycle of the second bit of data in the test sequence. By analogy, the delay time can be set to X+5Y, X+6Y, X+7Y, etc. At each sampling time point in the transmission period of each bit of data in the test sequence, the DLL is controlled to send a trigger signal to the trigger.

[0073] In an embodiment of the present invention, a test sequence is received multiple times continuously, and sampling is performed during each test sequence reception. Multiple sample values ​​corresponding to each bit of data in the test sequence are obtained, thereby obtaining the test sequence. During the sampling process, the clock adjustment circuit only needs to delay the clock signal, resulting in a simple structure of the clock adjustment circuit, which avoids increasing chip area.

[0074] Optionally, the main circuit is used to receive a test sequence through the input pin during the process of outputting each reference voltage; the clock adjustment circuit is used to determine the input time of the test sequence based on the delay time, and multiply the clock signal to send a trigger signal to the trigger at each sampling time point after the input time.

[0075] In one embodiment, the main circuit may receive the test sequence only once, and the clock adjustment circuit may delay and multiply the clock signal so as to send a trigger signal to the trigger at each sampling time point after the input time of the test sequence. In combination with the above example, the clock adjustment circuit 504 may include a frequency multiplier. After starting the calibration of the reference voltage, the logic control unit in the DDR interacts with the CPU to enable the CPU to send a test sequence to the DQ pin. At this time, the logic control unit can set the delay time of the clock adjustment circuit 504 to X (latency duration) and the multiplication number to 8. The frequency multiplier can multiply the clock signal by 8 and can perform delay processing. Then, after the clock signal is input to the clock adjustment circuit 504, the frequency of the trigger signal output by the clock adjustment circuit 504 is 8 times that of the clock signal, and the delay time X is separated between the first rising edge of the trigger signal and the first rising edge of the clock signal. At this time, within half the clock cycle of the clock signal, that is, within the transmission cycle of each bit of data, the clock adjustment circuit can output 4 rising edges, that is, 4 trigger signals. Each rising edge corresponds to a sampling time point, so that the trigger can sample each bit of data 4 times and obtain 4 sampling values.

[0076] In an embodiment of the present invention, the clock adjustment circuit includes a frequency multiplier that multiplies the frequency of the clock signal. This multiplier can then send a trigger signal to the trigger at multiple sampling time points within the transmission cycle of each bit of data in a test sequence. This multiplication of the clock signal reduces the number of test sequences sent by the CPU, thereby reducing power consumption during reference voltage calibration.

[0077] It should be noted that the clock adjustment circuit can also adjust the clock signal in other ways, sending a trigger signal to the trigger at each sampling time point. The specific structure and type of the clock adjustment circuit can be set according to needs, and this embodiment does not limit this.

[0078] Optionally, the main circuit is further configured to receive a plurality of different test sequences through an input pin during the process of outputting the reference voltage.

[0079] In one embodiment, the reference voltage can be calibrated through multiple different test sequences. Taking the number of test sequences as two as an example, in the process of outputting the first reference voltage, the DDR interacts with the CPU, causing the CPU to send the first test sequence to the DDR, and obtain the first sampling sequence corresponding to the first test sequence, and then judge whether the first reference voltage is an alternative reference voltage based on the first sampling sequence and the first test sequence. After obtaining the first sampling sequence, the DDR can interact with the CPU, causing the CPU to send a second test sequence to the DDR, and the second test sequence is a different test sequence from the first test sequence. The second sampling sequence corresponding to the second test sequence can be obtained, and then judge whether the first reference voltage is an alternative reference voltage based on the second sampling sequence and the second test sequence. By analogy, in the process of outputting each reference voltage, multiple different test sequences are received through the input pin, and it is judged whether the currently output reference voltage is an alternative reference voltage.

[0080] Alternatively, for the first test sequence, multiple reference voltages of different levels may be output sequentially. During the output of each reference voltage, only the first test sequence is received, a sampling sequence corresponding to the first test sequence is obtained, and a determination is made based on the first test sequence and the corresponding sampling sequence whether each reference voltage is an alternative reference voltage. After the first test sequence, the above process is repeated for the second test sequence, where multiple reference voltages of different levels are output sequentially. During the output of each reference voltage, a sampling sequence corresponding to the second test sequence is obtained, and a determination is made based on the second test sequence and the corresponding sampling sequence whether the currently output reference voltage is an alternative reference voltage.

[0081] When multiple different test sequences are used for reference voltage calibration, for the same reference voltage, some test sequences may match the corresponding sampling sequence and use the reference voltage as an alternative reference voltage, while other test sequences may not match the corresponding sampling sequence and not use the reference voltage as an alternative reference voltage. In the above example, for the first reference voltage, the first test sequence may match the corresponding sampling sequence and use the first reference voltage as an alternative reference voltage, while the second test sequence may not match the corresponding sampling sequence and not use the first reference voltage as an alternative reference voltage; or the first test sequence may match the corresponding sampling sequence and the second test sequence may match the corresponding sampling sequence and use the first reference voltage as an alternative reference voltage; or the first test sequence may not match the corresponding sampling sequence and the second test sequence may not match the corresponding sampling sequence and not use the first reference voltage as an alternative reference voltage. For the same reference voltage, when multiple test sequences all match the corresponding sampling sequence, the reference voltage may be used as an alternative reference voltage to avoid the situation where some test sequences match the corresponding sampling sequence and use the reference voltage as an alternative reference voltage under interference. In combination with the above example, when the first test sequence matches the corresponding sampling sequence and the second test sequence matches the corresponding sampling sequence, the first reference voltage is used as the candidate reference voltage; otherwise, the first reference voltage is not used as the candidate reference voltage.

[0082] In the embodiment of the present invention, different test sequences are used to calibrate the reference voltage, which can avoid the problem that the test sequence affects the sampling result and causes the inability to accurately determine the candidate reference voltage.

[0083] In summary, in an embodiment of the present invention, a chip includes a main circuit, a comparator, and a trigger. The main circuit is connected to a first input terminal of the comparator and to a clock input terminal of the trigger, and is configured to sequentially output reference voltages of different levels to the first input terminal. In the process of outputting the reference voltage, the main circuit receives a test sequence including multi-bit data through an input pin of the main circuit, and sends a trigger signal to the trigger at multiple sampling time points within a data transmission cycle. The second input terminal of the comparator is connected to the input pin, and is configured to output different level signals when the voltage at the second input terminal is greater than or less than the reference voltage, respectively. The data input terminal of the trigger is connected to the output terminal of the comparator, and the output terminal is connected to the main circuit, and is configured to obtain and send a sampled value of the level signal to the main circuit upon receiving the trigger signal. The main circuit is further configured to use the reference voltage as an alternative reference voltage when the sampling sequence matches the test sequence, and to select a target reference voltage from at least one obtained alternative reference voltage as the reference voltage during the communication process. During the reference voltage calibration process, the main circuit controls the trigger to perform multiple sampling within the transmission period of each bit of data in the test sequence, and determines whether the reference voltage is an alternative reference voltage based on the multiple sampling values ​​corresponding to each bit of data. This can more accurately determine whether the reference voltage is an alternative reference voltage, and further determine the accurate target reference voltage from at least one alternative reference voltage.

[0084] Reference Figure 9 , Figure 9 A flowchart of a reference voltage calibration method according to an embodiment of the present invention is shown. The method is applied to a chip including a main circuit, a comparator, and a trigger, and may include:

[0085] Step 701: output reference voltages of different levels to the first input terminal of the comparator in sequence.

[0086] Step 702: During the process of outputting the reference voltage, a test sequence including multi-bit data is received through an input pin in the main circuit, so that the comparator outputs different level signals when the voltage at the second input terminal is greater than or less than the reference voltage.

[0087] The second input terminal of the comparator is connected to the input pin.

[0088] Step 703: Send a trigger signal to the trigger at multiple sampling time points within the data transmission period, so that the trigger obtains and sends the sampling value of the level signal to the main circuit when receiving the trigger signal.

[0089] The data input terminal of the trigger is connected to the output terminal of the comparator, and the output terminal is connected to the main circuit.

[0090] Step 704: When the sampling sequence matches the test sequence, the reference voltage is used as a candidate reference voltage, and a target reference voltage is selected from the at least one candidate reference voltage obtained as a reference voltage in the communication process.

[0091] The sampling sequence is composed of multiple sampling values ​​corresponding to the test sequence.

[0092] Optionally, the step of sending a trigger signal to the trigger at multiple sampling time points within the data transmission cycle may include: sending the delay time and the clock signal of the main circuit to the clock adjustment circuit, so that the clock adjustment circuit determines the sampling time point based on the clock edge and delay time of the clock signal, and sends a trigger signal to the trigger at the sampling time point.

[0093] Optionally, the step of receiving a test sequence including multi-bit data through an input pin in the main circuit includes: receiving the test sequence multiple times continuously through the input pin during the process of outputting each reference voltage; sending the delay time and the clock signal of the main circuit to the clock adjustment circuit, including: sending the clock signal and the delay time to the clock adjustment circuit once during each process of receiving the test sequence, so that the clock adjustment circuit delays the clock signal based on the delay time, so as to send a trigger signal to the trigger at a corresponding sampling time point during each process of receiving the test sequence; the delay time sent each time corresponds to a sampling time point within the transmission cycle of one of the data.

[0094] Optionally, the step of receiving a test sequence including multi-bit data through an input pin in the main circuit includes: receiving the test sequence once through the input pin during the process of outputting each reference voltage, and enabling the clock adjustment circuit to determine the input time of the test sequence based on the delay time, and multiplying the clock signal to send a trigger signal to the trigger at each sampling time point after the input time.

[0095] Optionally, the step of receiving a test sequence including multi-bit data through an input pin in the main circuit during the process of outputting the reference voltage includes: receiving a plurality of different test sequences through the input pin during the process of outputting the reference voltage.

[0096] Optionally, step 704 may include:

[0097] A pre-set first feature sequence is obtained from a test sequence; the first feature sequence includes a plurality of consecutive first data located after the first data in the test sequence; a target feature sequence corresponding to the first feature sequence is obtained from a sampling sequence, and second data corresponding to the first data is obtained from the target feature sequence, and when the proportion of the second data in the second feature sequence is consistent with the proportion of the corresponding first data in the first feature sequence, the currently output reference voltage is used as an alternative reference voltage; the target feature sequence has the same data change trend as the first feature sequence, and the second feature sequence is a data sequence corresponding to the first feature sequence in the sampling sequence.

[0098] The reference voltage calibration method can be understood in conjunction with the chip in the above example, and will not be described in detail in this embodiment.

[0099] Reference Figure 10 , Figure 10 The block diagram of the structure of an electronic device in an embodiment of the present invention is shown. For example, the electronic device 800 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc. The electronic device includes the chip described above.

[0100] Among them, the electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0101] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 802 may include one or more units to facilitate interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia unit to facilitate interaction between the multimedia component 808 and the processing component 802.

[0102] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0103] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0104] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor can not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0105] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0106] I / O interface 812 provides an interface between processing component 802 and peripheral interface units, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0107] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of components, such as the display and keypad of the electronic device 800. The sensor assembly 814 can also detect changes in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and temperature changes of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0108] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) unit to facilitate short-range communication. For example, the NFC unit can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0109] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processing circuits (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0110] In this embodiment, the electronic device further includes the chip described above.

[0111] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0112] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0113] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the process in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0114] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0115] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0116] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0117] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0118] The above is a detailed introduction to a chip, a reference voltage calibration method, and an electronic device provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. The content of this specification should not be understood as limiting the present invention.

Claims

1. A reference voltage calibration method, characterized in that: Applied to a chip, the chip includes a main circuit, a comparator and a trigger, and the method includes: outputting reference voltages of different levels to the first input terminal of the comparator in sequence; In the process of outputting the reference voltage, a test sequence including multi-bit data is received through an input pin in the main circuit, so that the comparator outputs different level signals when the voltage at the second input terminal is greater than or less than the reference voltage, respectively; The second input terminal is connected to the input pin; At multiple sampling time points within the data transmission period, trigger signals are respectively sent to the trigger, so that the trigger obtains and sends the sampled value of the level signal to the main circuit when receiving the trigger signal; the data input terminal of the trigger is connected to the output terminal of the comparator, and the output terminal of the trigger is connected to the main circuit; When the sampling sequence matches the test sequence, the reference voltage is used as an alternative reference voltage, and a target reference voltage is selected from at least one obtained alternative reference voltage as a reference voltage in a communication process; The sampling sequence is composed of a plurality of sampling values ​​corresponding to the test sequence.

2. The method according to claim 1, characterized in that The sending of trigger signals to the trigger at respective sampling time points within the data transmission period includes: The delay time and the clock signal of the main circuit are sent to the clock adjustment circuit, so that the clock adjustment circuit determines the sampling time point based on the clock edge of the clock signal and the delay time, and sends the trigger signal to the trigger at the sampling time point.

3. The method according to claim 2, characterized in that The receiving of the test sequence including multi-bit data through the input pin in the main circuit includes: receiving the test sequence multiple times continuously through the input pin during the process of outputting each reference voltage; The sending of the delay time and the clock signal of the main circuit to the clock adjustment circuit includes: sending the clock signal and the delay time to the clock adjustment circuit once each time the test sequence is received, so that the clock adjustment circuit delays the clock signal based on the delay time, and sends a trigger signal to the trigger at a corresponding sampling time point each time the test sequence is received; the delay time sent each time corresponds to a sampling time point within a transmission period of one of the data.

4. The method according to claim 2, characterized in that The receiving of a test sequence including multi-bit data through an input pin in the main circuit includes: receiving the test sequence once through the input pin during the process of outputting each reference voltage, and enabling the clock adjustment circuit to determine the input time of the test sequence based on the delay time, and performing frequency multiplication processing on the clock signal so as to send a trigger signal to the trigger at each sampling time point after the input time.

5. The method according to claim 1, wherein The step of receiving a test sequence including multi-bit data through an input pin in the main circuit during the process of outputting the reference voltage comprises: During the process of outputting the reference voltage, a plurality of different test sequences are received through the input pin.

6. The method according to any one of claims 1 to 5, characterized in that The method of using the reference voltage as a candidate reference voltage when the sampling sequence matches the test sequence, and selecting a target reference voltage from at least one obtained candidate reference voltage as a reference voltage in a communication process, includes: Acquire a preset first characteristic sequence from the test sequence; the first characteristic sequence includes a plurality of consecutive first data bits located after the first data bit in the test sequence; A target feature sequence corresponding to the first feature sequence is obtained from the sampling sequence, and second data corresponding to the first data is obtained from the target feature sequence. When the proportion of the second data in the second feature sequence is consistent with the proportion of the corresponding first data in the first feature sequence, the currently output reference voltage is used as an alternative reference voltage; the target feature sequence has the same data change trend as the first feature sequence, and the second feature sequence is a data sequence in the sampling sequence corresponding to the first feature sequence.

7. A chip, characterized in that: The chip includes a main circuit, a comparator and a trigger; The main circuit is connected to the first input terminal of the comparator and to the clock input terminal of the trigger, and is configured to sequentially output reference voltages of different levels to the first input terminal. During the process of outputting the reference voltages, the main circuit receives a test sequence including multi-bit data through an input pin of the main circuit, and receives a plurality of sampling time points within a transmission period of the data, and sends trigger signals to the trigger respectively. The second input terminal of the comparator is connected to the input pin, and is configured to output different level signals when the voltage at the second input terminal is greater than or less than the reference voltage, respectively; The data input terminal of the trigger is connected to the output terminal of the comparator, and the output terminal is connected to the main circuit, and is used to obtain and send the sampled value of the level signal to the main circuit when receiving the trigger signal; The main circuit is further configured to use the reference voltage as an alternative reference voltage when the sampling sequence matches the test sequence, and select a target reference voltage from at least one obtained alternative reference voltage as a reference voltage during communication; The sampling sequence is composed of a plurality of sampling values ​​corresponding to the test sequence.

8. The chip according to claim 7, characterized in that Also included is a clock adjustment circuit; The main circuit is connected to the clock adjustment circuit, and the output end of the clock adjustment circuit is connected to the clock input end; The main circuit is used to send the delay time and the clock signal of the main circuit to the clock adjustment circuit; The clock adjustment circuit is configured to determine the sampling time point based on a clock edge of the clock signal and the delay time, and send the trigger signal to the trigger at the sampling time point.

9. The chip according to claim 8, characterized in that The main circuit is configured to receive the test sequence multiple times continuously through the input pin during the process of outputting each reference voltage, and send a delay time to the clock adjustment circuit each time the test sequence is received; The delay time sent each time corresponds to a sampling time point within a transmission period of the data; The clock adjustment circuit is used to delay the clock signal based on the delay time, so as to send a trigger signal to the trigger at a corresponding sampling time point during each reception of the test sequence.

10. The chip according to claim 8, characterized in that The main circuit is configured to receive the test sequence once through the input pin during the process of outputting each reference voltage; The clock adjustment circuit is used to determine the input time of the test sequence based on the delay time, and perform frequency multiplication processing on the clock signal to send a trigger signal to the trigger at each sampling time point after the input time.

11. The chip according to claim 7, characterized in that The main circuit is further configured to receive a plurality of different test sequences through the input pin during the process of outputting the reference voltage.

12. The chip according to any one of claims 7 to 11, characterized in that: The main circuit is specifically configured to obtain a preset first characteristic sequence from the test sequence; the first characteristic sequence includes a plurality of consecutive first data bits located after the first data bit in the test sequence; The main circuit is further configured to obtain a target characteristic sequence corresponding to the first characteristic sequence from the sampling sequence, and to obtain second data corresponding to the first data from the target characteristic sequence, and to use the currently output reference voltage as an alternative reference voltage when a proportion of the second data in the second characteristic sequence is consistent with a proportion of the corresponding first data in the first characteristic sequence; the target characteristic sequence has the same data change trend as the first characteristic sequence, and the second characteristic sequence is a data sequence in the sampling sequence corresponding to the first characteristic sequence.

13. An electronic device, characterized in that: A chip comprising any one of claims 7 to 12.

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