Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of improving reliability. According to an embodiment, a semiconductor storage device includes a first memory string SR, a first word line WL, a second word line WL, a first select gate line SGD, a second select gate line SGS, and a control circuit 16. The first memory string SR includes a first select transistor ST1, a first memory cell MT, a second memory cell MT, and a second select transistor ST2. The control circuit 16 repeatedly performs a program loop including a program operation and a program verify operation in a write operation to the first memory cell MT, and after the repetition of the program loop ends, performs a first operation of applying a first voltage VREAD to the first and second word lines, and applying a second voltage VSG to the first and second select gate lines.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on July 25, 2018, with application number 201810825378.3 and title "Semiconductor Memory Device".

[0003] [Related Applications]

[0004] This application claims priority to Japanese Patent Application No. 2017-252186 (filed on December 27, 2017). This application incorporates the entire contents of that basic application by reference. Technical Field

[0005] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0006] As a semiconductor memory device, NAND (Not-And) flash memory is known. Summary of the Invention

[0007] The implementation provides a semiconductor memory device that can improve reliability.

[0008] The semiconductor memory device of the embodiment includes: a first memory string, including a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor connected in series; a first word line connected to the gate of the first memory cell; a second word line connected to the gate of the second memory cell; a first selection gate line connected to the gate of the first selection transistor; a second selection gate line connected to the gate of the second selection transistor; and a control circuit for controlling a write operation. During the write operation to the first memory cell, the control circuit repeatedly performs a programming loop including programming and programming verification operations. After the programming loop ends, it performs a first operation: applying a first voltage to the first and second word lines to enable the first and second memory cells, and applying a second voltage to the first and second selection gate lines to enable the first and second selection transistors. Attached Figure Description

[0009] Figure 1 This is a block diagram of the semiconductor memory device according to the first embodiment.

[0010] Figure 2 This is a circuit diagram of the memory cell array included in the semiconductor memory device of the first embodiment.

[0011] Figure 3 This is a cross-sectional view of the memory cell array included in the semiconductor memory device of the first embodiment.

[0012] Figure 4 This diagram shows the connection of the line decoder included in the semiconductor memory device of the first embodiment.

[0013] Figure 5 This is a flowchart of the write operation in the semiconductor memory device of the first embodiment.

[0014] Figure 6 This is a timing diagram showing the voltage of each wiring during the write operation in the semiconductor memory device of the first embodiment.

[0015] Figure 7 This is an example of a timing diagram representing the voltage of the word line and the channel of the NAND string during the readout operation.

[0016] Figure 8 This is a timing diagram showing the voltage of each wiring during the write operation in the semiconductor memory device of the second embodiment.

[0017] Figure 9 This is a timing diagram showing the voltage of each wiring during the write operation in the semiconductor memory device of the second embodiment. Detailed Implementation

[0018] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In this description, common reference numerals will be used to label common parts across all figures.

[0019] 1. First Implementation Method

[0020] The semiconductor memory device according to the first embodiment will be described. Hereinafter, a three-dimensional stacked NAND flash memory in which memory cell transistors are three-dimensionally stacked on a semiconductor substrate will be used as an example for description as a semiconductor memory device. However, the semiconductor memory device is not limited to a three-dimensional stacked NAND flash memory, and can also be applied to a planar NAND flash memory in which memory cell transistors are disposed on a semiconductor substrate.

[0021] 1.1 Regarding the composition

[0022] 1.1.1 Overall Structure of Semiconductor Memory Devices

[0023] First, use Figure 1 The overall structure of a semiconductor memory device is explained. Furthermore, in... Figure 1 In the example, arrows are used to indicate a part of the connection between the blocks, but the connection is not limited to this.

[0024] picture Figure 1As shown, the semiconductor memory device 1 includes a memory cell array 10, a row decoder 11 (11a and 11b), a row driver 13, a readout amplifier 14, a voltage generation circuit 15, and a sequence generator 16.

[0025] The memory cell array 10 has eight blocks BLK (BLK0 to BLK7) that are collections of non-volatile memory cell transistors. Each block BLK has four string cells SU (SU0 to SU3) that are collections of NAND strings SR connected in series with the memory cell transistors. Furthermore, the number of blocks BLK in the memory cell array 10 and the number of string cells SU in the blocks BLK are arbitrary.

[0026] Horizontal decoder 11a is configured corresponding to blocks BLK0, BLK1, BLK5, and BLK6. Horizontal decoder 11b is configured corresponding to blocks BLK2, BLK3, BLK6, and BLK7. Horizontal decoders 11a and 11b each contain block decoders 12a and 12b. Block decoders 12a and 12b decode the horizontal address RA and, based on the decoding result, select the horizontal direction of the corresponding block BLK. Then, horizontal decoders 11a and 11b output the required voltage to the corresponding block BLK.

[0027] The line driver 13 supplies the voltage required for writing, reading, and deleting data to the line decoders 11a and 11b.

[0028] The sense amplifier 14 senses the data read from the memory cell transistor during data reading. Additionally, during data writing, it transmits the write data to the memory cell transistor.

[0029] The voltage generation circuit 15 generates the voltage required for writing, reading and deleting data, and supplies it to, for example, the line driver 13 and the sense amplifier 14.

[0030] The sequence generator 16 controls the overall operation of the semiconductor memory device 1. More specifically, the sequence generator 16 controls the line decoders 11a and 11b, the line driver 13, the sense amplifier 14, and the voltage generation circuit 15, etc. Furthermore, the sequence generator 16 internally includes a register 17. The register 17 stores various operation settings. The register 17 holds parameters indicating whether a dummy read is performed after a write operation. For example, if the register address corresponding to the dummy read in register 17 is set to "0", the sequence generator 16 does not perform a dummy read after a write operation ("disable"). Conversely, if the register address corresponding to the dummy read in register 17 is set to "1", the sequence generator 16 performs a dummy read after a write operation ("enable"). The parameter settings corresponding to the presence or absence of dummy reads are, for example, set at the factory.

[0031] 1.1.2 Regarding the composition of the memory cell array

[0032] Next, use Figure 2 The configuration of the memory cell array 10 will be described. Furthermore, Figure 2 The example shows the structure of block BLK0, and the structures of blocks BLK1 to BLK3 are the same as those of block BLK0.

[0033] picture Figure 2 As shown, each NAND string SR includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage layer, and non-volatilely retain data. Each memory cell transistor MT can hold more than one bit of data.

[0034] Furthermore, the memory cell transistor MT can be a MONOS (metal-oxide-nitride-oxide-semiconductor) type, which uses an insulating film in the charge storage layer, or an FG (floating gate) type, which uses a conductive layer in the charge storage layer. In this embodiment, the MONOS type will be used as an example for explanation. Additionally, the number of memory cell transistors MT is not limited to 8; it can be 16, 32, 64, 96, 128, etc. Furthermore, the number of transistors ST1 and ST2 can be arbitrary, as long as there is at least one of each.

[0035] Eight memory cell transistors MT are connected in series between the source of select transistor ST1 and the drain of select transistor ST2. More specifically, the current paths of memory cell transistors MT0 to MT7 are connected in series. Furthermore, the drain of memory cell transistor MT7 is connected to the source of select transistor ST1, and the source of memory cell transistor MT0 is connected to the drain of select transistor ST2.

[0036] The gates of the selection transistor ST1 in each of the series units SU0 to SU3 are respectively connected to selection gate lines SGD0 to SGD3. Similarly, the gates of the selection transistor ST2 in each of the series units SU0 to SU3 are respectively connected to selection gate lines SGS0 to SGS3. Hereinafter, selection gate lines SGD0 to SGD3 are not limited to selection gate lines, and selection gate lines SGS0 to SGS3 are not limited to selection gate lines, and are referred to as selection gate lines SGS. In addition, the selection gate lines SGS0 to SGS3 of each series unit SU may also be connected in a common manner.

[0037] The control gates of the memory cell transistors MT0 to MT7 located within block BLK are respectively connected to word lines WL0 to WL7. Hereinafter, without limiting word lines WL0 to WL7, they will be referred to as word lines WL.

[0038] The drains of the select transistors ST1 of each NAND string SR located within a string cell SU are connected to different bit lines BL0 to BL(N-1) (where N is an integer greater than or equal to 2). Hereinafter, without limitation, bit lines BL0 to BL(N-1) will be referred to as bit lines BL. Each bit line BL is connected to one NAND string SR located within each string cell SU via a shared ground connection among multiple block BLKs. Furthermore, the sources of multiple select transistors ST2 are shared ground connection to the source line SL. In other words, a string cell SU is a collection of NAND string SRs connected to different bit lines BL and connected to the same select gate lines SGD and SGS. Additionally, a block BLK is a collection of multiple string cells SUs sharing a word line WL. Moreover, the memory cell array 10 is a collection of multiple block BLKs sharing a bit line BL.

[0039] Regarding data writing and reading, each memory cell transistor MT connected to any word line WL in any string cell SU is performed at once. Hereinafter, the set of 1 bits of data written to each of the selected memory cell transistors MT at one time, or read from each of them, is called a "page".

[0040] 1.1.3 Cross-sectional configuration of the memory cell array

[0041] Next, use Figure 3 The cross-sectional configuration of the storage cell array 10 will be described. Figure 3 The examples show the cross-sections of string elements SU0 and SU1, and the configurations of string elements SU2 and SU3 are also the same. Furthermore, in Figure 3 The interlayer insulating film is omitted.

[0042] picture Figure 3 As shown, a plurality of source line contacts LI are provided along a first direction D1 parallel to the semiconductor substrate 100 and extending in a second direction D2 parallel to the semiconductor substrate 100 and perpendicular to the first direction D1. A string unit SU is disposed between two source line contacts LI. The source line contacts LI connect the semiconductor substrate 100 to a source line SL (not shown) disposed above the NAND string SR. Furthermore, the arrangement of the source line contacts LI and the NAND string SR can be arbitrarily set. For example, multiple string units SU can also be provided between two source line contacts LI. Furthermore, in Figure 3 In the example, for simplicity, the illustration shows the case where multiple NAND strings SR are arranged in a column along the second direction D2 within a string unit SU. However, the arrangement of NAND strings SR within a string unit SU can be arbitrarily set. For example, they can be arranged side-by-side along the second direction D2, or they can be arranged in a staggered configuration of four columns.

[0043] In each string cell SU, a NAND string SR is formed along a third direction D3 perpendicular to the semiconductor substrate 100. More specifically, an n-type well 101 is provided on the surface region of the semiconductor substrate 100. Furthermore, a p-type well 102 is provided on the surface region of the n-type well 101. Additionally, an n-type well 102 is provided on a portion of the surface region of the p-type well 102. + A p-type diffusion layer 103 is formed. Furthermore, above the p-type well 102, ten wiring layers 104 are sequentially deposited, serving as the select gate line SGS, word lines WL0 to WL7 connected to the memory cell transistors MT0 to MT7, and select gate line SGD, with each layer separated by an interlayer insulating film (not shown).

[0044] Furthermore, a columnar semiconductor layer 105 is formed, penetrating the 10 wiring layers 104 and reaching the p-type well 102. A tunnel insulating film 106, a charge storage layer 107, and a barrier insulating film 108 are sequentially formed on the sides of the semiconductor layer 105. The semiconductor layer 105 is, for example, made of polysilicon. The tunnel insulating film 106 and the barrier insulating film 108 are, for example, made of silicon oxide films. The charge storage layer 107 is, for example, made of silicon nitride films. The semiconductor layer 105 functions as a current path for the NAND string SR and forms the channel region for forming each transistor. Moreover, the upper end of the semiconductor layer 105 is connected to a wiring layer 110 extending in the first direction D1 via a contact plug 109. The wiring layer 110 functions as a bit line BL.

[0045] Hereinafter, the pillar formed by the semiconductor layer 105, the tunnel insulating film 106, the charge storage layer 107, and the barrier insulating film 108 will be referred to as the "memory pillar MP". The memory pillar MP and word lines WL0 to WL7 constitute the memory cell transistors MT0 to MT7. Similarly, the memory pillar MP and the select gate lines SGD and SGS constitute the select transistors ST1 and ST2, respectively.

[0046] In addition, Figure 3 In the example, the wiring layer 104, which functions as the gate line selection SGD and SGS, is provided as one layer, but multiple layers can also be provided.

[0047] The source line contact LI has a line shape along the second direction D2. The source line contact LI is, for example, made of polysilicon. Furthermore, the bottom surface of the source line contact LI is connected to n. + The diffusion layer 103 has its upper surface connected to a wiring layer (not shown) that functions as the source line SL.

[0048] Furthermore, the configuration of the memory cell array 10 can also be other configurations. That is, the configuration of the memory cell array 10 is described, for example, in U.S. Patent Application No. 12 / 407,403, filed on March 19, 2009, entitled "Three-dimensional stacked non-volatile semiconductor memory". Additionally, the contents of U.S. Patent Application No. 12 / 406,524, filed March 18, 2009, entitled "Three-dimensional stacked non-volatile semiconductor memory," U.S. Patent Application No. 12 / 679,991, filed March 25, 2010, entitled "Non-volatile semiconductor memory device and method of manufacturing the same," and U.S. Patent Application No. 12 / 532,030, filed March 23, 2009, entitled "Semiconductor memory and method of manufacturing the same," are incorporated herein by reference in their entirety.

[0049] 1.1.4 Regarding the structure of the line decoder

[0050] Next, use Figure 4The configuration of line decoders 11a and 11b is explained. Furthermore, in Figure 4 In the example, for simplicity, it means any one of the word lines WL0 to WL7, any one of the select gate lines SGS0 to SGS3, and any one of the select gate lines SGD0 to SGD3 connected to a block BLK. Furthermore, in the following description, without specifying the source and drain of the transistor, either the source or drain of the transistor will be referred to as "one end of the transistor," and the other will be referred to as "the other end of the transistor."

[0051] picture Figure 4 As shown, the line decoder 11a includes a block decoder 12a and multiple n-channel MOS (Metal Oxide Semiconductor) transistors 32a, 33a, 34a, and 35a. Similarly, the line decoder 11b includes a block decoder 12b and multiple n-channel MOS transistors 32b, 33b, 34b, and 35b.

[0052] Block decoder 12a determines the logic levels of signal lines BLKSEL1 and BLKSEL1n based on the row address RA, thereby controlling the on / off states of transistors 32a, 33a, 34a, and 35a. Similarly, block decoder 12b determines the logic levels of signal lines BLKSEL2 and BLKSEL2n based on the row address RA, thereby controlling the on / off states of transistors 32b, 33b, 34b, and 35b.

[0053] Transistors 32a, 32b, 33a, 33b, 34a, 34b, 35a, and 35b function as block selection transistors connecting the corresponding block BLK to the row driver 13 via signal line CGI. In the following description, unless otherwise specified, transistors 32a and 32b, 33a and 33b, 34a and 34b, and 35a and 35b are referred to as transistors 32, 33, 34, and 35.

[0054] More specifically, transistors 32a are configured to correspond to the word lines WL (WL0 to WL7) of blocks BLK0, BLK1, BLK4, and BLK5, respectively. The gates of transistors 32a corresponding to each BLK block are connected to the signal line BLKSEL1 via a common ground. One end of transistor 32a corresponding to block BLK0 is connected to any one of the word lines WL of block BLK0, and the other end of transistor 32a is connected to the line driver 13 via the signal line CGI. One end of transistor 32a corresponding to block BLK1 is connected to any one of the word lines WL of block BLK1, and the other end of transistor 32a is connected to the line driver 13 via a different signal line CGI than that corresponding to transistor 32a of block BLK0. One end of transistor 32a corresponding to block BLK4 is connected to any one of the word lines WL of block BLK4, and the other end of transistor 32a is connected to the line driver 13 via a different signal line CGI than that corresponding to transistors 32a of blocks BLK0 and BLK1. One end of transistor 32a corresponding to block BLK5 is connected to any one of the word lines WL of block BLK5, and the other end of transistor 32a is connected to line driver 13 via a different signal line CGI than that of transistor 32a corresponding to blocks BLK0, BLK1 and BLK4.

[0055] Transistors 33a and 34a are respectively configured to correspond to the select gate lines SGD (SGD0 to SGD3) of blocks BLK0, BLK1, BLK4, and BLK5. The gates of transistors 33a corresponding to each BLK block are connected to a common ground on the signal line BLKSEL1n. One end of transistor 33a corresponding to block BLK0 is connected to any one of the select gate lines SGD of block BLK0, and the other end of transistor 33a is grounded. One end of transistor 33a corresponding to block BLK1 is connected to any one of the select gate lines SGD of block BLK1, and the other end of transistor 33a is grounded. One end of transistor 33a corresponding to block BLK4 is connected to any one of the select gate lines SGD of block BLK4, and the other end of transistor 33a is grounded. One end of transistor 33a corresponding to block BLK5 is connected to any one of the select gate lines SGD of block BLK5, and the other end of transistor 33a is grounded.

[0056] The gates of transistors 34a corresponding to each BLK block are connected to a common ground on signal line BLKSEL1. One end of transistor 34a corresponding to block BLK0 is connected to any one of the select gate lines SGD of block BLK0, and the other end of transistor 34a is connected to the horizontal driver 13 via signal line CGI. One end of transistor 34a corresponding to block BLK1 is connected to any one of the select gate lines SGD of block BLK1, and the other end of transistor 34a is connected to the horizontal driver 13 via a different signal line CGI than that corresponding to transistor 34a in block BLK0. One end of transistor 34a corresponding to block BLK4 is connected to any one of the select gate lines SGD of block BLK4, and the other end of transistor 34a is connected to the horizontal driver 13 via a different signal line CGI than that corresponding to transistors 34a in blocks BLK0 and BLK1. One end of transistor 34a corresponding to block BLK5 is connected to any of the select gate lines SGD of block BLK5, and the other end of transistor 34a is connected to line driver 13 via a different signal line CGI than that of transistors 34a corresponding to blocks BLK0, BLK1 and BLK4.

[0057] Transistors 35a are configured to correspond to the select gate lines SGS (SGS0 to SGS3) of blocks BLK0, BLK1, BLK4, and BLK5, respectively. The gates of transistors 35a corresponding to each BLK block are connected to a common ground on signal line BLKSEL1. One end of transistor 35a corresponding to block BLK0 is connected to any one of the select gate lines SGS of block BLK0, and the other end of transistor 35a is connected to the horizontal driver 13 via signal line CGI. One end of transistor 35a corresponding to block BLK1 is connected to any one of the select gate lines SGS of block BLK1, and the other end of transistor 35a is connected to the horizontal driver 13 via a different signal line CGI than that corresponding to transistor 35a of block BLK0. One end of transistor 35a corresponding to block BLK4 is connected to any one of the select gate lines SGS of block BLK4, and the other end of transistor 35a is connected to the horizontal driver 13 via a different signal line CGI than that corresponding to transistors 35a of blocks BLK0 and BLK1. One end of transistor 35a corresponding to block BLK5 is connected to any of the select gate lines SGS of block BLK5, and the other end of transistor 35a is connected to line driver 13 via a different signal line CGI than that of transistor 35a corresponding to blocks BLK0, BLK1 and BLK4.

[0058] Like transistor 32a, transistor 32b is configured corresponding to the word lines WL (WL0 to WL7) of blocks BLK2, BLK3, BLK6, and BLK7, respectively. The gates of transistors 32b corresponding to each BLK block are connected to the signal line BLKSEL2 via a common ground. One end of transistor 32b is connected to any one of the word lines WL of the corresponding BLK block, and the other end of transistor 32b is connected to the line driver 13 via different signal lines CGI. Furthermore, in Figure 4 In the example, the other end of transistor 32a of block BLK0 and the other end of transistor 32b of block BLK2 are connected to the same signal line CGI, but they can also be connected to different signal lines CGI. The relationship between transistor 32a of block BLK1 and transistor 32b of block BLK3, transistor 32a of block BLK2 and transistor 32b of block BLK6, and transistor 32a of block BLK3 and transistor 32b of block BLK7 is the same.

[0059] Transistors 33b and 34b, like transistors 33a and 34b, are respectively configured to correspond to the select gate lines SGD of blocks BLK2, BLK3, BLK6, and BLK7. The gates of transistors 33b corresponding to each BLK block are connected to a common ground on signal line BLKSEL2n, and the gates of transistors 34b corresponding to each BLK block are connected to a common ground on signal line BLKSEL2. One end of transistor 33b is connected to any one of the select gate lines SGD of the corresponding BLK block, and the other end of transistor 33b is grounded. One end of transistor 34b is connected to any one of the select gate lines SGD of the corresponding BLK block, and the other end of transistor 34b is connected to the line driver 13 via different signal lines CGI. Furthermore, in Figure 4 In the example, the other end of transistor 34a of block BLK0 and the other end of transistor 34b of block BLK2 are connected to the same signal line CGI, but they can also be connected to different signal lines CGI. The relationship between transistor 34a of block BLK1 and transistor 34b of block BLK3, transistor 34a of block BLK2 and transistor 34b of block BLK6, and transistor 34a of block BLK3 and transistor 34b of block BLK7 is the same.

[0060] Like transistor 35a, transistor 35b is configured corresponding to the select gate line SGS of blocks BLK2, BLK3, BLK6, and BLK7, respectively. The gate of transistor 35b corresponding to each BLK block is connected to a common ground on signal line BLKSEL2. One end of transistor 35b is connected to any one of the select gate lines SGS of the corresponding BLK block, and the other end of transistor 35b is connected to the horizontal driver 13 via different signal lines CGI. Furthermore, in Figure 4In the example, the other end of transistor 35a in block BLK0 and the other end of transistor 35b in block BLK2 are connected to the same signal line CGI, but they can also be connected to different signal lines CGI. The relationship between transistor 35a in block BLK1 and transistor 35b in block BLK3, transistor 35a in block BLK2 and transistor 35b in block BLK6, and transistor 35a in block BLK3 and transistor 35b in block BLK7 is the same.

[0061] For example, during data writing, reading, or deletion, if the row address RA matches the block BLK0 corresponding to block decoder 12a, block decoder 12a applies a high ("H") voltage to signal line BLKSEL1 and a low ("L") voltage (e.g., ground voltage VSS) to signal line BLKSEL1n. Consequently, transistors 32a, 34a, and 35a corresponding to blocks BLK0, BLK1, BLK4, and BLK5 are turned on, and transistor 33a is turned off. Conversely, block decoder 12b applies an L voltage to signal line BLKSEL2 and an H voltage to signal line BLKSEL2n. Consequently, transistors 32b, 34b, and 35b corresponding to blocks BLK2, BLK3, BLK6, and BLK7 are turned off, and transistor 33b is turned on. In this state, the row driver 13 applies the required voltage to the word line WL of block BLK0 and the select gate lines SGD and SGD based on the row address RA.

[0062] 1.2 Regarding write operations

[0063] Next, the write operation will be explained. The write operation includes a programming operation and a programming verification operation. By repeatedly performing a combination of programming and programming verification operations (hereinafter referred to as the "programming loop"), the threshold voltage of the memory cell transistor MT rises to the target level. Furthermore, the write operation includes the on / off operation of the block select transistor and a pseudo-read operation. The on / off operation of the block select transistor and the pseudo-read operation are executed after the repetition of the programming loop ends.

[0064] Programming is an action that raises the threshold voltage by injecting electrons into the charge accumulation layer (or maintains the threshold voltage by inhibiting injection). Hereinafter, the action that raises the threshold voltage will be referred to as a "0" programming action, which applies a voltage (e.g., voltage VSS) corresponding to "0" data to the bit line BL that is to be programmed as "0" from the sense amplifier 20. On the other hand, the action that maintains the threshold voltage will be referred to as a "1" programming action or "write inhibit," which applies a voltage (hereinafter referred to as "voltage VBL1") corresponding to "1" data to the bit line BL that is to be programmed as "1" from the sense amplifier 20. Hereinafter, the bit line corresponding to the "0" programming action will be referred to as BL ("0"), and the bit line corresponding to the "1" programming action will be referred to as BL ("1").

[0065] The programming verification action is the action performed after programming, which involves reading the data and determining whether the threshold voltage of the memory cell transistor MT has reached the target level.

[0066] The block select transistor is turned on / off after the programming cycle has finished. This is done to reduce the leakage current of the block select transistors (32, 34, and 35) to turn off the block BLK (hereinafter referred to as "select block BLK") corresponding to the block being written. By turning the block select transistors on / off, the gate voltage of the block select transistor drops to voltage VSS.

[0067] A pseudo-read operation is the action of applying voltages to the word line WL, as well as the select gate lines SGD and SGS, during the read operation. Unlike a normal read operation, no positive voltage is applied to the bit line BL and the source line SL during a pseudo-read operation, and no data is read. Furthermore, data from any memory cell transistor MT can be read during a pseudo-read operation.

[0068] 1.2.1 The entire process of the write operation

[0069] Next, use Figure 5 The entire process of the write operation is explained.

[0070] picture Figure 5 As shown, the sequence generator 16 receives a write command (instruction, address, write data) from the unillustrated external controller (step S1).

[0071] The sequence generator 16 initiates the writing action based on the write command, and executes the programming action (step S2).

[0072] When the programming action ends, sequence generator 16 performs the programming verification action (step S3).

[0073] If the programming verification action fails (step S4_No), that is, if the threshold voltage of the memory cell transistor MT, which is the object of the "0" programming action, does not reach the target level, the sequence generator 16 checks whether the number of programming cycles has reached the preset upper limit.

[0074] If the maximum number of programming loop iterations has not been reached (step S5_No), the process returns to step S2, and the sequence generator 16 performs the programming action again. On the other hand, if the maximum number of programming loop iterations has been reached (step S5_Yes), the sequence generator 16 terminates the programming loop.

[0075] Additionally, if the programming verification action has passed (step S4_ is), the sequence generator 16 terminates the programming loop.

[0076] When the programming cycle ends, the sequence generator 16 performs the on / off operation of the block selection transistors (step S6). More specifically, after the programming cycle ends, with voltage VSS applied to the word line WL and the select gate lines SGD and SGS, the sequence generator 16 sets transistors 32, 34, and 35 corresponding to the selection block BLK to the off state. Then, after temporarily setting transistors 32, 34, and 35 to the on state, the sequence generator 16 sets transistors 32, 34, and 35 to the off state again.

[0077] The sequence generator 16 performs a pseudo-read (step S7) after the block select transistor is turned on / off. This ends the write operation.

[0078] 1.2.2 Regarding the voltage of each wiring line during the write operation

[0079] Next, use Figure 6 The voltage of each wiring line during the write operation is explained. Figure 6 The example shows the first programming loop (programming action and programming verification action) when block BLK0 is the write object, the programming verification action in the last programming loop, the turn-on / turn-off action of the block select transistor, and the pseudo-read action.

[0080] picture Figure 6As shown, the period from t1 to t5 represents the first programming operation (reference symbol "PGM"), and the period from t6 to t9 represents the first programming verification operation (reference symbol "P-VFY"). Furthermore, the period from t10 to t13 represents the final programming verification operation (reference symbol "P-VFY"), the period from t14 to t16 represents the on / off operation of the block select transistor (reference symbol "W-CLK"), and the period from t17 to t19 represents the pseudo-read operation (reference symbol "DM-RD"). Moreover, the voltage of each wiring in the programming verification operation is the same as the voltage of each wiring in the read operation.

[0081] First, at time t0, the block decoder 12a corresponding to block BLK0 applies voltage VBLKSEL to signal line BLKSEL1 to set it to H level, and applies voltage VSS to signal line BLKSEL1n (not shown) to set it to L level. Voltage VBLKSEL is the voltage that sets transistors 32, 34, and 35 to the ON state. Therefore, transistors 32a, 34a, and 35a are set to the ON state, and transistor 33a is set to the OFF state.

[0082] Next, the first programming action will be explained in detail.

[0083] At time t1, the readout amplifier 14 applies voltage VSS to the bit line BL ("0") corresponding to the "0" programming action and voltage VBL1 to the bit line BL ("1") corresponding to the "1" programming action.

[0084] The row driver 13 applies a voltage VSGD1 to the select gate line SGD (reference symbol "select SGD") of the select string unit SU of the select block BLK. If the threshold voltage of the select transistor ST1 is set to Vtsg, then the voltage VSD1 is a voltage greater than or equal to "VBL1 + Vtsg", and is the voltage that sets the select transistor ST1 to the on state. On the other hand, the row driver 13 applies a voltage VSS to the select gate line SGD (reference symbol "non-select SGD") of the non-select string unit SU of the select block BLK, and sets the corresponding select transistor ST1 to the off state. In addition, the row driver 13 applies a voltage VSS to the select gate line SGS (reference symbol "select SGS") of the select string unit SU and the select gate line SGS (reference symbol "non-select SGS") of the non-select string unit SU, and sets the select transistor ST2 to the off state.

[0085] Additionally, a voltage VCELSRC1 (>VSS) is applied to the source line SL via, for example, a source line driver (not shown).

[0086] At time t2, row driver 13 applies voltage VSGD2 to the select gate line SGD of select string cell SU. Voltage VSGD2 is lower than voltages VSGD1 and VBL1, and is a voltage that turns on select transistor ST1 with applied voltage VSS, but turns off select transistor ST1 with applied voltage VBL1. As a result, the channel of NAND string SR corresponding to bit line BL ("1") becomes floating.

[0087] At time t3, row driver 13 applies voltage VPASS to the non-select word line WL (reference symbol "non-select WL") of the select block BLK. Voltage VPASS is the voltage that sets the memory cell transistor MT to the on state regardless of its threshold voltage. Additionally, row driver 13 applies voltage VPGM to the select word line WL (reference symbol "select WL") of the select block BLK. Voltage VPGM is a high voltage used to inject electrons into the charge accumulation layer 107. Voltage VPGM and voltage VPASS are in the relationship that VPGM > VPASS. Furthermore, row driver 13 may apply voltage VPGM to the select word line WL after applying voltage VPASS.

[0088] In the NAND string SR corresponding to bit line BL (“0”), the select transistor ST1 becomes on, thus the channel potential of the memory cell transistor MT connected to the select word line WL becomes VSS. Therefore, the potential difference between the control gate and the channel (VPGM-VSS) increases. As a result, electrons are injected into the charge accumulation layer 107, and the threshold voltage of the memory cell transistor MT corresponding to bit line BL (“0”) rises.

[0089] In the NAND string SR corresponding to bit line BL (“1”), the select transistor ST1 becomes off, and thus the channel of the memory cell transistor MT connected to the select word line WL becomes electrically floating. As a result, the channel potential rises due to capacitive coupling with word line WL, etc. Therefore, the potential difference between the control gate and the channel becomes smaller than that of the memory cell transistor MT corresponding to bit line BL (“0”). Consequently, electrons are essentially not injected into the charge accumulation layer 107, and the threshold voltage of the memory cell transistor MT corresponding to bit line BL (“1”) is maintained (the higher the threshold voltage distribution, the less it changes).

[0090] During the period from time t4 to t5, the recovery process is performed, and the programming action ends.

[0091] Next, the first program verify operation will be described in detail. At time t6, the row driver 13 applies a voltage VSG to the select gate lines SGD and SGS of the selected string unit SU, applies a read voltage VCGRV to the selected word line WL, and applies a voltage VREAD to the unselected word lines WL. The voltage VSG is a voltage that turns on the select transistors ST1 and ST2. The voltage VCGRV is a voltage corresponding to the threshold level of data to be read. The voltage VREAD is a voltage applied to unselected word lines WL during a read operation, and the memory cell transistor MT whose control gate is applied with the voltage VREAD is turned on regardless of the data it holds. The voltage VCGRV and the voltage VREAD satisfy the relationship of VCGRV < VREAD.

[0092] At time t7, the sense amplifier 14 applies a voltage VBL2 to the bit line BL. The voltage VBL2 is a voltage applied to the bit line BL during a read operation. In addition, for the source line SL, a voltage VCELSRC2 is applied via the source line driver. The voltage VBL2 and the voltage VCELSRC2 satisfy the relationship of VBL2 > VCELSRC2 (> VSS).

[0093] During the period from time t7 to t8, the sense amplifier 14 senses, for example, the current flowing in the bit line BL. More specifically, when the threshold voltage of the memory cell transistor MT to be read is equal to or higher than the voltage VCGRV, the memory cell transistor MT is turned off (hereinafter referred to as an "off cell"), and substantially no current flows from the corresponding bit line BL to the source line SL. On the other hand, when the threshold voltage of the memory cell transistor MT to be read is lower than the voltage VCGRV, the memory cell transistor MT is turned on (hereinafter referred to as an "on cell"), and current flows from the corresponding bit line BL to the source line SL. The sequence generator 16 determines that the program verify operation is passed when the number of on cells is less than a preset number, and determines that the program verify operation is failed when the number of on cells is equal to or greater than the preset number.

[0094] During the period from time t8 to t9, recovery processing is performed, and the program verify operation ends. Furthermore, in a case where the memory cell transistor MT can hold data of 2 or more bits and program verify operations for a plurality of threshold levels are performed, the period from time t6 to t9 is repeated for each threshold level. In this case, the voltage VCGRV corresponding to the threshold level is set respectively.

[0095] During the period from time t9 to t10, the program operation in a plurality of program cycles and the last program cycle is executed.

[0096] Next, the programming verification actions in the final programming loop will be explained. The actions from time t10 to t13 are the same as those from time t6 to t9. In the final programming verification action, for example, if the number of conducting units falls below the preset number, the programming verification action will be passed.

[0097] During the period from t13 to t14, if the programming loop ends, the block decoder 12a applies voltage VSS to signal line BLKSEL1 to set it to L level, and applies voltage VBLKSEL to signal line BLKSEL1n to set it to H level. As a result, transistors 32a, 34a, and 35a are set to the off state, and transistor 33a is set to the on state.

[0098] Next, the on / off operation of the block select transistor will be explained in detail.

[0099] During the period from t14 to t15, block decoder 12a applies voltage VBLKSEL to signal line BLKSEL1 and voltage VSS to signal line BLKSEL1n. As a result, transistors 32a, 34a, and 35a are set to the on state, and transistor 33a is set to the off state.

[0100] During the period from t15 to t16, block decoder 12a applies voltage VSS to signal line BLKSEL1 to set it to L level, and applies voltage VBLKSEL to signal line BLKSEL1n to set it to H level. As a result, transistors 32a, 34a, and 35a are set to the off state, and transistor 33a is set to the on state.

[0101] At time t16, block decoder 12a applies voltage VBLKSEL to signal line BLKSEL1 and voltage VSS to signal line BLKSEL1n for pseudo-reading operation.

[0102] Next, the pseudo-reading action will be explained in detail.

[0103] At time t17, row driver 13 applies voltage VSG to the select gate lines SGD and SGS of the select string unit SU of the select block BLK, and to the select gate line SGS of the non-select string unit SU. Additionally, row driver 13 applies voltage VREAD to the select word line WL and the non-select word line of the select block BLK. Alternatively, instead of applying voltage VSG to the select gate line SGS of the non-select string unit SU, voltage VSG may be applied to the select gate line SGD of the non-select string unit SU.

[0104] During time intervals t18 to t19, a recovery process is performed, and the pseudo-readout action ends.

[0105] At time t19, block decoder 12a applies voltage VSS to signal line BLKSEL1 to set it to L level, and applies voltage VBLKSEL to signal line BLKSEL1n to set it to H level. As a result, transistors 32a, 34a, and 35a are set to the off state, and transistor 33a is set to the on state.

[0106] 1.3 Effects of this implementation method

[0107] If this embodiment is configured, then reliability can be improved. This effect will be described in detail.

[0108] In a NAND flash memory 1 with storage cells stacked in three dimensions, the channels of the storage cell transistors MT that constitute the NAND string SR are, for example, like... Figure 3 The structure shown is a common semiconductor layer 105. In this type of NAND flash memory 1, for example, there exists a structure that generates... Figure 7 The situation described is as shown. Figure 7 This represents an example of the voltage of the word line WL and the channel of the NAND string SR during a read operation.

[0109] picture Figure 7 As shown, when performing a read operation, the row driver 13 applies a voltage VREAD to the non-selected word line WL of the selected block BLK. At this time, the channel voltage rises to VCELSRC2 + VBL2. However, the voltage (VCELSRC2 + VBL2) is less than the voltage VREAD, for example, by a voltage difference of several volts. When the read data is determined, the row driver 13 causes the voltage of the non-selected word line WL to drop to the ground voltage VSS. At this time, the voltage of the channel of the NAND string SR drops from the ground voltage VSS to a negative voltage due to coupling with the word line WL. After the read operation, the block BLK is set to non-selected, and as a result, the word line WL becomes a floating state. In this state, if the voltage of the negative voltage channel recovers to the ground voltage VSS over time, the voltage of the word line WL will rise from the ground voltage VSS due to coupling with the channel of the NAND string SR. This phenomenon is called creepup.

[0110] In a block BLK where the voltage of the word line WL gradually increases, a potential difference is generated between the control gate and channel of the memory cell transistor MT in the block BLK, and there is a situation where the threshold voltage shifts due to the passage of time after the read operation.

[0111] Moreover, the voltage of the word line WL, which gradually increases, is like... Figure 7As shown, the voltage recovers to ground voltage VSS over time. When the voltage fluctuation of the word line WL, which has gradually increased, recovers after a further period of time, the threshold voltage of the memory cell transistor MT, which had risen, returns to its original state. Thus, the memory cell transistor MT can hold two states: a first state where the threshold voltage is initially set, and a second state where the threshold voltage shifts due to the gradual increase in voltage. For this purpose, the read voltage is optimally set to the second state, for example. Therefore, in a NAND flash memory 1 where gradual increases are possible, it is preferable to maintain the memory cell transistor MT in the second state.

[0112] During a write operation, the programming loop ends with a programming verification operation, but after the programming loop ends, the block select transistor is switched on / off. Compared to a read operation that occurs due to this on / off operation, the time for the memory cell transistor MT to transition from state 2 to state 1 is shorter. Therefore, during a read operation following a write operation, there is a tendency for the fail bit count (FBC) to increase and the retry read rate (RRR) to increase due to the state transition of the memory cell transistor MT.

[0113] Therefore, in this embodiment, a pseudo-read operation is performed after the programming cycle and the on / off operation of the block select transistor during the write operation. This suppresses the shortening of the time required for the memory cell transistor MT to transition from state 2 to state 1 after the write operation. Consequently, the increase in FBC and RRR can be suppressed during the read operation following the write operation. Therefore, the reliability of the semiconductor memory device can be improved.

[0114] Furthermore, if configured as described in this embodiment, threshold fluctuations that occur within a relatively short period after a write operation can be suppressed by performing a pseudo-read operation, i.e., short-term data retention (STDR).

[0115] Furthermore, in this embodiment, register 17 contains a register address for setting the spoofing operation, allowing the presence or absence of the spoofing operation to be set. Therefore, the presence or absence of the spoofing operation can be switched according to the purpose of the semiconductor memory device 1.

[0116] 2. Second Implementation Method

[0117] Next, the second embodiment will be described. In the second embodiment, the write operation process, which differs from that in the first embodiment, will be described. Hereinafter, only the differences from the first embodiment will be described.

[0118] 2.1 The entire process of the write operation

[0119] First, use Figure 8 The entire process of the write operation is explained.

[0120] picture Figure 8 As shown, the actions up to steps S1 to S5 are the same as those in the first embodiment. Figure 5 same.

[0121] After the programming loop ends in steps S4 and S5, the sequence generator 16 executes the programming action again (step S10). That is, the sequence generator 16 does not perform a programming verification action after the final programming action. For example, the memory cell transistor MT can hold 2 bits of data and has four distributions starting from the lowest threshold: "Er" level, "A" level, "B" level, and "C" level. In this case, the sequence generator 16 can also use the programming loop to repeatedly perform the programming action up to the "B" level, and after passing the programming verification action, perform the programming action at the "C" level without performing a programming verification action. Furthermore, the programming action can be repeated multiple times without performing a programming verification action.

[0122] When the programming action in step S10 ends, sequence generator 16, in conjunction with the first embodiment... Figure 5 Similarly, the block selection transistor is turned on / off (step S6).

[0123] The sequence generator 16 performs a pseudo-read (step S7) after the block select transistor is turned on / off. This ends the write operation.

[0124] 2.2 Regarding the voltage of each wiring line during the write operation

[0125] Next, use Figure 9 The voltage of each wiring line during the write operation is explained. Figure 9 The example shows the programming verification action of the last programming loop when block BLK0 is a write object, the last programming action after the programming loop, the turn-on / turn-off action of the block select transistor, and the pseudo-read action.

[0126] picture Figure 9 As shown, the period from t1 to t4 represents the programming verification action of the final programming cycle, and the period from t5 to t10 represents the final programming action after the programming cycle. Additionally, the period from t11 to t13 represents the on / off action of the block select transistor, and the period from t14 to t16 represents the pseudo-readout action.

[0127] The programming verification actions during times t1 to t4 are the same as those in the first implementation method. Figure 5The actions during the period from t6 to t9 described in the text are the same.

[0128] The programming actions during times t5 to t9 are the same as those in the first implementation method. Figure 5 The operation is the same during the period from t1 to t5 as described. Furthermore, regarding the voltage VPGM, the voltage is stepped up each time the programming cycle is repeated. For example, the row driver 13 applies a voltage (VPGM + DVPGM) to the select word line WL. The voltage DVPGM represents the boost voltage of VPGM.

[0129] The on / off operation of the block selection transistor during times t10 to t12 is the same as in the first embodiment. Figure 5 The actions during the period from t14 to t16 described in the text are the same.

[0130] Next, the pseudo-readout action will be explained. Furthermore, the pseudo-readout action can also be combined with that of the first embodiment. Figure 5 The actions during the period from t17 to t19 described in the text are the same.

[0131] At time t13, row driver 13 applies voltage VSG to the select gate lines SGD and SGS of the select string unit SU of the select block BLK, and the select gate line SGD of the non-select string unit SU. Additionally, row driver 13 applies voltage VREAD to the select word line WL and the non-select word line of the select block BLK.

[0132] During time t14 to t15, a recovery process is performed, and the pseudo-readout action ends.

[0133] At time t15, block decoder 12a applies voltage VSS to signal line BLKSEL1 to set it to L level, and applies voltage VBLKSEL to signal line BLKSEL1n to set it to H level. As a result, transistors 32a and 34a are set to the off state, and transistor 33a is set to the on state.

[0134] 2.3 Effects of this implementation method

[0135] According to the configuration of this embodiment, the same effects as those of the first embodiment can be obtained.

[0136] 3. Examples of variations, etc.

[0137] The semiconductor memory device of the embodiment includes: a first memory string (SR) including a first select transistor (ST1), a first memory cell (MT0), a second memory cell (MT1), and a second select transistor (ST2) connected in series; a first word line (WL0) connected to the gate of the first memory cell; a second word line (WL1) connected to the gate of the second memory cell; a first select gate line (SGD) connected to the gate of the first select transistor; a second select gate line (SGS) connected to the gate of the second select transistor; and a control circuit (16) for controlling the write operation. During the write operation to the first memory cell, the control circuit repeatedly performs a programming loop including programming and programming verification operations. After the programming loop ends, it performs a first operation (pseudo-readout) by applying a first voltage (VREAD) to the first and second word lines to enable the first and second memory cells, and applying a second voltage (VSG) to the first and second select gate lines to enable the first and second select transistors.

[0138] By applying the described embodiments, a semiconductor memory device with improved reliability can be provided.

[0139] Furthermore, the implementation method is not limited to the described method and various variations are possible.

[0140] For example, in the pseudo-read operation of the above embodiment, it means that no voltage is applied to the bit line BL and no data is read out, but for example, data of any memory cell transistor MT can also be read out.

[0141] Furthermore, in the pseudo-read operation of the above embodiment, the voltage applied to the word line WL can also be a voltage different from the voltage VREAD.

[0142] Furthermore, the term "connection" in the embodiments also includes a state of indirect connection through an intermediary such as a transistor or resistor.

[0143] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and their equivalents.

[0144] [Explanation of Symbols]

[0145] 1. Semiconductor memory device

[0146] 10-cell array

[0147] Line decoders 11, 11a, and 11b

[0148] 12a and 12b block decoders

[0149] 13-line drive

[0150] 14 Readout Amplifier

[0151] 15 Voltage Generation Circuit

[0152] 16 Sequence Generator

[0153] 17 Registers

[0154] 20 Readout Amplifier

[0155] 32, 32a, 32b, 33, 33a, 33b, 34, 34a, 34b transistors

[0156] 100 Semiconductor Substrate

[0157] 101 n-type well

[0158] 102 p-type trap

[0159] 103 n + Type diffusion layer

[0160] 104, 110 wiring layers

[0161] 105 Semiconductor Layer

[0162] 106 Tunnel Insulation Membrane

[0163] 107 Charge Accumulation Layer

[0164] 108 Barrier Insulating Film

[0165] 109 Contact plug

Claims

1. A semiconductor memory device comprising: The first memory string includes a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor connected in series; The second memory string includes a third selection transistor, a third memory cell, a fourth memory cell, and a fourth selection transistor connected in series; The first word line is connected to the gate of the first memory cell and the gate of the third memory cell; The second word line is connected to the gate of the second memory cell and the gate of the fourth memory cell; The first selected gate line is connected to the gate of the first selected transistor; The second selection gate line is connected to the gate of the second selection transistor; The third selection gate line is connected to the gate of the third selection transistor; The fourth selection gate line is connected to the gate of the fourth selection transistor; and The control circuit is configured to control the write and read operations of the first memory string; and The control circuit is: After applying the programming voltage to the first word line Perform the first action, namely, apply a first voltage to the first word line and the second word line, and apply a second voltage to at least one of the first select gate line, the second select gate line, the third select gate line, and the fourth select gate line; in, The third select gate line is subjected to a third voltage that turns the third select transistor off during the period when the programming voltage is applied to the first word line.

2. The semiconductor memory device according to claim 1, further comprising: The driving circuit is connected to the first word line via a first transistor, to the first selected gate line via a second transistor, and to the second selected gate line via a third transistor; The signal lines are connected to the gates of the first to third transistors via a common ground. and The decoder circuit is connected to the signal line; and The control circuit is as follows: after applying a programming voltage to the first word line, it performs a second action, and after performing the second action, it performs the first action. The second action is to apply a third voltage to the signal line to turn on the first to third transistors, and after applying the third voltage, it applies a fourth voltage lower than the third voltage to the signal line to turn off the first to third transistors.

3. The semiconductor memory device according to claim 1 or 2, wherein The first selection transistor also has a first bit line that is connected to the third selection transistor.

4. The semiconductor memory device according to claim 1, wherein After applying the programming voltage to the first word line Before the first action A fifth voltage is applied to the first selected gate line to turn off the first selected transistor. A sixth voltage is applied to the second selected gate line to turn off the second selected transistor. A seventh voltage is applied to the third selected gate line to turn off the third selected transistor. An eighth voltage is applied to the fourth selected gate line to turn off the fourth selected transistor.

5. The semiconductor memory device according to claim 4, wherein The fifth voltage, the sixth voltage, the seventh voltage, and the eighth voltage are the same voltage.

6. The semiconductor memory device according to claim 5, wherein The fifth voltage, the sixth voltage, the seventh voltage, and the eighth voltage are ground voltages.

7. The semiconductor memory device according to claim 1, wherein The first voltage is the voltage applied to the non-select word line during the readout operation.

8. The semiconductor memory device according to claim 1, wherein After the first action, A fifth voltage is applied to the first selected gate line to turn off the first selected transistor. A sixth voltage is applied to the second selected gate line to turn off the second selected transistor. A seventh voltage is applied to the third selected gate line to turn off the third selected transistor. An eighth voltage is applied to the fourth selected gate line to turn off the fourth selected transistor.

9. A semiconductor memory device comprising: The first memory string includes a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor connected in series respectively; The first word line is connected to the gate of the first memory cell; The second word line is connected to the gate of the second memory cell; The first selected gate line is connected to the gate of the first selected transistor; The second selection gate line is connected to the gate of the second selection transistor; The driving circuit is connected to the first word line via a first transistor, to the first selected gate line via a second transistor, and to the second selected gate line via a third transistor; The signal lines are connected to the gates of the first to third transistors via a common ground. The decoder circuit is connected to the signal line; and The control circuit controls the writing action; After the control circuit applies a programming voltage to the first memory cell, A third voltage is applied to the signal line to turn on the first to third transistors. After applying the third voltage, a fourth voltage lower than the third voltage is applied to the signal line to turn off the first to third transistors. after, A first voltage is applied to the first and second word lines to enable the first and second memory cells to conduct, and a second voltage is applied to the first and second select gate lines to enable the first and second select transistors to conduct.

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