An adaptive current comparator circuit and switching power supply circuit with delayed compensation

Abstract

This invention provides an adaptive delay-compensated current comparator circuit comprising a first current mirror, a second current mirror, a current compensation module, and a subsequent inverter. The low-voltage terminal of the first current mirror and the high-voltage terminal of the second current mirror are connected, and the connection point is the comparison voltage output terminal, which is configured to output a comparison voltage. The other low-voltage terminal of the first current mirror receives the sampling current, and the other high-voltage terminal of the second current mirror receives the reference current. The current compensation module provides compensation current between the input voltage source and the comparison voltage output terminal. The comparison voltage output terminal is connected to the input terminal of the subsequent inverter to output a logic control signal. This invention also provides a corresponding switching power supply circuit. The adaptive delay-compensated current comparator circuit provided by this invention compensates for the current error caused by parasitic delay in the circuit system by adding an additional compensation current module, thereby obtaining a delay-free and accurate inductor current.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to an adaptive delay compensation current comparison circuit. Background Technology

[0002] Current limiting control mode or zero-crossing detection mode is a method of controlling the power transistor in a switching power supply. The principle is to sample the power transistor current, compare it with an internal reference current, and control the power transistor's on / off state, thereby controlling the inductor current. In traditional current comparator circuit designs, due to parasitic capacitance, there is a response delay. This causes the sampled current to be higher (or lower) than the reference current when the power transistor is turned off, resulting in the actual inductor current being greater than (or less) than the ideal inductor current, making it impossible to stabilize the power transistor's peak (valley) current. For current limiting control mode, the response delay leads to inaccurate output current limiting values, causing excessive current and damaging the inductor. For zero-crossing detection, if the freewheeling diode turns off too late, current backflow occurs, leading to additional power loss; if the freewheeling diode turns off too early, freewheeling through the body diode also causes significant body diode power consumption.

[0003] like Figure 1 As shown, taking a peak current mode BOOST switching power supply circuit as an example, the switching power supply circuit includes an input voltage source Vin, a switching node SW connected to the input voltage source Vin through an energy storage inductor L, and an active switch S1 and a freewheeling diode S2 connected to the switching node SW. The end of the freewheeling diode S2 furthest from the switching node SW is the voltage output terminal Vout, which is grounded through an output capacitor C. The end of the active switch S1 furthest from the switching node SW is grounded. A sampling current I is provided between the active switch S1 and ground. CS The current sampling module 201 samples the active transistor current I. CS However, because the active transistor current I flows through the active transistor when the active switch S1 is turned on... CS Since the current is equal to the inductor current, the two are equivalent. The output of the current sampling module 201 is connected to the input of a current comparison circuit 202, and the other input of the current comparison circuit 202 is configured to receive a reference current I. ref The output of the current comparison circuit 202 is connected to the input of a logic control module 203, and the two outputs of the logic control module 203 are respectively connected to the gates of the active switch S1 and the freewheeling transistor S2. Therefore, the current comparison circuit 202 will use the reference current I... ref With active tube current I CS The comparison result is used as a logic control signal PWM and output to the logic control module 203, so that the logic control module 203 controls the active switch S1 and the freewheeling tube S2 to turn on and off.

[0004] Common current comparator modules such as Figure 2 As shown, the current comparator module includes two PMOS transistors (MP1 and MP2) forming the first current mirror and two NMOS transistors (MN1 and MN2) forming the second current mirror. The active transistor current I is converted into the active current I through the first and second current mirrors. CS and reference current I ref Compare and convert to comparison voltage V P The comparison voltage V P The signal is converted into a digital PWM signal by a subsequent inverter, which consists of the fifth MOSFET MP3 and the sixth MOSFET MN3. However, in the circuit, there are many parasitic capacitances in the MOSFETs. Major parasitic capacitances include the gate-drain parasitic capacitance C1 of the second MOSFET MP2, the gate-drain parasitic capacitance C2 of the fourth MOSFET MN2, and the gate-drain parasitic capacitance C3 of the sixth MOSFET MN3. All parasitic capacitances can be equivalently represented by the equivalent parasitic capacitance C connected between the comparator voltage output terminal and ground. X .

[0005] According to the traditional switching power supply circuit structure, such as Figure 1 It can be known that the inductor current I L With power supply voltage V in The relationship between the magnitude L of the energy storage inductor and time t is as follows:

[0006]

[0007] Active tube current I CS This is equivalent to proportionally reducing the external inductor current, which can be expressed as I. cs =k*I L Then the active tube current I CS The change over time can be expressed as:

[0008]

[0009] like Figure 2 As shown, due to the equivalent parasitic capacitance C X The presence of the switching threshold voltage V of the subsequent inverter TH Equivalent to current-directed equivalent parasitic capacitance C X The capacitor charging voltage, therefore the switching threshold voltage V of the subsequent inverter. TH for:

[0010]

[0011] ΔI represents the equivalent parasitic capacitance C XThe existence of this current causes a current error between the actual and ideal values, ΔI, which is equal to the active tube current I. CS and reference current I ref The difference. In formula (3), the reference current I... ref The value can be any value, depending on the specifications.

[0012] Therefore, due to the equivalent parasitic capacitance C X The resulting error delay Δt is:

[0013]

[0014] like Figure 3 It can be shown that, due to the parasitic capacitance C X The existence of V leads to V during the comparison process. P The point voltage changes relatively slowly, resulting in a slow response at the reference current I. ref and active tube current I CS When making comparisons, at the reference current I ref and active tube current I CS Once they are equal, compare the voltages V. P There is a delay of Δt before the voltage reaches the flip-flop threshold voltage of the subsequent inverter, causing the PWM signal to flip. This results in an error between the actual inductor current and the ideal inductor current, leading to inaccurate inductor current readings. Summary of the Invention

[0015] The purpose of this invention is to provide an adaptive current comparison circuit with compensation for delay, so as to avoid the delay in the current comparison circuit structure and obtain an accurate inductor current without delay.

[0016] To achieve the above objectives, the present invention provides an adaptive delay-compensated current comparison circuit comprising a first current mirror, a second current mirror, a current compensation module, and a subsequent inverter; one low-voltage terminal of the first current mirror and one high-voltage terminal of the second current mirror are connected, and the connection point is a comparison voltage output terminal, which is configured to output a comparison voltage; the other low-voltage terminal of the first current mirror serves as one input terminal of the current comparison circuit to receive a sampled current, and the other high-voltage terminal of the second current mirror serves as another input terminal of the current comparison circuit to receive a reference current; the high-voltage terminal of the first current mirror is connected to an input voltage source, and the low-voltage terminal of the second current mirror is grounded; the current compensation module is connected between the input voltage source and the comparison voltage output terminal, and is configured to provide compensation current; the comparison voltage output terminal is connected to the input terminal of the subsequent inverter, and the output terminal of the subsequent inverter is configured to output a logic control signal.

[0017] The first current mirror is composed of a first MOSFET and a second MOSFET whose gates are connected to each other. Both the first MOSFET and the second MOSFET are PMOS transistors. The gate and drain of the first MOSFET serve as a low-voltage terminal of the first current mirror to connect to the sampling current. The drain of the second MOSFET serves as a low-voltage terminal of the first current mirror to connect to the comparison voltage output terminal. The sources of the first MOSFET and the second MOSFET serve as high-voltage terminals of the first current mirror to connect to the input voltage source. The second current mirror is composed of a third MOSFET and a fourth MOSFET whose gates are connected to each other. Both the third MOSFET and the fourth MOSFET are NMOS transistors. The gate and drain of the third MOSFET serve as a high-voltage terminal of the second current mirror to connect to the reference current. The drain of the fourth MOSFET serves as a high-voltage terminal of the second current mirror to connect to the comparison voltage output terminal. The sources of the third MOSFET and the fourth MOSFET serve as low-voltage terminals of the second current mirror and are grounded.

[0018] The second MOS transistor has a gate-drain parasitic capacitance between its gate and drain, and the fourth MOS transistor has a gate-drain parasitic capacitance between its gate and drain.

[0019] The subsequent inverter consists of a fifth MOS transistor and a sixth MOS transistor. The fifth MOS transistor is a PMOS transistor, and the sixth MOS transistor is an NMOS transistor. The gates of the fifth MOS transistor and the sixth MOS transistor are connected to each other and serve as the input terminal of the subsequent inverter. The drains of the fifth MOS transistor and the sixth MOS transistor are connected to each other and serve as the output terminal of the subsequent inverter.

[0020] The sixth MOS transistor has a gate-drain parasitic capacitance between its gate and drain.

[0021] The current compensation module includes a first voltage divider resistor and a second voltage divider resistor connected in series between the input voltage source and ground. The connection point of the first and second voltage divider resistors is connected to the positive input terminal of the amplifier. The negative input terminal of the amplifier is connected to one end of a third resistor and the source of a seventh MOSFET. The other end of the third resistor is grounded. The gate of the seventh MOSFET is connected to the output terminal of the amplifier. The current compensation module also includes a third current mirror and a fourth current mirror. The high-voltage terminals of the third and fourth current mirrors are both connected to the input voltage source. One low-voltage terminal of the third current mirror is connected to the drain of the seventh MOSFET. One low-voltage terminal of the fourth current mirror is connected to a fixed bias current. The other low-voltage terminals of the third and fourth current mirrors are connected as the output terminal of the current compensation module.

[0022] The third current mirror is composed of an eighth MOS transistor and a ninth MOS transistor with their gates connected to each other. The fourth current mirror is composed of a tenth MOS transistor and an eleventh MOS transistor with their gates connected to each other. The drain and gate of the eighth MOS transistor serve as a low-voltage terminal of the third current mirror and are connected to the drain of the seventh MOS transistor. The gate and drain of the eleventh MOS transistor serve as a low-voltage terminal of the fourth current mirror and are connected to a fixed bias current. The drain of the ninth MOS transistor, which serves as a low-voltage terminal of the third current mirror, is connected to the drain of the tenth MOS transistor, which serves as a low-voltage terminal of the fourth current mirror. The eighth, ninth, tenth, and eleventh MOS transistors are all PMOS transistors, and the seventh MOS transistor is an NMOS transistor.

[0023] The compensation current ΔI is:

[0024]

[0025] Where R1 is the resistance of the first voltage divider resistor, R2 is the resistance of the second voltage divider resistor, R3 is the resistance of the third resistor, Vin is the voltage of the input voltage source, and I... O For fixed bias current.

[0026] This invention provides an adaptive delay-compensating switching power supply circuit, comprising an input voltage source, a switching node connected to the input voltage source via an energy storage inductor, and an active switching transistor and a freewheeling transistor whose drains are connected to the switching node. The active switching transistor is an NMOS power transistor, and the freewheeling transistor is a PMOS power transistor. The source of the active switching transistor is grounded via a ground wire, and the source of the freewheeling transistor is the voltage output terminal of the switching power supply circuit, which is grounded via an output capacitor. The source of the active switching transistor is connected to the input terminal of a current sampling module. The output terminal of the current sampling module is connected to one input terminal of a current comparison circuit described above to receive a sampled current. The other input terminal of the current comparison circuit is configured to receive a reference current. The output terminal of the current comparison circuit is configured to obtain and output a logic control signal based on the comparison result between the reference current and the active transistor current. The output terminal of the current comparison circuit is connected to the input terminal of a logic control module. The logic control module has two output terminals, which are respectively connected to the gates of the active switching transistor and the freewheeling transistor.

[0027] The adaptive delay-compensated current comparator circuit provided by this invention adds an additional compensation current module to offset the current error caused by parasitic delay in the circuit system, thereby avoiding delays caused by parasitic capacitance during current comparison and obtaining a delay-free and accurate inductor current. Using the current comparator design method of this invention, the compensation current can be adaptively adjusted according to changes in error, ensuring that the actual generated inductor current matches the ideal inductor current, thus obtaining a delay-free and accurate inductor current. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a traditional DC-DC boost switching power supply circuit.

[0029] Figure 2 This is a schematic diagram of the circuit structure of a traditional current comparator.

[0030] Figure 3 This is a schematic diagram of the current and voltage waveforms at each node of a traditional current comparator.

[0031] Figure 4 This is a schematic diagram of the adaptive delay compensation current compensation circuit of the present invention.

[0032] Figure 5 This is a schematic diagram of the current and voltage waveforms at each node of the adaptive delay compensation current comparison circuit of the present invention.

[0033] Figure 6 This is a schematic diagram of the circuit structure of the adaptive delay compensation current compensation circuit of the present invention. Detailed Implementation

[0034] To make the objectives, solutions, and advantages of this invention clearer, the detailed working principle and state of this invention will be described in more detail below with reference to the accompanying drawings. The embodiments described are for illustrative purposes only and are not intended to limit the scope of application of this invention.

[0035] The purpose of the following description is to provide the public with a clearer understanding of the present invention, while those skilled in the art will be able to understand the invention clearly even without the following detailed explanation.

[0036] The adaptive delay-compensated current comparison circuit provided by this invention is applicable to switching power supply circuits in current-limiting control mode or zero-crossing detection mode that use current comparison to control the on / off state of the switching transistor. Furthermore, the adaptive delay-compensated current comparison circuit provided by this invention is also applicable to any circuit requiring precise current comparison. Figure 1 The circuit is only used to explain the present invention, and the adaptive compensation delay current comparison circuit of the present invention is not limited to switching power supply circuits.

[0037] The adaptive compensation delay current comparison circuit provided by this invention adds an additional compensation current module to offset the current error caused by parasitic delay in the circuit system, thereby avoiding delay in the current comparison circuit structure and obtaining a delay-free and accurate inductor current.

[0038] The adaptive delay compensation current comparison circuit of the present invention can be applied to, for example... Figure 1The switching power supply circuit shown derives the adaptive delay compensation switching power supply circuit of the present invention. Figure 1 As shown, the switching power supply circuit includes an input voltage source Vin, a switching node SW connected to the input voltage source Vin via an energy storage inductor L, and an active switching transistor S1 and a freewheeling transistor S2 whose drains are connected to the switching node SW. The active switching transistor S1 is an NMOS power transistor, and the freewheeling transistor S2 is a PMOS power transistor. The freewheeling transistor S2 has a body diode D. The source of the active switching transistor S1 is grounded via a ground wire, and the source of the freewheeling transistor S2 is the voltage output terminal V of the switching power supply circuit. out Voltage output terminal V out The current comparison circuit 100 of the present invention, which is grounded through an output capacitor C, is connected to a current sampling module 201. In applications such as... Figure 1 In the switching power supply circuit shown, the input terminal of the current sampling module 201 is connected to the source of the active switching transistor S1 to receive the active transistor current I. CS The output terminal of the current sampling module 201 is connected to one of the input terminals of the current comparison circuit 100 of the present invention to receive the sampled current, while the other input terminal of the current comparison circuit 100 is configured to receive the reference current I. ref The output of the current comparison circuit 100 is configured to be based on the reference current I. ref With active tube current I CS The comparison result yields a logic control signal PWM, which is then output. The output of the current comparison circuit is connected to the input of the logic control module 203. The logic control module 203 is configured to convert the logic control signal PWM into two non-overlapping clock signals for output. In this embodiment, the logic control module 203 has two outputs, which are respectively connected to the gates of the active switching transistor S1 and the freewheeling transistor S2. The adaptive delay compensation current comparison circuit 100 of this invention is used to compensate for delay errors and obtain a precise inductor current.

[0039] The current sampling module can be understood as a current mirror circuit with the gate and S1 transistor connected together, except that the number of transistors connected in parallel is different. For example, if the S1 transistor has m=10000 and the sampling transistor has m=1, then the sampling current is equal to the current of the S1 transistor divided by 10000. The specific ratio value depends on the actual specifications.

[0040] like Figure 4 As shown, the adaptive compensation delay current comparison circuit 100 of the present invention improves upon the conventional current comparison circuit by adding a current compensation module 101 to compensate for the reference current I. ref (I'm about to) refSubtracting a compensation current ΔI from the current yields the current-compensated reference current I. ref The adaptive delay-compensating current comparison circuit 100 includes a first current mirror, a second current mirror, a current compensation module 101, and a subsequent inverter. One low-voltage terminal of the first current mirror and one high-voltage terminal of the second current mirror are connected, and the connection point is the comparison voltage output terminal, which is configured to output a comparison voltage V. P The other low-voltage terminal of the first current mirror is connected to the active transistor current I. CS (In other embodiments, the active transistor current I) CS (This can be any sampling current), and the other high-voltage terminal of the second current mirror is connected to the reference current I. ref The high-voltage end of the first current mirror is connected to the input voltage source Vin, and the low-voltage end of the second current mirror is grounded.

[0041] In this embodiment, the first current mirror is composed of a first MOS transistor MP1 and a second MOS transistor MP2 whose gates are connected to each other. Both the first MOS transistor MP1 and the second MOS transistor MP2 are PMOS transistors. The gate and drain of the first MOS transistor MP1 serve as a low-voltage terminal of the first current mirror to connect to the active transistor current I. CS The drain of the second MOSFET MP2 is used as the low-voltage terminal of the first current mirror to connect to the comparison voltage output terminal. The sources of the first MOSFET MP1 and the second MOSFET MP2 are used as the high-voltage terminals of the first current mirror to connect to the input voltage source Vin. The gate-drain parasitic capacitance C1 of the second MOSFET MP2 is located between the gate and the drain of the second MOSFET MP2.

[0042] Similarly, the second current mirror is composed of a third MOSFET MN1 and a fourth MOSFET MN2 with their gates connected to each other. Both the third MOSFET MN1 and the fourth MOSFET MN2 are NMOS transistors. The gate and drain of the third MOSFET MN1 serve as a high-voltage terminal of the second current mirror to be connected to the reference current I. ref The drain of the fourth MOSFET MN2 is connected to the comparison voltage output terminal as a high-voltage terminal of the second current mirror. The sources of the third MOSFET MN1 and the fourth MOSFET MN2 are grounded as low-voltage terminals of the second current mirror. The gate-drain parasitic capacitance C2 of the fourth MOSFET MN2 is located between the gate and the drain of the fourth MOSFET MN2.

[0043] The current compensation module is connected between the input voltage source Vin and the comparison voltage output terminal (which provides the comparison voltage V). P Between ), it is set to provide compensation current ΔI.

[0044] The comparison voltage output terminal is connected to the input terminal of the subsequent inverter, and the output terminal of the subsequent inverter is set to output the logic control signal PWM.

[0045] In this embodiment, the subsequent inverter consists of a fifth MOS transistor MP3 and a sixth MOS transistor MN3. The fifth MOS transistor is a PMOS transistor, and the sixth MOS transistor MN3 is an NMOS transistor. The gates of the fifth MOS transistor MP3 and the sixth MOS transistor MN3 are connected to each other and serve as the input terminals of the subsequent inverter. The drains of the fifth MOS transistor MP3 and the sixth MOS transistor MN3 are connected to each other and serve as the output terminals of the subsequent inverter. A gate-drain parasitic capacitance C3 of the sixth MOS transistor MN3 exists between its gate and drain.

[0046] Many parasitic capacitances exist in MOSFETs. Major parasitic capacitances include the gate-drain parasitic capacitance C1 of the second MOSFET MP2, the gate-drain parasitic capacitance C2 of the fourth MOSFET MN2, and the gate-drain parasitic capacitance C3 of the sixth MOSFET MN3. All parasitic capacitances can be equivalently represented by the equivalent parasitic capacitance C connected between the comparator voltage output terminal and ground. X .

[0047] refer to Figure 5 The diagram illustrates a comparison of the voltage and current waveforms at each node in a conventional current comparison circuit and the current comparison circuit of this invention with the addition of a current compensation module. For the conventional current comparison circuit, the output waveform is obtained by referencing a reference current I. ref and active tube current I CS The comparison is used to generate the signal. Ideally, when the two currents at point a are equal, if there is no parasitic capacitance delay, the logic control signal PWM at the corresponding point a should toggle. However, due to the existence of the parasitic delay Δt, the active transistor current I... CS When the current overshoots by ΔI, the logic control signal PWM flips, causing the sampled current to be inaccurate, and the corresponding inductor current is also inaccurate.

[0048] For the current comparison circuit of the present invention after adding a current compensation module, such as Figure 4 As shown, a current compensation module has been added to the comparison voltage V. P A compensation current ΔI was applied at the location, combined with Figure 5 As shown, this is equivalent to using the reference current I ref Subtracting a compensation current ΔI from the current yields the current-compensated reference current I. ref Then, it is compared with the active transistor current I. CS The logic control signal PWM is obtained through comparison. Ideally, the logic control signal PWM is at point c (i.e., the reference current I after current compensation). ref 'With active tube current I CS (Where they are equal) they should flip, but due to the parasitic delay Δt, the active transistor current I...CS Similarly, the compensation current ΔI was overshooted before reaching the flip-flop threshold voltage of the subsequent inverter, causing the logic control signal PWM to flip. Therefore, the flip occurred exactly at point a, at which point the active transistor current I was obtained. CS This is equivalent to the ideal toggle point of the logic control signal PWM in an unmodified traditional current comparator circuit. It can also be seen as canceling out the delay caused by parasitic capacitance to obtain a precise inductor current.

[0049] The compensation current ΔI is the sampling current error ΔI caused by the existence of the parasitic delay Δt. CS .

[0050] In this embodiment, since the adaptive delay compensation current comparison circuit of the present invention is applied to, for example... Figure 1 The switching power supply circuit shown can be used to calculate the sampling current error ΔI caused by the parasitic delay Δt by substituting equation (4) into equation (2). CS The relation is:

[0051]

[0052] Where k is the inductor current reduction factor, V TH C is the switching threshold voltage of the subsequent inverter. X L is the equivalent parasitic capacitance, and L is the energy storage inductance. These values ​​are constants when the structure of the switching power supply circuit is fixed.

[0053] In other embodiments, the current comparison circuit is suitable for any application requiring precise current comparison, and is not limited to switching power supply circuits. The current error ΔI is sampled in different circuits. CS The formula can be adjusted accordingly. The embodiments provided above are merely for illustrative purposes.

[0054] The adaptive delay-compensated current comparison circuit of this invention achieves accurate current comparison by compensating for delay. This concept is applicable to any circuit requiring accurate current comparison. However, the formulas provided in this invention are all based on switching power supply circuits, i.e. Figure 1 The corresponding adaptive delay compensation switching power supply circuit proposed for reference is merely one specific embodiment of the present invention.

[0055] Therefore, the change in error current ΔI is only related to the voltage of the input voltage source Vin, and is proportional to it. Since the input voltage source Vin has a certain application range, and it is an exponential function, a linear approximation method can be used for ease of design, resulting in:

[0056] ΔI≈αVin+I O (6)

[0057] Where α is the slope, I O For a fixed bias current, slope α and fixed bias current I O All are constants. Within the power supply voltage application range, the maximum voltage value V of the input voltage source Vin is... INMAX The minimum voltage value V of the input voltage source Vin INMIN Substituting into formula (5) yields the corresponding maximum compensation current value I. INMAX and minimum compensation current value I INMIN Substituting these values ​​into formula (6) will yield α and I. O value.

[0058] Based on this, the current compensation module consists of, as follows: Figure 6 As shown, the specific components include: a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series between the input voltage source Vin and ground. The connection point of the first voltage divider resistor R1 and the second voltage divider resistor R2 is connected to the positive input terminal V+ of the amplifier, so as to proportionally divide the voltage of the input voltage source Vin and output it to the positive terminal of the error amplifier. The negative input terminal V- of the amplifier is connected to one end of the third resistor R3 and the source of the seventh MOS transistor MN4. The other end of the third resistor R3 is grounded. The gate of the seventh MOS transistor MN4 is connected to the output terminal of the amplifier. The seventh MOS transistor MN4 is an NMOS transistor. The current compensation module also includes a third current mirror and a fourth current mirror. The high-voltage terminals of the third current mirror and the fourth current mirror are both connected to the input voltage source Vin. One low-voltage terminal of the third current mirror is connected to the drain of the seventh MOS transistor MN4, and one low-voltage terminal of the fourth current mirror is connected to the fixed bias current I. O The third current mirror and the fourth current mirror are connected together as the output terminals of the current compensation module. Therefore, the output terminal of the current compensation module can output a compensation current equal to the sum of the input voltage source Vin and the fixed bias current I. O The sum, the direction of the current is as follows Figure 6 As shown by the arrow in the image.

[0059] In this embodiment, the third current mirror is composed of the eighth MOS transistor MP4 and the ninth MOS transistor MP5, whose gates are connected to each other. The fourth current mirror is composed of the tenth MOS transistor MP6 and the eleventh MOS transistor MP7, whose gates are connected to each other. The drain and gate of the eighth MOS transistor MP4 serve as a low-voltage terminal of the third current mirror and are connected to the drain of the seventh MOS transistor MN4. The gate and drain of the eleventh MOS transistor MP7 serve as a low-voltage terminal of the fourth current mirror and are connected to the fixed bias current I. OThe drain of the ninth MOSFET MP5, which serves as a low-voltage terminal of the third current mirror, is connected to the drain of the tenth MOSFET MP6, which serves as a low-voltage terminal of the fourth current mirror. Therefore, the current flowing through the seventh MOSFET MN4 is equal to the current flowing through the ninth MOSFET MP5, and the current flowing through the tenth MOSFET MP6 is equal to the fixed bias current I. O Since they are equal in magnitude, the sum of the currents of the ninth MOSFET MP5 and the tenth MOSFET MP6 is the current ΔI.

[0060] In this embodiment, the eighth MOSFET MP4, the ninth MOSFET MP5, the tenth MOSFET MP6, and the eleventh MOSFET MP7 are all PMOS transistors, while the seventh MOSFET MN4 is an NMOS transistor. Therefore, the equivalent parasitic capacitance C is transmitted through the ninth MOSFET MP5 and the tenth MOSFET MP6. X Charge.

[0061] because Since V+ is equal to V-, the current I flowing through the seventh MOSFET MN4 is... MN4 It can be expressed by the following formula:

[0062]

[0063] The obtained current I MN4 After being reflected by a current mirror, and then compared with a fixed bias current I reflected by a current mirror. O The summation yields a compensation current ΔI that is linearly related to the voltage of the input voltage source Vin.

[0064] The compensation current ΔI is:

[0065]

[0066] in Equal to the constant α in formula (6), I O It can be provided by a fixed bias current.

[0067] The adaptive delay-compensated current comparison circuit of this invention incorporates a current compensation module, which feeds the comparison voltage V... P Inject compensation current ΔI at the location, combined with Figure 5 As shown, this is equivalent to using the reference current I. ref Subtracting a compensation current ΔI yields the current-compensated reference current I. ref The obtained current-compensated reference current I ref 'With active tube current I CS In comparison, after a delay of Δt where the two are equal, the active transistor current I... CSWhen the overshoot reaches the switching threshold voltage of the subsequent inverter by a compensation current ΔI, the PWM signal flips. The current I of the active transistor at this time... CS It is precisely the ideal sampling current value required before the improvement that is achieved. Figure 1 In applications, this corresponds to the ideal inductor current value.

[0068] Then, the compensation current ΔI obtained above is as follows: Figure 4 As shown, injected into V P By using this point, current compensation can be achieved for traditional structures, offsetting the effect of parasitic capacitance on circuit delay, and obtaining accurate inductor current without delay.

[0069] The adaptive compensation delay current comparison circuit provided by the present invention adds an additional compensation current module to offset the current error caused by parasitic delay in the circuit system, so as to avoid the delay caused by the presence of parasitic capacitance during the current comparison process and obtain a delay-free and accurate inductor current.

[0070] The above description is merely a preferred embodiment of the present invention and does not limit the scope of the invention. The present invention can also be applied to various circuits that require compensation for parasitic capacitance delay. That is, all simple and equivalent changes and modifications made in accordance with the claims and description of this invention fall within the scope of protection of the claims of this patent. All aspects not described in detail in this invention are conventional technical content.

Claims

1. A current comparator circuit with adaptive delay compensation, characterized in that, It includes a first current mirror, a second current mirror, a current compensation module, and a subsequent inverter; One of the low-voltage terminals of the first current mirror and one of the high-voltage terminals of the second current mirror are connected, and the connection point is the comparison voltage output terminal, which is set to output the comparison voltage. The other low-voltage terminal of the first current mirror serves as one of the input terminals of the current comparison circuit to receive the sampled current, and the other high-voltage terminal of the second current mirror serves as another input terminal of the current comparison circuit to receive the reference current. The high-voltage terminal of the first current mirror is connected to the input voltage source, and the low-voltage terminal of the second current mirror is grounded. The current compensation module is connected between the input voltage source and the comparison voltage output terminal and is configured to provide compensation current; The comparison voltage output terminal is connected to the input terminal of the subsequent inverter, and the output terminal of the subsequent inverter is set to output logic control signal; The current compensation module includes a first voltage divider resistor and a second voltage divider resistor connected in series between the input voltage source and ground. The connection point of the first voltage divider resistor and the second voltage divider resistor is connected to the positive input terminal of the amplifier. The negative input terminal of the amplifier is connected to one end of the third resistor and the source of the seventh MOS transistor. The other end of the third resistor is grounded. The gate of the seventh MOS transistor is connected to the output terminal of the amplifier. The current compensation module also includes a third current mirror and a fourth current mirror. The high-voltage terminals of the third current mirror and the fourth current mirror are both connected to the input voltage source. One low-voltage terminal of the third current mirror is connected to the drain of the seventh MOS transistor. One low-voltage terminal of the fourth current mirror is connected to the fixed bias current. The other low-voltage terminals of the third current mirror and the other low-voltage terminals of the fourth current mirror are connected as the output terminals of the current compensation module. The third current mirror is composed of an eighth MOS transistor and a ninth MOS transistor whose gates are connected to each other. The fourth current mirror is composed of a tenth MOS transistor and an eleventh MOS transistor whose gates are connected to each other. The drain and gate of the eighth MOS transistor are connected to the drain of the seventh MOS transistor as a low-voltage terminal of the third current mirror. The gate and drain of the eleventh MOS transistor are connected to the fixed bias current as a low-voltage terminal of the fourth current mirror. The drain of the ninth MOS transistor, which is a low-voltage terminal of the third current mirror, is connected to the drain of the tenth MOS transistor, which is a low-voltage terminal of the fourth current mirror. The eighth, ninth, tenth, and eleventh MOS transistors are all PMOS transistors, and the seventh MOS transistor is an NMOS transistor; The compensation current ΔI is: Where R1 is the resistance of the first voltage divider resistor, R2 is the resistance of the second voltage divider resistor, R3 is the resistance of the third resistor, Vin is the voltage of the input voltage source, and I... O For fixed bias current.

2. The adaptive delay compensation current comparison circuit according to claim 1, characterized in that, The first current mirror is composed of a first MOS transistor and a second MOS transistor whose gates are connected to each other. Both the first MOS transistor and the second MOS transistor are PMOS transistors. The gate and drain of the first MOS transistor serve as a low-voltage terminal of the first current mirror to connect to the sampling current. The drain of the second MOS transistor serves as a low-voltage terminal of the first current mirror to connect to the comparison voltage output terminal. The sources of the first MOS transistor and the second MOS transistor serve as high-voltage terminals of the first current mirror to connect to the input voltage source. The second current mirror is composed of a third MOS transistor and a fourth MOS transistor whose gates are connected to each other. Both the third MOS transistor and the fourth MOS transistor are NMOS transistors. The gate and drain of the third MOS transistor serve as a high-voltage terminal of the second current mirror to be connected to the reference current. The drain of the fourth MOS transistor serves as a high-voltage terminal of the second current mirror to be connected to the comparison voltage output terminal. The sources of the third MOS transistor and the fourth MOS transistor serve as low-voltage terminals of the second current mirror and are grounded.

3. The adaptive delay-compensating current comparison circuit according to claim 2, characterized in that, The second MOS transistor has a gate-drain parasitic capacitance between its gate and drain, and the fourth MOS transistor has a gate-drain parasitic capacitance between its gate and drain.

4. The adaptive delay compensation current comparison circuit according to claim 1, characterized in that, The subsequent inverter consists of a fifth MOS transistor and a sixth MOS transistor. The fifth MOS transistor is a PMOS transistor, and the sixth MOS transistor is an NMOS transistor. The gates of the fifth MOS transistor and the sixth MOS transistor are connected to each other and serve as the input terminal of the subsequent inverter. The drains of the fifth MOS transistor and the sixth MOS transistor are connected to each other and serve as the output terminal of the subsequent inverter.

5. The adaptive delay-compensating current comparison circuit according to claim 4, characterized in that, The sixth MOS transistor has a gate-drain parasitic capacitance between its gate and drain.

6. A switching power supply circuit with adaptive delay compensation, characterized in that, It includes an input voltage source, a switching node connected to the input voltage source through an energy storage inductor, and an active switching transistor and a freewheeling transistor whose drains are connected to the switching node. The active switching transistor is an NMOS power transistor, and the freewheeling transistor is a PMOS power transistor. The source of the active switching transistor is grounded through a ground wire, and the source of the freewheeling transistor is the voltage output terminal of the switching power supply circuit. The voltage output terminal is grounded through an output capacitor. The source of the active switching transistor is connected to the input of a current sampling module. The output of the current sampling module is connected to one input of the adaptive delay compensation current comparison circuit according to any one of claims 1-5 to receive the sampled current. The other input of the current comparison circuit is configured to receive a reference current. The output of the current comparison circuit is configured to obtain a logic control signal based on the comparison result between the reference current and the active transistor current and output it. The output of the current comparison circuit is connected to the input of a logic control module. The logic control module has two outputs, which are respectively connected to the gates of the active switching transistor and the freewheeling transistor.

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