A control circuit for a push-pull converter
By designing the control circuit of the push-pull converter, the switching transistors are alternately turned on and off. Combined with output voltage detection and logic control, self-starting and current limiting protection are achieved, solving the problems of complex circuits, large size and high loss in the existing technology, and improving the safety and reliability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUNAN UNIV
- Filing Date
- 2023-04-20
- Publication Date
- 2026-06-16
AI Technical Summary
The existing push-pull converter control circuit has problems such as complex circuit, large size, high loss, high cost, low safety and lack of protection measures, especially during startup, which can easily damage the switching transistor.
A push-pull converter control circuit is adopted, which avoids short circuits by alternately turning on the first and second switching transistors. The output voltage detection circuit and logic control circuit realize self-starting and current limiting protection. Combined with the drive circuit, flexible control is achieved to reduce conduction losses. Over-temperature and under-voltage/over-voltage detection ensures system reliability.
It achieves miniaturization and integration of control circuits, reduces power consumption, improves circuit safety and reliability, prevents damage to switching transistors, and ensures that the system does not malfunction under abnormal conditions.
Smart Images
Figure CN116545235B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to switching power supply technology, and in particular to a control circuit for a push-pull converter. Background Technology
[0002] Push-pull converters are widely used switching power supplies. In a push-pull converter circuit, the two primary-side switching transistors operate alternately, resulting in high transformer utilization and, ideally, a very high duty cycle. They offer electrical isolation between input and output and are primarily used in applications requiring low-voltage input and high-current output. Existing research and technologies mainly focus on improving and optimizing the main circuit structure of push-pull converters. However, this has also brought many problems and challenges, such as excessive circuit complexity, large size, increased losses, and higher costs. Although some technologies have improved the control circuit by introducing batteries and stable voltage supply circuits, this approach results in excessively large circuits, hindering miniaturization; they only contain one driving mode, neglecting situations with long overvoltage periods or heavy load interference on the switching transistors, making the circuit prone to short circuits without corresponding protection measures, leading to low safety and reliability; during circuit startup, there is no current-limiting protection, which can easily cause significant impact on the switching transistors; and the circuit design is complex, resulting in high power consumption and cost. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a control circuit for a push-pull converter that effectively prevents damage to the switching transistors and reduces conduction losses, in order to address the shortcomings of the prior art.
[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a control circuit for a push-pull converter, comprising:
[0005] transformer;
[0006] The primary side of the transformer is connected to the first and second switching transistors.
[0007] Each of the two taps on the secondary side of the transformer is connected to a diode, and both diodes are connected to the positive terminal of the capacitor; the middle tap on the secondary side of the transformer is connected to the negative terminal of the capacitor.
[0008] in,
[0009] When the first switch and the second switch are turned on alternately, the two diodes are turned on alternately.
[0010] When the control terminal drive signal of the first switch is high, the input terminal voltage VD1 of the first switch and the input terminal voltage VD2 of the second switch are respectively: VD1 = V IN -N*(V OUT +V D2 VD2 = V IN+N*(V OUT +V D2 );
[0011] When the control terminal drive signal of the second switch is high, the input terminal voltage VD1 of the first switch and the input terminal voltage VD2 of the second switch are respectively: VD1 = V IN +N*(V OUT +V D1 VD2 = V IN -N*(V OUT +V D1 );
[0012] N is the transformer turns ratio, V IN V represents the magnitude of the voltage input signal. OUT V is the output voltage across the capacitor. D1 V D2 These are the forward voltage drops of diodes D1 and D2, respectively.
[0013] The push-pull converter of this invention has good electrical isolation between the input and output. There is a dead time between the alternating conduction of the first and second switching transistors, which avoids the simultaneous conduction of the two switching transistors, thereby avoiding a short circuit in the winding, preventing damage to the switching transistors, and reducing conduction losses.
[0014] When the magnitude of the voltage input signal V IN The push-pull converter operates when the value is within the set range.
[0015] Both the first and second switching transistors are NMOS transistors; the drains of both the first and second NMOS transistors are connected to the output voltage detection circuit; the gates of both the first and second NMOS transistors are connected to the driving circuit; and the sources of both the first and second NMOS transistors are grounded.
[0016] The output voltage detection circuit includes a first comparator and a second comparator; the positive input terminal of the first comparator is connected to the drain of the first NMOS transistor, the negative input terminal of the first comparator is connected to the negative input terminal of the second comparator, and the positive input terminal of the second comparator is connected to the drain of the second NMOS transistor; the output terminals of the first and second comparators are respectively connected to the two input terminals of a NAND gate; the output terminal of the NAND gate is connected to the first input terminal of a D flip-flop, the second input terminal of the D flip-flop is connected to the output terminal of a first OR gate, and the two input terminals of the first OR gate are respectively connected to the two output terminals of the PWM waveform generation circuit.
[0017] Compared to traditional output-side sampling circuits, the output voltage detection circuit of this invention has a simple structure, and indirectly represents the output voltage V using the input voltages VD1 / VD2 of the first and second switching transistors.OUT The size of the circuit eliminates the need to design a sampling circuit for the output voltage, thus reducing circuit complexity.
[0018] The current value I of the first NMOS transistor / second NMOS transistor D With gate-source voltage V GS The relationship is: Where, μ n For electron mobility, C ox V is the gate oxide capacitance per unit area, W and L are the gate width and gate length, respectively, λ is the channel length modulation coefficient, and V DS This is the drain-source voltage.
[0019] The output voltage detection circuit is connected to the logic control circuit; the logic control circuit includes a third switch and a fourth switch; the input terminals of the third and fourth switches receive power enable signals, the output terminal of the third switch is connected to the enable input terminal of the timer circuit, and the output terminal of the fourth switch is connected to the enable input terminal of the PWM waveform generation circuit; the control terminal of the third switch is connected to the output terminal of the output voltage detection circuit, and the control terminal of the fourth switch is connected to the output terminal of the first NOT gate; the input terminal of the first NOT gate is connected to the output terminal of the RS flip-flop; the first input terminal and the output terminal of the RS flip-flop are respectively connected to the two input terminals of the first AND gate, and the output terminal of the first AND gate is connected to the first input terminal of the third OR gate; the second input terminal of the third OR gate... The first input terminal of the XNOR gate is connected to the first logic signal; the output terminal of the XNOR gate is connected to the first input terminal of the RS flip-flop, and the second input terminal of the XNOR gate is connected to the output terminal of the second AND gate; the first input terminal of the second AND gate is connected to the output terminal of the RS flip-flop, and the second input terminal is connected to the first input terminal of the third AND gate and the output terminal of the third NOT gate, the input signal of the third NOT gate being the second logic signal; the second input terminal of the third AND gate is connected to the output terminal of the fourth NOT gate, the input signal of the fourth NOT gate being the first logic signal; the third input terminal of the third AND gate is connected to the input terminal of the second NOT gate and the output terminal of the RS flip-flop; the output terminal of the second NOT gate is connected to the first input terminal of the second OR gate, the output terminal of the third AND gate is connected to the second input terminal of the second OR gate; the output terminal of the second OR gate is connected to the second input terminal of the RS flip-flop.
[0020] Compared to the traditional method of using control chips and peripheral circuits, the logic control circuit of this invention uses several logic gates and MOS transistors, which makes the structure simpler, the size smaller, easier to integrate into the control circuit, and provides clear logic and reliable output of enable signals.
[0021] The output of the first OR gate is connected to the second input of the D flip-flop via a delay chopper circuit.
[0022] The time-delay chopper circuit includes a first capacitor, the positive terminal of which is connected to the output of a first OR gate, and the negative terminal of which is connected to the first input of a NOR gate and the input of a parallel branch. The parallel branch includes a first diode and a first resistor connected in parallel. The output of the NOR gate is connected to the input of a fifth NOT gate through a second capacitor, and the output of the fifth NOT gate is connected to a second resistor, which is grounded through a third capacitor. The second resistor is connected in parallel with the second diode. The anode of the second diode is connected to the positive input of a third comparator, and the cathode of the second diode is connected to the second input of the NOR gate. A reference voltage signal is input to the negative input of the second comparator. The anode of the third diode and one end of the third resistor are connected between the second capacitor and the input of the fifth NOT gate, and the cathode of the third diode and the other end of the third resistor are used to input a power enable signal. The time-delay chopper circuit of this invention has a simple structure. The two outputs of the PWM waveform are passed through an OR gate and used as the input of the circuit. Only one time-delay chopper circuit is needed, reducing the number of components and facilitating the miniaturization of the control circuit. The delay time of the PWM waveform can be adjusted by adjusting the values of the resistor and capacitor, achieving flexible control.
[0023] Both the negative input terminals of the first comparator and the negative input terminals of the second comparator are connected to the output terminals of the reference / voltage divider circuit.
[0024] The driving circuit includes a selector; the first and second input terminals of the selector are respectively connected to the two output terminals of the reference / voltage divider circuit, and the third input terminal is connected to the output terminal of the output voltage detection circuit; the output terminal of the selector is connected to the input terminals of the first and third transistors, the output terminal of the third transistor is connected to the input terminal of the fourth transistor, the output terminal of the fourth transistor is connected to the output terminal of the second transistor, and the input terminal of the second transistor is connected to the output terminal of the first transistor; the control terminals of the first and second transistors are connected to a resistor, and the resistor input terminal is connected to the first output terminal of the PWM waveform generation circuit; the control terminals of the third and fourth transistors are connected to the second output terminal of the PWM waveform generation circuit; the first output terminal of the driving circuit is led out between the output terminal of the first transistor and the input terminal of the second transistor, and the second output terminal of the driving circuit is led out between the output terminal of the third transistor and the input terminal of the fourth transistor; the first and second output terminals are respectively connected to the control terminals of the first and second switching transistors.
[0025] In this invention, based on the drain-source voltage of the switching transistor, the drive circuit selects the amplitude of the PWM waveform using a selector, resulting in two sets of PWM waveforms with different amplitudes but the same duty cycle. The drive circuit uses two transistors in a transistor pair to achieve co-directional drive. Compared to using MOSFETs, the co-directional drive circuit of transistors has a simpler structure, requires fewer components, and has lower losses. It also improves the current supply capability and can quickly complete the charging process of the gate input capacitor of the main circuit switching transistor.
[0026] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0027] 1) This invention does not increase the complexity of the main circuit, reduces the complexity of the circuit, reduces the system size, further reduces power consumption, and facilitates the miniaturization and integration of the control chip;
[0028] 2) Through the control and coordination of the output voltage detection circuit, logic control circuit, timer circuit and drive circuit during startup and normal push-pull operation, the system can achieve self-starting. During startup, current limiting protection can be achieved for NMOS transistors N1 and N2. During normal push-pull operation, the circuit outputs stably.
[0029] 3) By controlling the output voltage detection circuit, logic control circuit, and timer circuit, serious consequences caused by short circuits or heavy load interference can be prevented, and long-term overvoltage of NMOS transistors N1 and N2 can be avoided, thus improving the safety and reliability of the circuit.
[0030] 4) This invention can realize real-time monitoring of voltage input signal and system temperature, prevent circuit malfunction when the input voltage is outside the set threshold range, thereby improving the reliability of the system. Attached Figure Description
[0031] Figure 1 This is a block diagram illustrating the structural principle of a push-pull converter according to an embodiment of the present invention.
[0032] Figure 2 This is a schematic diagram of the output voltage detection circuit according to an embodiment of the present invention;
[0033] Figure 3 The signals (V1, V2, VD1, VD2, VD3, VD4, VD5) of the output voltage detection circuit in this embodiment of the invention are... SET V NOR T sam Waveform diagram;
[0034] Figure 4 This is a schematic diagram of the logic control circuit according to an embodiment of the present invention;
[0035] Figure 5 T is the logic control circuit of the embodiment of the present invention. OSD T SLEEP PWM EN Waveform diagram of RST;
[0036] Figure 6 This is a schematic diagram of the drive circuit during startup and normal push-pull operation in the control circuit of an embodiment of the present invention;
[0037] Figure 7 When the embodiment of the present invention is started (V) NOR =0) and normal push-pull (V NOR =1) Waveform diagrams of drive signals PWM1 and PWM2;
[0038] Figure 8 This is a schematic diagram of the over-temperature detection and under-voltage / over-voltage detection circuit for the input signal in the control circuit of an embodiment of the present invention;
[0039] Figure 9 This is a circuit diagram of the delay chopping stage in the output voltage detection circuit of this invention. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0041] like Figure 1 As shown, the push-pull converter in this embodiment of the invention includes NMOS transistors N1 (the first switching transistor, i.e., the first NMOS transistor) and N2 (the second switching transistor, i.e., the second NMOS transistor) on the primary side of the main circuit, a transformer, and diodes and capacitors on the secondary side. The control section (control chip) includes a reference / voltage divider circuit, an over-temperature detection circuit and an under-voltage / over-voltage detection circuit for the input signal, a logic control circuit, an output voltage detection circuit, a timer circuit, a PWM waveform generation circuit, and drive circuits for startup and normal push-pull operation. The voltage input signal for the control section is V. IN .
[0042] When the over-temperature detection and under-voltage / over-voltage detection circuits of the input signal in the control chip are operating within normal and safe ranges (normal internal circuit temperature of the control chip is 25-80℃, and normal input voltage is 2.7-5.2V), the over-temperature detection and under-voltage / over-voltage detection circuits of the input signal (see...) Figure 8 Only when VCCD is high will it output a valid power supply enable signal VCCD. When VCCD is high, the logic control circuit, output voltage detection circuit, timer circuit, PWM waveform generation circuit, and drive circuits during startup and normal push-pull operation will start working, thus enabling a stable output voltage.
[0043] In the main circuit, the two NMOS transistors N1 and N2 alternately conduct, and to prevent both transistors from conducting simultaneously, there is a brief dead zone in between. When NMOS transistor N1 is conducting, diode D2 is conducting; when NMOS transistor N2 is conducting, diode D1 is conducting.
[0044] The control circuit is distributed between the main circuit and the voltage input signal V. INIn addition, interference to the control circuit can be minimized, and the control chip can be integrated onto a single circuit chip, making the system more compact. Compared to adding capacitors and inductors to the main circuit, which significantly alters the main circuit structure, this invention substantially reduces the power consumption of the control circuit without increasing the main circuit's power consumption, thereby reducing system complexity and size.
[0045] The reference / voltage divider circuit, over-temperature detection, and under-voltage / over-voltage detection circuit for the input signal enable the system to monitor the input voltage and temperature in real time. The reference / voltage divider circuit (its structure can be found in CN203455403U) generates a reference voltage signal V based on the principles of resistor voltage division and Zener diode voltage regulation. SET The voltage signal VL during startup and the voltage signal VH during normal push-pull operation.
[0046] like Figure 2 As shown, the output voltage detection circuit includes six input terminals and one output terminal. The first input terminal is connected to the drain-source voltage VD1 of the NMOS transistor N1 in the main circuit, the second input terminal is connected to the drain-source voltage VD2 of the NMOS transistor N2 in the main circuit, and the third input terminal is connected to the output terminal V of the reference / voltage divider circuit. SET The fourth and fifth input terminals are connected to the two quasi-complementary outputs V1 and V2 of the PWM waveform generation circuit, respectively. The sixth input terminal is connected to the power enable signal VCCD, and the output terminal is connected to the second input terminal V of the logic control circuit. NOR .
[0047] The first input terminal VD1 is connected to the positive terminal of comparator COMP1 (the first comparator), the second input terminal VD2 is connected to the positive terminal of comparator COMP2 (the second comparator), and the third input terminal V... SET The negative terminals of comparators COMP1 and COMP2 are connected to each other. The output terminals of comparators COMP1 and COMP2 are connected to the input terminals of the NAND gate, respectively. The output terminal of the NAND gate is connected to the input terminal D of the D flip-flop. The fourth input terminal V1 and the fifth input terminal V2 are connected to the input terminals of the OR gate OR1, respectively. The output terminal of the OR gate OR1 (the first OR gate) is connected to the delay chopper circuit (see...). Figure 9 The input terminal of the delay chopper circuit is connected to the input terminal CLK of the D flip-flop, and the output terminal of the D flip-flop is connected to the output terminal V. NOR .
[0048] like Figure 2 As shown, the output voltage detection circuit samples the drain voltages of the two NMOS transistors in the main circuit, and compares the drain voltages VD1 and VD2 of NMOS transistors N1 and N2 with the reference voltage signal V. SETComparison. The voltages VD1 and VD2 are actually related to the output voltage, hence the name "output voltage detection circuit." When the gate drive signal PWM1 of NMOS transistor N1 is high, the drain voltages VD1 of NMOS transistor N1 and VD2 of NMOS transistor N2 are:
[0049] VD1=V IN -N*(V OUT +V D2 (1)
[0050] VD2=V IN +N*(V OUT +V D2 (2)
[0051] Where N is the transformer turns ratio, V IN V represents the magnitude of the voltage input signal. OUT Main circuit output voltage, V D1 V D2 These are the forward voltage drops of diodes D1 and D2, respectively. Similarly, when the gate drive signal PWM2 of NMOS transistor N2 is high, the drain voltage VD1 of NMOS transistor N1 and the drain voltage VD2 of NMOS transistor N2 are respectively:
[0052] VD1=V IN +N*(V OUT +V D1 (3)
[0053] VD2=V IN -N*(V OUT +V D1 (4)
[0054] VD1 and VD2 and V SET After comparison, the NAND output is sent to a D flip-flop via a NAND gate. When the output is short-circuited, just started up, or under heavy load interference, the output voltage of the circuit will drop and remain at a low level. At this time, regardless of whether NMOS transistors N1 or N2 are turned on, VD1 and VD2 are both greater than V. SET Then V will eventually be made NOR The output is low. And V NOR A low level indicates that the circuit is in an abnormal state, such as just starting up, short circuit, or under heavy load interference. These abnormal states cause the drain-source voltage of the conducting switching transistor to be at a very high level. If this voltage remains too high for an extended period, conduction losses increase, leading to increased temperature and reduced circuit reliability. If the circuit remains in an abnormal state for an extended period, it will enter a sleep mode and fail to function properly.
[0055] Figure 2In the circuit, the two quasi-complementary output signals V1 and V2 of the PWM waveform generation circuit are output to the CLK terminal of the D flip-flop after delay and chopping. For example... Figure 3 As shown, from V NOR =0 transition to V NOR The process of VD1 = 1, from the initial start to normal push-pull operation, occurs when either VD1 or VD2 is less than VD2. SET V NOR The output is high. Delay signal T sam When the drive signals PWM1 and PWM2 are applied to the CLK terminal of the D flip-flop, and the output voltage detection circuit detects a certain delay in VD1 and VD2, in order to obtain the normal VD1 and VD2 under the current circuit state, a delay signal T is introduced into the CLK terminal of the D flip-flop. sam The delay-chopping stage can detect VD1 / VD2 within the corresponding period of the PWM signal, preventing the PWM signal and VD1 / VD2 from being out of the same period during detection. The D flip-flop is used to latch the logic signal V indicating whether the output voltage is normal or too low. NOR .
[0056] like Figure 4 As shown, the logic control circuit has four input terminals and three output terminals. The first input terminal is connected to the power enable signal VCCD, and the second input terminal is connected to the output terminal V of the output voltage detection circuit. NOR The third input terminal is connected to the logic signal T indicating whether the duration of the NMOS transistor voltage in the main circuit has reached the threshold. OSD The fourth input terminal is connected to the logic signal T indicating whether the circuit's sleep time has reached the threshold. SLEEP The first output terminal is connected to the enable signal TIM of the timer circuit. EN The second output terminal is connected to the enable signal PWM of the PWM waveform generation circuit. EN The third output terminal is connected to the timer circuit reset signal RST.
[0057] The first input terminal VCCD is connected to the sources of PMOS transistors P1 (the third switch) and P2 (the fourth switch), and the drain of PMOS transistor P1 is connected to the first output terminal TIM. EN Connected, the gate of PMOS transistor P1 is connected to the second input terminal V. NOR Connected, the drain of PMOS transistor P2 is connected to the second output terminal PWM. ENThe gate of PMOS transistor P2 is connected to the output of NOT1 (first NOT gate). The input of NOT1 is connected to the output Q of an RS flip-flop. The two inputs of AND1 (first AND gate) are connected to the input R and output Q of the RS flip-flop, respectively. The output of AND1 is connected to one of the inputs of OR3 (third OR gate). The output of XNOR is connected to the input R of the RS flip-flop. The two inputs of XNOR are connected to the output of AND2 and the logic signal T, respectively. SLEEP The output of OR2 (the second OR gate) is connected to the input S of an RS flip-flop. The two inputs of OR2 are connected to the outputs of NOT2 (the second NOT gate) and AND3, respectively. The input of NOT2 is connected to the output Q of the RS flip-flop. The other input of OR3 (the third OR gate) is connected to the logic signal T. SLEEP The output of OR3 is connected to the timer circuit reset signal RST. The two inputs of AND2 are connected to the outputs Q of the RS flip-flop and NOT3 (the third NOT gate), respectively. The input of NOT3 is connected to the logic signal T. OSD The three inputs of AND gate AND3 (the third AND gate) are connected to the output Q of an RS flip-flop, the output of NOT gate NOT3, and the output of NOT gate NOT4 (the fourth NOT gate), respectively. The input of NOT gate NOT4 is connected to the logic signal T. SLEEP .
[0058] The timer circuit includes three input terminals, including the enable signal TIM. EN The input terminal is the reset signal RST, the third input terminal is the power enable signal VCCD, and the two output terminals are logic signals T. OSD and logic signal T SLEEP The PWM waveform generator circuit has two input terminals: an enable signal (PWM) and a default signal (PWM). EN And the power enable signal VCCD, and two quasi-complementary output signals V1 and V2.
[0059] Based on the existing timer module, a binary counting method is used, combined with the counting frequency, for timing. The timer enable signal is TIM. EN From logic signal V NOR Decision. When the timer reaches 0.1 seconds, the logic signal T... OSD The signal transitions from low to high, and simultaneously, the reset signal RST generates a high-level pulse via the logic control circuit; when the timer restarts counting down to 0.8 seconds, the logic signal T... SLEEP When the signal changes from low to high, the reset signal RST generates a high-level pulse through the logic control circuit.
[0060] Based on the existing PWM waveform generation module, enable signal PWM ENThe logic control circuit outputs the input voltage of the module through a resistor divider, which adjusts the duty cycle of the PWM waveform and outputs two complementary signals.
[0061] like Figure 4 As shown, when PMOS transistor P1 is turned on, it indicates that V NOR When the signal is low, the enable signal TIM for the timer circuit is active. EN When the output is high, the timer circuit works normally and starts timing. At this time, the circuit is in the startup state. When the startup state exceeds 0.1 seconds, the circuit is determined to be in a short circuit state and immediately goes into sleep mode for 0.8 seconds.
[0062] In startup state, T OSD and T SLEEP When the logic signal T is low, it is considered low. OSD and T SLEEP The input R of the RS flip-flop is kept low by NOT3, AND2, and XNOR gates, thus controlling the logic signal T. OSD and T SLEEP The RS flip-flop's input S is kept high by OR gate OR2, NOT gate NOT2, AND gate AND3, and NOT gate NOT4, thus keeping the RS flip-flop's output Q high. The PWM signal is then generated via NOT gate NOT1 and PMOS transistor P2. EN When the signal is high, the PWM waveform generation circuit outputs V1 and V2 normally, enabling the circuit to start normally.
[0063] When the timer reaches the threshold of 0.1 seconds, the logic signal T... OSD When the signal transitions to a high level, the input R of the RS flip-flop becomes high through the XNOR gate, NOT3 gate, and AND2 gate. Simultaneously, the OR2 gate, NOT2 gate, AND3 gate, and NOT4 gate cause the input S of the RS flip-flop to go low, resulting in the output Q of the RS flip-flop going low. This output Q then passes through the NOT1 gate and the PMOS transistor P2 to generate the PWM signal. EN When the voltage drops to low, the circuit is in a short-circuit state.
[0064] AND gate AND1 and OR gate OR3 enable the RST signal. After the timer is reset, RST goes low, and the timer enters sleep mode. When the output Q of the RS flip-flop goes low, logic signal T... SLEEP Before the signal goes high, the XNOR gate, NOT3 gate, and AND2 gate keep the input R of the RS flip-flop high. The OR gate, NOT2 gate, AND3 gate, and NOT4 gate keep the input S of the RS flip-flop high, and the output Q of the RS flip-flop low. The signal is then processed by NOT1 gate and PMOS transistor P2 to obtain the PWM signal. ENIf the level remains low, the PWM waveform generation circuit will not operate.
[0065] RST remains low until the 0.8-second sleep time threshold is reached. When the timer reaches the 0.8-second threshold, the logic signal T... SLEEP When the voltage level changes to high, the XNOR gate, NOT3 gate, and AND2 gate cause the input R of the RS flip-flop to go low, while the input S of the RS flip-flop remains high. The output Q of the RS flip-flop then goes high, and through NOT1 gate and PMOS transistor P2, a PWM signal is generated. EN The RST signal remains high. At this time, the RST signal is valid, the timer is reset, the timer ends the previous timing cycle, and begins preparation for the next timing cycle.
[0066] Figure 5 T is the timer's cycle. OSD T SLEEP PWM EN The waveform diagram of RST shows the enable signal PWM of the PWM waveform generation circuit before the first set threshold of 0.1s is reached. EN A high level indicates that the PWM waveform generation circuit has two quasi-complementary outputs V1 and V2, and the circuit is in the startup state. When the logic output signal T of the timer circuit is high... OSD The output voltage goes high. Since the low-voltage period reaches the first threshold of 0.1s, it is determined that the output is in a short-circuit state, and the circuit enters sleep mode. At the same time, the RST signal of the timer circuit becomes valid, and the timer is reset. At this time, the enable signal PWM of the PWM waveform generation circuit... EN When the signal goes low, the PWM waveform generation circuit stops working. Simultaneously, the timer restarts, and during this process, the logic signal T is activated every 0.1 seconds. OSD It will jump to a high level, and when the timer reaches the second threshold of 0.8s, the logic signal T... SLEEP When the signal goes high, the sleep mode ends, the RST signal of the timer circuit becomes valid, the timer is reset, and the current timing cycle ends. The output voltage detection circuit determines the output voltage state and re-evaluates the logic signal V. NOR .
[0067] like Figure 6 As shown, the drive circuit during startup and normal push-pull operation includes six input terminals and two output terminals. The first and second input terminals are connected to the two outputs VH and VL of the reference / voltage divider circuit, respectively, and the third input terminal is connected to the output terminal V of the output voltage detection circuit. NORThe fourth and fifth input terminals are connected to the output terminals V1 and V2 of the PWM waveform generator circuit, respectively. The sixth input terminal is connected to the power enable signal VCCD. The first output terminal PWM1 and the second output terminal PWM2 are connected to the gates of the NMOS transistors N1 and N2 in the main circuit, respectively.
[0068] The first input terminal VH and the second input terminal VL are connected to the first and second input terminals of the selector, and the third input terminal V... NOR The third input terminal, fourth input terminal V1, and fifth input terminal V2 are connected to one end of resistors R1 and R2, respectively. The other end of resistor R1 is connected to the base of NPN transistor J1 and the base of PNP transistor J2. The other end of resistor R2 is connected to the base of NPN transistor J3 and the base of PNP transistor J4. The emitter of NPN transistor J1 is connected to the emitter of PNP transistor J2. The first output terminal PWM1 is connected to the emitter of NPN transistor J1. The emitter of NPN transistor J3 is connected to the emitter of PNP transistor J4. The second output terminal PWM2 is connected to the emitter of NPN transistor J3. The collectors of PNP transistor J2 and PNP transistor J4 are grounded. The collectors of NPN transistor J1 and NPN transistor J3 are connected to the output terminal of the selector.
[0069] like Figure 6 As shown, the selector's normal operation is ensured by the power supply enable signal VCCD. The two outputs of the reference / voltage divider circuit, namely the voltage signal VL during startup and the voltage signal VH during normal push-pull operation, are both used as inputs to the selector. The logic signal V output by the output voltage detection circuit is... NOR The switch orientation of the selector is determined by the logic signal V. NOR When the voltage level is low, the circuit is in the initial startup state. The selector connects the startup voltage signal VL. One output V1 of the PWM waveform generator circuit drives NPN transistor J1 and PNP transistor J2 through resistor R1. The other output V2 of the PWM waveform generator circuit drives NPN transistor J3 and PNP transistor J4 through resistor R2. The emitters of NPN transistor J1 and NPN transistor J3 output drive signals PWM1 and PWM2 respectively, which limit the current of the gates of NMOS transistors N1 and N2.
[0070] When logic signal V NOR When the voltage level is high, the circuit is in normal push-pull output state. The selector connects the voltage signal VH during normal push-pull operation. VH is greater than VL. The emitters of NPN transistor J1 and NPN transistor J3 output drive signals PWM1 and PWM2 respectively, which fully drive the gates of NMOS transistors N1 and N2, and the circuit outputs stably.
[0071] When the circuit is in a short-circuit state, the PWM waveform generation circuit does not work, and both V1 and V2 are at low level, which makes the gate drive signals PWM1 and PWM2 of NMOS transistors N1 and N2 at low level, and the main circuit will not work.
[0072] like Figure 7 As shown in the figure, the waveforms of PWM1 and PWM2 are displayed during startup and normal push-pull operation. There is a certain dead time between the two drive signals, and the amplitude of the drive signal is about 1.3V during startup and about 5V during normal push-pull operation.
[0073] The selector controls the amplitude of the PWM waveform to switch between two states: startup and normal push-pull. The logic signal V... NOR The NMOS transistor determines the switching of the selector. When the NMOS transistor operates in the saturation region, it acts as a controlled current source, providing current limiting protection. The current value I through the NMOS transistor... D With gate-source voltage V GS The relationship is:
[0074]
[0075] In equation (5) μ n For electron mobility, C ox Let V be the gate oxide capacitance per unit area, W and L be the gate width and gate length, respectively, λ be the channel length modulation coefficient, and V be the drain-source voltage. DS And the "threshold voltage" V corresponding to the formation of the channel TH This equation shows the finite slope of the saturation region caused by the channel length modulation effect, when the drain-source voltage V DS After reaching a certain value, the current value I of the NMOS transistor... D It remains almost unchanged. When the circuit is first started, the output voltage is relatively low, causing the drain-source voltage V of the turned-on NMOS transistor to remain almost constant. DS The current I is relatively large. To minimize losses when the NMOS transistor is turned on, this formula ensures that the NMOS transistor operates in the saturation region. D The slope of the change is finite, I D The value can be considered almost constant, achieving the effect of current limiting protection. When the circuit is just started or short-circuited, it avoids the NMOS transistor being in a bad state of high voltage and high current for a long time, reducing losses and reducing the possibility of safety hazards caused by excessive temperature, thus improving the reliability of the system.
[0076] Figure 8 For over-temperature detection and under-voltage / over-voltage detection circuits for input signals, the voltage input signal V IN and reference voltage signal V SETThe input terminal of the undervoltage / overvoltage detection circuit, which serves as both the over-temperature detection and input signal, receives the input signal. The undervoltage / overvoltage detection circuit measures the input voltage V. IN The internal temperature of the control circuit is detected. The output of the PMOS transistor is connected to VCCD, and the input of the PMOS transistor is connected to VCC. VCC is the power source for the power enable signal VCCD. The PMOS transistor is driven by the output of a three-way NAND gate. The inputs of the three NAND gates are respectively connected to the outputs of comparators corresponding to over-temperature, under-voltage, and over-voltage conditions. Based on the input voltage within the normal range (2.7-5.2V), the reference voltage signal V is determined by the proportional relationship of the three resistors R3, R4, and R5. SET The magnitude of the input voltage is determined by the output voltage. When the input voltage is within the normal range, both the fourth and fifth comparators output a high level. If the temperature is also within the normal range, the sixth comparator also outputs a high level. The three signals, after passing through a NAND gate, output a low level, turning on the PMOS transistor. The power supply enable signal VCCD is then valid, allowing the control circuit requiring VCCD power to operate normally. Conversely, if at least one of the three comparator outputs is low, it indicates that the circuit is in at least one of the abnormal states: undervoltage, overvoltage, or overtemperature. In this case, the power supply enable signal VCCD outputs a low level, shutting down all control chips requiring VCCD power. This prevents the circuit from malfunctioning under abnormal conditions, avoiding unnecessary losses and safety hazards, and increasing system reliability.
[0077] Figure 9 This is a time-delay chopper circuit in the output voltage detection circuit. The time-delay chopper circuit includes a first capacitor C1, with its positive terminal connected to the output of the first OR gate and its negative terminal connected to the first input of the NOR gate and the input of the parallel branch. The parallel branch includes a first diode D3 and a first resistor R8 connected in parallel. The output of the NOR gate is connected to the input of the fifth NOT gate (NOT5) through a second capacitor C2. The output of the fifth NOT gate is connected to a second resistor R10, which is grounded through a third capacitor C3. The second resistor is connected in parallel with the second diode D5. The anode of the second diode is connected to the positive input of the third comparator COMP5, and the cathode of the second diode is connected to the second input of the NOR gate. The negative input of the third comparator receives the reference voltage signal V. SET The anode of the third diode D4 and one end of the third resistor R9 are connected between the second capacitor and the input of the fifth NOT gate. The cathode of the third diode and the other end of the third resistor are connected to the power supply enable signal VCCD.
[0078] The section before resistor R10 and diode D5 is used to chop the latter part of the PWM waveform. Utilizing the charging time of R9 and C2, the PWM waveform is brought low in advance. The NOR gate and NOT gate (NOT5) are used to maintain the signal state. The section after the NOT gate is used to chop the first part of the PWM waveform. Utilizing the charging time of R10 and C3, the PWM waveform returns to a high level after a delay, and the output T is then sent to the third comparator. sam Delayed signal, thus obtaining Figure 3 waveform, Figure 9 The diodes in the capacitor are mainly used for capacitor discharge.
[0079] Compared with existing technologies, this invention, from the perspective of control circuit design, has the following characteristics: Without increasing the complexity of the main circuit, the complexity of the circuit is reduced by designing the control circuit, thus reducing the system size and further reducing power consumption, which is beneficial for the miniaturization and integration of the control chip; through the control and coordination of the output voltage detection circuit, logic control circuit, timer circuit, and drive circuits during startup and normal push-pull operation, the system can achieve self-starting. During startup, current limiting protection can be implemented for NMOS transistors N1 and N2, and the circuit outputs stably during normal push-pull operation; through the control of the output voltage detection circuit, logic control circuit, and timer circuit, serious consequences caused by short circuits or heavy load interference can be prevented, avoiding prolonged overvoltage of NMOS transistors N1 and N2, and improving the safety and reliability of the circuit; through over-temperature detection and undervoltage / overvoltage detection circuits, real-time monitoring of the voltage input signal and system temperature can be achieved, preventing the circuit from malfunctioning when the input voltage is outside the set threshold range, thereby improving the reliability of the system.
Claims
1. A control circuit for a push-pull converter, characterized in that, include: transformer; The primary side of the transformer is connected to the first and second switching transistors; both the first and second switching transistors are NMOS transistors; the drains of the first and second NMOS transistors are connected to the output voltage detection circuit; the gates of the first and second NMOS transistors are connected to the driving circuit; and the sources of the first and second NMOS transistors are grounded. The output voltage detection circuit includes a first comparator and a second comparator; the positive input terminal of the first comparator is connected to the drain of the first NMOS transistor, the negative input terminal of the first comparator is connected to the negative input terminal of the second comparator, and the positive input terminal of the second comparator is connected to the drain of the second NMOS transistor; the output terminals of the first and second comparators are respectively connected to the two input terminals of a NAND gate; the output terminal of the NAND gate is connected to the first input terminal of a D flip-flop, the second input terminal of the D flip-flop is connected to the output terminal of a first OR gate, and the two input terminals of the first OR gate are respectively connected to the two output terminals of the PWM waveform generation circuit; The output voltage detection circuit is connected to the logic control circuit; the logic control circuit includes a third switch and a fourth switch; the input terminals of the third and fourth switches receive power enable signals, the output terminal of the third switch is connected to the enable input terminal of the timer circuit, and the output terminal of the fourth switch is connected to the enable input terminal of the PWM waveform generation circuit; the control terminal of the third switch is connected to the output terminal of the output voltage detection circuit, and the control terminal of the fourth switch is connected to the output terminal of the first NOT gate; the input terminal of the first NOT gate is connected to the output terminal of the RS flip-flop; the first input terminal and the output terminal of the RS flip-flop are respectively connected to the two input terminals of the first AND gate, and the output terminal of the first AND gate is connected to the first input terminal of the third OR gate; the second input terminal of the third OR gate... The first input terminal of the XNOR gate is connected to the first logic signal; the output terminal of the XNOR gate is connected to the first input terminal of the RS flip-flop, and the second input terminal of the XNOR gate is connected to the output terminal of the second AND gate; the first input terminal of the second AND gate is connected to the output terminal of the RS flip-flop, and the second input terminal is connected to the first input terminal of the third AND gate and the output terminal of the third NOT gate, the input signal of the third NOT gate being the second logic signal; the second input terminal of the third AND gate is connected to the output terminal of the fourth NOT gate, the input signal of the fourth NOT gate being the first logic signal; the third input terminal of the third AND gate is connected to the input terminal of the second NOT gate and the output terminal of the RS flip-flop; the output terminal of the second NOT gate is connected to the first input terminal of the second OR gate, the output terminal of the third AND gate is connected to the second input terminal of the second OR gate; the output terminal of the second OR gate is connected to the second input terminal of the RS flip-flop.
2. The control circuit of the push-pull converter according to claim 1, characterized in that, When the magnitude of the voltage input signal V IN The push-pull converter operates when the value is within the set range.
3. The control circuit of the push-pull converter according to claim 1, characterized in that, The current value I of the first NMOS transistor / second NMOS transistor D With gate-source voltage V GS The relationship is: ; where μ n For electron mobility, C ox V is the gate oxide capacitance per unit area, W and L are the gate width and gate length, respectively, λ is the channel length modulation coefficient, and V DS This is the drain-source voltage.
4. The control circuit of the push-pull converter according to claim 1, characterized in that, The output of the first OR gate is connected to the second input of the D flip-flop via a delay chopper circuit.
5. The control circuit of the push-pull converter according to claim 4, characterized in that, The delay chopper circuit includes a first capacitor, the positive terminal of which is connected to the output of a first OR gate, and the negative terminal of which is connected to the first input of a NOR gate and the input of a parallel branch. The parallel branch includes a first diode and a first resistor connected in parallel. The output of the NOR gate is connected to the input of a fifth NOT gate through a second capacitor, and the output of the fifth NOT gate is connected to a second resistor. The second resistor is grounded through a third capacitor. The second resistor is connected in parallel with the second diode. The anode of the second diode is connected to the positive input of a third comparator, and the cathode of the second diode is connected to the second input of the NOR gate. A reference voltage signal is input to the negative input of the third comparator. The anode of the third diode and one end of the third resistor are connected between the second capacitor and the input of the fifth NOT gate, and the cathode of the third diode and the other end of the third resistor are used to input a power enable signal.
6. The control circuit of the push-pull converter according to claim 1, characterized in that, Both the negative input terminals of the first comparator and the negative input terminals of the second comparator are connected to the output terminals of the reference / voltage divider circuit.
7. The control circuit of the push-pull converter according to claim 1, characterized in that, Each of the two taps on the secondary side of the transformer is connected to a diode, and both diodes are connected to the positive terminal of the capacitor; the middle tap on the secondary side of the transformer is connected to the negative terminal of the capacitor. in, When the first switch and the second switch are turned on alternately, the two diodes are turned on alternately. When the control terminal drive signal of the first switch is high, the input terminal voltage VD1 of the first switch and the input terminal voltage VD2 of the second switch are respectively: ; ; When the control terminal drive signal of the second switch is high, the input terminal voltage VD1 of the first switch and the input terminal voltage VD2 of the second switch are respectively: ; ; N is the transformer turns ratio, V IN V represents the magnitude of the voltage input signal. OUT V is the output voltage across the capacitor. D1 V D2 These are the forward voltage drops of the two diodes.
8. The control circuit of the push-pull converter according to claim 1, characterized in that, The driving circuit includes a selector; the first and second input terminals of the selector are respectively connected to the two output terminals of the reference / voltage divider circuit, and the third input terminal is connected to the output terminal of the output voltage detection circuit; the output terminal of the selector is connected to the input terminals of the first and third transistors, the output terminal of the third transistor is connected to the input terminal of the fourth transistor, the output terminal of the fourth transistor is connected to the output terminal of the second transistor, and the input terminal of the second transistor is connected to the output terminal of the first transistor; the control terminals of the first and second transistors are connected to a resistor, and the resistor input terminal is connected to the first output terminal of the PWM waveform generation circuit; the control terminals of the third and fourth transistors are connected to the second output terminal of the PWM waveform generation circuit; the first output terminal of the driving circuit is led out between the output terminal of the first transistor and the input terminal of the second transistor, and the second output terminal of the driving circuit is led out between the output terminal of the third transistor and the input terminal of the fourth transistor; the first and second output terminals are respectively connected to the control terminals of the first and second switching transistors.