Channel decoding apparatus and method based on reconfigurable processor architecture design

Abstract

The application relates to a channel decoding device and method based on a reconfigurable processor architecture design. The channel decoding device comprises a first calculator, a second calculator and an output device; the first calculator is used for determining extrinsic information of each variable node in a current decoding operation according to a preset check matrix, target variables corresponding to each variable node and intermediate variables; the second calculator is used for determining check information of each check node corresponding to each variable node according to the preset check matrix, the extrinsic information of each variable node in the current decoding operation and the target variables; and the output device is used for determining target decoding information corresponding to each to-be-decoded information according to the check information of each check node. The efficiency of channel decoding is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of channel decoding, in particular to a channel decoding device and method based on reconfigurable processor architecture design. BACKGROUND

[0002] For a long time, human beings have been pursuing efficient, reliable and safe information communication methods, and a variety of communication tools and means have been born, which are constantly promoting the development and progress of human society. In a communication system, in order to enhance the ability of data to resist various interference when transmitted in a channel of the communication system and improve the reliability of the communication system, the original information transmitted in the communication system needs to be channel encoded to obtain encoded information. The encoded information will be interfered by noise when transmitted through the channel. In order to extract the original information from the encoded information, channel decoding needs to be performed on the encoded information interfered by noise.

[0003] The traditional channel decoding device is a channel decoding device based on soft decision decoding algorithm. The decoding efficiency of the traditional channel decoding device is low. SUMMARY

[0004] Therefore, it is necessary to provide a channel decoding device and method based on reconfigurable processor architecture design, which can improve the channel decoding efficiency.

[0005] In a first aspect, the present application provides a channel decoding device based on block codes. The device comprises a first calculator, a second calculator and an output device.

[0006] The first calculator is configured to determine extrinsic information of each variable node in a current decoding operation according to a preset check matrix, a target variable and an intermediate variable corresponding to each variable node. The initial information of the target variable is to-be-decoded information. The target variable in other decoding operations is determined according to check information of a check node corresponding to the variable node in a previous decoding operation. The intermediate variable is determined according to extrinsic information of the variable node in the previous decoding operation.

[0007] The second calculator is configured to determine check information of a check node corresponding to each variable node according to the preset check matrix, extrinsic information of each variable node in the current decoding operation and the target variable.

[0008] The output device is configured to determine target decoding information corresponding to each to-be-decoded information according to check information of each check node.

[0009] In one embodiment, the first calculator is configured to determine a first target variable node from each variable node according to the preset check matrix, and determine a target variable and an intermediate variable corresponding to the first target variable node.

[0010] the first calculator is configured to determine variable node information corresponding to each of the first target variable nodes according to the target variable and the intermediate variable corresponding to each of the first target variable nodes;

[0011] the first calculator is configured to determine extrinsic information of the first target variable nodes according to the variable node information corresponding to each of the first target variable nodes, and determine extrinsic information of the second target variable nodes according to the target variable of the second target variable nodes; each of the variable nodes includes the first target variable nodes and the second target variable nodes.

[0012] In one of the embodiments, the first calculator includes a synchronous shift unit, a calculation unit, a control unit and a register unit.

[0013] the control unit is configured to send a first instruction to the synchronous shift unit and a second instruction to the calculation unit;

[0014] the synchronous shift unit is configured to determine a starting variable node from the variable nodes corresponding to each of the first target variable nodes, and send each of the starting variable nodes to the calculation unit according to the first instruction; the starting variable node is the first variable node in the variable nodes corresponding to each of the first target variable nodes in each decoding operation;

[0015] the calculation unit is configured to determine extrinsic information of each of the variable nodes in the current decoding operation according to the preset check matrix, the target variable corresponding to each of the variable nodes, the intermediate variable and the starting variable node, and output the extrinsic information of each of the variable nodes according to the second instruction.

[0016] the register unit is configured to receive a third instruction sent by the control unit, and send the variable node information corresponding to each of the variable nodes to the synchronous shift unit and the calculation unit according to the third instruction.

[0017] In one of the embodiments, the second calculator is configured to determine a first target check node from each of the check nodes according to the preset check matrix, and determine extrinsic information of the variable nodes corresponding to the first target check node and the target variable.

[0018] the second calculator is configured to determine check information of the first target check node according to the extrinsic information of the variable nodes corresponding to the first target check node and the target variable, and determine check information of the second target check node according to the target variable of the second target check node; each of the check nodes includes the first target check node and the second target check node.

[0019] In one of the embodiments, the output device includes a decoding information register and a decoding information checker, and the decoding information register is connected to the decoding information checker.

[0020] The decoding information register is configured to obtain the check information of each check node determined by the second calculator, and perform hard decision on the check information of each check node to determine the quasi-decoding information;

[0021] The decoding information checker is configured to obtain the quasi-decoding information, and perform check on the quasi-decoding information according to the preset check matrix to obtain a check result, and if the check result is a check pass, take the quasi-decoding information as the target decoding information, and output the target decoding information.

[0022] In one of the embodiments, the channel decoding device further comprises a controller connected with the first calculator, the second calculator, the decoding information register and the decoding information checker;

[0023] The controller is configured to obtain the check result in the decoding information checker, if the check result is a check fail, accumulate the total number of current decoding operations, if the total number of current decoding operations is less than a preset number, send a fourth instruction to the first calculator and the second calculator;

[0024] The first calculator is configured to return to perform the step of determining the extrinsic information of each variable node in the current decoding operation according to the preset check matrix, the target variable and the intermediate variable corresponding to each variable node according to the fourth instruction;

[0025] The second calculator is configured to return to perform the step of determining the check information of each check node corresponding to each variable node according to the preset check matrix, the extrinsic information of each variable node in the current decoding operation and the target variable according to the fourth instruction.

[0026] In one of the embodiments, the controller is configured to send a fifth instruction to the decoding information register if the total number of current decoding operations is equal to the preset number;

[0027] The decoding information register is configured to take the quasi-decoding information of the current time as the target decoding information according to the fifth instruction, and output the target decoding information.

[0028] In one of the embodiments, the channel decoding device further comprises an intermediate variable register connected with the first calculator, the second calculator, the decoding information register and the controller;

[0029] The intermediate variable register is configured to receive a sixth instruction sent by the controller, obtain the extrinsic information corresponding to each variable node according to the sixth instruction, and send the check information of each check node in the last decoding operation and the extrinsic information corresponding to each variable node in the last decoding operation to the first calculator;

[0030] The intermediate variable register is configured to receive a seventh instruction sent by the controller, obtain the check information of each check node according to the seventh instruction, and send the extrinsic information corresponding to each variable node in the current decoding operation and the check information of each check node in the last decoding operation to the second calculator;

[0031] The intermediate variable register is configured to receive an eighth instruction sent by the controller, and send the check information of each check node in the current decoding operation to the decoding information register according to the seventh instruction.

[0032] In one of the embodiments, the intermediate variable register comprises a skip unit;

[0033] The skip unit is configured to select a third target variable node that needs to be skipped according to a preset skipping rule, and skip the step of sending the extrinsic information of the third target variable node to the first calculator and the second calculator;

[0034] The skip unit is configured to select a third target check node that needs to be skipped according to the preset skipping rule, and skip the step of sending the check information of the third target check node to the first calculator and the second calculator.

[0035] In a second aspect, the present application further provides a channel decoding method based on a block code. The method comprises:

[0036] Determining the extrinsic information of each variable node according to the preset check matrix and the to-be-decoded information corresponding to each variable node;

[0037] Determining the check information of a check node corresponding to each variable node according to the preset check matrix and the extrinsic information corresponding to each variable node;

[0038] Determining the target decoding information according to the check information of each check node.

[0039] In a third aspect, the present application further provides a computer device. The computer device comprises a memory and a processor, the memory stores a computer program, and the processor realizes the following steps when executing the computer program:

[0040] Determining the extrinsic information of each variable node according to the preset check matrix and the to-be-decoded information corresponding to each variable node;

[0041] Determining the check information of a check node corresponding to each variable node according to the preset check matrix and the extrinsic information corresponding to each variable node;

[0042] Determining the target decoding information according to the check information of each check node.

[0043] In a fourth aspect, the present application provides a computer readable storage medium. The computer readable storage medium has a computer program stored thereon, which, when executed by a processor, implements the following steps:

[0044] According to the preset check matrix and the to-be-decoded information corresponding to each variable node, external information of each variable node is determined;

[0045] According to the preset check matrix and the external information corresponding to each variable node, check information of a check node corresponding to each variable node is determined;

[0046] According to the check information of each check node, the target decoding information is determined.

[0047] In a fifth aspect, the present application provides a computer program product. The computer program product comprises a computer program, which, when executed by a processor, implements the following steps:

[0048] According to the preset check matrix and the to-be-decoded information corresponding to each variable node, external information of each variable node is determined;

[0049] According to the preset check matrix and the external information corresponding to each variable node, check information of a check node corresponding to each variable node is determined;

[0050] According to the check information of each check node, the target decoding information is determined.

[0051] The channel decoding device and method based on the reconfigurable processor architecture design, the channel decoding device comprises a first calculator, a second calculator and an output device. The first calculator is configured to determine external information of each variable node in a current decoding operation according to a preset check matrix, target variables and intermediate variables corresponding to each variable node. The second calculator is configured to determine check information of a check node corresponding to each variable node according to the preset check matrix, the external information and the target variables corresponding to each variable node in the current decoding operation. The output device is configured to determine target decoding information corresponding to each to-be-decoded information according to the check information of each check node. In a traditional channel decoding device, variable information of each variable node and check information of a check node need to be determined in sequence, and the calculation of the variable information of each variable node cannot be performed synchronously, so the decoding efficiency is low. In the present application, the external information of each variable node is determined according to the preset check matrix, the target variables and the intermediate variables corresponding to each variable node. If the preset check matrix, the target variables and the intermediate variables corresponding to each variable node are known, the external information of each variable node can be calculated synchronously, thereby improving the efficiency of channel decoding. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1is one of structural block diagrams of a channel decoding device provided by an embodiment of the present application;

[0053] Figure 2 is one of structural block diagrams of a channel decoding device provided by an embodiment of the present application;

[0054] Figure 3 is one of structural block diagrams of a channel decoding device provided by an embodiment of the present application;

[0055] Figure 4 is one of structural block diagrams of a channel decoding device provided by an embodiment of the present application;

[0056] Figure 5 is one of structural block diagrams of a channel decoding device provided by an embodiment of the present application; DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0058] Unless otherwise defined, all technical and scientific terms used herein are intended to have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the present application belong. The terminology used in the description of the embodiments of the present application herein is only for the purpose of describing specific embodiments of the present application and is not intended to limit the present application.

[0059] First, before specifically introducing the technical solutions of the embodiments of the present application, the technical background or technical evolution context based on which the embodiments of the present application are introduced. In a communication system, in order to enhance the ability of data to resist various interference when transmitted in the channel of the communication system, and to improve the reliability of the communication system, the original information transmitted in the communication system needs to be channel encoded to obtain encoded information. The encoded information will be interfered by noise when transmitted through the channel. In order to extract the original information from the encoded information, channel decoding needs to be performed on the encoded information interfered by noise.

[0060] The traditional channel decoding device is a channel decoding device based on a soft decision decoding algorithm. Common soft decision algorithms include Min Sum (MS), Normalized Min Sum (NMS), Offset Min Sum (OMS), etc. Since the calculation complexity of the above-mentioned several soft decision algorithms is high, the channel decoding device based on the above-mentioned several soft decision algorithms has large resource consumption in the process of channel decoding, and the variable information of each variable node needs to be calculated in sequence, so the channel decoding efficiency is low.

[0061] Based on this, this application provides a channel decoding device 100 based on block codes. In this application, the information to be decoded is divided into multiple sub-information, and each variable node and each check node is applied to process each sub-information of the information to be decoded. The device uses the Sum Product Algorithm (SPA) to calculate the extrinsic information of each variable node. Since the channel decoding device provided by this application can process the sub-information of the information to be decoded and apply each variable node and each check node to process each sub-information of the information to be decoded, and when the check node and variable node change, the channel decoding device provided by this application can also reconstruct according to the number of variable nodes and check nodes in the information to be decoded, thus exhibiting high flexibility. Figure 1 As shown, the channel decoding device 100 includes a first calculator 101, a second calculator 102, a decoding information register 103, a decoding information verifier 104, a controller 105, a register of information to be decoded 106, a preset check matrix register 107, and an intermediate variable register 108. The first calculator 101 is connected to the controller 105, the register of information to be decoded 106, the preset check matrix register 107, and the intermediate variable register 108. It is used to determine the external information of each variable node in the current decoding operation based on the preset check matrix stored in the preset check matrix register 107 and the target variable and intermediate variable corresponding to each variable node stored in the intermediate variable register 108. The initial information of the target variable is the information to be decoded stored in the register of information to be decoded 106. The second calculator 102 is connected to the controller 105, the preset check matrix register 107, and the intermediate variable register 108. The second calculator 102 is used to determine the check information of the check nodes corresponding to each variable node based on the preset check matrix stored in the preset check matrix register 107, the external information corresponding to each variable node in the current decoding operation stored in the intermediate variable register 108, and the target variable. The decoding information register 103 is connected to the decoding information verifier 104, the controller 105, and the intermediate variable register 108, and is used to determine the quasi-decoding information based on the check information of the check nodes stored in the intermediate variable register 108. The decoding information verifier 104 is connected to the preset check matrix register 107, the decoding information register 103, and the controller 105, and is used to verify the quasi-decoding information in the decoding information register 103 to determine the target decoding information. Since the first calculator 101 determines the extrinsic information of each variable node based on the preset check matrix, the target variable and intermediate variable corresponding to each variable node, if the preset check matrix, the target variable and intermediate variable corresponding to each variable node are known, the extrinsic information of each variable node can be calculated synchronously, which improves the efficiency of channel decoding.

[0062] In one embodiment, such asFigure 2 As shown, Figure 2 This is a second structural block diagram of the channel decoding device provided in the embodiments of this application. The channel decoding device 200 includes a first calculator 201, a second calculator 202, and an output device 203.

[0063] The first calculator 201 is used to determine the external information of each variable node in the current decoding operation based on the preset check matrix, the target variable and intermediate variable corresponding to each variable node; the initial information of the target variable is the information to be decoded, and in other decoding operations, the target variable is determined according to the check information of the check node corresponding to the variable node in the previous decoding operation, and the intermediate variable is determined according to the external information corresponding to the variable node in the previous decoding operation.

[0064] Among them, variable nodes can be preset according to the actual information to be decoded.

[0065] The preset verification matrix stores operation instructions indicating whether each variable node should perform the corresponding extrinsic information calculation. If the number of variable nodes is m, each variable node is set as V = {v1, v2, ..., v...} m The set of target variables corresponding to each variable node is S. v ={s v1 s v2 , ..., s vm In the first decoding operation, the initial information of the target variable is the pre-stored decoding information in the first calculator. In subsequent decoding operations, the first calculator 201 obtains the verification information of each verification node from the second calculator 202 during the previous decoding operation, and uses the verification information of the verification node corresponding to each variable node as the target variable of each variable node. The set of intermediate variables corresponding to each variable node is M. v ={M v1 M v2 M vm}. If, according to the preset check matrix, the indicator variable nodes v1 to v m If external information needs to be calculated, then v1 to v m target variable minus v1 to v m Intermediate variables determine the transition from v1 to v m The variable node information. Using a preset algorithm, based on v1 to v... m The variable node information determines the path from v1 to v m External information Y v ={y v1 y v2 , ..., y vm The default algorithm can be the SumProduct Algorithm (SPA).

[0066] In this embodiment, it should be noted that during the first decoding operation, the intermediate variable M of each variable node... v When the value is 0, the target variable of each variable node is the information to be decoded; during other decoding operations, the intermediate variable M of each variable node is 0. v The external information of each variable node is the extrinsic information from the previous decoding operation, and the target variable of each variable node is the check information of the check node corresponding to each variable node in the previous decoding operation. After determining the variable node information of each variable node, the external information of each variable node can be calculated synchronously to improve the calculation efficiency of the external information of each variable node.

[0067] The second calculator 202 is used to determine the verification information of the verification nodes corresponding to each variable node based on the preset verification matrix, the external information corresponding to each variable node in the current decoding operation, and the target variable.

[0068] Among them, the verification nodes can be preset according to the actual information to be decoded.

[0069] The preset verification matrix stores operation instructions indicating whether each verification node should perform the corresponding verification information calculation. Each verification node is set as C = {c1, c2, ..., c...} n Each verification node and each variable node are related. For example... Figure 3 As shown, node c1 is associated with nodes v1 and v3. The verification information of c1 is obtained by adding the extrinsic information corresponding to v1 and v3 and the target variable during the current decoding operation. The target variable is the verification information of c1 during the previous decoding operation, and its initial information is the information to be decoded. In this embodiment, the second calculator 202 obtains the extrinsic information of each variable node in the first calculator 201, and adds the target variable to the extrinsic information of the variable nodes corresponding to each verification node to obtain the verification information of each verification node. Similarly, the target variable corresponding to each variable node is the verification information of the corresponding verification node in the previous decoding operation, for example, Figure 3 In the middle, the v2 node is related to c2 and c n If they are related, then the target variables corresponding to v2 are c2 and c. n The node's verification information from the previous decoding operation.

[0070] The output device 203 is used to determine the target decoding information corresponding to each piece of information to be decoded based on the verification information of each verification node.

[0071] In this embodiment, after obtaining the verification information of each verification node, the output device 203 acquires the verification information corresponding to each verification node in the second calculator 202, and processes the verification information of each verification node. The hard decision is performed to obtain the quasi-decoding information X. At this time, the output device 203 performs checking on the quasi-decoding information X by using the preset check matrix H stored in advance, and if the checking is passed, the quasi-decoding information X is taken as the target decoding information, and the target decoding information is output.

[0072] In the embodiment of the present application, the channel decoding device comprises a first calculator, a second calculator and an output device. The first calculator is configured to determine extrinsic information of each variable node in the current decoding operation according to a preset check matrix, target variables and intermediate variables corresponding to each variable node. The second calculator is configured to determine check information of each check node corresponding to each variable node according to the preset check matrix, the extrinsic information and the target variables of each variable node in the current decoding operation. The output device is configured to determine target decoding information corresponding to each to-be-decoded information according to the check information of each check node. In the conventional channel decoding device, the variable information of each variable node and the check information of each check node are determined sequentially, and the calculation of the variable information of each variable node cannot be performed synchronously, so the decoding efficiency is low. In the embodiment, the extrinsic information of each variable node is determined according to the preset check matrix, the target variables and the intermediate variables corresponding to each variable node. If the preset check matrix, the target variables and the intermediate variables corresponding to each variable node are known, the extrinsic information of each variable node can be calculated synchronously, so the efficiency of channel decoding is improved.

[0073] In one of the embodiments, the first calculator 201 is configured to determine a first target variable node from each variable node according to a preset check matrix, and determine target variables and intermediate variables corresponding to the first target variable node.

[0074] The first calculator 201 is configured to determine variable node information corresponding to each first target variable node according to the target variables and the intermediate variables corresponding to the first target variable node.

[0075] For example, the first calculator 201 determines the target variables and the intermediate variables corresponding to each first target variable node according to the operation indication information of the preset check matrix. m The first target variable node is determined, and the target variables and the intermediate variables corresponding to the first target variable node are obtained. For each first target variable node, the target variables and the intermediate variables corresponding to each first target variable node are first determined according to the operation indication information of the preset check matrix. to and the intermediate variables to are subtracted to obtain variable node information For example: After the variable node information of each first target variable node is determined, the extrinsic information of each first target variable node is determined by using a preset algorithm according to the variable node information of each first target variable node. For example, the extrinsic information of the v2 node The variable node information of v3 to v m The variable node information of v3 to v The variable node information of v3 to v

[0076] The first calculator 201 is configured to determine extrinsic information of the first target variable node according to the variable node information corresponding to each first target variable node, and determine extrinsic information of the second target variable node according to the target variable of the second target variable node. Each variable node includes the first target variable node and the second target variable node.

[0077] When determining the extrinsic information of the second target variable node, the target variable of the second target variable node can be directly taken as the extrinsic information of the second target variable node. For example, when the v1 node is taken as the second target variable node, the target variable corresponding to the v1 node can be taken as the extrinsic information of the v1 node.

[0078] Alternatively, the target variable corresponding to the v1 node can also be taken as the variable node information corresponding to the v1 node. The extrinsic information of the v1 node is determined according to the variable node information of each variable node by using a preset algorithm.

[0079] In the embodiments of the present application, the first calculator is configured to determine the first target variable node from each variable node according to the preset check matrix, and determine the target variable and the intermediate variable corresponding to the first target variable node. The first calculator is configured to determine the variable node information corresponding to each first target variable node according to the target variable and the intermediate variable corresponding to the first target variable node. The first calculator is configured to determine the extrinsic information of the first target variable node according to the variable node information corresponding to each first target variable node, and determine the extrinsic information of the second target variable node according to the target variable of the second target variable node. By distinguishing each variable node into the first target variable node and the second target variable node, the calculation process of the extrinsic information of the second target variable node is reduced, the resource consumption of the channel decoding device is reduced, and the efficiency of determining the extrinsic information of each variable node is improved.

[0080] In one of the embodiments, the first calculator 201 further includes a synchronous shift unit, a calculation unit, a control unit and a register unit.

[0081] The control unit is configured to send a first instruction to the synchronous shift unit and a second instruction to the calculation unit.

[0082] ​​​In this embodiment, the control unit is configured to send a first instruction to the synchronous shift unit and a second instruction to the calculation unit, the first instruction is an instruction indicating the synchronous shift unit to send the starting variable nodes to the calculation unit, and the second instruction is an instruction indicating the calculation unit to output the extrinsic information of each variable node.

[0083] The synchronous shift unit is configured to determine the starting variable nodes from the variable nodes corresponding to each first target variable node, and send each starting variable node to the calculation unit according to the first instruction; the starting variable node is the first variable node in each variable node corresponding to each first target variable node in each decoding operation.

[0084] In this embodiment, it should be noted that in the process of calculating the extrinsic information of the first target variable node using the SPA algorithm, the variable node information corresponding to each variable node is required, and the synchronous shift unit determines the starting variable node from each variable node corresponding to the first target variable node. For example, if the extrinsic information of the v2 node needs to be determined according to the variable node information of v3 to v m The variable nodes corresponding to the v2 node are v3 to v m At this time, the synchronous shift unit can take v3 as the starting variable node, and send the starting variable node v3 to the calculation unit.

[0085] The calculation unit is configured to determine the extrinsic information of each variable node in the current decoding operation according to the preset check matrix, the target variable, the intermediate variable, and the starting variable node corresponding to each variable node, and output the extrinsic information of each variable node according to the second instruction.

[0086] After the calculation unit receives the starting variable node sent by the synchronous shift unit, the extrinsic information of each variable node in the current decoding operation is determined according to the preset check matrix, the target variable, the intermediate variable, and the starting variable node corresponding to each variable node, and the extrinsic information of each variable node in the current decoding operation is output according to the second instruction.

[0087] Alternatively, the calculation unit can also directly determine the extrinsic information of each variable node according to the variable node information of each variable node sent by the register unit.

[0088] The register unit is configured to receive a third instruction sent by the control unit, and send the variable node information corresponding to each variable node to the synchronous shift unit and the calculation unit according to the third instruction.

[0089] The register unit stores the variable node information of each variable node, and in this embodiment, the register unit 404 receives a third instruction sent by the control unit, and the third instruction is an instruction indicating the register unit to send the variable node information corresponding to each variable node to the synchronous shift unit 401 and the calculation unit. ​

[0090] Optionally, the register unit is also used to determine the variable node information of each variable node by subtracting the intermediate variable from the target variable of each variable node according to the preset check matrix, and store the variable node information of each variable node.

[0091] In one embodiment, the second calculator 202 is used to determine the first target check node from each check node according to the preset check matrix, and determine the extrinsic information of the variable node corresponding to the first target check node and the target variable.

[0092] For example, taking the first target check node c2 as an example, the second calculator 202 determines the extrinsic information of the variable node corresponding to the first target check node c2 and the target variable according to the operation instruction information of the preset check matrix. Figure 3 The c2 node is connected with v1, v2 and v m , so the extrinsic information of the variable node corresponding to c2 is the extrinsic information of v1, v2 and v m in the current decoding operation process. v1 , y v2 and y vm . In the first decoding operation, the target variable is the to-be-decoded information, and in other decoding operations, the target variable is the check information of the c2 node in the last decoding operation. Similarly, the extrinsic information of the variable node corresponding to other first target check nodes and the target variable are obtained.

[0093] The second calculator 202 is used to determine the check information of the first target check node according to the extrinsic information of the variable node corresponding to the first target check node and the target variable, and determine the check information of the second target check node according to the target variable of the second target check node; each check node includes the first target check node and the second target check node.

[0094] For the check information of each first target check node, the extrinsic information of the variable node corresponding to each first target check node and the target variable obtained by the above steps can be added to obtain, for example, if the current time is the first decoding operation, the check information of c2 in the current decoding operation process can be obtained by adding the extrinsic information of v1, v2, v m and the to-be-decoded information corresponding to the c2 node; if the current time is not the first decoding operation, the check information of c2 in the current decoding operation process can be obtained by adding the extrinsic information of v1, v2, v m and the check information of the c2 node in the last decoding operation.

[0095] For the second target check node, the target variable of the second target check node can be directly taken as the check information of the second target check node. For example, c1 is determined as the second target check node, if the current decoding operation is the first decoding operation, the to-be-decoded information corresponding to the c1 node can be determined as the check information of the c1 node. If the current decoding operation is not the first decoding operation, the check information of the c1 node in the last decoding operation can be taken as the check information of the c1 node in the current decoding operation.

[0096] In the embodiment of the present application, the second calculator is configured to determine a first target check node from the check nodes according to the preset check matrix, and determine the extrinsic information and the target variable of the variable node corresponding to the first target check node. The second calculator is configured to determine the check information of the first target check node according to the extrinsic information and the target variable of the variable node corresponding to the first target check node, and determine the check information of the second target check node according to the target variable of the second target check node. The check nodes include the first target check node and the second target check node. By distinguishing the check nodes into the first target check node and the second target check node, the calculation process of the check information of the second target check node is reduced, thereby reducing the resource consumption of the channel decoding device and improving the efficiency of determining the extrinsic information of the variable nodes.

[0097] In one of the embodiments, the output device 203 includes a decoding information register and a decoding information checker, and the decoding information register is connected to the decoding information checker.

[0098] The decoding information register is configured to acquire the check information of the check nodes determined by the second calculator 202, and perform hard decision on the check information of the check nodes to determine the quasi-decoding information.

[0099] For example, the second calculator sends the check information of the check nodes in the current decoding operation to the decoding information register, and the decoding information register performs hard decision on the check information of the check nodes to obtain the quasi-decoding information X.

[0100] Optionally, the decoding information register can also actively acquire the check information of the check nodes from the second calculator.

[0101] The decoding information checker is configured to acquire the quasi-decoding information, perform check on the quasi-decoding information according to the preset check matrix to obtain a check result, take the quasi-decoding information as the target decoding information if the check result is passed, and output the target decoding information.

[0102] ​With the above examples, the decoding information register sends the quasi-decoding information to the decoding information checker, and the decoding information checker can check the quasi-decoding information according to the preset check matrix H stored, and the check formula is as follows:

[0103] X x H T = 0

[0104] If X satisfies the above check formula, the check result is check passed, X is taken as the target decoding information, and the target decoding information is output.

[0105] In the embodiment of the application, the output device includes a decoding information register and a decoding information checker, and the decoding information register is connected to the decoding information checker; the decoding information register is configured to acquire the check information of each check node determined by the second calculator, and perform hard decision on the check information of each check node to determine quasi-decoding information; the decoding information checker is configured to acquire the quasi-decoding information, and check the quasi-decoding information according to a preset check matrix to obtain a check result, and if the check result is check passed, the quasi-decoding information is taken as the target decoding information, and the target decoding information is output. By adding the decoding information checker in the output device, the accuracy of the output target decoding information is improved.

[0106] In one of the embodiments, the channel decoding device 200 further includes a controller, and the controller is connected to the first calculator 201, the second calculator 202, the decoding information register, and the decoding information checker.

[0107] The controller is configured to acquire the check result in the decoding information checker, and if the check result is check failed, the total number of current decoding operations is accumulated, and if the total number of current decoding operations is less than a preset number, a fourth instruction is sent to the first calculator and the second calculator.

[0108] After the decoding information checker checks the quasi-decoding information, the controller acquires the check result of the decoding information checker, and if the check result is check failed, the total number of current decoding operations is accumulated by 1. It is determined whether the total number of current decoding operations after the accumulation is less than the preset number, and if the total number of current decoding operations after the accumulation is less than the preset number, the fourth instruction is sent to the first calculator 201 and the second calculator 202, and the fourth instruction is used to instruct the first calculator and the second calculator to continue decoding operation.

[0109] For example, the preset number of times is 10, the current decoding operation is the second decoding operation, the total number of current decoding operations is 1 before the decoding information checker checks the quasi-decoding information, if the controller obtains a check result that the check fails, the total number of current decoding operations is accumulated by 1, at this time, the total number of current decoding operations is 2, because the total number of current decoding operations 2 is less than the preset number of times 10, the fourth instruction is sent to the first calculator 201 and the second calculator 202.

[0110] The first calculator 201 is used for returning to execute the step of determining the extrinsic information of each variable node in the current decoding operation according to the preset check matrix, the target variable and the intermediate variable corresponding to each variable node according to the fourth instruction.

[0111] The first calculator 201 receives the fourth instruction sent by the controller, can obtain the check information of each check node in the last decoding operation process from the decoding information register, and takes the check information of each check node corresponding to each variable node in the last decoding operation process as the target variable corresponding to each variable node in the current decoding operation process, takes the extrinsic information of each variable node in the last decoding operation process as the intermediate variable, and returns to execute the step of determining the extrinsic information of each variable node in the current decoding operation according to the preset check matrix, the target variable and the intermediate variable corresponding to each variable node.

[0112] The second calculator 202 is used for returning to execute the step of determining the check information of each check node corresponding to each variable node according to the preset check matrix, the extrinsic information and the target variable corresponding to each variable node in the current decoding operation according to the fourth instruction.

[0113] The second calculator receives the fourth instruction sent by the controller, can obtain the check information of each check node in the last decoding operation process from the decoding information register, obtains the extrinsic information of each variable node in the current decoding operation process from the first calculator 201, takes the check information of each check node in the last decoding operation process as the target variable of each check node, and returns to execute the step of determining the check information of each check node corresponding to each variable node according to the preset check matrix, the extrinsic information and the target variable corresponding to each variable node in the current decoding operation.

[0114] In the embodiment, the controller is configured to acquire a check result in the decoding information checker, accumulate a total number of current decoding operations if the check result is not passed, and send a fourth instruction to the first calculator and the second calculator if the total number of current decoding operations is less than a preset number; the first calculator is configured to return to execute a step of determining extrinsic information of each variable node in the current decoding operation according to the preset check matrix, target variables and intermediate variables corresponding to each variable node according to the fourth instruction; and the second calculator is configured to return to execute a step of determining check information of each check node corresponding to each variable node according to the preset check matrix, extrinsic information and target variables corresponding to each variable node in the current decoding operation according to the fourth instruction. The controller enables the decoding operation process to be iteratively performed, thereby improving the reliability of channel decoding using the channel decoding device.

[0115] In one of the embodiments, the controller is configured to send a fifth instruction to the decoding information register if the total number of current decoding operations is equal to the preset number.

[0116] The decoding information register is configured to take the quasi-decoding information in the current decoding operation as target decoding information and output the target decoding information according to the fifth instruction.

[0117] For example, the preset number is set to 10, the controller compares the total number of current decoding operations after accumulation with the preset number, and sends the fifth instruction to the decoding information register if the total number of current decoding operations is also 10. After receiving the fifth instruction, the decoding information register takes the quasi-decoding information in the current decoding operation as the target decoding information and outputs the target decoding information.

[0118] In the embodiment, the total number of current decoding operations is compared with the preset number, the fifth instruction is sent to the decoding information register if the total number of current decoding operations is equal to the preset number, and the decoding information register is configured to take the quasi-decoding information in the current decoding operation as the target decoding information and output the target decoding information according to the fifth instruction. This avoids excessive resource consumption of the channel decoding device caused by decoding information with a high error rate, thereby prolonging the service life of the channel decoding device.

[0119] In one of the embodiments, the channel decoding device 200 further includes an intermediate variable register connected with the first calculator 201, the second calculator 202, the decoding information register and the controller.

[0120] The intermediate variable register is configured to receive a sixth instruction sent by the controller, acquire extrinsic information corresponding to each variable node according to the sixth instruction, and send check information of each check node in the last decoding operation and extrinsic information corresponding to each variable node in the last decoding operation to the first calculator 201.

[0121] Exemplarily, the channel decoding apparatus 200 can further comprise an intermediate variable register, configured to store the interaction information between the first calculator 201 and the second calculator 202 during the decoding operation, i.e. the extrinsic information of each variable node and the check information of each check node. During the current decoding operation, the intermediate variable register sends the check information of each check node in the last decoding operation and the corresponding extrinsic information of each variable node in the last decoding operation to the first calculator 201 according to the sixth instruction; after the first calculator 201 obtains the extrinsic information of each variable node in the current decoding operation, the intermediate variable register obtains the extrinsic information of each variable node in the first calculator 201.

[0122] Optionally, after the first calculator 201 obtains the extrinsic information of the first variable node v1, the intermediate variable register can obtain the extrinsic information of v1 first, and at the same time, the first calculator 201 performs the calculation of the extrinsic information of v2, so that the intermediate variable register and the first calculator 201 work simultaneously.

[0123] The intermediate variable register is configured to receive the seventh instruction sent by the controller, obtain the check information of each check node according to the seventh instruction, and send the corresponding extrinsic information of each variable node in the current decoding operation and the check information of each check node in the last decoding operation to the second calculator 202.

[0124] During the current decoding operation, the intermediate variable register can send the corresponding extrinsic information of each variable node in the current decoding operation and the check information of each check node in the last decoding operation to the second calculator 202 according to the seventh instruction. After the second calculator 202 obtains the check information of each check node in the current decoding operation, the intermediate variable register obtains the check information of each check node obtained by the second calculator 202.

[0125] Optionally, after the second calculator 202 obtains the check information of the first variable node s1, the intermediate variable register can obtain the check information of s1 first, and at the same time, the second calculator 202 performs the calculation of the check information of s2, so that the intermediate variable register and the second calculator 202 work simultaneously.

[0126] The intermediate variable register is configured to receive the eighth instruction sent by the controller, and send the check information of each check node in the current decoding operation to the decoding information register according to the seventh instruction.

[0127] Exemplarily, during the current decoding operation, after the intermediate variable register obtains the check information of each check node obtained by the second calculator 202, the intermediate variable register can send the check information of each check node in the current decoding operation to the decoding information register according to the eighth instruction sent by the controller.

[0128] In the embodiment, the intermediate variable register is added in the channel decoding device, so that the first calculator and the second calculator can directly obtain the required information from the intermediate variable register during the decoding operation, and the channel decoding efficiency is improved.

[0129] In one of the embodiments, the intermediate variable register comprises a skip unit.

[0130] The skip unit is configured to select a third target variable node to be skipped according to a preset skip rule, and skip the step of sending the extrinsic information of the third target variable node to the first calculator and the second calculator.

[0131] The skip unit is configured to select a third target check node to be skipped according to a preset skip rule, and skip the step of sending the check information of the third target check node to the first calculator and the second calculator.

[0132] For example, when the channel decoding is performed, the user can select whether to start the skip unit. If the skip unit is started, the skip unit traverses the extrinsic information of each variable node and the check information of each check node stored in the intermediate variable register, determines the third target variable node and the third target check node according to the preset skip rule, and skips sending the extrinsic information of the third target variable node and the check information of the third target check node to the first calculator and the second calculator. For example, the preset skip rule can be a rule set according to the information amount. After the skip unit traverses the extrinsic information of each intermediate variable and the check information of each check node, it is found that the extrinsic information of the v3 node contains an information amount less than a first preset information amount threshold, and the skip unit skips sending the extrinsic information of the v3 node to the first calculator 201 and the second calculator 202. For another example, the skip unit finds that the data amount of the check information of the s4 node is less than a second preset information amount threshold, and the skip unit skips sending the check information of the s4 node to the first calculator 201 and the second calculator 202.

[0133] In the embodiment, the skip unit is set in the intermediate variable register, the extrinsic information of the third target variable node and the check information of the third target check node are skipped to be sent to the first calculator and the second calculator, and correspondingly, the first calculator and the second calculator also skip the operation on the third target variable node and the third target check node, so that the resource consumption of the channel decoding device is reduced, and the channel decoding efficiency is improved.

[0134] In one of the embodiments, as shown in Figure 4 The application further provides a channel decoding device 400,

[0135] The first calculator 401, the second calculator 402, the decoding information register 403, the decoding information checker 404, the controller 405, the to-be-decoded information register 406, the preset check matrix register 407 and the intermediate variable register 408 are included. The first calculator 401 is connected with the controller 405, the to-be-decoded information register 406, the preset check matrix register 407 and the intermediate variable register 408, and is used for determining the extrinsic information of each variable node in the current decoding operation according to the preset check matrix stored in the preset check matrix register 407, and the target variable and the intermediate variable corresponding to each variable node stored in the intermediate variable register 408. The initial information of the target variable is the to-be-decoded information stored in the to-be-decoded information register 406. The second calculator 402 is connected with the controller 405, the preset check matrix register 407 and the intermediate variable register 408. The second calculator 402 is used for determining the check information of the check node corresponding to each variable node according to the preset check matrix stored in the preset check matrix register 407, and the extrinsic information and the target variable corresponding to each variable node stored in the intermediate variable register 408. The decoding information register 403 is connected with the decoding information checker 404, the controller 405 and the intermediate variable register 408, and is used for determining the quasi-decoding information according to the check information of the check node stored in the intermediate variable register 408. The decoding information checker 404 is connected with the preset check matrix register 407, the decoding information register 403 and the controller 405, and is used for checking the quasi-decoding information in the decoding information register 403 to determine the target decoding information.

[0136] The first calculator 401 includes m first calculation units, the number of the first calculation units is the same as the total number of the variable nodes, each first calculation unit is used for calculating the extrinsic information of each variable node, and each first calculation unit can work simultaneously. The second calculator 402 includes n second calculation units, the number of the second calculation units is the same as the total number of the check nodes, each second calculation unit is used for calculating the check information of each check node, and each second calculation unit can work simultaneously. Correspondingly, the intermediate variable register 408 also includes w intermediate variable storage units, the number of the intermediate variable storage units is more than the number of the first calculation units and the second calculation units. Each first calculation unit, second calculation unit and intermediate variable storage unit can work synchronously. For example, taking the case of m=4, n=3 and w=6 as an example. Figure 3The connection relationship between each check node and variable node is taken as an example, c1 is associated with v1 and v3 nodes. After the first calculation unit determines the extrinsic information of the v1 and v3 nodes, the intermediate variable register unit obtains the extrinsic information of the v1 and v3 nodes and sends the extrinsic information of the v1 and v3 nodes to the second calculation unit, and the second calculation unit starts to calculate the check information of the c1 node, while the first calculation unit calculates the extrinsic information of other variable nodes. The first calculator 401, the second calculator 402, and the intermediate variable register 408 work at the same time, further improving the efficiency of the channel decoding device in channel decoding. Moreover, when the number of check nodes and variable nodes changes, the number of the first calculation units and the second calculation units in the corresponding first calculator 401 and the second calculator 402 can also be changed correspondingly. The flexibility of using the channel decoding device for channel decoding is improved.

[0137] Figure 5 is a flowchart of a channel decoding method provided by an embodiment of the present application, which is suitable for Figure 2 the channel decoding device 200 in the above embodiment, and includes the following steps:

[0138] S501, determining extrinsic information of each variable node according to a preset check matrix and to-be-decoded information corresponding to each variable node.

[0139] S502, determining check information of a check node corresponding to each variable node according to the preset check matrix and the extrinsic information corresponding to each variable node.

[0140] S503, determining target decoding information according to the check information of each check node.

[0141] In the embodiment of the present application, the extrinsic information of each variable node is determined according to the preset check matrix and the to-be-decoded information corresponding to each variable node, the check information of the check node corresponding to each variable node is further determined according to the preset check matrix and the extrinsic information corresponding to each variable node, and the target decoding information is determined according to the check information of each check node. Since the extrinsic information of each variable node can be calculated synchronously, the efficiency of channel decoding is improved.

[0142] It should be understood that although the steps in the flowcharts involved in the embodiments described above are shown in sequence according to the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the embodiments described above can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of the steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0143] In one embodiment, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program:

[0144] According to the preset check matrix and the to-be-decoded information corresponding to each variable node, the extrinsic information of each variable node is determined;

[0145] According to the preset check matrix and the extrinsic information corresponding to each variable node, the check information of the check node corresponding to each variable node is determined;

[0146] According to the check information of each check node, the target decoding information is determined.

[0147] In one embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0148] According to the preset check matrix and the to-be-decoded information corresponding to each variable node, the extrinsic information of each variable node is determined;

[0149] According to the preset check matrix and the extrinsic information corresponding to each variable node, the check information of the check node corresponding to each variable node is determined;

[0150] According to the check information of each check node, the target decoding information is determined.

[0151] In one embodiment, a computer program product is provided, comprising a computer program, and the computer program is executed by a processor to implement the following steps:

[0152] According to the preset check matrix and the to-be-decoded information corresponding to each variable node, the extrinsic information of each variable node is determined;

[0153] According to the preset check matrix and the extrinsic information corresponding to each variable node, check information of a check node corresponding to each variable node is determined;

[0154] According to the check information of each check node, the target decoding information is determined.

[0155] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties.

[0156] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to a memory, database or other medium used in the embodiments provided by the present application can include at least one of a non-volatile and volatile memory. The non-volatile memory can include a read-only memory (Read-Only Memory, ROM), a magnetic tape, a floppy disk, a flash memory, an optical storage, a high-density embedded non-volatile memory, a resistive memory (ReRAM), a magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), a ferroelectric memory (Ferroelectric Random Access Memory, FRAM), a phase change memory (Phase Change Memory, PCM), a graphene memory, etc. The volatile memory can include a random access memory (Random Access Memory, RAM) or an external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The database involved in the embodiments provided by the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., but is not limited thereto. The processor involved in the embodiments provided by the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0157] Any combination of the technical features in the above embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, any combination of the technical features is deemed to be within the scope of the present disclosure as long as there is no inconsistency.

[0158] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A channel decoding apparatus based on a reconfigurable processor architecture design, characterized by, The channel decoding device comprises a first calculator, a second calculator and an output device; The first calculator is configured to determine extrinsic information of each variable node in a current decoding operation according to a preset check matrix, target variables corresponding to each variable node and intermediate variables; initial information of the target variables is to-be-decoded information, the target variables in other decoding operations are determined according to check information of check nodes corresponding to the variable nodes in a previous decoding operation, and the intermediate variables are determined according to extrinsic information of the variable nodes in the previous decoding operation; The second calculator is configured to determine check information of check nodes corresponding to each variable node according to the preset check matrix, the extrinsic information of each variable node in the current decoding operation and the target variables; The output device is configured to determine target decoding information corresponding to each to-be-decoded information according to the check information of each check node.

2. The device of claim 1, wherein The first calculator is configured to determine first target variable nodes from each variable node according to the preset check matrix, and determine target variables and intermediate variables corresponding to the first target variable nodes; The first calculator is configured to determine variable node information corresponding to each first target variable node according to the target variables and the intermediate variables corresponding to the first target variable node; The first calculator is configured to determine extrinsic information of the first target variable nodes according to the variable node information corresponding to each first target variable node, and determine extrinsic information of second target variable nodes according to target variables of the second target variable nodes; each variable node comprises the first target variable nodes and the second target variable nodes.

3. The apparatus of claim 2, wherein, The first calculator comprises a synchronous shift unit, a calculation unit, a control unit and a register unit; The control unit is configured to send a first instruction to the synchronous shift unit and a second instruction to the calculation unit; The synchronous shift unit is configured to determine starting variable nodes from variable nodes corresponding to each first target variable node, and send each starting variable node to the calculation unit according to the first instruction; the starting variable node is the first variable node in each variable node corresponding to each first target variable node in each decoding operation; The calculation unit is configured to determine extrinsic information of each variable node in a current decoding operation according to the preset check matrix, target variables corresponding to each variable node, the intermediate variables and the starting variable nodes, and output the extrinsic information of each variable node according to the second instruction; The register unit is configured to receive a third instruction sent by the control unit, and send variable node information corresponding to each variable node to the synchronous shift unit and the calculation unit according to the third instruction.

4. The device of claim 1, wherein The second calculator is configured to determine a first target check node from the check nodes according to the preset check matrix, and determine extrinsic information of a variable node corresponding to the first target check node and the target variable; The second calculator is configured to determine check information of the first target check node according to the extrinsic information of the variable node corresponding to the first target check node and the target variable, and determine check information of a second target check node according to a target variable of the second target check node, wherein the check nodes include the first target check node and the second target check node.

5. The apparatus of claim 1, wherein, The output device includes a decoding information register and a decoding information checker, and the decoding information register is connected to the decoding information checker; The decoding information register is configured to obtain the check information of the check nodes determined by the second calculator, and perform hard decision on the check information of the check nodes to determine quasi-decoding information; The decoding information checker is configured to obtain the quasi-decoding information, and check the quasi-decoding information according to the preset check matrix to obtain a check result, and if the check result passes the check, the quasi-decoding information is taken as the target decoding information, and the target decoding information is output.

6. The apparatus of claim 5, wherein, The channel decoding device further includes a controller connected to the first calculator, the second calculator, the decoding information register, and the decoding information checker; The controller is configured to obtain the check result in the decoding information checker, and if the check result fails the check, accumulate a total number of current decoding operations, and if the total number of current decoding operations is less than a preset number, send a fourth instruction to the first calculator and the second calculator; The first calculator is configured to return to the step of determining the extrinsic information of the variable nodes in the current decoding operation according to the preset check matrix, the target variables corresponding to the variable nodes, and the intermediate variables according to the fourth instruction; The second calculator is configured to return to the step of determining the check information of the check nodes corresponding to the variable nodes according to the preset check matrix, the extrinsic information of the variable nodes in the current decoding operation, and the target variables according to the fourth instruction.

7. The device of claim 6, wherein The controller is configured to send a fifth instruction to the decoding information register if the total number of current decoding operations is equal to the preset number; The decoding information register is configured to take the quasi-decoding information in the current decoding operation as the target decoding information according to the fifth instruction, and output the target decoding information.

8. The apparatus of claim 6 or 7, wherein, The channel decoding device further includes an intermediate variable register connected to the first calculator, the second calculator, the decoding information register, and the controller. The intermediate variable register is configured to receive a sixth instruction sent by the controller, acquire extrinsic information corresponding to each variable node according to the sixth instruction, and send the check information of each check node in the last decoding operation and the extrinsic information corresponding to each variable node in the last decoding operation to the first calculator; The intermediate variable register is configured to receive a seventh instruction sent by the controller, acquire check information of each check node according to the seventh instruction, and send the extrinsic information corresponding to each variable node in the current decoding operation and the check information of each check node in the last decoding operation to the second calculator; The intermediate variable register is configured to receive an eighth instruction sent by the controller, and send the check information of each check node in the current decoding operation to the decoding information register according to the seventh instruction.

9. The apparatus of claim 8, wherein, The intermediate variable register comprises a skip unit. The skip unit is configured to select a third target variable node that needs to be skipped according to a preset skip rule, and skip the step of sending the extrinsic information of the third target variable node to the first calculator and the second calculator. The skip unit is configured to select a third target check node that needs to be skipped according to the preset skip rule, and skip the step of sending the check information of the third target check node to the first calculator and the second calculator.

10. A channel decoding method based on a reconfigurable processor architecture design, the method being applied to the channel decoding device of any one of claims 1-9, and the method comprising: determining extrinsic information of each variable node according to the preset check matrix and the to-be-decoded information corresponding to each variable node; determining check information of a check node corresponding to each variable node according to the preset check matrix and the extrinsic information corresponding to each variable node; determining the target decoding information according to the check information of each check node.

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