Method and system for forming test layout information

Abstract

A method and system for forming test layout information, wherein the system comprises: an input module configured to provide a test layout, the test layout having a plurality of pattern arrays, and each of the pattern arrays having a plurality of test patterns; a size acquisition module configured to acquire a pattern array size of each of the pattern arrays and a pattern geometric size of each of the test patterns; an array processing module configured to perform array processing on the pattern geometric size and the pattern array size to obtain initial pattern array information, the initial pattern array information including vertex coordinates of each of the test patterns in a corresponding pattern array; and a format conversion module configured to perform format conversion processing on each of the vertex coordinates to convert a format of each of the vertex coordinates into an optical proximity correction model readable format to form the test layout information. The format conversion module does not need to write corresponding readable texts for tool interfaces provided by different third-party processing software, thereby reducing workload and improving test efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method and system for forming test layout information. Background Technology

[0002] Photolithography is a crucial technology in semiconductor manufacturing. It transfers patterns from a photomask to the surface of a silicon wafer, forming semiconductor products that meet design requirements. The photolithography process includes an exposure step, a development step following exposure, and an etching step following development. In the exposure step, light passes through the light-transmitting areas of the photomask and shines onto the silicon wafer coated with photoresist, causing a chemical reaction in the photoresist. In the development step, the different solubility of the developer in the photoresist and the non-photoresist is used to form a photolithographic pattern, transferring the photomask pattern onto the photoresist. In the etching step, the silicon wafer is etched based on the photolithographic pattern formed by the photoresist layer, further transferring the photomask pattern onto the silicon wafer.

[0003] In semiconductor manufacturing, as design dimensions continue to shrink and approach the limits of photolithography imaging systems, the diffraction effect of light becomes increasingly pronounced, leading to optical image degradation of the final design pattern. The actual photolithographic pattern formed is severely distorted relative to the pattern on the mask, resulting in a difference between the actual pattern formed on the silicon wafer and the design pattern. This phenomenon is called the Optical Proximity Effect (OPE).

[0004] To correct the optical proximity effect, Optical Proximity Correction (OPC) was developed. The core idea of ​​OPC is to establish an OPC model based on the consideration of counteracting the optical proximity effect. The photomask pattern is designed according to the OPC model. In this way, although the lithographic pattern and the corresponding photomask pattern have an optical proximity effect, the cancellation of this phenomenon has been considered when designing the photomask pattern according to the OPC model. Therefore, the lithographic pattern after photolithography is close to the target pattern actually desired by the user.

[0005] In advanced technology nodes of integrated circuit manufacturing, model-based optical proximity correction (OPC) is widely used. The performance of the OPC model significantly impacts the accuracy of OPC. Therefore, establishing robust OPC models is becoming increasingly important. Currently, OPC models are trained on a large number of test layouts to improve their pattern coverage. These test layouts are simple abstract patterns based on real chips and design rules.

[0006] However, there are still many problems in the process of obtaining test layouts in the existing technology. Summary of the Invention

[0007] The technical problem solved by this invention is to provide a method and system for forming test layout information to improve testing efficiency.

[0008] To address the aforementioned problems, the present invention provides a method for forming test layout information, comprising: providing a test layout, wherein the test layout has a plurality of graphic arrays, and each graphic array has a plurality of test graphics; obtaining the graphic array size of each graphic array in the test layout and the graphic geometric size of each test graphic; performing arraying processing on the graphic geometric size and the graphic array size to obtain initial graphic array information, wherein the initial graphic array information includes the vertex coordinates of each test graphic in the corresponding graphic array; traversing each initial graphic array information, performing format conversion processing on each vertex coordinate to convert the format of each vertex coordinate into a format readable by the optical proximity correction model, and converting each initial graphic array information into graphic array information to form test layout information.

[0009] Optionally, each of the test patterns is a rectangle; the geometric dimensions of each test pattern include: the length dimension and the width dimension; the array dimensions of each pattern array include: the horizontal spacing dimension and the vertical spacing dimension.

[0010] Optionally, the method for arraying the geometric dimensions of the graphics and the array dimensions of the graphics to obtain initial graphic array information includes: performing full permutation and combination of several graphic length dimensions, several graphic width dimensions, several graphic horizontal spacing dimensions, and several graphic vertical spacing dimensions to obtain several sets of matching dimensions. Each set of matching dimensions includes the length dimension, width dimension, horizontal spacing dimension between test graphics, and vertical spacing dimension between test graphics in any graphic array; and performing arraying processing on each set of matching dimensions to obtain the initial graphic array information.

[0011] Optionally, the vertex coordinates of each test graphic include: a first horizontal coordinate, a second horizontal coordinate, a first vertical coordinate, and a second vertical coordinate, wherein the first horizontal coordinate and the second horizontal coordinate are arranged along the length direction of the test graphic, the first horizontal coordinate and the first vertical coordinate are arranged along the width direction of the test graphic, and the second horizontal coordinate and the second vertical coordinate are arranged along the width direction of the test graphic.

[0012] Optionally, the first horizontal coordinate of the test graphic in the first row and first column of each graphic array is (0, 0); the first horizontal coordinate of the test graphic in the i-th row and j-th column of each graphic array is: {(j-1)*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the second horizontal coordinate is: {j*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the first vertical coordinate is: {(j-1)*L+(j-1)*Hs, i*W+(i-1)*Vs}; the second vertical coordinate is: {j*L+(j-1)*Hs, i*W+(i-1)*Vs}, where L is the length dimension of the graphic in the corresponding graphic array, W is the width dimension of the graphic in the corresponding graphic array, Hs is the horizontal spacing dimension of the graphic in the corresponding graphic array, and Vs is the vertical spacing dimension of the graphic in the corresponding graphic array.

[0013] Optionally, after forming the test layout information, the method further includes: outputting several graphic array information horizontally until the number of output graphic array information reaches the horizontal quantity threshold of each row, forming several rows of horizontally arranged array information, and the several rows of horizontally arranged array information are arranged vertically.

[0014] Accordingly, the technical solution of the present invention also provides a test layout information formation system, comprising: an input module for providing a test layout, wherein the test layout has a plurality of graphic arrays, and each graphic array has a plurality of test graphics; a size acquisition module for acquiring the graphic array size of each graphic array in the test layout, and the graphic geometric size of each test graphic; an arraying processing module for performing arraying processing on the graphic geometric size and the graphic array size to obtain initial graphic array information, wherein the initial graphic array information includes the vertex coordinates of each test graphic in the corresponding graphic array; and a format conversion module for traversing each initial graphic array information, performing format conversion processing on each vertex coordinate, such that the format of each vertex coordinate is converted into a format readable by the optical proximity correction model, and converting each initial graphic array information into graphic array information to form test layout information.

[0015] Optionally, each of the test patterns is a rectangle; the geometric dimensions of each test pattern include: the length dimension and the width dimension; the array dimensions of each pattern array include: the horizontal spacing dimension and the vertical spacing dimension.

[0016] Optionally, the arraying processing module includes: a full permutation combination module, used to perform full permutation combination of several graphic length dimensions, several graphic width dimensions, several graphic horizontal spacing dimensions, and several graphic vertical spacing dimensions to obtain several sets of matching dimensions, each set of matching dimensions including the length dimension, width dimension, horizontal spacing dimension between test graphics, and vertical spacing dimension between test graphics in any graphic array; and a first processing module, used to perform arraying processing on each set of matching dimensions to obtain the initial graphic array information.

[0017] Optionally, the vertex coordinates of each test graphic include: a first horizontal coordinate, a second horizontal coordinate, a first vertical coordinate, and a second vertical coordinate, wherein the first horizontal coordinate and the second horizontal coordinate are arranged along the length direction of the test graphic, the first horizontal coordinate and the first vertical coordinate are arranged along the width direction of the test graphic, and the second horizontal coordinate and the second vertical coordinate are arranged along the width direction of the test graphic.

[0018] Optionally, the first horizontal coordinate of the test graphic in the first row and first column of each graphic array is (0, 0); the first horizontal coordinate of the test graphic in the i-th row and j-th column of each graphic array is: {(j-1)*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the second horizontal coordinate is: {j*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the first vertical coordinate is: {(j-1)*L+(j-1)*Hs, i*W+(i-1)*Vs}; the second vertical coordinate is: {j*L+(j-1)*Hs, i*W+(i-1)*Vs}, where L is the length dimension of the graphic in the corresponding graphic array, W is the width dimension of the graphic in the corresponding graphic array, Hs is the horizontal spacing dimension of the graphic in the corresponding graphic array, and Vs is the vertical spacing dimension of the graphic in the corresponding graphic array.

[0019] Optionally, it also includes: a layout output module, used to output several of the graphic array information horizontally until the number of the output graphic array information reaches the horizontal quantity threshold of each row, forming several rows of horizontal layout array information, and the several rows of horizontal layout array information are arranged vertically.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] In the method for forming test layout information of the technical solution of the present invention, by traversing each of the initial graphic array information, the format conversion processing of each of the vertex coordinates is performed so that the format of each of the vertex coordinates is converted into a format readable by the optical proximity correction model, and the initial graphic array information is converted into graphic array information to form test layout information. This eliminates the need to write corresponding readable text for tool interfaces provided by different third-party processing software, reduces workload, and thus improves testing efficiency.

[0022] In the test layout information formation system of this invention, a format conversion module is used to traverse each of the initial graphic array information, perform format conversion processing on each of the vertex coordinates, so that the format of each vertex coordinate is converted into a format readable by the optical proximity correction model, and convert each of the initial graphic array information into graphic array information to form test layout information. This format conversion module eliminates the need to write corresponding readable text for different third-party processing software tool interfaces, reducing workload and thus improving testing efficiency. Attached Figure Description

[0023] Figure 1 This is a flowchart of a method for forming test layout information according to an embodiment of the present invention;

[0024] Figures 2 to 4 This is a schematic diagram of the structure of each step in the method for forming test layout information in an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of the system structure for forming test layout information in an embodiment of the present invention. Detailed Implementation

[0026] As described in the background section, there are still many problems in the existing technology for obtaining test layouts. These will be explained in detail below.

[0027] Currently, the design of test layouts that can be recognized by the optical proximity correction model must rely on third-party processing software. Since different third-party processing software provides different tool interfaces, it is necessary to write corresponding standard texts for different tool interfaces, which undoubtedly increases the workload.

[0028] Based on this, the present invention provides a method and system for forming test layout information. By traversing each of the initial graphic array information, the format of each vertex coordinate is converted into a format readable by the optical proximity correction model, and the initial graphic array information is converted into graphic array information to form test layout information. This eliminates the need to write corresponding readable text for different third-party processing software tool interfaces, reducing workload and improving testing efficiency.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a flowchart of a method and system for forming test layout information according to an embodiment of the present invention, including:

[0031] Step S101: Traverse each of the initial graphic array information, perform format conversion processing on each of the vertex coordinates, so that the format of each of the vertex coordinates is converted into a format readable by the optical proximity correction model, and convert each of the initial graphic array information into graphic array information to form test layout information;

[0032] Step S102: Obtain the graphic array size of each graphic array in the test layout and the graphic geometric size of each test graphic;

[0033] Step S103: Perform arraying processing on the geometric dimensions of the graphic and the size of the graphic array to obtain initial graphic array information, which includes the vertex coordinates of each test graphic in the corresponding graphic array;

[0034] Step S104: Perform arraying processing on the geometric dimensions of the graphic and the array dimensions of the graphic to obtain initial graphic array information, which includes the vertex coordinates of each test graphic in the corresponding graphic array.

[0035] The steps of the method for forming the test layout information are described in detail below with reference to the accompanying drawings.

[0036] Figures 2 to 5 This is a schematic diagram of the steps in the method and system for forming test layout information in an embodiment of the present invention.

[0037] Please refer to Figure 2 and Figure 3 , Figure 3 yes Figure 2 The enlarged schematic diagram of part A shows a test layout 100, which has several pattern arrays 101, and each pattern array 101 has several test patterns 102.

[0038] In this embodiment, the test layout 100 is a design layout used to train the optical proximity correction model. By pre-designing the required style of the test layout 100, the test layout 100 is subsequently converted into text information that the optical proximity correction model can read.

[0039] Please continue to refer to this. Figure 2 and Figure 3The graphic array size of each graphic array 101 in the test layout 100 and the graphic geometric size of each test graphic 102 are obtained.

[0040] It should be noted that the graphic array size of each graphic array 101 in the test layout 100 and the graphic geometric dimensions of each test graphic 102 are different, and each test graphic 102 is designed as a rectangle. Therefore, the graphic geometric dimensions of each test graphic include: graphic length dimension L and graphic width dimension W; the graphic array size of each graphic array includes: graphic horizontal spacing dimension Hs and graphic vertical spacing dimension Vs.

[0041] Please refer to Figure 4 The geometric dimensions of the graphic and the size of the graphic array are arrayed to obtain initial graphic array information, which includes the vertex coordinates of each test graphic 102 in the corresponding graphic array 101.

[0042] In this embodiment, the method for arraying the geometric dimensions of the graphics and the array dimensions of the graphics to obtain initial graphic array information includes: performing full permutation and combination of several graphic length dimensions L, several graphic width dimensions W, several graphic horizontal spacing dimensions Hs, and several graphic vertical spacing dimensions Vs to obtain several sets of matching dimensions. Each set of matching dimensions includes the length dimension, width dimension, horizontal spacing dimension between test graphics 102 in any graphic array 101, and vertical spacing dimension between test graphics; and performing arraying processing on each set of matching dimensions to obtain the initial graphic array information.

[0043] In one example, the obtained pattern length dimension L includes 10nm and 15nm; the obtained pattern width dimension W includes 5nm and 8nm; the obtained pattern horizontal spacing dimension Hs includes 2nm and 3nm; and the obtained pattern vertical spacing dimension Vs includes 2nm and 3nm. Therefore, after all permutations and combinations, there will be 16 possible combinations, corresponding to (pattern length dimension L, pattern width dimension W, pattern horizontal spacing dimension Hs, and pattern vertical spacing dimension Vs) as follows: (10nm, 5nm, 2nm, 2nm); (10nm, 5nm, 2nm, 3nm); (10nm, 5nm, 3nm, 2nm); (10nm, 5nm, 3nm, 3nm); (10nm, 8nm, 2nm, 2nm); (10nm, 8nm, 2nm, 3 ...8nm, 2nm, 3nm); (10nm, 8nm, 8nm, 2nm, 3nm); (10nm, 8nm, 8nm, 2nm, 3nm); (10nm, 8nm, 8nm, 2nm, 3 m, 8nm, 3nm, 2nm); (10nm, 8nm, 3nm, 3nm); (15nm, 5nm, 2nm, 2nm); (15nm, 5nm, 2nm, 3nm); (15nm, 5nm, 3nm, 2nm); (1 5nm, 5nm, 3nm, 3nm); (15nm, 8nm, 2nm, 2nm); (15nm, 8nm, 2nm, 3nm); (15nm, 8nm, 3nm, 2nm); (15nm, 8nm, 3nm, 3nm).

[0044] In this embodiment, the vertex coordinates of each test pattern 102 include: a first horizontal coordinate a1, a second horizontal coordinate a2, a first vertical coordinate b1, and a second vertical coordinate b2, wherein the first horizontal coordinate a1 and the second horizontal coordinate a2 are arranged along the length direction of the test pattern 102, the first horizontal coordinate a1 and the first vertical coordinate b1 are arranged along the width direction of the test pattern 102, and the second horizontal coordinate a2 and the second vertical coordinate b2 are arranged along the width direction of the test pattern 102.

[0045] In this embodiment, the first horizontal coordinate a1 of the test pattern 102 in the first row and first column of each pattern array 101 is (0, 0); the first horizontal coordinate a1 of the test pattern 102 in the i-th row and j-th column of each pattern array 101 is: {(j-1)*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the second horizontal coordinate a2 is: {j*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the first vertical coordinate b1 is: {(j-1)*L+(j-1)*Hs, i*W+(i-1)*Vs}; the second vertical coordinate b2 is: {j*L+(j-1)*Hs, i*W+(i-1)*Vs}, where L is the length dimension of the graphic in the graphic array 101, W is the width dimension of the graphic in the graphic array 101, Hs is the horizontal spacing dimension of the graphic in the graphic array 101, and Vs is the vertical spacing dimension of the graphic in the graphic array 101.

[0046] Please continue to refer to this. Figure 4 The process iterates through each of the initial graphic array information, performs format conversion processing on each of the vertex coordinates, converts the format of each vertex coordinate into a format readable by the optical proximity correction model, and converts each of the initial graphic array information into graphic array information to form test layout information.

[0047] It should be noted that in this embodiment, the vertex coordinates are all in decimal notation, which is unreadable by the optical proximity correction model. Therefore, it is necessary to convert the decimal notation into a format readable by the optical proximity correction model.

[0048] In this embodiment, the readable format of the optical proximity correction model includes: GDSII / OASIS format.

[0049] Please continue to refer to this. Figure 4 In this embodiment, after forming the test layout information, the method further includes: outputting several graphic array information horizontally until the number of output graphic array information reaches the horizontal number threshold of each row, forming several rows of horizontally arranged array information, and the several rows of horizontally arranged array information are arranged vertically.

[0050] In this embodiment, by performing format conversion processing on the vertex coordinates, the vertex coordinates are converted into vertex coordinates, so that the initial graphic array information forms graphic array information. Moreover, the format of the vertex coordinates in the graphic array information is a format readable by the optical proximity correction model. This eliminates the need to write corresponding readable text for the tool interfaces provided by different third-party processing software, reducing workload and thus improving testing efficiency.

[0051] Figure 5 This is a schematic diagram of the system structure for forming test layout information in an embodiment of the present invention.

[0052] Accordingly, embodiments of the present invention also provide a system for forming test layout information, please refer to... Figure 5 The system includes: an input module 10 for providing a test layout 100, wherein the test layout 100 has a plurality of graphic arrays 101, and each graphic array 101 has a plurality of test graphics 102; a size acquisition module 20 for acquiring the graphic array size of each graphic array 101 in the test layout 100 and the graphic geometric size of each test graphics 102; an arraying processing module 30 for performing arraying processing on the graphic geometric size and the graphic array size to obtain initial graphic array information, wherein the initial graphic array information includes the vertex coordinates of each test graphics 102 in the corresponding graphic array 101; and a format conversion module 40 for traversing each initial graphic array information, performing format conversion processing on each vertex coordinate to convert the format of each vertex coordinate into a format readable by the optical proximity correction model, and converting each initial graphic array information into graphic array information to form test layout information.

[0053] In this embodiment, the format conversion module eliminates the need to write corresponding readable text for different third-party processing software tool interfaces, reducing workload and thus improving testing efficiency.

[0054] In this embodiment, each of the test patterns 102 is a rectangle; the geometric dimensions of each test pattern include: the length dimension L and the width dimension W; the array dimensions of each pattern array include: the horizontal spacing dimension Hs and the vertical spacing dimension Vs.

[0055] In this embodiment, the arraying processing module 30 includes: a full permutation combination module 301, used to perform full permutation combination of several graphic length dimensions L, several graphic width dimensions 2, several graphic horizontal spacing dimensions Hs, and several graphic vertical spacing dimensions Vs to obtain several sets of matching dimensions, each set of matching dimensions including the length dimension, width dimension, horizontal spacing dimension between test graphics 102 in any graphic array 101, and vertical spacing dimension between test graphics 102; and a first processing module 302, used to perform arraying processing on each set of matching dimensions to obtain the initial graphic array information.

[0056] In this embodiment, the vertex coordinates of each test pattern 102 include: a first horizontal coordinate a1, a second horizontal coordinate a2, a first vertical coordinate b1, and a second vertical coordinate b2, wherein the first horizontal coordinate a1 and the second horizontal coordinate a2 are arranged along the length direction of the test pattern 102, the first horizontal coordinate a1 and the first vertical coordinate b1 are arranged along the width direction of the test pattern 102, and the second horizontal coordinate a2 and the second vertical coordinate b2 are arranged along the width direction of the test pattern 102.

[0057] In this embodiment, the first horizontal coordinate a1 of the test pattern 102 in the first row and first column of each pattern array 101 is (0, 0); the first horizontal coordinate a1 of the test pattern 102 in the i-th row and j-th column of each pattern array 101 is: {(j-1)*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the second horizontal coordinate a2 is: {j*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the first vertical coordinate b1 is: {(j-1)*L+(j-1)*Hs, i*W+(i-1)*Vs}; the second vertical coordinate b2 is: {j*L+(j-1)*Hs, i*W+(i-1)*Vs}, where L is the length dimension of the graphic in the graphic array 101, W is the width dimension of the graphic in the graphic array 101, Hs is the horizontal spacing dimension of the graphic in the graphic array 101, and Vs is the vertical spacing dimension of the graphic in the graphic array 101.

[0058] Please continue to refer to this. Figure 5 In this embodiment, it further includes: a layout output module 50, used to output several graphic array information in a horizontal manner until the number of output graphic array information reaches the horizontal quantity threshold of each row, forming several rows of horizontal layout array information, and the several rows of horizontal layout array information are arranged in a vertical direction.

[0059] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming test layout information, characterized in that, include: A test layout is provided, wherein the test layout has a plurality of pattern arrays, and each pattern array has a plurality of test patterns; Obtain the graphic array size of each graphic array in the test layout, and the graphic geometric size of each test graphic; The geometric dimensions of the graphic and the size of the graphic array are arrayed to obtain initial graphic array information, which includes the vertex coordinates of each test graphic in the corresponding graphic array; The initial graphic array information is traversed, and the format of each vertex coordinate is converted to a format readable by the optical proximity correction model. The initial graphic array information is also converted into graphic array information to form test layout information.

2. The method for forming test layout information as described in claim 1, characterized in that, Each of the test patterns is a rectangle; the geometric dimensions of each test pattern include: the length dimension and the width dimension; the array dimensions of each pattern array include: the horizontal spacing dimension and the vertical spacing dimension.

3. The method for forming test layout information as described in claim 2, characterized in that, The method for arraying the geometric dimensions of the graphics and the array dimensions of the graphics to obtain initial graphic array information includes: performing full permutation and combination of several graphic length dimensions, several graphic width dimensions, several graphic horizontal spacing dimensions, and several graphic vertical spacing dimensions to obtain several sets of matching dimensions. Each set of matching dimensions includes the length dimension, width dimension, horizontal spacing dimension, and vertical spacing dimension of each test graphic in any graphic array; and performing arraying processing on each set of matching dimensions to obtain the initial graphic array information.

4. The method for forming test layout information as described in claim 2, characterized in that, The vertex coordinates of each test graphic include: a first horizontal coordinate, a second horizontal coordinate, a first vertical coordinate, and a second vertical coordinate, wherein the first horizontal coordinate and the second horizontal coordinate are arranged along the length direction of the test graphic, the first horizontal coordinate and the first vertical coordinate are arranged along the width direction of the test graphic, and the second horizontal coordinate and the second vertical coordinate are arranged along the width direction of the test graphic.

5. The method for forming test layout information as described in claim 4, characterized in that, The first horizontal coordinate of the test graphic in the first row and first column of each graphic array is (0, 0); the first horizontal coordinate of the test graphic in the i-th row and j-th column of each graphic array is: {(j-1)*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the second horizontal coordinate is: {j*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the first vertical coordinate is: {(j-1)*L+(j-1)*Hs, i*W+(i-1)*Vs}; the second vertical coordinate is: {j*L+(j-1)*Hs, i*W+(i-1)*Vs}, where L is the length dimension of the graphic in the corresponding graphic array, W is the width dimension of the graphic in the corresponding graphic array, Hs is the horizontal spacing dimension of the graphic in the corresponding graphic array, and Vs is the vertical spacing dimension of the graphic in the corresponding graphic array.

6. The method for forming test layout information as described in claim 1, characterized in that, After forming the test layout information, the method further includes: outputting several graphic array information horizontally until the number of output graphic array information reaches the horizontal number threshold of each row, forming several rows of horizontally arranged array information, and the several rows of horizontally arranged array information are arranged vertically.

7. A system for generating test layout information, characterized in that, include: An input module is used to provide a test layout, wherein the test layout has a plurality of graphic arrays, and each graphic array has a plurality of test graphics; The size acquisition module is used to acquire the graphic array size of each graphic array in the test layout and the graphic geometric size of each test graphic; An arraying processing module is used to perform arraying processing on the geometric dimensions of the graphic and the array dimensions of the graphic to obtain initial graphic array information, wherein the initial graphic array information includes the vertex coordinates of each test graphic in the corresponding graphic array; The format conversion module is used to traverse each of the initial graphic array information, perform format conversion processing on each of the vertex coordinates, so that the format of each vertex coordinate is converted into a format readable by the optical proximity correction model, and convert each of the initial graphic array information into graphic array information to form test layout information.

8. The test layout information formation system as described in claim 7, characterized in that, Each of the test patterns is a rectangle; the geometric dimensions of each test pattern include: the length dimension and the width dimension; the array dimensions of each pattern array include: the horizontal spacing dimension and the vertical spacing dimension.

9. The test layout information formation system as described in claim 8, characterized in that, The arraying processing module includes: a full permutation combination module, used to perform full permutation combination of several graphic length dimensions, several graphic width dimensions, several graphic horizontal spacing dimensions, and several graphic vertical spacing dimensions to obtain several sets of matching dimensions, each set of matching dimensions including the length dimension, width dimension, horizontal spacing dimension between test graphics, and vertical spacing dimension between test graphics in any graphic array; and a first processing module, used to perform arraying processing on each set of matching dimensions to obtain the initial graphic array information.

10. The test layout information formation system as described in claim 8, characterized in that, The vertex coordinates of each test graphic include: a first horizontal coordinate, a second horizontal coordinate, a first vertical coordinate, and a second vertical coordinate, wherein the first horizontal coordinate and the second horizontal coordinate are arranged along the length direction of the test graphic, the first horizontal coordinate and the first vertical coordinate are arranged along the width direction of the test graphic, and the second horizontal coordinate and the second vertical coordinate are arranged along the width direction of the test graphic.

11. The test layout information formation system as described in claim 10, characterized in that, The first horizontal coordinate of the test graphic in the first row and first column of each graphic array is (0, 0); the first horizontal coordinate of the test graphic in the i-th row and j-th column of each graphic array is: {(j-1)*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the second horizontal coordinate is: {j*L+(j-1)*Hs, (i-1)*W+(i-1)*Vs}; the first vertical coordinate is: {(j-1)*L+(j-1)*Hs, i*W+(i-1)*Vs}; the second vertical coordinate is: {j*L+(j-1)*Hs, i*W+(i-1)*Vs}, where L is the length dimension of the graphic in the corresponding graphic array, W is the width dimension of the graphic in the corresponding graphic array, Hs is the horizontal spacing dimension of the graphic in the corresponding graphic array, and Vs is the vertical spacing dimension of the graphic in the corresponding graphic array.

12. The test layout information formation system as described in claim 7, characterized in that, Also includes: The layout output module is used to output several graphic array information in a horizontal manner until the number of output graphic array information reaches the horizontal quantity threshold of each row, forming several rows of horizontal layout array information, and the several rows of horizontal layout array information are arranged in a vertical direction.

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