Control circuit for warning lights

Abstract

The present invention discloses a control circuit for a warning light, comprising: a signal processor; the control circuit comprising at least a control signal source and an active switch, the output end of the active switch being connected to the control input side of the signal processor via a control bus; a data synchronization circuit comprising at least one data signal source and another set of active switches, the output end of the other set of active switches being connected to the data input side of the signal processor via a data bus, and the signal processor being connected to the signal connection circuit via a data output side to achieve signal and command synchronization between the data input side and the data output side; a warning light control IC being connected to a plurality of warning lights and electrically connected to a data bus external to the data output side, with data signals, clock signals, and identity data being transmitted via the data output side, and an initiator and a plurality of receivers selecting one of a plurality of light signal modes to cause the lights to flash.

Description

Technical Field

[0001] The present invention relates to a control circuit for warning lights, and more particularly to a control circuit architecture in which each warning light is configured with its own identification number, and an initiator transmits data, clock and identification signals via a data bus to control multiple receivers, thereby improving the control stability and flashing coordination of the warning lights. Background Art

[0002] Warning lights are used in many environments and locations, such as road construction warnings, public safety warnings, high-rise building safety warnings, fire trucks, ambulances, and police vehicles. Warning lights can be single or multiple. Warning light assemblies are often mounted on the roof of the vehicle that needs to provide warnings. Existing warning light assemblies require an electronic control device to control the multiple warning lights to achieve a coordinated flashing warning effect. While all currently available warning light assemblies have nearly identical appearances and flashing effects, the flashing effects of the multiple warning lights controlled by the electronic control device are not very coordinated, resulting in poor warning effectiveness. Furthermore, the additional electronic control device in commercially available warning light assemblies increases manufacturing costs, which in turn increases the terminal sales price of the warning light assemblies, hindering their price competitiveness in the market. These shortcomings of commercially available warning light assemblies need to be addressed by those in the industry. Summary of the Invention

[0003] Therefore, in view of the above problems and deficiencies, the main purpose of the present invention is to provide a control circuit for a warning light.

[0004] The present invention provides a control circuit for a warning light, comprising: a signal processor; a control circuit including at least a control signal source and an active switch, the output of the active switch being connected to the control input of the signal processor via a control bus; a data synchronization circuit including at least one data signal source and another set of active switches, the output of the other set of active switches being connected to the data input of the signal processor via a data bus, and the signal processor being connected to the signal connection circuit via a data output to synchronize signals and commands between the data input and data output sides; a warning light control IC connected to a plurality of warning lights and electrically connected to a data bus external to the data output side, with the data output side transmitting data signals, clock signals, and identity data, and an initiator and a plurality of receivers selecting one of a plurality of light signal modes to flash the lights. Through the aforementioned control circuit architecture, each warning light is assigned an identity number, and the initiator controls the plurality of receivers by transmitting data, clock signals, and identity signals via the data bus, thereby improving the control stability and flashing coordination of the warning lights.

[0005] A secondary object of the present invention is that the multiple active switches are composed of an N-channel enhancement mode metal oxide semiconductor field effect transistor, and the N-channel enhancement mode metal oxide semiconductor field effect transistor is connected to a Zener diode between its source and drain to prevent electrostatic discharge.

[0006] Another object of the present invention is to connect a current limiter and two resistors in series between the control signal source and the active switch, wherein the floating ends of the two resistors are connected to a ground point, a first node between the two resistors is electrically connected to the gate of the active switch, the source of the active switch is connected to the ground point, and the drain of the active switch is connected to the control input side of the signal processor, and the current limiter is formed by a diode.

[0007] Yet another object of the present invention is to provide a second node between the data signal source and the other set of active switches, wherein a first side of the second node is connected to an input voltage source, a current limiter, and a resistor, and a second side of the second node is connected in series with another current limiter and two other resistors. The other set of active switches comprises a first-stage active switch and a second-stage active switch, wherein the floating ends of the two other resistors are connected to a ground point in series, and a third node between the two other resistors is electrically connected to a gate of the second-stage active switch. The sources of the first-stage active switch and the second-stage active switch are connected to the ground point, and the drain of the second-stage active switch is connected to the data bus and the data input side of the signal processor. The current limiter and the other current limiter are formed by diodes.

[0008] Yet another object of the present invention is that the signal connection circuit includes a signal processor power supply and two resistors connected in series, wherein a floating end of the first resistor is connected to the signal processor power supply, and a fourth node electrically connected to an external data bus on the data output side is formed between the first resistor and the second resistor. The second resistor is electrically connected to the gate of an active switch, and the source of the active switch is connected to a ground point. Another resistor is connected in series to the drain of the active switch, and the floating end of the other resistor is electrically connected between the data signal source and the other set of active switches via a synchronization connection line.

[0009] Yet another object of the present invention is to provide a signal processor power supply and three resistors connected in series, in sequence, between the data bus outside the data output side and the warning light control IC. The floating end of the first resistor is connected to the signal processor power supply. A fifth node electrically connected to the data bus is formed between the first and second resistors. A sixth node electrically connected to an enable pin of the warning light control IC is formed between the second and third resistors. The floating end of the third resistor is connected to a ground point. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1This is a functional block diagram of the warning light assembly and its control architecture of the present invention.

[0011] Figure 2 This is a functional block diagram of the data stored inside the signal processor of the present invention.

[0012] Figure 3 FIG. 2 is another functional block diagram of the warning light assembly and its control architecture of the present invention.

[0013] Figure 4 This is a schematic diagram of the connection between the warning light assembly and its circuits of the present invention.

[0014] Figure 5 This is a circuit diagram of a single warning light of the present invention.

[0015] Explanation of Reference Numerals: 1-warning light assembly; 11a-warning light 1; 11n-warning light N; 12-signal processor; 121-light signal mode; 1211-synchronous flashing; 1212-interlaced flashing; 1213-polling flashing; 1214-recursive flashing; 1215-low power mode; 1216-sleep mode; 122-identification number; 123-control input side; 124-data input side; 125-data output side; 13-warning light control IC; 14-buffer; 2-control bus; 21-start command signal; 22-change identity command signal; 23-control circuit; 231-control signal source; 3-data bus; 31-data signal; 32-clock signal; 33-identity data; 34-data synchronization circuit; 341-data signal source; 342-signal connection circuit; 343-signal connection line; 4-initiator; 5-receiver; POWER ON OFF - power switch signal; LOW POWER - low power signal; SWITCH PATTERN - switching mode signal; MCUVCC - signal processor power supply; VIN - input voltage source; GND - ground point; SYNC - synchronization signal; SYNC Line - synchronization signal line; IND - command signal; Indicator - command signal line; Enable - enable pin; D1, D2, D3, D4, D5 - current limiters; R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17 - resistors; Q1, Q2, Q3, Q4, Q5, DLQ1 - active switches; D - drain; G - gate; S - source; n1 - first node; n2 - second node; n3 - third node; n4 - fourth node; n5 - fifth node; n6 - sixth node. DETAILED DESCRIPTION

[0016] In order to achieve the above-mentioned objectives and effects, the technical means and structures adopted by the present invention are illustrated in detail below with reference to the preferred embodiments of the present invention, and their features and functions are described for a complete understanding.

[0017] See also Figures 1 to 3 The figures show a functional block diagram of the warning light assembly and its control architecture according to the present invention, a functional block diagram of data stored within the signal processor, and another functional block diagram of the warning light assembly and its control architecture. As can be clearly seen from the figures, the control circuit for the warning light according to the present invention includes: a warning light assembly 1, a control bus 2, and a data bus 3. The main components and features thereof are described in detail below:

[0018] See also Figure 1 As shown, the warning light assembly (Light Device) 1 includes a plurality of warning lights 11a~11n, and the plurality of warning lights 11a~11n are electrically connected to a control bus (Control Bus) 2 and a data bus (Data Bus) 3 through a signal line, and the plurality of warning lights 11a~11n further include a signal processor 12 therein, and the signal processor 12 is composed of a micro control unit (Micro Control Unit, MCU) or a central processing unit (CPU).

[0019] See also Figure 2 As shown, the signal processor 12 of the plurality of warning lights 11a-11n each stores a flash mode 121 and an ID number 122. The flash mode 121 includes a synchronous flashing 1211, an interlace flashing 1212, a polling flashing 1213, a recursive flashing 1214, a low power mode 1215, and a sleep mode 1216. In addition to the aforementioned flash modes 121, the initiator 4 can also control the plurality of receivers 5 to flash in different modes via the data bus 3 (for example, the first receiver performs synchronous flashing, the second receiver performs polling flashing, and the third receiver performs interlace flashing). The aforementioned control of the flashing of the plurality of receivers 5 by the initiator 4 also falls within the scope of protection of the present invention. The identity number 122 is determined according to the start command signal 21 and the change identity command signal 22 of the control bus 2. Therefore, the identity numbers 122 of the plurality of warning lights 11a to 11n are in a floating state, but are only changed upon receiving the start command signal 21 and the change identity command signal 22.

[0020] See also Figure 3As shown, the control bus 2 sends a start command signal 21 to notify the plurality of warning lights 11a~11n, sets the light signal pattern 121 and sequentially numbers each warning light 11a~11n starting from 1, and uses the light signal pattern 121 number to synchronously set the identity number 122 of each warning light 11a~11n, sets the predetermined identity number of the plurality of warning lights 11a~11n as a starter (Starter) 4, and the remaining identity numbers are set as receivers (Receiver) 5. The warning light set as the starter 4 receives a start command signal (Start Command) 21 through the control bus 2, and transmits a data signal (Data) 31 and a clock signal (Clock) from the data bus 3. Pulse) 32 and an identity data (IDInformation) 33, and the light signal mode 121 selects one of them (synchronous flashing 1211, staggered flashing 1212, polling flashing 1213, recursive flashing 1214, low power mode 1215 or a sleep mode 1216) to flash the light, and the multiple warning lights set as receivers 5 obtain the data signal 31, the clock signal 32 and the identity data 33 through the data bus 3, and the multiple receivers 5 and the light signal mode 121 of the initiator 4 flash the light in synchronization, asynchronous, low power mode 1215 or sleep mode 1216.

[0021] In the mode in which the plurality of warning lights 11a-11n are numbered by the light signal pattern 121 to synchronously set the identification number 122 of each warning light 11a-11n, generally, the identification number 1 can be set as the starter 4. However, the present invention is not limited to this. Each identification number set via the control bus 2 may be set as the starter 4. For example, identification numbers other than 1, such as 2nd, 5th, 8th, etc., may also be set as the starter 4. Such a mode in which the warning light 11a-11n with any identification number is set as the starter 4 via the control bus 2 is also within the scope of protection of the present invention.

[0022] When the initiator 4 and the plurality of receivers 5 are each performing synchronous or asynchronous flashing of lights, if they receive the identity change command signal 22 transmitted by their common control bus 2, the identities of the initiator 4 and the plurality of receivers 5 will be changed. Specifically, before the initiator 4 and the plurality of receivers 5 change their identities, the plurality of receivers first suspend the current light signal mode 121 and then perform a self-flash mode. The control bus 2 will re-send a start command signal 21 to notify the plurality of warning lights 11a~11n, set the light signal mode 121 and number each warning light 11a~11n in sequence starting from 1, and use the light signal mode 121 number to synchronously set the identity number 122 of each warning light (11a~11n).

[0023] See also Figure 3 、 Figure 4 、 Figure 5 As shown, the signal processor 12 stores data of a plurality of light signal patterns 121, and uses the light signal pattern 121 number to synchronously set the identity number 122 of the plurality of warning lights 11a~11n, and sets the predetermined identity number of the plurality of warning lights 11a~11n as an initiator 4, and the remaining identity numbers are set as a receiver 5.

[0024] The control circuit 23 includes at least one control signal source 231. The control signal source 231 is electrically connected to an active switch Q1, Q3, or Q5. The output end of the active switch Q1, Q3, or Q5 is electrically connected to a control input side 123 of the signal processor 12 via a control bus 2.

[0025] The data synchronization circuit 34 includes at least one data signal source 341, which is electrically connected to another set of active switches. The output end of the other set of active switches is electrically connected to a data input side 124 of the signal processor 12 via a data bus 3. The signal processor 12 is electrically connected to a signal connection circuit 342 through a data output side 125 electrically connected to the data bus 3, thereby achieving signal and command synchronization between the data input side 124 and the data output side 125.

[0026] The warning light control IC 13 is connected to the plurality of warning lights 11a-11n and is electrically connected to the data bus 3 outside the data output side 125. The data output side 125 transmits a data signal 31, a clock signal 32, and an identity data 33, and the initiator 4 and the plurality of receivers 5 select one of the plurality of light signal modes 121 to flash the light.

[0027] The above-mentioned multiple active switches Q1, Q2, Q3, Q4, Q5, and DLQ1 are composed of an N-channel enhancement mode metal oxide semiconductor field effect transistor (N-Channel E-MOSFET), and a Zener diode (Zener Diode) is connected between the source S and the drain D of the N-channel enhancement mode metal oxide semiconductor field effect transistor to prevent electrostatic discharge (ESD).

[0028] A current limiter D1, D3, or D5 and two resistors [R1, R4], [R6, R8], or [R10, R13] are connected in series between the control signal source 231 and the active switch Q1, Q3, or Q5. The floating ends of the two resistors [R1, R4], [R6, R8], or [R10, R13] are connected to a ground point. A first node n1 (Node) between the two resistors [R1, R4], [R6, R8], or [R10, R13] is electrically connected to the gate G of the active switch Q1, Q3, or Q5. The source S of the active switch Q1, Q3, or Q5 is connected to the ground point, and the drain D of the active switch Q1, Q3, or Q5 is connected to the control input side 123 of the signal processor 12. The current limiter D1, D3, or D5 is formed by a diode.

[0029] The control signal source 231 includes a power switch signal POWER ON OFF, a low power signal LOWPOWER, a switch pattern signal SWITCH PATTERN, and an instruction signal IND.

[0030] A second node n2 is defined between the data signal source and the other set of active switches. A first side of the second node n2 is connected to an input voltage source VIN, a current limiter D2, and a resistor R3. Another current limiter D3 and two other resistors R7 and R9 are connected in series on a second side of the second node n2. The other set of active switches comprises a first-stage active switch Q4 and a second-stage active switch Q2. The floating ends of the two other resistors R7 and R9 are connected in series to a ground point. A third node n3 between the two other resistors R7 and R9 is electrically connected to the gate G of the second-stage active switch Q2. Sources S of the first-stage active switch Q4 and the second-stage active switch Q2 are connected to ground, and a drain D of the second-stage active switch Q2 is connected to the data bus 3 and the data input side 124 of the signal processor 12. The current limiter D2 and the other current limiter D3 are formed by diodes.

[0031] The data signal source 341 includes a synchronization signal SYNC and an instruction signal IND.

[0032] The signal connection circuit 342 includes a signal processor power supply MCUVCC and two resistors R12 and R14 connected in series. The floating end of the first resistor R12 is connected to the signal processor power supply MCUVCC. A fourth node n4 electrically connected to the external data bus 3 on the data output side 125 is formed between the first resistor R12 and the second resistor R14. The second resistor R14 is electrically connected to the gate G of an active switch DLQ1, and the source S of the active switch DLQ1 is connected to the ground point. Another resistor R11 is connected in series to the drain D of the active switch, and the floating end of the other resistor R11 is electrically connected between the data signal source 341 and the other set of active switches via a signal connection line 343.

[0033] Between the data bus 3 outside the data output side 125 and the warning light control IC 13, a signal processor power supply MCUVCC and three resistors R15, R16, and R17 are sequentially arranged. The floating end of the first resistor R15 is connected to the signal processor power supply MCUVCC. A fifth node n5 electrically connected to the data bus 3 is formed between the first resistor R15 and the second resistor R16. A sixth node n6 electrically connected to the enable pin Enable of the warning light control IC is formed between the second resistor R16 and the third resistor R17. The floating end of the third resistor R17 is connected to ground.

[0034] The signal processor 12 is internally or externally connected to a register 14 for storing the data signal 31 , the clock signal 32 , and the identity data 33 . The register 14 is formed of a non-volatile memory (NVM).

[0035] During actual operation, the control circuit for warning lights of the present invention receives an initialization command to set a light pattern 121 for the plurality of warning lights 11a-11n. The initialization command is a plurality of control signals provided by a control signal source 231, including a power switch signal POWER ONOFF, a low power signal LOW POWER, a switch pattern signal SWITCH PATTERN, and an instruction signal IND. The plurality of control signals cause the gates G of the plurality of active switches (Q1, Q3, Q5) to generate forward currents. The output terminals of the plurality of active switches Q1, Q3, Q5 transmit the plurality of control signals to a control input side 123 of a signal processor 12. Upon receiving the control command, the signal processor 12 uses the light pattern 121 stored therein to synchronously set the identification numbers 122 of the plurality of warning lights 11a-11n. The predetermined identification number of the plurality of warning lights 11a-11n is set to an initiator 4, and the remaining identification numbers are set to a receiver 5.

[0036] As described above, the warning light set as the initiator 4 receives multiple control signals via the control bus 2 and transmits the data signal 31, the clock signal 32, and the identification data 33 via the data bus 3 outside the data output side 125. The light flashes in one of the following modes: synchronous flashing 1211, staggered flashing 1212, polling flashing 1213, recursive flashing 1214, low power mode 1215, or sleep mode 1216. The multiple warning lights set as the receivers receive the data signal 31, the clock signal 32, and the identification data 33 via the data bus 3 and the warning light control IC 13. The multiple receivers 5 flash in synchronization or asynchronously with the light signal mode 121 of the initiator 4. The initiator 4 transmits the data, clock, and identification signals 31, 32, and 33 via the data bus 3 to control the multiple receivers 5. Furthermore, the transmission and synchronization of commands between the initiator 4 and the plurality of receivers 5 require the connection of the signal connection circuit 342 and the signal connection line 343 to the data signal source 341, and the connection of the synchronization signal SYNC and the command signal IND of the data signal source 341 to the data bus 3 and the data input side 124 of the signal processor 12 via the drain D of the second-stage active switch Q2, so as to synchronize the signals and commands between the data input side 124 and the data output side 125.

[0037] See also Figure 3 、 Figure 5 As shown, upon receiving the identity change command signal 22 transmitted by the switch pattern signal SWITCH PATTERN from the control signal source 231, the control bus 2 of the initiator 4 and the plurality of receivers 5 executes the change of the light pattern 121, the identity number 122, the initiator 4 and the plurality of receivers 5, thereby changing the light pattern 121 of the plurality of warning lights 11a-11n.

[0038] The present invention mainly adopts the above Figures 1 to 5 The control circuit architecture sets each warning light with its own identification number, and the initiator controls multiple receivers by transmitting data, clock and identification signals through the data bus. This can improve the control stability and flashing coordination of the warning lights, and has excellent practicality when applied to vehicles equipped with warning light groups (such as fire trucks, ambulances and police vehicles).

[0039] The above is only a preferred embodiment of the present invention, and does not limit the scope of the present invention. Therefore, all simple modifications and equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the scope of protection of the present invention and are hereby stated.

[0040] In summary, the control circuit for the warning light of the present invention can truly achieve its efficacy and purpose when used, and therefore the present invention is an invention with excellent practicality.

Claims

1. A control circuit for a warning light, characterized in that: include: A signal processor storing data of a plurality of light signal patterns, using the light signal pattern numbers to synchronously set the identification numbers of a plurality of warning lights, and setting a predetermined identification number of the plurality of warning lights as a starter, and setting the remaining identification numbers as a receiver; a control circuit comprising at least one control signal source electrically connected to an active switch, wherein an output terminal of the active switch is electrically connected to a control input side of the signal processor via a control bus; a data synchronization circuit comprising at least one data signal source electrically connected to another set of active switches, the output end of the other set of active switches electrically connected to a data input side of the signal processor via a data bus, and the signal processor electrically connected to a data output side of the signal processor electrically connected to the data bus, thereby achieving signal and command synchronization between the data input side and the data output side; and A warning light control IC is connected to the plurality of warning lights and electrically connected to the data bus outside the data output side, and transmits a data signal, a clock signal and an identity data from the data output side, and the initiator and the plurality of receivers select one of the plurality of light signal modes to flash the light.

2. The control circuit for a warning light according to claim 1, wherein: The plurality of active switches are formed by an N-channel enhancement mode metal oxide semiconductor field effect transistor, and a Zener diode capable of preventing electrostatic discharge is connected between the source and the drain of the N-channel enhancement mode metal oxide semiconductor field effect transistor.

3. The control circuit for a warning light according to claim 1, wherein: A current limiter and two resistors are connected in series between the control signal source and the active switch. The floating ends of the two resistors are connected to a ground point, and a first node between the two resistors is electrically connected to the gate of the active switch. The source of the active switch is connected to the ground point, and the drain of the active switch is connected to the control input side of the signal processor. The current limiter is formed by a diode.

4. The control circuit for a warning light according to claim 1, wherein: A second node is defined between the data signal source and the other set of active switches. An input voltage source, a current limiter, and a resistor are connected to a first side of the second node. Another current limiter and two additional resistors are connected in series to a second side of the second node. The other set of active switches comprises a first-stage active switch and a second-stage active switch. The floating ends of the two additional resistors are connected to a ground point in series, and a third node between the two additional resistors is electrically connected to the gate of the second-stage active switch. The sources of the first-stage active switch and the second-stage active switch are connected to the ground point, and the drain of the second-stage active switch is connected to the data bus and the data input side of the signal processor. The current limiter and the additional current limiter are formed by diodes.

5. The control circuit for a warning light according to claim 1, wherein: The signal connection circuit includes a signal processor power supply and two resistors connected in series. The floating end of the first resistor is connected to the signal processor power supply. A fourth node electrically connected to the data output-side external data bus is formed between the first and second resistors. The second resistor is electrically connected to the gate of an active switch, and the source of the active switch is connected to a ground point. Another resistor is connected in series to the drain of the active switch, and the floating end of the other resistor is electrically connected between the data signal source and the other set of active switches via a synchronization connection line.

6. The control circuit for a warning light according to claim 1, wherein: A signal processor power supply and three resistors are sequentially connected between the data bus outside the data output side and the warning light control IC. The floating end of the first resistor is connected to the signal processor power supply. A fifth node electrically connected to the data bus is formed between the first and second resistors. A sixth node electrically connected to the enable pin of the warning light control IC is formed between the second and third resistors. The floating end of the third resistor is connected to a ground point.

7. The control circuit for a warning light according to claim 1, wherein: The signal processor is built-in or externally connected with a register capable of storing the data signal, the clock signal and the identity data. The register is composed of a non-volatile memory.

8. The control circuit for a warning light according to claim 1, wherein: The control signal source includes a power switch signal, a low power signal, a switching mode signal and a command signal.

9. The control circuit for a warning light according to claim 1, wherein: The data signal source includes a synchronization signal and a command signal.

10. The control circuit for a warning light according to claim 1, wherein: The signal processor is composed of a micro control unit or a central processing unit.

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