A fully integrated LDO circuit for high-current applications and its operation method

Abstract

A fully integrated LDO circuit for high-current applications and its operating method are disclosed. The circuit includes a main loop and an auxiliary loop. The main loop includes a first operational amplifier, a second power transistor, a feedback module, and a load resistor. The auxiliary loop includes a second operational amplifier and the first power transistor. The negative input terminal of the first operational amplifier is connected to the feedback voltage. The output terminals of both the first and second operational amplifiers are connected to the gate terminals of the second power transistor. The gate terminals of the first and second power transistors are connected together, and their drain terminals are connected together and then connected to the input voltage. The negative input terminal of the second operational amplifier is connected to the source terminal of the first power transistor. The source terminal of the second power transistor is the output terminal of the LDO circuit. Based on the superposition principle, the main and auxiliary loops have simultaneous frequency responses. When the gain of the main loop is greater than that of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the main loop; otherwise, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the auxiliary loop. This invention improves the stability and transient response capability of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit power management technology, specifically, it relates to a fully integrated LDO circuit for high current applications and its operating method. Background Technology

[0002] With the advancement of technology in today's society, people's demand for portable terminal devices is constantly increasing, and they are now widely used in people's production, work, and daily life. In the field of electronic systems, power management chip products are not only developing towards miniaturization, low power consumption, and intelligence, but also paying more attention to stability and high driveability. Among various power management chips, low dropout regulators (LDOs) are widely used in various integrated circuits to provide stable voltage due to their advantages such as simple structure, low cost, high power supply ripple suppression capability, low output noise, and fast transient response.

[0003] In existing technologies, LDOs require a large external output capacitor for filtering and voltage regulation, and the capacitor's built-in equivalent series resistance can provide a zero point for circuit compensation. However, because the large output capacitor occupies a significant area, even if it's not placed on-chip, additional pins must be designed for the off-chip output capacitor, increasing design costs. With the development of integrated circuits, the requirements for the output current capability of power management chips are becoming increasingly stringent. To meet the requirement of high output current capability, LDOs need large-size power transistors with gate capacitances reaching hundreds of pF. Combined with the lack of an off-chip capacitor, this presents even greater challenges to the stability and transient response capabilities of LDOs. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a fully integrated LDO circuit and its operating method for high-current applications. An auxiliary loop is added to compensate for the circuit's frequency response, and adaptive bias technology is used to enhance the circuit's transient response capability, thereby giving the circuit better stability and transient response capability.

[0005] The present invention adopts the following technical solution.

[0006] This invention proposes a fully integrated LDO circuit for high-current applications, including a main loop. The main loop includes an error amplifier, a second power transistor, a feedback module, and a load resistor. When the load resistor changes, causing the output voltage of the LDO circuit to fluctuate, the main loop reduces the gate voltage of the second power transistor according to the feedback voltage output by the feedback module.

[0007] The LDO circuit includes an auxiliary loop; wherein the error amplifier includes a first operational amplifier, and the auxiliary loop includes a second operational amplifier and a first power transistor;

[0008] The positive input terminal of the first operational amplifier is connected to the reference voltage, and the negative input terminal is connected to the feedback voltage. The output terminals of both the first and second operational amplifiers are connected to the gate terminals of the second power transistor. The gate terminals of the first and second power transistors are connected together, and their drain terminals are connected together and then connected to the input voltage. The positive input terminal of the second operational amplifier is grounded, and its negative input terminal is connected to the source terminal of the first power transistor. The source terminal of the second power transistor is the output terminal of the LDO circuit.

[0009] Based on the superposition principle, the main loop and the auxiliary loop respond simultaneously. When the gain of the main loop is greater than the gain of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the main loop. When the gain of the main loop is not greater than the gain of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the auxiliary loop.

[0010] The main loop also includes: an adaptive bias module; the error amplifier also includes a bias current source;

[0011] The input terminal of the detection module is connected to the output terminal of the first operational amplifier, and the output terminal of the detection module is connected to the control terminal of the bias current source. When the detection module detects a decrease in output voltage, it increases the current of the bias current source, thereby increasing the bandwidth of the first operational amplifier.

[0012] The first power transistor is used to replicate the gate voltage of the second power transistor.

[0013] The auxiliary loop also includes auxiliary resistors, auxiliary capacitors, and current sources;

[0014] The negative input terminal of the second operational amplifier is connected to one end of the auxiliary resistor and one end of the auxiliary capacitor, and the other end of the auxiliary resistor is grounded. The source terminal of the first power transistor is connected to the other end of the auxiliary capacitor and the current source.

[0015] The first operational amplifier includes 1 to 11 MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, ...1, M1, M1, M1, M1, M1, M1, M1, M2, M3, M4, M5, M6, M7, M8, M9, M1, M1, M 10 M 11 The first capacitor is C1, where the gate terminal of M1 is connected to the reference voltage V. REF Both source terminals M1 and M2 are connected to M 11 The drain terminals of M1 and M5 are both connected to the source terminal of M3, and the gate terminal of M2 is connected to the feedback voltage V. FB The drain terminals of M2 and M6 are both connected to the source terminal of M4, and the gate terminals of M3 and M4 are both connected to the first bias voltage V. b1 Both the gate terminals of M5 and M6 are connected to the third bias voltage V. b3 Both source terminals M5 and M6 are grounded, and the drain terminals of M3, M7, M9, and M are connected to each other. 10All gate terminals are connected together. The drain terminals of M4 and M8 are connected and form the output terminal of the first operational amplifier EA1, with an output voltage of V. OUT，EA M7 gate, M8 gate and M 11 The gate terminals are all connected to a second bias voltage V. b2 M7 source terminal connects to M9 drain terminal, M8 source terminal connects to M 10 Drain, M9 source and M 10 Source and M 11 The source terminals are all connected to the power supply voltage VDD; one end of C1 is connected to the drain terminal of M6, and the other end of C1 is connected to the drain terminal of M4.

[0016] The auxiliary loop includes: a second operational amplifier and a fifteenth MOSFET M. 15 The sixteenth MOSFET M 16 The second operational amplifier includes MOSFETs M3, M4, M5, M6, M7, M8, M9, and M10. 10 MOSFETs 12 to 14 12 M 13 M 14 Auxiliary resistor R F Auxiliary capacitor C F ; where M 12 Gate terminal and auxiliary capacitor C F One end, auxiliary resistor R F Connect one end, M 12 Drain terminal connected to M6 drain terminal, M 12 Source and M 13 The source end is connected to M. 14 Drain, M 13 Drain and auxiliary resistor R F The other end, M 15 Both source terminals are grounded, M 15 Drain terminal connected to M5 drain terminal, M 14 Source and M 16 The drain terminals are all connected to the power supply voltage VDD, M 14 The gate terminal is connected to the second bias voltage V b2 M 15 The drain terminal is connected to an auxiliary capacitor C. F The other end and M 16 Source end, M 15 The gate terminal is connected to the first bias voltage Vb1, M 16 The gate terminal is connected to the output terminal of the first operational amplifier EA1.

[0017] The first operational amplifier and the second operational amplifier share the third to tenth MOS transistors, forming a folded common-source and common-gate structure.

[0018] The adaptive bias module includes the seventeenth to twenty-first MOSFETs M 17 M 18 M19 M 20 M ab M 17 Gate and drain terminals with M 19 Drain, M 18 Gate terminals connected, M 17 Source and M 18 Source and M ab The source terminals are all connected to the power supply voltage VDD, M 18 Drain, M 20 Gate end, M 20 Source and M ab Gate terminals connected, M 19 The gate terminal is connected to the output terminal of the first operational amplifier EA1, M 19 Source and M 20 Both source terminals are grounded, M ab The drain terminal is connected to the source terminal M1 in the first operational amplifier EA1.

[0019] M 19 The gate terminal is connected to the gate terminal of the second power transistor. When the load current decreases, the output voltage V of the first operational amplifier... OUT，EA Decrease, M 19 The gate voltage drops, through M 17 and M 18 The current mirror formed will respond to the voltage change to M 20 Drain voltage V ab V ab With V OUT，EA Decrease and decrease, when V ab Decrease, M ab As the gate voltage decreases, the bias current source current increases.

[0020] The auxiliary resistor and auxiliary capacitor form an RC high-pass loop. In the static state, M... 16 The gate voltage is constant, and all current flows through M. 15 When the transistor is grounded, no current flows through the RC high-pass loop, and the input voltage of the second operational amplifier is 0. When the gate voltage of the second power transistor changes, M... 16 The gate voltage changes accordingly, and a current flows through the RC high-pass loop, M 12 The gate voltage fluctuates, and the output voltage V of the first operational amplifier is changed by folding the cascode structure. OUT，EA .

[0021] The second power transistor is an NMOS power transistor.

[0022] This invention also proposes a method for operating a fully integrated LDO circuit for high-current applications, comprising: when the output voltage increases, in the main loop, the feedback voltage output by the feedback module increases, the voltage at the negative input terminal of the first operational amplifier increases, the output voltage of the first operational amplifier decreases, the gate voltage of the second power transistor decreases, and the output voltage decreases accordingly; simultaneously, in the auxiliary loop, under the effect of the parasitic capacitance at the gate terminal of the second power transistor, the gate voltage of the second power transistor increases as the output voltage increases, the first power transistor replicates the gate voltage of the second power transistor, the source voltage of the first power transistor increases, causing the voltage at the negative input terminal of the second operational amplifier to increase, the output voltage of the second operational amplifier to decrease, the gate voltage of the second power transistor to decrease, and the output voltage decreases accordingly; when the detection module detects a decrease in output voltage, it increases the current of the bias current source.

[0023] The beneficial effects of this invention are that, compared with the prior art, the LDO circuit proposed in this invention constructs an auxiliary loop to jointly handle voltage fluctuations and compensate for circuit frequency response, especially when the gain of the main loop is lower than that of the auxiliary loop, the auxiliary loop mainly performs frequency compensation, thereby improving the phase margin and stability of the overall circuit. The auxiliary loop circuit proposed in this invention is simple and integrated with the error amplifier, reducing the number of components used and saving chip area.

[0024] This invention constructs an adaptive bias module that detects the output voltage V. OUT When the current is reduced, the current of the bias current source is increased, thereby increasing the bandwidth of the error amplifier. This helps to handle output voltage fluctuations caused by load switching, improving the transient response speed during output load switching and enhancing output voltage stability and accuracy. Furthermore, the adaptive bias module is integrated with the error amplifier, reducing the number of components used and saving chip area.

[0025] The LDO circuit proposed in this invention uses an NMOS power transistor whose gate-source voltage is unaffected by the input voltage ripple, which can improve the power supply rejection ratio of the circuit.

[0026] The LDO circuit proposed in this invention does not use large off-chip capacitors, making it easy to integrate, while providing a large load current of up to 3A. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a fully integrated LDO circuit for high-current applications proposed in this invention.

[0028] Figure 1 The annotations in the accompanying drawings are explained as follows:

[0029] 1-Error amplifier, 2-Adaptive bias module, 3-Auxiliary loop, 4a-First power transistor, 4b-Second power transistor, 5-Feedback module, 6-Detection module;

[0030] Figure 2 This is a circuit schematic of an error amplifier in a fully integrated LDO circuit for high-current applications proposed in this invention.

[0031] Figure 3 This is a circuit diagram of the auxiliary loop in a fully integrated LDO circuit for high-current applications proposed in this invention.

[0032] Figure 4 This is a circuit schematic of the adaptive bias module and feedback module in a fully integrated LDO circuit for high-current applications proposed in this invention.

[0033] Figure 5 This is a schematic diagram of the frequency response of a fully integrated LDO circuit for high-current applications in an embodiment of the present invention.

[0034] Figure 6 This is a simulation curve of the transient response of a fully integrated LDO circuit for high-current applications in an embodiment of the present invention.

[0035] Figure 7 This is a simulation curve of the frequency response of a fully integrated LDO circuit for high-current applications in an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0037] This invention proposes a fully integrated LDO circuit for high-current applications, such as... Figure 1 As shown, it includes: main loop, auxiliary loop 3, second power transistor 4b, and load resistor R. L The main loop includes: error amplifier 1, adaptive bias module 2, second power transistor 4b, feedback module 5, and load resistor RL.

[0038] The error amplifier 1 includes a first operational amplifier EA1 and a bias current source S1; the adaptive bias module 2 includes a detection module 6; and the auxiliary loop 3 includes a second operational amplifier EA2 and an auxiliary resistor R. F Auxiliary capacitor C FThe circuit consists of a current source S2 and a first power transistor 4a. The feedback module 5 includes a first resistor R1 and a second resistor R2. When a change in load resistance causes fluctuations in the output voltage of the LDO circuit, the main loop reduces the gate voltage of the second power transistor based on the feedback voltage output by the feedback module.

[0039] Specifically, such as Figure 1 As shown, the positive input terminal of the first operational amplifier EA1 is connected to the reference voltage V. REF The output terminal A of the first operational amplifier EA1 and the output terminal B of the second operational amplifier EA2 are both connected to the gate terminal of the second power transistor 4b. The gate terminals of the first power transistor 4a and the second power transistor 4b are connected together. The drain terminals of the first power transistor 4a and the second power transistor 4b are connected together and then connected to the input voltage V. IN The source terminal of the second power transistor 4b is connected to one end C of the first resistor R1 and one end of the load resistor RL. The other end D of the first resistor R1 is connected to the negative input terminal of the first operational amplifier EA1 and one end of the second resistor R2. The other end of the second resistor R2 is connected to the load resistor R. L The other end of each is grounded; the input terminal of detection module 6 is connected to the output terminal A of the first operational amplifier EA1, and the output terminal of detection module 6 is connected to the control terminal of the bias current source S1; the positive input terminal of the second operational amplifier EA2 is grounded, and the negative input terminal is connected to the auxiliary resistor R. F One end and auxiliary capacitor C F One end, auxiliary resistor R F The other end is grounded, and the source terminal of the first power transistor 4a is connected to the auxiliary capacitor C. F The other end is connected to the current source S2; the source of the second power transistor 4b is the output of the fully integrated LDO, and the output is connected to the load resistor R. L One end has an output voltage of V. OUT The first power transistor 4a is used to replicate the gate voltage of the second power transistor 4b.

[0040] When the output voltage V OUT When voltage fluctuations occur, both the main loop and the auxiliary loop work together to handle them. At high frequencies, the auxiliary loop replaces the main loop as the dominant circuit element; that is, the auxiliary loop performs primary frequency compensation, while the main loop provides secondary compensation. Therefore, a high-gain main loop is required. In existing technologies, high gain inevitably results in low bandwidth and low phase margin. Therefore, this invention constructs an auxiliary loop with low gain but high bandwidth and high phase margin. When the gain of the main loop is lower than that of the auxiliary loop, the auxiliary loop takes the lead in frequency compensation, improving the phase margin of the overall circuit. This invention uses the auxiliary loop to compensate for circuit fluctuations, and after handling the fluctuations, it changes the input voltage of the power transistor to achieve a stable output voltage.

[0041] Specifically, when the main loop and the auxiliary loop work together to handle voltage fluctuations, the output voltage V OUTAs the voltage increases, the feedback voltage output by the feedback module in the main loop rises, the voltage at the negative input terminal of the first operational amplifier EA1 rises, the output voltage of the first operational amplifier EA1 decreases, the gate voltage of the second power transistor decreases, and the output voltage V... OUT Consequently, it decreases; simultaneously, in the auxiliary loop, due to the parasitic capacitance at the gate of the second power transistor, the gate voltage of the second power transistor decreases with the output voltage V. OUT As the voltage increases, the first power transistor replicates the gate voltage of the second power transistor, causing the voltage at the negative input terminal of the second operational amplifier EA2 to rise. Consequently, the output voltage of the second operational amplifier EA2 decreases, the gate voltage of the second power transistor decreases, and the output voltage V... OUT It decreases accordingly.

[0042] Furthermore, due to the large gate-source capacitance of the second power transistor and the limited bandwidth of the error amplifier, when the load resistance R... L When changes occur, it will cause a large output voltage V. OUT The fluctuation, the detection module detects the output voltage V OUT When the current is reduced, the current of the bias current source is increased, thereby increasing the bandwidth of the error amplifier and reducing the output voltage V due to load switching. OUT Fluctuations are processed to improve transient response capabilities.

[0043] like Figure 2 As shown, the first operational amplifier EA1 includes eleven MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M11. 10 M 11 The first capacitor is C1, where the gate terminal of M1 is connected to the reference voltage V. REF Both source terminals M1 and M2 are connected to M 11 The drain terminals of M1 and M5 are both connected to the source terminal of M3, and the gate terminal of M2 is connected to the feedback voltage V. FB The drain terminals of M2 and M6 are both connected to the source terminal of M4, and the gate terminals of M3 and M4 are both connected to the first bias voltage V. b1 Both the gate terminals of M5 and M6 are connected to the third bias voltage V. b3 Both source terminals M5 and M6 are grounded, and the drain terminals of M3, M7, M9, and M are connected to each other. 10 All gate terminals are connected together. The drain terminals of M4 and M8 are connected and form the output terminal of the first operational amplifier EA1, with an output voltage of V. OUT，EA M7 gate, M8 gate and M 11 The gate terminals are all connected to a second bias voltage V. b2 M7 source terminal connects to M9 drain terminal, M8 source terminal connects to M 10 Drain, M9 source and M 10 Source and M 11Both ends are connected to the power supply voltage VDD. One end of C1 is connected to the drain of M6, and the other end of C1 is connected to the drain of M4.

[0044] like Figure 2 and 3 As shown, the auxiliary loop includes: the second operational amplifier EA2, and the fifteenth MOSFET M. 15 The sixteenth MOSFET M 16 The second operational amplifier EA2 includes the third to tenth MOSFETs M3, M4, M5, M6, M7, M8, M9, and M10. 10 MOSFETs 12 to 14 12 M 13 M 14 Auxiliary resistor R F Auxiliary capacitor C F ; where M 12 Gate terminal and auxiliary capacitor C F One end, auxiliary resistor R F Connect one end, M 12 Drain terminal connected to M6 drain terminal, M 12 Source and M 13 The source end is connected to M. 14 Drain, M 13 Drain and auxiliary resistor R F The other end, M 15 Both source terminals are grounded, M 15 Drain terminal connected to M5 drain terminal, M 14 Source and M 16 The drain terminals are all connected to the power supply voltage VDD, M 14 The gate terminal is connected to the second bias voltage V b2 M 15 The drain terminal is connected to an auxiliary capacitor C. F The other end and M 16 Source end, M 15 The gate terminal is connected to the first bias voltage Vb1, M 16 The gate terminal is connected to the output terminal of the first operational amplifier EA1.

[0045] Furthermore, the first operational amplifier EA1 and the second operational amplifier EA2 share the third to tenth MOS transistors, forming a folded common-source and common-gate structure.

[0046] like Figure 2 and 4 As shown, the adaptive bias module includes the seventeenth to twenty-first MOSFETs M 17 M 18 M 19 M 20 M ab M 17 Gate and drain terminals with M 19 Drain, M 18Gate terminals connected, M 17 Source and M 18 Source and M ab The source terminals are all connected to the power supply voltage VDD, M 18 Drain, M 20 Gate end, M 20 Source and M ab Gate terminals connected, M 19 The gate terminal is connected to the output terminal of the first operational amplifier EA1, M 19 Source and M 20 Both source terminals are grounded, M ab The drain terminal is connected to the source terminal of M1 in the first operational amplifier EA1. During simulation, I... LOAD A current source represents the load current.

[0047] M19 is used to detect the output voltage V. OUT Is there fluctuation? This invention proposes adding an adaptive bias module to the error amplifier, M 19 The gate terminal is connected to the gate terminal of the second power transistor, which is also connected to the output terminal of the first operational amplifier. When the load current decreases, the output voltage V of the first operational amplifier... OUT，EA Decrease, M 19 The gate voltage drops, through M 17 and M 18 The current mirror formed will respond to the voltage change to M 20 Drain voltage V ab V ab With V OUT，EA Decrease and decrease, when V ab Decrease, M ab The gate voltage decreases, the bias current source current increases, the bandwidth of the error amplifier increases, and the transient response capability of the error amplifier is enhanced.

[0048] Furthermore, the second power transistor 4b is an NMOS power transistor. The gate-source voltage of the second power transistor is not affected by the input voltage ripple, which can improve the power supply rejection ratio of the circuit.

[0049] like Figure 4 As shown, the feedback module includes a first resistor R1 and a second resistor R2. One end of R1 is connected to the source terminal of the second power transistor 4b, and the other end of R1 is connected to one end of resistor R2. The feedback voltage V output by the feedback module is... FB Connect the gate terminal of M2, and ground the other end of R2.

[0050] The main loop gain is the gain A of the first operational amplifier. V As shown below:

[0051] A V =g m R OUT

[0052] g m ≈g m1

[0053] R OUT ≈[(g m3 +g mb )r O3 (r O1 ||r O5 )]||[(g m7 +g mb7 )r O7 r O9 ]

[0054] In the formula,

[0055] g m The equivalent transconductance of the first operational amplifier,

[0056] R OUT The equivalent output impedance of the first operational amplifier is...

[0057] g m1 g m3 g m7 These are the transconductances of MOSFETs M1, M3, and M7, respectively.

[0058] g mb3 g mb7 The body-effect equivalent transconductances of MOSFETs M3 and M7 are respectively.

[0059] r O1 r O3 r O5 r O7 r O9 These are the output impedances of MOSFETs M1, M3, M7, and M9, respectively.

[0060] The main pole p0 of the main loop is shown below:

[0061] p0 = R OUT C GG

[0062] In the formula, C GG This is the gate parasitic capacitance of the second power transistor.

[0063] When the output of a fully integrated LDO circuit is connected to a capacitive load or has an output capacitor, the secondary pole p1 is as follows:

[0064] p1 = R L C L

[0065] In the formula, R L For the load resistance, C LThis is the load capacitor.

[0066] As can be seen, the secondary pole will shift depending on the load at the LDO output.

[0067] Based on the superposition principle, the main loop and the auxiliary loop respond simultaneously. When the gain of the main loop is greater than the gain of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the main loop. When the gain of the main loop is not greater than the gain of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the auxiliary loop.

[0068] The frequency response of the main loop is characterized by high gain and narrow bandwidth, while the frequency response of the auxiliary loop is characterized by low gain and wide bandwidth.

[0069] like Figure 1 and 3 As shown, the positive input terminal of the second operational amplifier EA2 is grounded, and the negative input terminal is connected to the auxiliary resistor R. F and auxiliary capacitor C F In the constructed RC high-pass loop, M in static state 16 The gate voltage is constant, and all current flows through M. 15 With the circuit grounded, no current flows through the RC high-pass loop, and the input terminal (M) of the second operational amplifier EA2... 12 The gate voltage is 0; when the gate voltage of the second power transistor changes, M... 16 The gate voltage changes accordingly, and a current flows through the RC high-pass loop, M 12 The gate voltage fluctuates, and the output voltage V of the first operational amplifier is changed by folding the cascode structure. OUT，EA This allows the output voltage of the LDO circuit to be changed via a second operational amplifier.

[0070] like Figure 2 As shown, a first capacitor C1 is connected between the drain and source terminals of M4, increasing the equivalent capacitance C at the output terminal of the first operational amplifier through the Miller effect. OUT This makes the main pole p0 of the loop closer to the origin and farther away from the secondary pole p1, thus improving the stability of the loop.

[0071] This invention also proposes a method for operating a fully integrated LDO circuit for high-current applications, including:

[0072] When the output voltage increases, in the main loop, the feedback voltage output by the feedback module increases, the voltage at the negative input terminal of the first operational amplifier increases, the output voltage of the first operational amplifier decreases, the gate voltage of the second power transistor decreases, and the output voltage decreases accordingly. Simultaneously, in the auxiliary loop, due to the parasitic capacitance at the gate of the second power transistor, the gate voltage of the second power transistor increases as the output voltage increases. The first power transistor replicates the gate voltage of the second power transistor, causing the voltage at the negative input terminal of the second operational amplifier to increase, the output voltage of the second operational amplifier to decrease, the gate voltage of the second power transistor to decrease, and the output voltage decreases accordingly.

[0073] When the detection module detects fluctuations in the output voltage, it increases the current of the bias current source, thereby increasing the bandwidth of the error amplifier and mitigating the impact of load switching on the output voltage V. OUT Fluctuations are processed to improve transient response capabilities.

[0074] Figure 5 This diagram illustrates the frequency response of a fully integrated LDO circuit for high-current applications according to an embodiment of the present invention. The solid line represents the main loop frequency response, and the dashed line represents the auxiliary loop frequency response. The main and auxiliary loops are superimposed to obtain the overall frequency response of the dual loops. In the low-frequency range, the main loop dominates, and the overall frequency response is primarily driven by the main loop frequency response. As the frequency increases, after reaching frequencies above the secondary pole p1, the main loop gain G decreases at a rate of 40 dB per decade. At this point, the main loop gain is still higher than the auxiliary loop gain, so the main loop continues to dominate the dual-loop frequency response until the gains of the main and auxiliary loops intersect at the frequency point ω in the diagram. z , in ω z After the point, the auxiliary loop takes over from the main loop to dominate the overall frequency response of the dual loop. The rate of gain decreases from 40dB per decade to 20dB per decade, and finally crosses the 0dB point, improving the phase margin and stability of the circuit.

[0075] The fully integrated LDO circuit proposed in this invention for high-current applications was simulated and tested. Figure 6 The transient response simulation curve is derived from... Figure 6 It can be seen that when the load current changes from 100mA to 3A and from 3A to 100mA at a rate of 1A / μs, the output voltage V OUT The overshoot voltage is 72mV, and the undershoot voltage is 53mV. The frequency response under different load conditions is as follows: Figure 7 As shown, the LDO circuit at its maximum output current I OUT When the current is 3A, the phase margin is 94.41°. Under no-load conditions in the LDO circuit, the output current I... OUT When the phase margin is 0, the phase margin is 111.79°.

[0076] This invention proposes a fully integrated LDO circuit for high-current applications. By adding an auxiliary loop and an adaptive bias module, it ensures stability across the entire current range when the maximum output load current is 3A, and improves the fast transient response when the load current changes rapidly.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A fully integrated LDO circuit for high-current applications, comprising a main loop, the main loop including an error amplifier, a second power transistor, a feedback module, and a load resistor, wherein when a change in the load resistor causes fluctuations in the output voltage of the LDO circuit, the main loop reduces the gate voltage of the second power transistor according to the feedback voltage output by the feedback module, characterized in that... The LDO circuit includes an auxiliary loop; wherein the error amplifier includes a first operational amplifier, and the first operational amplifier includes eleven MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, ...1, M1, M1, M1, M1, M1, M1, M1, M1, M1, M1, M1, M1 10 M 11 The first capacitor is C1, where the gate terminal of M1 is connected to the reference voltage V. REF Both source terminals M1 and M2 are connected to M 11 The drain terminals of M1 and M5 are both connected to the source terminal of M3, and the gate terminal of M2 is connected to the feedback voltage V. FB The drain terminals of M2 and M6 are both connected to the source terminal of M4, and the gate terminals of M3 and M4 are both connected to the first bias voltage V. b1 Both the gate terminals of M5 and M6 are connected to the third bias voltage V. b3 Both source terminals M5 and M6 are grounded, and the drain terminals of M3, M7, M9, and M are connected to each other. 10 All gate terminals are connected together. The drain terminals of M4 and M8 are connected and form the output terminal of the first operational amplifier EA1, with an output voltage of V. OUT，EA M7 gate, M8 gate and M 11 The gate terminals are all connected to a second bias voltage V. b2 M7 source terminal connects to M9 drain terminal, M8 source terminal connects to M 10 Drain, M9 source and M 10 Source and M 11 The source terminals are all connected to the power supply voltage VDD; one end of C1 is connected to the drain terminal of M6, and the other end of C1 is connected to the drain terminal of M4. The auxiliary loop includes a second operational amplifier and a fifteenth MOSFET M. 15 The sixteenth MOSFET M 16 The first power transistor; wherein, the second operational amplifier includes the third to tenth MOSFETs M3, M4, M5, M6, M7, M8, M9, and M10. 10 MOSFETs 12 to 14 12 M 13 M 14 Auxiliary resistor R F Auxiliary capacitor C F ; where M 12 Gate terminal and auxiliary capacitor C F One end, auxiliary resistor R F Connect one end, M 12 Drain terminal connected to M6 drain terminal, M 12 Source and M 13 The source end is connected to M. 14 Drain, M 13 Drain and auxiliary resistor R F The other end, M 15 Both source terminals are grounded, M 15 Drain terminal connected to M5 drain terminal, M 14 Source and M 16 The drain terminals are all connected to the power supply voltage VDD, M 14 The gate terminal is connected to the second bias voltage V b2 M 15 The drain terminal is connected to an auxiliary capacitor C. F The other end and M 16 Source end, M 15 The gate terminal is connected to the first bias voltage Vb1, M 16 The gate terminal is connected to the output terminal of the first operational amplifier EA1; The positive input terminal of the first operational amplifier is connected to the reference voltage, and the negative input terminal is connected to the feedback voltage. The output terminals of both the first and second operational amplifiers are connected to the gate terminals of the second power transistor. The gate terminals of the first and second power transistors are connected together, and their drain terminals are connected together and then connected to the input voltage. The positive input terminal of the second operational amplifier is grounded, and its negative input terminal is connected to the source terminal of the first power transistor. The source terminal of the second power transistor is the output terminal of the LDO circuit. Based on the superposition principle, the main loop and the auxiliary loop respond simultaneously. When the gain of the main loop is greater than the gain of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the main loop. When the gain of the main loop is not greater than the gain of the auxiliary loop, the gain characteristic of the LDO circuit is consistent with the gain characteristic of the auxiliary loop.

2. The fully integrated LDO circuit for high-current applications according to claim 1, characterized in that, The main loop also includes: an adaptive bias module; the error amplifier also includes a bias current source; The input terminal of the detection module is connected to the output terminal of the first operational amplifier, and the output terminal of the detection module is connected to the control terminal of the bias current source. When the detection module detects a decrease in output voltage, it increases the current of the bias current source, thereby increasing the bandwidth of the first operational amplifier.

3. The fully integrated LDO circuit for high-current applications according to claim 1, characterized in that, The first power transistor is used to replicate the gate voltage of the second power transistor.

4. The fully integrated LDO circuit for high-current applications according to claim 1, characterized in that, The auxiliary loop also includes auxiliary resistors, auxiliary capacitors, and current sources; The negative input terminal of the second operational amplifier is connected to one end of the auxiliary resistor and one end of the auxiliary capacitor, and the other end of the auxiliary resistor is grounded. The source terminal of the first power transistor is connected to the other end of the auxiliary capacitor and the current source.

5. The fully integrated LDO circuit for high-current applications according to claim 1, characterized in that, The first operational amplifier and the second operational amplifier share the third to tenth MOS transistors, forming a folded common-source and common-gate structure.

6. The fully integrated LDO circuit for high-current applications according to claim 1, characterized in that, The adaptive bias module includes the seventeenth to twenty-first MOSFETs M 17 M 18 M 19 M 20 M ab M 17 Gate and drain terminals with M 19 Drain, M 18 Gate terminals connected, M 17 Source and M 18 Source and M ab The source terminals are all connected to the power supply voltage VDD, M 18 Drain, M 20 Gate end, M 20 Source and M ab Gate terminals connected, M 19 The gate terminal is connected to the output terminal of the first operational amplifier EA1, M 19 Source and M 20 Both source terminals are grounded, M ab The drain terminal is connected to the source terminal M1 in the first operational amplifier EA1.

7. The fully integrated LDO circuit for high-current applications according to claim 6, characterized in that, M 19 The gate terminal is connected to the gate terminal of the second power transistor. When the load current decreases, the output voltage V of the first operational amplifier... OUT,EA Decrease, M 19 The gate voltage drops, through M 17 and M 18 The current mirror formed will respond to the voltage change to M 20 Drain voltage V ab V ab With V OUT,EA Decrease and decrease, when V ab Decrease, M ab As the gate voltage decreases, the bias current source current increases.

8. The fully integrated LDO circuit for high-current applications according to claim 1, characterized in that, The auxiliary resistor and auxiliary capacitor form an RC high-pass loop. In the static state, M... 16 The gate voltage is constant, and all current flows through M. 15 When the transistor is grounded, no current flows through the RC high-pass loop, and the input voltage of the second operational amplifier is 0. When the gate voltage of the second power transistor changes, M... 16 The gate voltage changes accordingly, and a current flows through the RC high-pass loop, M 12 The gate voltage fluctuates, and the output voltage V of the first operational amplifier is changed by folding the cascode structure. OUT,EA .

9. The fully integrated LDO circuit for high-current applications according to claim 1, characterized in that, The second power transistor is an NMOS power transistor.

10. A method for operating a fully integrated LDO circuit for high-current applications, applicable to the fully integrated LDO circuit for high-current applications as described in any one of claims 1-9, characterized in that: When the output voltage increases, in the main loop, the feedback voltage output by the feedback module increases, the voltage at the negative input terminal of the first operational amplifier increases, the output voltage of the first operational amplifier decreases, the gate voltage of the second power transistor decreases, and the output voltage decreases accordingly. Simultaneously, in the auxiliary loop, due to the parasitic capacitance at the gate of the second power transistor, the gate voltage of the second power transistor increases as the output voltage increases. The first power transistor replicates the gate voltage of the second power transistor, and the source voltage of the first power transistor increases, causing the voltage at the negative input terminal of the second operational amplifier to increase, the output voltage of the second operational amplifier to decrease, the gate voltage of the second power transistor to decrease, and the output voltage decreases accordingly. When the detection module detects a decrease in output voltage, it increases the current of the bias current source.

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