Gate drive circuit, display panel, and display device

Abstract

The present application discloses a gate drive circuit, a display panel, and a display device. The main output module in the gate drive circuit is used to alternately output a first level signal and a second level signal under the control of a first node and a second node; the transmission control unit is connected between the main start signal terminal and the first node, and when the first refresh frequency is switched to the second refresh frequency, the transmission control unit switches from the on state to the off state, and the first refresh frequency is greater than the second refresh frequency; the first control unit is connected between the standby start signal terminal and the first node, and when the second refresh frequency is switched to the first refresh frequency, the first control unit switches from the off state to the on state, and the pulse change frequency of the signal provided by the standby start signal terminal is greater than the pulse change frequency of the signal provided by the main start signal terminal. According to the embodiment of the present application, it is conducive to realizing the zoned and frequency-controlled display of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit, a display panel, and a display device. Background Art

[0002] With the continuous advancement of display technology, the refresh rates of display panels have repeatedly reached new highs. For example, refresh rates can reach 165Hz and even exceed 240Hz. Furthermore, reducing power consumption of display panels is also a goal in this field, so low refresh rate displays continue to break through, for example, reaching as low as 1Hz.

[0003] In order to achieve a certain balance between display quality and power consumption, the display panel can support dynamic refresh rates, for example, the display panel can support refresh rates of 1 to 120 Hz. The related art only supports simultaneous switching of the entire display area of ​​the display panel, for example, the entire display area is switched from one refresh rate to another refresh rate at the same time. However, this cannot meet the possibility of multiple display scenarios in the entire display area of ​​the display panel, for example, part of the display area is displayed at a high refresh rate, and part of the display area is displayed at a low refresh rate.

[0004] How to make the display panel display different regions and frequencies becomes a technical problem faced by those skilled in the art. Summary of the Invention

[0005] The embodiments of the present application provide a gate driving circuit, a display panel, and a display device, which are conducive to realizing the zoned and frequency-divided display of the display panel.

[0006] In a first aspect, an embodiment of the present application provides a gate drive circuit, which includes a multi-stage shift register cascaded with each other; the shift register includes a main output module, a transfer control unit, and a first control unit; wherein the main output module is used to alternately output a first level signal and a second level signal under the control of a first node and a second node; the transfer control unit is connected between the main start signal terminal and the first node, and when the first refresh frequency is switched to the second refresh frequency, the transfer control unit switches from the on state to the off state, and the first refresh frequency is greater than the second refresh frequency; the first control unit is connected between the standby start signal terminal and the first node, and when the second refresh frequency is switched to the first refresh frequency, the first control unit switches from the off state to the on state, and the pulse change frequency of the signal provided by the standby start signal terminal is greater than the pulse change frequency of the signal provided by the main start signal terminal.

[0007] In a possible embodiment of the first aspect, the shift register includes a transfer control unit and a second control unit, where the second control unit is configured to reset the potential of the first node to a cutoff level when the transfer control unit is cutoff.

[0008] In a possible embodiment of the first aspect, the shift register further includes:

[0009] A backup signal generating module, used for generating a backup start signal;

[0010] The standby output terminal of the standby signal generating module in the i-th stage shift register serves as the standby start signal terminal connected to the first control unit in the i+1-th stage shift register; wherein i is an integer greater than or equal to 1;

[0011] Preferably, the standby output terminal of the standby signal generating module in the (i+1)th stage shift register is connected to the control terminal of the second control unit in the (i)th stage shift register.

[0012] In a possible embodiment of the first aspect, the backup signal generating module includes:

[0013] A backup output unit, configured to output a backup start signal under the control of the second node and the third node;

[0014] Preferably, the main output module includes a first main output module and a second main output module, the control end of the first main output module is connected to the first node, the input end of the first main output module is connected to the first signal end, the control end of the second main output module is connected to the second node, the input end of the second main output module is connected to the second signal end, and the output end of the first main output module and the output end of the second main output module are connected to the main output end of the main output module;

[0015] Preferably, the backup output unit includes a first backup output unit and a second backup output unit, the control end of the first backup output unit is connected to the third node, the input end of the first backup output unit is connected to the first signal end, the control end of the second backup output unit is connected to the second node, the input end of the second backup output unit is connected to the second signal end, and the output end of the first backup output unit and the output end of the second backup output unit are connected to the backup output end of the backup output module.

[0016] In a possible embodiment of the first aspect, the shift register further includes a main startup module, the main startup module and the transfer control unit are connected in series between the main startup signal terminal and the first node, and the main startup module is configured to transmit a signal from the main startup signal terminal to the first node;

[0017] The backup signal generating module further includes a backup starting unit connected between the backup starting signal terminal and the third node, and the backup starting unit is used to transmit the signal of the backup starting signal terminal to the third node;

[0018] Preferably, the signals of the main start signal terminal and the backup start signal terminal connected to the first stage shift register are the same;

[0019] Preferably, the shift register further comprises a main mutual control module, the main mutual control module being used to enable the first node and the second node to control each other;

[0020] The backup signal generation module further includes a backup mutual control unit, which is used to enable the second node and the third node to control each other;

[0021] Preferably, the shift register further includes a second node control module for controlling the potential of the second node.

[0022] Based on the same inventive concept, in a second aspect, an embodiment of the present application further provides a display panel, comprising a gate driving circuit as described in any embodiment of the first aspect.

[0023] In a possible embodiment of the second aspect, the display panel includes a first display area and a second display area, each of the first display area and the second display area includes multiple rows of pixel circuits, and the pixel circuits are connected to a main output terminal of the main output module;

[0024] The transfer control unit is controlled by a first control signal, and the first control unit is controlled by a second control signal;

[0025] When the screen refresh frequency of the first display area is the first refresh frequency, the screen refresh frequency of the second display area is the second refresh frequency, and the refresh frequency is switched from the first refresh frequency to the second refresh frequency, the first control signal received by the multiple shift registers connected to the pixel circuits in each row except the last row in the first display area is the on-level, the first control signal received by the multiple shift registers connected to the pixel circuits in the last row in the first display area and the pixel circuits in each row in the second display area is the off-level, the second control signal received by the multiple shift registers connected to the pixel circuits in each row in the first display area is the off-level, and the second control signal received by the multiple shift registers connected to the pixel circuits in each row in the second display area except the last row is the off-level.

[0026] In a possible embodiment of the second aspect, when switching from the second refresh frequency to the first refresh frequency, the first control signal received by the multiple shift registers connected to the pixel circuits in each row in the first display area is a conduction level, the first control signal received by the multiple shift registers connected to the pixel circuits in each row in the second display area is a cut-off level, the second control signal received by the multiple shift registers connected to the pixel circuits in each row in the first display area is a cut-off level, the second control signal received by the multiple shift registers connected to the pixel circuits in each row except the last row in the second display area is a cut-off level, and the second control signal received by the shift register connected to the pixel circuits in the last row in the second display area is a conduction level.

[0027] In a possible embodiment of the second aspect, an operation process of the display panel includes writing data into a subframe and maintaining the subframe;

[0028] In the data writing subframe, the first control signal is at an on level, and the second control signal is at an off level;

[0029] In the hold subframe, the first control signal switches between an on level and an off level, and the second control signal switches between an on level and an off level.

[0030] In a possible embodiment of the second aspect, the display area includes a first edge extending along a first direction, the first display area and the second display area are adjacent to each other in the second direction, and the first direction and the second direction intersect;

[0031] The working scenarios of the display panel include a first scenario and a second scenario. In the first scenario, the minimum distance between the boundary line between the first display area and the second display area and the first edge is d1. In the second scenario, the minimum distance between the boundary line between the first display area and the second display area and the first edge is d2, and d1≠d2.

[0032] Based on the same inventive concept, in a third aspect, an embodiment of the present application further provides a display device, comprising a display panel as described in any embodiment of the second aspect.

[0033] According to the gate drive circuit, display panel and display device provided in the embodiments of the present application, the transmission control unit can control whether the signal at the main start signal end can be transmitted to the first node, and when switching from the first refresh frequency to the second refresh frequency, the transmission control unit can be used to switch from the on state to the off state, so that the first node can start the main output unit at a relatively high first refresh frequency, switch to the first node to start the main output unit at a relatively low second refresh frequency, and then enable the main output unit to output the first level signal and the second level signal alternating at the relatively high first refresh frequency, and switch to output the first level signal and the second level signal alternating at the relatively low second refresh frequency, so that a part of the display area can be driven for display at the first refresh frequency, and another part of the display area can be driven for display at the second refresh frequency.

[0034] The first control unit can control whether the signal at the standby start signal end can be transmitted to the first node, and when switching from the second refresh frequency to the first refresh frequency, the first control unit can be used to switch from the cut-off state to the on state, so that the first node can start the main output unit at a relatively low refresh frequency, switch to the first node to start the main output unit at a relatively high refresh frequency, and then enable the main output unit to output the first level signal and the second level signal alternating at a relatively low refresh frequency, and switch to outputting the first level signal and the second level signal alternating at a relatively high refresh frequency, so that a part of the display area can be driven to display at a lower refresh frequency, and another part of the display area can be driven to display at a lower refresh frequency.

[0035] Therefore, the embodiment of the present application can achieve the effect of partitioning the display panel and displaying at different refresh rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0037] Figure 1 A schematic diagram showing a structure in which a gate driving circuit provided by an embodiment of the present application is disposed in a display panel;

[0038] Figure 2 A schematic diagram showing a circuit structure of a pixel circuit in a display panel provided by an embodiment of the present application is shown;

[0039] Figure 3 A schematic diagram showing a circuit structure of a shift register in a gate drive circuit provided in an embodiment of the present application is shown;

[0040] Figure 4 Another circuit structure diagram of a shift register in a gate drive circuit provided in an embodiment of the present application is shown;

[0041] Figure 5 A schematic diagram showing another circuit structure of a shift register in a gate drive circuit provided in an embodiment of the present application is shown;

[0042] Figure 6 A schematic diagram showing a connection relationship between multiple shift registers in a display panel provided by an embodiment of the present application;

[0043] Figure 7 A schematic diagram showing another circuit structure of a shift register in a gate drive circuit provided in an embodiment of the present application is shown;

[0044] Figure 8A schematic diagram showing a partition structure of a display area of ​​a display panel provided in an embodiment of the present application is shown;

[0045] Figure 9 A timing diagram showing a control signal in a display panel provided by an embodiment of the present application is shown;

[0046] Figure 10 A schematic diagram showing a frame refresh of a display panel provided by an embodiment of the present application is shown;

[0047] Figure 11 A timing diagram showing two refresh frequencies of a display panel provided by an embodiment of the present application;

[0048] Figure 12 A schematic diagram showing a timing sequence of switching the refresh rate of a display panel provided by an embodiment of the present application;

[0049] Figure 13 A schematic diagram showing another partition structure of the display area of ​​the display panel provided in an embodiment of the present application is shown;

[0050] Figure 14 Show Figure 7 A timing diagram of the circuit structure shown;

[0051] Figure 15 Show Figure 7 Another timing diagram of the circuit structure shown;

[0052] Figure 16 Show Figure 7 A simulation timing diagram of the circuit structure shown;

[0053] Figure 17 Show Figure 7 Another simulation timing diagram of the circuit structure shown;

[0054] Figure 18 Show Figure 7 Another simulation timing diagram of the circuit structure shown;

[0055] Figure 19 Another circuit structure diagram of a pixel circuit in a display panel provided by an embodiment of the present application is shown;

[0056] Figure 20 A schematic diagram showing another circuit structure of a shift register in a gate drive circuit provided in an embodiment of the present application is shown;

[0057] Figure 21 A schematic diagram showing another partition structure of the display area of ​​the display panel provided in an embodiment of the present application is shown;

[0058] Figure 22Another timing diagram of control signals in a display panel provided by an embodiment of the present application is shown;

[0059] Figure 23 A schematic structural diagram of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0060] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0061] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0062] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0063] It should be noted that, when an element is described as being “connected” or “electrically connected” to another element, it may be directly connected to the other element, or one or more intervening elements may exist therebetween.

[0064] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0065] Embodiments of the present application provide a gate driving circuit, a display panel, and a display device. Embodiments of the gate driving circuit, the display panel, and the display device will be described below with reference to the accompanying drawings.

[0066] The gate driving circuit provided in the embodiment of the present application may be provided in a display panel, which may be an organic light emitting diode (OLED) display panel or other types of display panels.

[0067] like Figure 1 As shown, the gate driving circuit 10 provided in the embodiment of the present application can be set in the display panel 100, and the gate driving circuit 10 may include a multi-stage shift register VSR connected in cascade. For example, the display panel 100 may also include a pixel circuit 20 and a gate signal line 30, and the gate signal line 30 is connected to the shift register VSR and the pixel circuit 20. The signal output by the shift register VSR can control at least part of the transistors in the pixel circuit 20 to turn on or off, and the pixel circuit 20 can be used to drive the light-emitting element ( Figure 1 (not shown) luminous display.

[0068] The gate driver circuit 10 may be located in the non-display area NA of the display panel, and the pixel circuit 20 may be located in the display area AA of the display panel. The pixel circuit 20 may be arranged in an array along a first direction X and a second direction Y, and a plurality of shift registers VSR may be arranged along the second direction Y. The first direction X may be a row direction, and the second direction Y may be a column direction.

[0069] The pixel circuit 20 may be a 7T1C, 8T1C, 2T1C, 4T2C, etc. structure. For example, "7T1C" means 7 transistors and 1 capacitor, and the same applies to the others. As an example, the pixel circuit 20 may be a 7T1C. The pixel circuit 20 may include: Figure 2 The transistors M1 to M7 and the storage capacitor CsM are shown, wherein: Figure 2In the figure, transistors M1 to M7 are PMOS transistors, VDD represents a first power supply terminal, VSS represents a second power supply terminal, Vref1 represents a first initialization signal, Vref2 represents a second initialization signal, VdaMa represents a data signal, S1 and S2 represent scan signals, and EM represents a light-emitting control signal. For example, the gate drive circuit 10 can be used to output scan signals S1 and S2.

[0070] Figure 2 The 7T1C structure of the pixel circuit shown is merely an example and is not intended to limit the present application.

[0071] like Figure 3 As shown, the shift register may include a main output module 11, a transfer control unit 12, and a first control unit 13. The shift register shown in the drawings of the present application includes the transfer unit 12 and the first control unit 13. It should be noted that the shift register may include the transfer control unit 12, or the shift register may include the first control unit 13, or the shift register may include the transfer unit 12 and the first control unit 13.

[0072] The main output module 11 is used for alternately outputting a first level signal and a second level signal under the control of the first node PU and the second node PD.

[0073] One of the first level signal and the second level signal is at a low level, and the other is at a high level.

[0074] For example, the main output module 11 may include a main output terminal Sout, which may be connected to the gates of at least some transistors in the pixel circuit 20 to control the on or off state of at least some transistors in the pixel circuit. For example, for a PMOS transistor, the on level is a low level, and the off level is a high level. For another example, for an NMOS transistor, the on level is a high level, and the off level is a low level.

[0075] The transmission control unit 12 is connected between the main startup signal terminal SIN and the first node PU. When switching from the first refresh frequency F1 to the second refresh frequency F2, the transmission control unit 12 can be configured to switch from an on state to an off state, where F1 > F2. When the transmission control unit 12 is on, the signal from the main startup signal terminal SIN can be transmitted to the first node PU. When the transmission control unit 12 is off, the signal from the main startup signal terminal SIN is prevented from being transmitted to the first node PU.

[0076] The first control unit 13 is connected between the backup startup signal terminal Backup-IN_n-1 and the first node PU. When the second refresh frequency F2 is switched to the first refresh frequency F1, the first control unit 13 can be switched from the off state to the on state, and the pulse change frequency of the signal provided by the backup startup signal terminal Backup-IN_n-1 is greater than the pulse frequency of the signal provided by the main startup signal terminal SIN. When the first control unit 13 is on, the signal of the backup startup signal terminal Backup-IN_n-1 can be transmitted to the first node PU. When the first control unit 13 is off, the signal of the backup startup signal terminal Backup-IN_n-1 can be prevented from being transmitted to the first node PU.

[0077] It is understood that when switching from the second refresh frequency F2 to the first refresh frequency F1, the transmission control unit 12 can be switched from an off state to an on state, so that the signal of the main start signal terminal SIN can be normally transmitted to the first node PU at the higher first refresh frequency F1. When switching from the first refresh frequency F1 to the second refresh frequency F2, the first control unit 13 can be switched from an on state to an off state.

[0078] The refresh rate indicates the number of times a display panel can display an image per second. For example, if a display area of ​​a display panel has a first refresh rate F1 of 120 Hz, then the number of images that can be displayed in that display area per second is 120. If another display area of ​​the display panel has a second refresh rate F2 of 1 Hz, then the number of images that can be displayed in that display area per second is 1. The higher the refresh rate of the display panel, the greater the stability of the displayed image (picture), that is, the better the display quality. The lower the refresh rate of the display panel, the lower the power consumption.

[0079] The pulse frequency of a signal indicates the number of times per second the signal can provide an on-level state. The backup startup signal terminal Backup-IN_n-1 and the main startup signal terminal SIN are used to provide alternating on-level and off-level states. The pulse frequency of the signal provided by the backup startup signal terminal Backup-IN_n-1 indicates the number of times per second the signal can provide an on-level state, while the pulse frequency of the signal provided by the main startup signal terminal SIN indicates the number of times per second the signal can provide an on-level state.

[0080] According to the gate drive circuit provided in the embodiment of the present application, the transfer control unit 12 can control whether the signal of the main start signal terminal SIN can be transmitted to the first node PU, and when switching from the first refresh frequency F1 to the second refresh frequency F2, the transfer control unit 12 can be used to switch from the on state to the off state, so that the first node PU can start the main output module 11 at a relatively high first refresh frequency F1, and switch to the first node PU to start the main output module 11 at a relatively low second refresh frequency F2, thereby enabling the main output module 11 to output the alternating first level signal and the second level signal at the relatively high first refresh frequency F1, and switch to outputting the alternating first level signal and the second level signal at the relatively low second refresh frequency F2, so that a part of the display area can be driven for display at the first refresh frequency F1, and another part of the display area can be driven for display at the second refresh frequency F2.

[0081] The first control unit 13 can control whether the signal of the backup start signal terminal Backup-IN_n-1 can be transmitted to the first node PU, and when switching from the second refresh frequency F2 to the first refresh frequency F1, the first control unit 13 can be used to switch from the cut-off state to the on state, so that the first node PU can start the main output module 11 at a relatively low refresh frequency, switch to the first node PU to start the main output module 11 at a relatively high refresh frequency, and then enable the main output module 11 to output the first level signal and the second level signal alternating at a relatively low refresh frequency, and switch to outputting the first level signal and the second level signal alternating at a relatively high refresh frequency, so that a part of the display area can be driven for display at a lower refresh frequency, and another part of the display area can be driven for display at a lower refresh frequency.

[0082] It can be seen that the embodiment of the present application can achieve the effect of partitioning the display panel and displaying at different refresh rates.

[0083] The main start signal terminal SIN is used to provide alternating on-level and off-level. The inventors have found that when the transmission control unit 12 is cut off, the off-level of the main start signal terminal SIN cannot be transmitted to the first node PU, which is not conducive to the control stability of the first node PU over the main output unit 11.

[0084] In some embodiments, as Figure 4 As shown, when the shift register includes the transfer control unit 12, the shift register may further include a second control unit 14. The second control unit 14 may reset the potential of the first node PU to a cut-off level when the transfer control unit 12 is cut off. In this way, the control stability of the first node PU over the main output unit 11 can be improved.

[0085] Here, the cutoff level may be a level capable of controlling the main output module 11 to be cut off.

[0086] When switching from the second refresh frequency F2 to the first refresh frequency F1, that is, switching from a relatively low refresh frequency to a relatively high refresh frequency, the backup enable signal terminal Backup-IN_n-1 needs to transmit a signal with a relatively high pulse change frequency to the first node PU. In the gate drive circuit, multiple shift registers are cascaded and need to sequentially output conduction levels to sequentially scan each row of pixel circuits.

[0087] In some embodiments, as Figure 5 As shown, the shift register may further include a backup signal generating module 15, which may be used to generate a backup start signal. The backup signal generating module 15 may include a backup output terminal Backup-IN, and the backup start signal generated by the backup signal generating module 15 may be output through the backup output terminal Backup-IN. Figure 6 As shown, the backup output terminal Backup-IN of the backup signal generation module in the i-th stage shift register VSR_i serves as the backup start signal terminal Backup-IN_n-1 connected to the first control unit in the i+1-th stage shift register VSR_i+1. When the second refresh frequency F2 is switched to the first refresh frequency F1, the backup start signal generated by the backup signal generation module 15 can realize step-by-step control of the first node PU of each shift register, thereby enabling the multi-stage shift register to sequentially output the conduction level to sequentially scan each row of pixel circuits.

[0088] It should be noted that in order to clearly illustrate the connection relationship of the shift registers at each level, Figure 6 The i-1th stage shift register VSR_i-1 is also shown. The connection relationship between the i-1th stage shift register VSR_i and the i-th stage shift register VSR_i is shown in FIG. Figure 6 , I will not go into details here.

[0089] For example, the standby signal generating module 15 may not be affected by the transfer control unit 12, and the pulse change frequency of the standby start signal outputted by it may remain unchanged. The standby signal generating module 15 in each stage of the shift register VSR is capable of outputting a signal with a high refresh frequency. For example, if the second refresh frequency is switched to the first refresh frequency, the standby signal generating module 15 in each stage of the shift register VSR is capable of outputting a signal with the first refresh frequency. As described above, when the transfer control unit 12 is cut off, the cutoff level of the main start signal terminal SIN cannot be transmitted to the first node PU, and the potential of the first node PU can be reset to the cutoff level by the second control unit 14.

[0090] like Figure 6As shown, the backup output terminal Backup-IN of the backup signal generating module in the i+1th stage shift register VSR_i+1 is connected to the control terminal Backup-IN_n+1 of the second control unit in the i-th stage shift register. In this way, when the transmission control unit 12 is cut off, the control of the second control unit can be easily achieved.

[0091] In some embodiments, as Figure 7 As shown, the backup signal generating module 15 may include a backup output unit 151. The backup output unit 151 may be configured to output a backup startup signal under the control of the second node PD and the third node PU_Backup. In this way, the backup output unit 151 and the main output module 11 may share the second node PD, which is beneficial for simplifying the overall structure of the shift register.

[0092] For example, Figure 7 As shown, the main output module 11 may include a first main output module 111 and a second main output module 112. The control terminal of the first main output module 111 is connected to the first node PU, the input terminal of the first main output module 111 is connected to the first signal terminal V1, the control terminal of the second main output module 112 is connected to the second node PD, the input terminal of the second main output module 112 is connected to the second signal terminal V2, and the output terminal of the first main output module 111 and the output terminal of the second main output module 112 are connected to the main output terminal Sout of the main output module 11. In this way, the first main output module 111 and the second main output module 112 can alternately output the first level signal and the second level signal.

[0093] The first signal terminal V1 may be used to alternately provide an on-level and an off-level, and the second signal terminal V2 may be used to provide an off-level.

[0094] One of the on-level and the off-level is a low level, and the other is a high level. For example, for a PMOS transistor, the on-level is a low level, and the off-level is a high level. For another example, for an NMOS transistor, the on-level is a high level, and the off-level is a low level.

[0095] If the signal output by the main output terminal Sout is used to control a PMOS transistor in a pixel circuit, the cutoff level provided by the second signal terminal V2 may be a high level, and the conduction level provided by the first signal terminal V1 may be a low level. Conversely, if the signal output by the main output terminal Sout is used to control an NMOS transistor in a pixel circuit, the cutoff level provided by the second signal terminal V2 may be a low level, and the conduction level provided by the first signal terminal V1 may be a high level.

[0096] This application provides Figure 3In the example of a signal output from the main output terminal Sout for controlling a PMOS transistor in a pixel circuit, the first signal terminal V1 may include a clock signal terminal SCK2, and the second signal terminal V2 may include a high-level signal terminal VGH. The clock signal terminal SCK2 is used to alternate between a high level and a low level. The high-level signal terminal VGH is used to provide a high level. The high level may be approximately +7V, and the low level may be approximately -7V. To facilitate differentiation from other clock signal terminals, the first signal terminal V1 is referred to as the second clock signal terminal SCK2.

[0097] For example, Figure 7 As shown, the backup output unit 151 may include a first backup output unit 1511 and a second backup output unit 1512. The control terminal of the first backup output unit 1511 is connected to the third node PU_Backup, the input terminal of the first backup output unit 1511 is connected to the first signal terminal V1, the control terminal of the second backup output unit 1512 is connected to the second node PD, the input terminal of the second backup output unit 1512 is connected to the second signal terminal V2, and the output terminals of the first backup output unit 1511 and the second backup output unit 1512 are connected to the backup output terminal Backup-IN of the backup output unit 151. In this way, the first and second backup output units 1511 and 1512 can alternately output the first and second level signals.

[0098] In some embodiments, as Figure 7 As shown, the shift register may further include a main start-up module 16 , and the main start-up module 16 and the transfer control unit 12 are connected in series between the main start-up signal terminal SIN and the first node PU. Figure 7 FIG3 illustrates that the transmission control unit 12 is connected between the main startup module 16 and the first node PU, and the main startup module 16 is connected to the main startup signal terminal SIN. It is understood that the transmission control unit 12 can also be connected between the main startup signal terminal SIN and the main startup module 16, and connected to the first node PU through the main startup module 16. In this embodiment of the present application, the main startup module 16 can transmit a signal from the main startup signal terminal SIN to the first node PU to start the main output module 11 to start working.

[0099] like Figure 7 As shown, the backup signal generation module 15 may further include a backup startup unit 152, which is connected between the backup startup signal terminal Backup-IN_n-1 and the third node PU_Backup. In this embodiment of the present application, the backup startup unit 152 can transmit the signal of the backup startup signal terminal Backup-IN_n-1 to the third node PU_Backup to start the backup output unit 151 to start working.

[0100] Exemplarily, the signals of the main start signal terminal SIN and the backup start signal terminal Backup-IN_n-1 connected to the first-stage shift register are the same. For example, a pad may be provided in the non-display area of ​​the display panel, which may be connected to a driver chip. The driver chip may be used to provide an initial start signal. The pad may serve as the main start signal terminal SIN and the backup start signal terminal Backup-IN_n-1 connected to the first-stage shift register.

[0101] In some embodiments, as Figure 7 As shown, the shift register may further include a main mutual control module 17, which is used to control the first node PU and the second node PD. The backup signal generation module 15 also includes a backup mutual control unit 153, which is used to control the second node PD and the third node PU_Backup.

[0102] In some embodiments, as Figure 7 As shown, the shift register further includes a second node control module 18 for controlling the potential of the second node PD.

[0103] A shift register may include multiple transistors. As an example, Figure 7 As shown, the main startup module 16 may include a transistor T1, the main mutual control module 17 includes transistors T2, T3, and T3, the second node control module 18 includes a transistor T5, the first main output module 111 includes a transistor T6, the second main output module 112 includes a transistor T7, the transfer control unit 12 includes a transistor T9, the second control unit 14 includes a transistor T10, the first control unit 13 includes a transistor T11, the first backup output unit 1511 includes a transistor T13, the second backup output unit 1512 includes a transistor T13, the backup startup unit 152 includes a transistor T14, and the backup mutual control unit 153 includes transistors T15, T16, and T17. The shift register may also include a transistor T8. The shift register may also include a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0104] For details on how to connect the various components in the shift register, see Figure 7 , I will not go into details here. Figure 7 In the embodiment, the first clock signal terminal SCK1 and the second clock signal terminal SCK2 are used to stagger and provide alternating high and low levels, the low-level signal terminal VGL is used to provide a low level, and the high-level signal terminal VGH is used to provide a high level. The high level can be around +7V, and the low level can be around -7V.

[0105] Based on the same inventive concept, Figure 1As shown, an embodiment of the present application further provides a display panel 100 , which may include the gate driving circuit 10 described in any one of the above embodiments.

[0106] In some embodiments, as Figure 8 As shown, the display area of ​​the display panel 100 may include a first display area AA1 and a second display area AA2. Each of the first display area AA1 and the second display area AA2 may include multiple rows of pixel circuits, which are connected to the main output terminal Sout of the main output module in the shift register. For example, the display area of ​​the display panel 100 may include two first display areas AA1 and one second display area AA2, with the second display area AA2 located between the two first display areas AA1. For ease of distinction, one of the first display areas AA1 may also be referred to as the first display area AA11, and the other first display area AA1 may also be referred to as the first display area AA12.

[0107] For example, the image refresh rate of the first display area AA11 is the first refresh rate F1, the image refresh rate of the second display area AA2 is the second refresh rate F2, and the image refresh rate of the first display area AA12 is the first refresh rate F1, where F1>F2. For example, if F1 is 120 Hz and F2 is 1 Hz, the refresh rate switching order of the entire display area of ​​the display panel is 120 Hz to 1 Hz to 120 Hz.

[0108] like Figure 7 As shown, the control terminal of the transfer control unit 12 receives the first control signal SW1, and the transfer control unit 12 is turned on or off under the control of the first control signal SW1. The control terminal of the first control unit 13 receives the second control signal SW2, and the first control unit 13 is turned on or off under the control of the second control signal SW2.

[0109] like Figure 9 As shown, when switching from the first refresh frequency F1 to the second refresh frequency F2, the first control signal SW1 received by the multiple shift registers connected to the pixel circuits in each row except the last row in the first display area AA11 is at an on-level, the first control signal SW1 received by the multiple shift registers connected to the pixel circuits in the last row in the first display area AA11 and each row in the second display area AA2 is at an off-level, the second control signal SW2 received by the multiple shift registers connected to the pixel circuits in each row in the first display area AA11 is at an off-level, and the second control signal SW2 received by the multiple shift registers connected to the pixel circuits in each row except the last row in the second display area AA2 is at an off-level. In this way, the first display area AA11 is driven for display at the first refresh frequency F1, and the second display area AA2 is driven for display at the second refresh frequency F2.

[0110] like Figure 9 As shown, when switching from the second refresh frequency F2 to the first refresh frequency F1, the first control signal SW1 received by the multiple shift registers connected to each row of pixel circuits in the second display area AA2 is at an off-level, the first control signal SW1 received by the multiple shift registers connected to each row of pixel circuits in the first display area AA12 is at an on-level, the second control signal SW2 received by the multiple shift registers connected to each row of pixel circuits in the second display area AA2 except for the last row of pixel circuits is at an off-level, the second control signal SW2 received by the shift registers connected to the last row of pixel circuits in the second display area AA2 is at an on-level, and the second control signal SW2 received by the multiple shift registers connected to each row of pixel circuits in the first display area AA12 is at an off-level. In this way, the second display area AA2 is driven for display at the second refresh frequency F2, and the first display area AA11 is driven for display at the first refresh frequency F1.

[0111] For example, the display panel includes a total of 2400 rows of pixel circuits, the first display area AA11 includes the 1st to mth rows of pixel circuits, the second display area AA2 includes the m+1th to n-1th rows of pixel circuits, and the first display area AA12 includes the nth to 2400th rows of pixel circuits.

[0112] The first control signal SW1 received by the multiple shift registers connected to the pixel circuits in the 1st row to the m-1th row is at an on-level, the first control signal SW1 received by the multiple shift registers connected to the pixel circuits in the mth row to the n-1th row is at an off-level, and the first control signal SW1 received by the multiple shift registers connected to the pixel circuits in the nth row to the 2400th row is at an on-level.

[0113] The second control signal SW2 received by the multiple shift registers connected to the pixel circuits in the 1st row to the n-2th row is at the cut-off level, the second control signal SW2 received by the multiple shift registers connected to the pixel circuits in the n-1th row is at the on level, and the second control signal SW2 received by the multiple shift registers connected to the pixel circuits in the nth row to the 2400th row is at the cut-off level.

[0114] Figure 7 and Figure 9 The on-level of the module controlled by the first control signal SW1 and the second control signal SW2 is low level, and the off-level is high level, the high level may be equal to the level of the high level signal terminal VGH, and the low level may be equal to the level of the low level signal terminal VGL.

[0115] In some embodiments, the operation process of the display panel may include a data writing subframe (active frame) and a holding subframe (idle frame). For example, the operation process of each pixel circuit in the display panel may include a data writing subframe (active frame). The operation process of some pixel circuits may also include a holding subframe (idle frame). In the data writing subframe, the data signal (Vdata) can be written to the gate of the driving transistor of the pixel circuit. In the holding subframe, the data signal (Vdata) is no longer written to the gate of the driving transistor of the pixel circuit.

[0116] like Figure 10 As shown, the data writing subframe (active frame) and the holding subframe (idle frame) are first introduced with a refresh frequency of 60 Hz.

[0117] When the refresh rate is 60 Hz, 60 frames are refreshed in 1 second, and the time per frame = 1s / 60 = 16.67ms.

[0118] When the refresh rate is reduced, the frame skipping method is used for scanning drive. Taking 30Hz as an example, the refresh rate is still maintained at 60 times per second, but the data signal (Vdata) is written in the 1st / 3rd / 5th / 7th...57th / 59th odd-numbered frames as data writing subframes (active frames); the data signal (Vdata) is not written in the 2nd / 4th / 6th / 8th...58th / 60th even-numbered frames as holding subframes (Idle Frames). In this way, the row scanning time of 30Hz is consistent with the row scanning time of 60Hz. In addition, Figure 10 VSYNC represents the vertical synchronization signal.

[0119] In some embodiments, as Figure 8 As shown, for example, a display panel includes two first display areas AA1 and one second display area AA2. The second display area AA2 is located between the two first display areas AA1. The image refresh rate of the first display areas AA1 is the first refresh rate F1, and the image refresh rate of the second display areas AA2 is the second refresh rate F2. For example, if F1 is 120 Hz and F2 is 1 Hz, the refresh rate switching sequence of the entire display area is 120 Hz to 1 Hz to 120 Hz.

[0120] like Figure 11As shown, the image refresh frequency of the first display area AA1 is 120HZ, and the working process of the pixel circuit in the first display area AA1 can at least include data writing to the subframe (Active frame). The image refresh frequency of the second display area AA2 is 1HZ, and the working process of the pixel circuit in the second display area AA2 can include data writing to the subframe (Active frame) and holding the subframe (Idle Frame). The refresh frequency switching sequence is 120HZ~1HZ~120HZ, and the gate drive circuit needs to output as follows Figure 12 It is understandable that the main output terminal Sout of the shift register for driving the first display area AA1 needs to output a timing corresponding to 120HZ, and the main output terminal Sout of the shift register for driving the second display area AA2 needs to output a timing corresponding to 1HZ.

[0121] As described above, in the data write subframe, the data signal (Vdata) needs to be written, and in the hold subframe, the data signal (Vdata) is no longer written. To avoid affecting the writing of the data signal during the refresh frequency switching process, in the data write subframe, the first control signal SW1 can be maintained at the on level and the second control signal SW2 can be maintained at the off level. In the hold subframe, the first control signal SW1 switches between the on level and the off level, and the second control signal SW2 switches between the on level and the off level. In other words, the state switching of the transfer control unit 12 and the first control unit 13 both occurs in the hold subframe.

[0122] In an embodiment of the present application, the first control signal SW1 and the second control signal SW2 remain unchanged in the data writing subframe. In this way, in the data writing subframe, the waveforms of the main output terminal Sout of the shift register corresponding to the high refresh frequency display area and the low refresh frequency display area are output normally, and the transformation of the output waveform of the main output terminal Sout of the shift register corresponding to the refresh frequency switching occurs in the maintaining subframe, thereby realizing frequency switching and avoiding affecting the writing of data signals during the refresh frequency switching process.

[0123] Still Figure 8 and Figure 9 As shown in the example, during the data write subframe, the first control signal SW1 can be maintained at the on-level, and the second control signal SW2 can be maintained at the off-level. During the hold subframe, the first control signal SW1 switches from the on-level to the off-level, and then switches from the off-level to the on-level. During the hold subframe, the second control signal SW2 switches from the off-level to the on-level, and then switches from the on-level to the off-level.

[0124] In some embodiments, please refer to Figure 8 and Figure 13The display area AA includes a first edge a1 extending along a first direction X. The first display area AA1 and the second display area AA2 are adjacent to each other in a second direction Y, and the first direction and the second direction intersect. For example, a boundary line between the first display area AA1 and the second display area AA2 is L.

[0125] The working scene of the display panel may include a first scene and a second scene. In the first scene, the minimum distance between the dividing line L and the first edge a1 is d1. In the second scene, the minimum distance between the dividing line L and the first edge a1 is d2, and d1≠d2.

[0126] In this way, the partition positions may not be fixed, and the partition positions of display areas with different refresh rates may be dynamically adjusted according to scene requirements and / or display images.

[0127] Exemplarily, the first control signal SW1 and the second control signal SW2 can be synchronized with scene requirements or picture requirements. For example, according to the scene requirements or picture requirements, the positions of display areas with different refresh frequencies can be determined, and then the levels of the first control signal SW1 and the second control signal SW2 can be determined according to the positions of the display areas with different refresh frequencies.

[0128] In order to better understand that the shift register provided in the embodiment of the present application can realize the switching of the refresh frequency, the following Figure 7 The circuit structure shown illustrates the working process of the shift register.

[0129] Please refer to Figure 7 and Figure 14 As shown, for example, from the stage t1 to the stage t4 , the first control signal SW1 is at a low level, and the second control signal SW2 is at a high level.

[0130] In stage t1, the main start signal terminal SIN, the backup start signal terminal Backup-IN_n-1, and the first clock signal terminal SCK1 provide a low level, the second clock signal terminal SCK2 provides a high level, transistors T1, T5, and T14 are turned on, the potentials of the first node PU, the second node PD, and the third node PU_Backup are all low levels, transistors T6, T7, T12, and T13 are turned on, the backup output terminal Backup-IN outputs a high level, and the main output terminal Sout outputs a high level.

[0131] In the t2 stage, the first clock signal terminal SCK1 provides a high level, the main start signal terminal SIN, the backup start signal terminal Backup-IN_n-1, and the second clock signal terminal SCK2 provide a low level, the potentials of the first node PU and the third node PU_Backup maintain a low level, the potential of the second node PD becomes a high level, the transistors T13 and T6 are turned on, the backup output terminal Backup-IN outputs a low level, and the main output terminal Sout outputs a low level.

[0132] In the t3 stage, the main start signal terminal SIN, the backup start signal terminal Backup-IN_n-1, and the second clock signal terminal SCK2 provide a high level, the first clock signal terminal SCK1 provides a low level, the potentials of the first node PU and the third node PU_Backup become high levels, the potential of the second node PD becomes low levels, the transistors T12 and T7 are turned on, the backup output terminal Backup-IN outputs a high level, and the main output terminal Sout outputs a high level.

[0133] In stage t4, the main start signal terminal SIN, the backup start signal terminal Backup-IN_n-1, and the first clock signal terminal SCK1 provide a high level, the second clock signal terminal SCK2 provides a low level, the potentials of the first node PU and the third node PU_Backup maintain a high level, the potential of the second node PD maintains a low level, transistors T12 and T7 are turned on, the backup output terminal Backup-IN outputs a high level, and the main output terminal Sout outputs a high level.

[0134] If the first control signal SW1 and the second control signal SW2 do not change subsequently, the cycle of the phases t3 and t4 begins.

[0135] It can be seen that when the first control signal SW1 is low and the second control signal SW2 is high, that is, when the transfer control unit 12 is turned on and the first control unit 13 is turned off, the backup output terminal Backup-IN and the main output terminal Sout can both output waveforms normally.

[0136] In the case where the frequency of the main output terminal Sout outputting the conduction level needs to be reduced, the transmission control unit 12 can be controlled to be turned off in at least part of the time period, and the first control unit 13 can be controlled to be turned off. Figure 7 and Figure 15 As shown, for example, from the stage t5 to the stage t8 , the first control signal SW1 is at a high level, and the second control signal SW2 is at a high level.

[0137] In the t5 stage, the main start signal terminal SIN, the backup start signal terminal Backup-IN_n-1, and the first clock signal terminal SCK1 provide a low level, the second clock signal terminal SCK2 provides a high level, transistors T1, T5, and T14 are turned on, and the potentials of the second node PD and the third node PU_Backup are both low levels. However, since the transistor T9 is turned off, the first node PU maintains a high level, T12 and T13 are turned on, the backup output terminal Backup-IN outputs a high level, and the main output terminal Sout outputs a high level.

[0138] In the t6 stage, the first clock signal terminal SCK1 provides a high level, the main start signal terminal SIN, the backup start signal terminal Backup-IN_n-1, and the second clock signal terminal SCK2 provide a low level, the first node PU maintains a high level, the potential of the third node PU_Backup maintains a low level, the potential of the second node PD becomes a high level, the transistor T13 is turned on, the backup output terminal Backup-IN outputs a low level, and the main output terminal Sout output maintains a high level.

[0139] In the t7 stage, the main start signal terminal SIN, the backup start signal terminal Backup-IN_n-1, and the second clock signal terminal SCK2 provide a high level, the first clock signal terminal SCK1 provides a low level, the potential of the third node PU_Backup becomes a high level, the signal of the backup start signal terminal Backup-IN_n-1 is a low level, the transistor T10 is turned on, so that the first node PU is stably maintained at a high level, the potential of the second node PD becomes a low level, the transistors T12 and T7 are turned on, the backup output terminal Backup-IN outputs a high level, and the main output terminal Sout outputs a high level.

[0140] In stage t8, the main start signal terminal SIN, the backup start signal terminal Backup-IN_n-1, and the first clock signal terminal SCK1 provide a high level, the second clock signal terminal SCK2 provides a low level, the potentials of the first node PU and the third node PU_Backup maintain a high level, the potential of the second node PD maintains a low level, transistors T12 and T7 are turned on, the backup output terminal Backup-IN outputs a high level, and the main output terminal Sout outputs a high level.

[0141] See also Figure 14 and Figure 15 , the backup signal generating unit 15 is not affected by the transmission control unit 12 and the first control unit 13, and the backup output terminal Backup-IN can always output the waveform normally.

[0142] In the case that the frequency of outputting the conduction level at the main output terminal Sout needs to be increased, the transfer control unit 12 may be controlled to be turned off, and the first control unit 13 may be controlled to be turned on.

[0143] In addition, by controlling the transmission control unit 12 and the first control unit 13 to be turned on or off, switching from a high refresh frequency to a low refresh frequency and from a low refresh frequency to a high refresh frequency can be achieved.

[0144] To further verify the function of the shift register provided in the embodiment of the present application, please refer to Figures 16 to 18 The simulation diagram shown. Figures 16 to 18 Where S1 to S12 represent signals output from the main output terminal Sout of the first-stage shift register to the twelfth-stage shift register.

[0145] Figure 16 The pulse change frequencies of the middle signals S1 , S2 and signals S7 - S12 are equal and greater than the pulse change frequencies of the signals S3 - S6 .

[0146] Figure 17 The pulse change frequencies of the middle signals S1 to S4 and the signals S9 to S12 are equal and greater than the pulse change frequencies of the signals S5 to S8 .

[0147] Figure 18 The pulse change frequencies of the middle signals S1 - S6 and the signals S11 - S12 are equal and greater than the pulse change frequencies of the signals S7 - S10 .

[0148] It can be seen that the embodiment of the present application can achieve the effect of partitioning the display panel and displaying at different refresh rates, and the partition positions can be dynamically adjusted.

[0149] In the above embodiments, the signal output from the main output terminal Sout is used to control the PMOS transistor in the pixel circuit as an example. The signal output from the main output terminal Gout of the gate drive circuit provided in the embodiment of the present application can also be used to control the NMOS transistor in the pixel circuit.

[0150] like Figure 19 As shown, Figure 19 and Figure 2 The similarities are not repeated here. The difference is that transistors M4 and M5 are NMOS transistors, and the other transistors are PMOS transistors. Scan signals S1N and S2N are used to control the NMOS transistors to be turned on or off, and scan signals S1P and S2P are used to control the PMOS transistors to be turned on or off. The signal output by the main output terminal Sout of the gate drive circuit provided in the embodiment of the application may include scan signals S1N and S2N.

[0151] In the case where the signal output from the main output terminal Sout is used to control the NMOS transistor in the pixel circuit, such as Figure 20As shown, the first signal terminal V1 may include the clock signal terminal SCK1, and the second signal terminal V2 may include the low level signal terminal VGL. The cutoff level provided by the second signal terminal V2 may be a low level, and the conduction level provided by the first signal terminal V1 may be a high level.

[0152] in addition Figure 20 and Figure 7 The difference is that Figure 20 The transistors shown can all be NMOS transistors. For specific connection methods, see Figure 20 , I will not go into details here.

[0153] In the case where the signal outputted from the main output terminal Sout is used to control the NMOS transistor in the pixel circuit, the timing sequence of the first control signal SW1 and the second control signal SW2 can be as follows: Figure 21 and Figure 22 shown.

[0154] It should be noted that the transistors in the embodiments of the present application may be either NMOS transistors or PMOS transistors. For NMOS transistors, the on-level is a high level and the off-level is a low level. That is, when the gate potential of the NMOS transistor is a high level, the first and second poles are connected, and when the gate potential of the NMOS transistor is a low level, the first and second poles are disconnected. For PMOS transistors, the on-level is a low level and the off-level is a high level. That is, when the gate potential of the PMOS transistor is a low level, the first and second poles are connected, and when the gate potential of the PMOS transistor is a high level, the first and second poles are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, depending on the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present application are general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / off the transistor.

[0155] Based on the same inventive concept, the present application also provides a display device, including the display panel provided by the present application. Figure 23 , Figure 23 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Figure 23 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Figure 23The embodiment only uses a mobile phone as an example to illustrate the display device 1000. It is understandable that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, an in-vehicle display device, or other display device with a display function, and the present application does not impose specific limitations on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0156] While the embodiments described above are not exhaustive, they do not limit the present application to the specific embodiments described. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A gate drive circuit, characterized in that: include: Multi-stage shift registers cascaded with each other; The shift register includes a main output module, a transfer control unit and a first control unit; Wherein, the main output module is used to alternately output a first level signal and a second level signal under the control of the first node and the second node; The transmission control unit is connected between the main start signal terminal and the first node, and switches from an on state to an off state when the first refresh frequency is switched to the second refresh frequency, and the first refresh frequency is greater than the second refresh frequency; The first control unit is connected between the standby start signal terminal and the first node. When the second refresh frequency is switched to the first refresh frequency, the first control unit is switched from an off state to an on state. The pulse change frequency of the signal provided by the standby start signal terminal is greater than the pulse change frequency of the signal provided by the main start signal terminal. The shift register further includes: A backup signal generating module, used for generating a backup start signal; The standby output terminal of the standby signal generating module in the i-th stage shift register serves as the standby start signal terminal connected to the first control unit in the (i+1)-th stage shift register; wherein i is an integer greater than or equal to 1.

2. The gate drive circuit according to claim 1, wherein: The shift register further includes the transfer control unit and a second control unit, wherein the second control unit is configured to reset the potential of the first node to a cut-off level when the transfer control unit is cut off.

3. The gate drive circuit according to claim 1 or 2, characterized in that: The standby output terminal of the standby signal generating module in the shift register at the (i+1)th stage is connected to the control terminal of the second control unit in the shift register at the i-th stage.

4. The gate driving circuit according to claim 3, wherein: The standby signal generating module includes: The backup output unit is configured to output the backup start signal under the control of the second node and the third node.

5. The gate driving circuit according to claim 4, wherein: The main output module includes a first main output module and a second main output module, the control end of the first main output module is connected to the first node, the input end of the first main output module is connected to the first signal end, the control end of the second main output module is connected to the second node, the input end of the second main output module is connected to the second signal end, and the output end of the first main output module and the output end of the second main output module are connected to the main output end of the main output module.

6. The gate driving circuit according to claim 5, wherein: The backup output unit includes a first backup output unit and a second backup output unit, the control end of the first backup output unit is connected to the third node, the input end of the first backup output unit is connected to the first signal end, the control end of the second backup output unit is connected to the second node, the input end of the second backup output unit is connected to the second signal end, and the output end of the first backup output unit and the output end of the second backup output unit are connected to the backup output end of the backup output unit.

7. The gate driving circuit according to claim 4, wherein: The shift register further includes a main start-up module, wherein the main start-up module and the transfer control unit are connected in series between the main start-up signal terminal and the first node, and the main start-up module is used to transmit the signal of the main start-up signal terminal to the first node; The backup signal generating module further includes a backup starting unit connected between the backup starting signal terminal and the third node, and configured to transmit the signal of the backup starting signal terminal to the third node.

8. The gate driving circuit according to claim 7, wherein: The signals at the main start signal terminal and the backup start signal terminal connected to the first-stage shift register are the same.

9. The gate driving circuit according to claim 7, wherein: The shift register further includes a main mutual control module, and the main mutual control module is used to enable the first node and the second node to control each other; The backup signal generation module further includes a backup mutual control unit, and the backup mutual control unit is used to enable the second node and the third node to control each other.

10. The gate driving circuit according to claim 9, wherein: The shift register further includes a second node control module for controlling the potential of the second node.

11. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 10.

12. The display panel according to claim 11, wherein: The display panel includes a first display area and a second display area, each of the first display area and the second display area includes a plurality of rows of pixel circuits, and the pixel circuits are connected to the main output terminal of the main output module; The transfer control unit is controlled by a first control signal, and the first control unit is controlled by a second control signal; When the screen refresh frequency of the first display area is the first refresh frequency, the screen refresh frequency of the second display area is the second refresh frequency, and the refresh frequency is switched from the first refresh frequency to the second refresh frequency, the first control signal received by the multiple shift registers connected to the pixel circuits in other rows except the last row of pixel circuits in the first display area is a conduction level, the first control signal received by the multiple shift registers connected to the last row of pixel circuits in the first display area and the pixel circuits in each row of the second display area is a cut-off level, the second control signal received by the multiple shift registers connected to the pixel circuits in each row of the first display area is a cut-off level, and the second control signal received by the multiple shift registers connected to the pixel circuits in other rows except the last row of pixel circuits in the second display area is a cut-off level.

13. The display panel according to claim 12, wherein: When switching from the second refresh frequency to the first refresh frequency, the first control signal received by the multiple shift registers connected to each row of pixel circuits in the first display area is a conduction level, the first control signal received by the multiple shift registers connected to each row of pixel circuits in the second display area is a cut-off level, the second control signal received by the multiple shift registers connected to each row of pixel circuits in the first display area is a cut-off level, the second control signal received by the multiple shift registers connected to each row of pixel circuits in the second display area except the last row of pixel circuits is a cut-off level, and the second control signal received by the shift register connected to the last row of pixel circuits in the second display area is a conduction level.

14. The display panel according to claim 12, wherein: The working process of the display panel includes writing data into a subframe and maintaining the subframe; In the data writing subframe, the first control signal is at an on level, and the second control signal is at an off level; In the holding subframe, the first control signal switches between an on level and an off level, and the second control signal switches between an on level and an off level.

15. The display panel according to claim 12, wherein: The first display area and the second display area include a first edge extending along a first direction, the first display area and the second display area are adjacent to each other in a second direction, and the first direction and the second direction intersect; The working scenarios of the display panel include a first scenario and a second scenario. In the first scenario, the minimum distance between the dividing line between the first display area and the second display area and the first edge is d1. In the second scenario, the minimum distance between the dividing line between the first display area and the second display area and the first edge is d2, and d1≠d2.

16. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 11 to 15.

Images