Logic gate circuit, electronic device, and method for eliminating signal glitch
By adding parallel input pins to the logic gate circuit to form a four-input logic gate device, the problem of increased power consumption caused by glitches in the prior art is solved, and glitches can be effectively eliminated without adding additional logic units.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MAXIO TECHNOLOGY (HANGZHOU) CO LTD
- Filing Date
- 2022-01-27
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies for eliminating glitches in digital circuits can lead to increased power consumption.
By adding two parallel input pins to a logic gate circuit, a four-input logic gate device is formed. The four input pins work together with the output pins to eliminate glitches in the signal.
It effectively eliminates glitches in logic gate circuits and avoids increasing circuit power consumption.
Smart Images
Figure CN116566382B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital circuit technology, and more particularly to a logic gate circuit, electronic device, and method for eliminating signal glitches. Background Technology
[0002] Numerous glitches exist in digital circuit design, often originating from multi-input logic gates such as NAND, NOR, and XOR gates. These glitches can lead to significant unnecessary power consumption and negatively impact the overall performance of the circuit.
[0003] To address the impact of glitches in traditional digital circuits on the overall digital circuit, methods such as isolation logic, transmission path isolation, glitch filtering, and clock gating have been proposed to reduce glitches.
[0004] However, these methods insert additional logic units, leading to increased power consumption in the circuit. Summary of the Invention
[0005] This application provides a logic gate circuit, an electronic device, and a method for eliminating signal glitches, in order to solve the problem that existing glitches elimination methods lead to increased circuit power consumption.
[0006] In a first aspect, this application provides a logic gate circuit, the logic gate circuit comprising:
[0007] First electronic device, second electronic device, third electronic device, and logic gate device;
[0008] The logic gate device includes: a logic gate body, four input pins connected to the logic gate body: a first pin, a second pin, a third pin, and a fourth pin, and an output pin connected to the logic gate body: a fifth pin;
[0009] The third and fourth pins are connected in parallel, the first pin is connected to the output terminal of the first electronic device, the second pin is connected to the output terminal of the second electronic device, and the fifth pin is connected to the input terminal of the third electronic device. The four input pins cooperate with the output pins to eliminate glitches in the signal output by the fifth pin.
[0010] Secondly, this application provides an electronic device including the logic gate circuits described in the first aspect.
[0011] Thirdly, this application provides a method for eliminating signal glitches, the method comprising:
[0012] Identify at least one logic gate to be replaced inside the electronic device, wherein the logic gate to be replaced is one of a NOR gate, OR gate, NAND gate and AND gate with two input pins, and the logic gate to be replaced is a logic gate in the circuit logic stage with a toggle rate greater than a preset value.
[0013] The logic gate to be replaced is replaced with a logic gate device with four input pins, wherein any two of the four input pins of the logic gate device are connected to a high level or a low level to eliminate glitches generated by the signal passing through the logic gate to be replaced.
[0014] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:
[0015] The logic gate circuit provided in this application includes: a first electronic device, a second electronic device, a third electronic device, and a logic gate device; the logic gate device includes: a logic gate body, four input pins connected to the logic gate body: a first pin, a second pin, a third pin, and a fourth pin, and an output pin connected to the logic gate body: a fifth pin; wherein, the third pin and the fourth pin are connected in parallel, the first pin is connected to the output terminal of the first electronic device, the second pin is connected to the output terminal of the second electronic device, and the fifth pin is connected to the input terminal of the third electronic device; the four input pins and the output pin cooperate to eliminate glitches in the signal output by the fifth pin. Thus, unlike the prior art which adds additional logic units to the circuit, the embodiments of this application can modify the original structure of the logic gate device in the logic gate circuit by adding two parallel third pins and a fourth pin to the original first and second pins of the logic gate device. Through the cooperation of the four input pins and the output pin, glitches generated by the logic gate device in the logic gate circuit are eliminated, thereby solving the problem that existing glitch elimination methods lead to increased circuit power consumption. Attached Figure Description
[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0017] Figure 1 A schematic diagram of a logic gate circuit provided in an embodiment of this application;
[0018] Figure 2 A schematic diagram of a logic gate circuit provided in an embodiment of this application;
[0019] Figure 3 A schematic diagram of a logic gate device provided in an embodiment of this application;
[0020] Figure 4 A schematic diagram of a logic gate device provided in an embodiment of this application;
[0021] Figure 5 A schematic diagram of a four-input NAND gate provided for embodiments of this application;
[0022] Figure 6 A schematic diagram of a four-input AND gate provided for embodiments of this application;
[0023] Figure 7 A schematic diagram of a four-input NOR gate provided for an embodiment of this application;
[0024] Figure 8 A schematic diagram of a four-input OR gate provided for an embodiment of this application;
[0025] Figure 9-1 A waveform diagram of a two-input NAND gate provided for an embodiment of this application;
[0026] Figure 9-2 A waveform diagram of a four-input NAND gate provided for an embodiment of this application;
[0027] Figure 10-1 A waveform diagram of a two-input NOR gate provided for an embodiment of this application;
[0028] Figure 10-2 A waveform diagram of a four-input NOR gate provided for an embodiment of this application;
[0029] Figure 11-1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;
[0030] Figure 11-2 A schematic diagram of an array multiplier provided in an embodiment of this application;
[0031] Figure 12 A flowchart illustrating a method for eliminating signal glitches provided in an embodiment of this application.
[0032] Figure label:
[0033] 10 - Logic gate circuit, 11 - First electronic device, 12 - Second electronic device, 13 - Third electronic device, 100 - Logic gate device, 101 - Logic gate body, 110 - First pin, 120 - Second pin, 130 - Third pin, 140 - Fourth pin, 150 - Fifth pin, 200 - Electronic device, F - Falling delay, R - Rising delay. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0035] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0036] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "setting," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0037] The technical solutions provided by various embodiments of this application are described in detail below with reference to the accompanying drawings.
[0038] Figure 1 This is a schematic diagram of a logic gate circuit provided in an embodiment of this application, such as... Figure 1 As shown in the embodiment of this application, the logic gate circuit 10 may include: a first electronic device 11, a second electronic device 12, a third electronic device 13, and a logic gate device 100; the logic gate device 100 may include: a logic gate body 101, four input pins connected to the logic gate body 101: a first pin 110, a second pin 120, a third pin 130, and a fourth pin 140, and an output pin connected to the logic gate body 101: a fifth pin 150;
[0039] The third pin 130 and the fourth pin 140 can be connected in parallel. The first pin 110 can be connected to the output terminal of the first electronic device 11. The second pin 120 can be connected to the output terminal of the second electronic device 12. The fifth pin 150 can be connected to the input terminal of the third electronic device 13. The four input pins can cooperate with the output pins to eliminate glitches in the signal output by the fifth pin 150.
[0040] It is important to understand that Figure 1 The devices shown are only a part of the logic gate circuit 10, which may also include components not shown in the diagram. Figure 1 Other devices shown in the diagram; for example, the logic gate circuit 10 may also include resistors, capacitors or inductors.
[0041] In this embodiment, the logic gate body 101 can be the original structure of the logic gate device 100 except for the input pins and output pins; the logic gate device 100 can be a four-input logic gate device; the input level of the third pin 130 and the input level of the fourth pin 140 can be high at the same time, or the input level of the third pin 130 and the input level of the fourth pin 140 can be low at the same time.
[0042] Optionally, in one embodiment of this application, such as Figure 2 As shown, the first electronic device 11 can be a first logic gate device with two inputs, the second electronic device 12 can be a second logic gate device with two inputs, and the third electronic device 13 can be a third logic gate device with two inputs; the first pin 110 can be connected to the output pin of the first logic gate device, the second pin 120 can be connected to the output pin of the second logic gate device, and the fifth pin 150 can be connected to one of the input pins of the third logic gate device.
[0043] It should be understood that the specific types of the first, second, and third logic gate devices can be configured according to actual application conditions and are not limited here. For example, such as Figure 2 As shown, the first electronic device 11 can be a two-input AND gate, the second electronic device 12 can be a two-input OR gate, and the third electronic device 13 can be a two-input NOR gate.
[0044] In digital systems, signals experience delays as they pass through wiring and logic units. The magnitude of these delays depends on the length of the wiring and the number of logic units, and is also affected by factors such as device manufacturing processes, operating voltage, and temperature. High-to-low level transitions also require a certain transition time. Due to these factors, when the levels of multiple signals change, the outputs of combinational logic change sequentially, not simultaneously, often resulting in incorrect spike signals called "glitch" signals. In digital circuits, a glitch is typically defined as any transition that crosses the logic threshold more than once between samples. It mainly refers to short, regular or irregular pulses in the circuit output waveform that are useless to the design or have other negative impacts; glitches generally need to be removed.
[0045] It is understood that, in one embodiment of this application, since glitches are easily generated in a two-input logic gate device, resulting in high power consumption in the circuit, in order to eliminate the glitches generated by the logic gate device itself, two additional parallel input pins can be added to the original two-input logic gate device to obtain a four-input logic gate device 100.
[0046] The logic gate circuit provided in this application embodiment differs from the prior art in that it adds additional logic units to the circuit. It can modify the original structure of the logic gate device in the logic gate circuit by adding two parallel third and fourth pins to the original first and second pins of the logic gate device. The four input pins cooperate with the output pins to eliminate the glitches generated by the logic gate device in the logic gate circuit, thereby solving the problem that the existing glitches elimination methods will lead to increased circuit power consumption.
[0047] Optionally, in one embodiment of this application, the logic gate body 101 can be a NAND gate, a NOR gate, an AND gate, or an OR gate.
[0048] Figure 3 This is a schematic diagram of a logic gate device provided in an embodiment of this application.
[0049] The following section uses the case where the logic gate body 101 is a NAND gate as an example to further describe the structure of the logic gate device 100 in the logic gate circuit 10, such as... Figure 3 As shown, the logic gate devices provided in the embodiments of this application are merely examples and are not intended to be limiting.
[0050] like Figure 3 As shown, the logic gate body 101 can be a NAND gate, and both the third pin 130 and the fourth pin 140 can be connected to a high level. The high level can be provided by the control signal circuit of the stable output signal 1.
[0051] Specifically, such as Figure 5 As shown, when the logic gate body 101 is a NAND gate, let the first pin 110 be A, the second pin 120 be B, the third pin 130 be C, the fourth pin 140 be D, and the fifth pin 150 be Z; the NAND gate may include: four N-type MOS transistors connected in series and four P-type MOS transistors connected in parallel; the first end of the third pin 130 can be connected to the control signal circuit of the stable output signal 1, the second end of the third pin 130 can be connected to the gate of one of the N-type MOS transistors, and the second end of the third pin 130 can also be connected to the gate of one of the P-type MOS transistors; the first end of the fourth pin 140 can be connected to the control signal circuit of the stable output signal 1, the second end of the fourth pin 140 can be connected to the gate of one of the N-type MOS transistors, and the second end of the fourth pin 140 can also be connected to the gate of one of the P-type MOS transistors.
[0052] In the embodiments of this application, such as Figure 5 As shown, the second terminal (i.e., C) of the third pin 130 can be connected to an N-type MOS transistor (i.e., T). N3 The gate of a MOSFET and a P-type MOSFET (i.e., T) P3 The gate of the fourth pin 140 is connected; the second terminal (i.e., D) of the fourth pin 140 can be connected to an N-type MOS transistor (i.e., T). N4 The gate of a MOSFET and a P-type MOSFET (i.e., T) P4 ) gate connection.
[0053] In one embodiment of this application, such as Figure 5 As shown, a NAND gate circuit can include four N-type MOSFETs connected in series and four P-type MOSFETs connected in parallel. Each input terminal of the NAND gate can be connected to the gate of one N-type and one P-type MOSFET. When any one of the input terminals A, B, C, or D is low, the N-type MOSFET connected to it will be turned off, and the P-type MOSFET connected to it will be turned on, resulting in a high-level output. Only when all four input terminals A, B, C, and D are high will all four N-type MOSFETs in series be turned on and all four P-type MOSFETs in parallel be turned off, resulting in a low-level output.
[0054] In this way, two parallel third and fourth pins can be added to the original two-input NAND gate in the logic gate circuit to make it a four-input NAND gate. The glitches generated by the two-input NAND gate itself can be eliminated by the four-input NAND gate, and a high level can be input through the third and fourth pins, so as not to affect the function of the NAND gate itself.
[0055] Similarly, in one embodiment of this application, the logic gate body 101 can be an AND gate, and both the third pin 130 and the fourth pin 140 can be connected to a high level, wherein the high level can be provided by the control signal circuit of the stable output signal 1.
[0056] Specifically, such as Figure 6 As shown, when the logic gate body 101 is an AND gate, let the first pin 110 be A, the second pin 120 be B, the third pin 130 be C, the fourth pin 140 be D, and the fifth pin 150 be Z; the AND gate may include: four N-type MOS transistors connected in series, four P-type MOS transistors connected in parallel, and one P-type MOS transistor and one N-type MOS transistor connected in parallel; since the one P-type MOS transistor and one N-type MOS transistor connected in parallel can be NOT gates, the AND gate can be composed of one NAND gate and one NOT gate.
[0057] Among them, such as Figure 6 As shown, the first end of the third pin 130 can be connected to the control signal circuit of the stable output signal 1, the second end of the third pin 130 can be connected to the gate of one of the four N-type MOS transistors connected in series, and the second end of the third pin 130 can also be connected to the gate of one of the four P-type MOS transistors connected in parallel; the first end of the fourth pin 140 can be connected to the control signal circuit of the stable output signal 1, the second end of the fourth pin 140 can be connected to the gate of one of the four N-type MOS transistors connected in series, and the second end of the fourth pin 140 can also be connected to the gate of one of the four P-type MOS transistors connected in parallel.
[0058] In the embodiments of this application, such as Figure 6 As shown, the second terminal (i.e., C) of the third pin 130 can be connected to an N-type MOS transistor (i.e., T). N3 The gate of a MOSFET and a P-type MOSFET (i.e., T) P3 The gate of the fourth pin 140 is connected; the second terminal (i.e., D) of the fourth pin 140 can be connected to an N-type MOS transistor (i.e., T). N4 The gate of a MOSFET and a P-type MOSFET (i.e., T) P4 The gate connection of the N-type MOSFET is as follows: When the input level is high, the N-type MOSFET can be turned on and the P-type MOSFET can be turned off; when the input level is low, the P-type MOSFET can be turned on and the N-type MOSFET can be turned off.
[0059] In this way, two parallel third and fourth pins can be added to the original two-input AND gate in the logic gate circuit to make it a four-input AND gate. The glitches generated by the two-input AND gate itself can be eliminated by the four-input AND gate, and a high level can be input through the third and fourth pins, so as not to affect the function of the AND gate itself.
[0060] Figure 4 This is a schematic diagram of a logic gate device provided in an embodiment of this application.
[0061] The following section uses the case where the logic gate body 101 is a NOR gate as an example to further describe the structure of the logic gate device 100 in the logic gate circuit 10, such as... Figure 4 As shown, the logic gate devices provided in the embodiments of this application are merely examples and are not intended to be limiting.
[0062] like Figure 4 As shown, the logic gate body 101 can be a NOR gate, and both the third pin 130 and the fourth pin 140 can be connected to a low level. The low level can be provided by a control signal circuit that outputs a stable signal 0.
[0063] In this embodiment of the application, both the third pin 130 and the fourth pin 140 can be connected to the control signal circuit of the stable output signal 0, so that the input voltages of the third pin 130 and the fourth pin 140 can be low.
[0064] Specifically, such as Figure 7 As shown, when the logic gate body 101 is a NOR gate, let the first pin 110 be A, the second pin 120 be B, the third pin 130 be C, the fourth pin 140 be D, and the fifth pin 150 be Z; the NOR gate may include: four N-type MOS transistors connected in parallel and four P-type MOS transistors connected in series; the first end of the third pin 130 can be connected to the control signal circuit for the stable output signal 0, the second end of the third pin 130 can be connected to the gate of one of the N-type MOS transistors, and the second end of the third pin 130 can also be connected to the gate of one of the P-type MOS transistors; the first end of the fourth pin 140 can be connected to the control signal circuit for the stable output signal 0, the second end of the fourth pin 140 can be connected to the gate of one of the N-type MOS transistors, and the second end of the fourth pin 140 can also be connected to the gate of one of the P-type MOS transistors.
[0065] It is understandable that, such as Figure 7 As shown, the second terminal (i.e., C) of the third pin 130 can be connected to an N-type MOS transistor (i.e., T). N3 The gate of a MOSFET and a P-type MOSFET (i.e., T)P3 The gate of the fourth pin 140 is connected; the second terminal (i.e., D) of the fourth pin 140 can be connected to an N-type MOS transistor (i.e., T). N4 The gate of a MOSFET and a P-type MOSFET (i.e., T) P4 ) gate connection.
[0066] In one embodiment of this application, such as Figure 7 As shown, a NOR gate circuit can include four N-type MOSFETs connected in parallel and four P-type MOSFETs connected in series. Each input terminal of the NOR gate can be connected to the gate of one N-type and one P-type MOSFET. When any one of the input terminals A, B, C, or D is high, the P-type MOSFET connected to it will be turned off, and the N-type MOSFET connected to it will be turned on, resulting in a low output. Only when all four input terminals A, B, C, and D are low will all four P-type MOSFETs connected in series be turned on and all four N-type MOSFETs connected in parallel be turned off, resulting in a high output.
[0067] In this way, two parallel third and fourth pins can be added to the original two-input NOR gate in the logic gate circuit to make it a four-input NOR gate. The glitches generated by the two-input NOR gate itself can be eliminated by the four-input NOR gate, and a low level can be input through the third and fourth pins, so as not to affect the function of the NOR gate itself.
[0068] Similarly, in one embodiment of this application, the logic gate body 101 can be an OR gate, and the third pin 130 and the fourth pin 140 can both be connected to the control signal circuit of the stable output signal 0, so that the input voltages of the third pin 130 and the fourth pin 140 can both be low level.
[0069] Specifically, such as Figure 8 As shown, when the logic gate body 101 is an OR gate, let the first pin 110 be A, the second pin 120 be B, the third pin 130 be C, the fourth pin 140 be D, and the fifth pin 150 be Z; the OR gate may include: four N-type MOS transistors connected in parallel, four P-type MOS transistors connected in series, and one P-type MOS transistor and one N-type MOS transistor connected in parallel; since the one P-type MOS transistor and one N-type MOS transistor connected in parallel can be NOT gates, the OR gate may be composed of one NOR gate and one NOT gate.
[0070] Among them, such as Figure 8As shown, the first end of the third pin 130 can be connected to the control signal circuit of the stable output signal 0, the second end of the third pin 130 can be connected to the gate of one of the four N-type MOS transistors connected in parallel, and the second end of the third pin 130 can also be connected to the gate of one of the four P-type MOS transistors connected in series; the first end of the fourth pin 140 can be connected to the control signal circuit of the stable output signal 0, the second end of the fourth pin 140 can be connected to the gate of one of the four N-type MOS transistors connected in parallel, and the second end of the fourth pin 140 can also be connected to the gate of one of the four P-type MOS transistors connected in series.
[0071] In the embodiments of this application, such as Figure 8 As shown, the second terminal (C) of the third pin 130 can be connected to the gate of an N-type MOSFET (TN3) and the gate of a P-type MOSFET (TP3); the second terminal (D) of the fourth pin 140 can be connected to the gate of an N-type MOSFET (TN4) and the gate of a P-type MOSFET (TP4). When the input level is high, the N-type MOSFET is turned on and the P-type MOSFET is turned off; when the input level is low, the P-type MOSFET is turned on and the N-type MOSFET is turned off.
[0072] In this way, two parallel third and fourth pins can be added to the original two-input OR gate in the logic gate circuit to make it a four-input OR gate. The glitches generated by the two-input OR gate itself can be eliminated by the four-input OR gate, and a low level can be input through the third and fourth pins, so as not to affect the function of the OR gate itself.
[0073] It is important to understand that, such as Figure 5-8 As shown, the N-type MOS transistor connected to the second terminal of the third pin 130 and the N-type MOS transistor connected to the second terminal of the fourth pin 140 can be different. That is, the N-type MOS transistor (T) connected to the second terminal of the third pin 130 can be different. N3 The N-type MOS transistor (T) connected to the second terminal of the fourth pin 140 and the fourth pin 140 N4 The P-type MOSFETs connected to the second terminal of the third pin 130 and the second terminal of the fourth pin 140 can also be different. That is, the P-type MOSFET (T) connected to the second terminal of the third pin 130 can be different. P3 The P-type MOS transistor (T) connected to the second terminal of the fourth pin 140 and the fourth pin 140 P4 They are not the same P-type MOSFET.
[0074] To further explain the specific principle by which the logic gate device in the logic gate circuit provided in this application can eliminate the glitches it generates, the following will take the case where the logic gate body 101 is a NAND gate or a NOR gate as an example for specific explanation.
[0075] Figure 9-1 A waveform diagram of a two-input NAND gate provided in an embodiment of this application is shown below. Figure 9-1 As shown, let pin 110 of the two-input NAND gate be A, pin 120 be B, and pin 150 be Z. Because the time when the input level at pin A changes from 0 to 1 (i.e., from low to high) is inconsistent with the time when the input level at pin B changes from 1 to 0 (i.e., from high to low), the input levels at pins A and B sometimes both become high at the same moment. This causes the fall delay F at pin A to precede the rise delay R at pin B, resulting in the output level at pin Z changing from 1 to 0 and then back to 1, i.e., a glitch.
[0076] In one embodiment of this application, using TSMC's (Taiwan Semiconductor Manufacturing Company, TMSC) 12nm process, when the process corner is tt85c, the input transition time is 40 picoseconds, and the output load is 10 ff, the delay values for different cells are shown in Table 1. From the rise-fall delay data of different logic gate devices shown in Table 1, it can be seen that the rise delay R and fall delay F of a two-input NAND gate are approximately the same, so two-input NAND gates are more prone to glitches; while the fall delay F of a four-input NAND gate is significantly larger than its rise delay R.
[0077] unit Rise Delay Descent delay Average delay Two-input NAND gate 55.2 62.9 59.0 Four-input NAND gate 56.5 131.7 94.1 Two-input NOR gate 62.1 58.5 60.3 Four-input NOR gate 133.0 54.5 93.8
[0078] Table 1
[0079] It's important to understand that the rise and fall delays of different logic gate devices follow the same pattern across different nanometer-scale processes: the fall and rise delays of a two-input NAND gate are roughly the same, but the fall delay of a four-input NAND gate is significantly larger than its rise delay; similarly, the fall and rise delays of a two-input NOR gate are roughly the same, but the rise delay of a four-input NOR gate is significantly larger than its fall delay. The units for rise delay, fall delay, and average delay can be picoseconds.
[0080] In this embodiment of the application, the two-input NAND gate can be introduced to two additional pins with high input levels, such as... Figure 9-2 As shown. Figure 9-2 A waveform diagram of a four-input NAND gate provided in an embodiment of this application is shown below. Figure 9-2 Let the first pin 110 of the four-input NAND gate be A, the second pin 120 be B, the third pin 130 be C, the fourth pin 140 be D, and the fifth pin 150 be Z. When replaced with a four-input NAND gate and the two additional pins C and D are input to a high level (i.e., logic set to 1), it is still equivalent to a two-input NAND gate with only pins A and B, and the circuit logic function is not affected. Meanwhile, as shown in Table 1, the fall delay F of the four-input NAND gate nearly doubles, increasing from 62.9 to 131.7; from... Figure 9-2 The above describes how the falling edge of the Z-terminus of a four-input NAND gate is delayed until the glitches disappear, thus achieving the effect of glitch elimination. In digital circuits, the instant the digital level changes from high to low is called the falling edge.
[0081] Optionally, in one embodiment of this application, such as Figure 9-2 As shown, when the input level of the first pin 110 (i.e., terminal A) changes, the output level of the fifth pin 150 (i.e., terminal Z) may have a falling delay F; when the input level of the second pin 120 (i.e., terminal B) changes, the output level of the fifth pin 150 (i.e., terminal Z) may have a rising delay R; for the time period in which the same glitch occurs, the end time of the falling delay F may be after the end time of the rising delay R. In this case, the falling edge of the Z terminal of the four-input NAND gate is delayed until the glitch disappears, thereby eliminating the glitch generated by the two-input NAND gate.
[0082] The difference between the end time and the start time of the rise delay R can be a fixed value; similarly, the difference between the end time and the start time of the fall delay F can be a fixed value. In other words, after replacing a two-input NAND gate with a four-input NAND gate, the values of the rise delay R and fall delay F at the output of the four-input NAND gate can be fixed. For example, as shown in Table 1, the rise delay R of the four-input NAND gate can be 56.5 picoseconds, and the fall delay F can be 131.7 picoseconds.
[0083] In one embodiment of this application, the same principle applies to a two-input NOR gate. Figure 10-1 A waveform diagram of a two-input NOR gate provided in an embodiment of this application is shown below. Figure 10-1As shown, let the first input pin 110 of the two-input NOR gate be A, the second input pin 120 be B, and the fifth output pin 150 be Z. The glitch occurs because the input levels at terminals A and B of the NOR gate are both low at the same time. As can be seen from Table 1, the falling delay and rising delay of the two-input NOR gate are approximately the same, causing the Z terminal of the NOR gate to jump from 0 to 1 and then back to 0.
[0084] Figure 10-2 A waveform diagram of a four-input NOR gate provided in an embodiment of this application is shown below. Figure 10-2 As shown, let the first pin 110 of the four-input NOR gate be A, the second pin 120 be B, the third pin 130 be C, the fourth pin 140 be D, and the fifth pin 150 be Z. In this embodiment, by replacing the two-input NOR gate with a four-input NOR gate and setting the two additional pins C and D to low level (i.e., logic 0), it is still equivalent to a two-input NOR gate and will not affect the logic function of the circuit. As can be seen from Table 1, the rise delay of the four-input NOR gate increases by nearly double, from 62.1 to 133.0; Figure 10-2 As shown in the waveform diagram of the four-input NOR gate, the increased rise delay of the four-input NOR gate helps to eliminate glitches.
[0085] Optionally, in one embodiment of this application, such as Figure 10-2 As shown, when the input level of the first pin 110 (i.e., terminal A) changes, the output level of the fifth pin 150 (i.e., terminal Z) experiences a fall delay F; when the input level of the second pin 120 (i.e., terminal B) changes, the output level of the fifth pin 150 (i.e., terminal Z) experiences a rise delay R; for the time period in which the same glitch occurs, the end time of the rise delay R is after the end time of the fall delay F. At this time, the rising edge of the Z terminal of the four-input NOR gate is delayed until the glitch disappears, thereby eliminating the glitch generated by the two-input NOR gate.
[0086] Similarly, the difference between the end time and the start time of the rising delay R of the four-input NOR gate can be a fixed value; the difference between the end time and the start time of the falling delay F can also be a fixed value. In other words, after replacing the two-input NOR gate with a four-input NOR gate, the values of the rising delay R and falling delay F at the output of the four-input NOR gate can be fixed. For example, as shown in Table 1, the rising delay R of the four-input NOR gate can be 133.0 picoseconds, and the falling delay F can be 54.5 picoseconds.
[0087] Figure 11-1This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 11-1 As shown, the electronic device 200 provided in this application embodiment may include logic gate circuits 10.
[0088] In this embodiment of the application, all target logic gates inside the electronic device 200 can be four-input logic gate devices, or, as... Figure 11-1 As shown, at least one key logic gate inside the electronic device 200 can be a logic gate device with four input pins.
[0089] The target logic gate and the key logic gate can be one of NOR gate, OR gate, NAND gate, and AND gate, respectively. The key logic gate can be a logic gate in the circuit logic pre-stage with a toggle rate greater than a preset value. The logic gate in the circuit logic pre-stage can be understood as the logic gate in the pre-stage stage near the input terminal of the logic gate circuit 10. The logic gate with a toggle rate greater than the preset value can be understood as a logic gate that toggles more than a preset number of times within the same period. A signal transition from 0 to 1 or from 1 to 0 can be called one toggle. The magnitude of the preset value can be set according to practical experience and is not limited here.
[0090] Understandably, in the operational logic of digital circuits, all two-input logic gates that generate glitches in the logic gate circuits of electronic devices can be replaced with four-input logic gates; alternatively, two-input logic gates with a high flip rate in the logic gate circuits of electronic devices can be replaced with four-input logic gates.
[0091] For example, the electronic device 200 can be a multiplier. A multiplier is an electronic device that performs the multiplication of two uncorrelated analog signals; it can multiply two binary numbers and is composed of more basic adders. Multipliers can be implemented using a series of computer arithmetic techniques. Multipliers are not only the main basic units for analog operations such as multiplication, division, exponentiation, and root extraction, but are also widely used in electronic communication systems for modulation, demodulation, mixing, phase detection, and automatic gain control; they can also be used for filtering, waveform shaping, and frequency control, making them a versatile functional circuit.
[0092] Optionally, in one embodiment of this application, when the electronic device 200 is an array multiplier, the key logic gate may include an AND gate in the partial product operation logic of the preceding stage of the circuit logic; when the electronic device 200 is a Wallace multiplier, the key logic gate may include an AND gate in the partial product operation logic of the preceding stage of the circuit logic.
[0093] Figure 11-2This is a schematic diagram of an array multiplier provided in an embodiment of this application, as shown below. Figure 11-2 As shown, the dashed arrows can represent the carry propagation path in the array multiplier. For example, a0b0, a1b0, a2b0, and a3b0 in the figure can be represented as AND gates in the array multiplier.
[0094] When eliminating signal glitches, some of the logic gates with larger glitches in array multipliers or Wallace multipliers can be replaced with logic gates with four input pins. For example, ... Figure 11-2 As shown, when the electronic device 200 is an array multiplier, the two input pins with a higher toggle rate in the array multiplier can be ANDed with a gate (e.g., Figure 11-2 The AND gate in the dashed box can be replaced with an AND gate with four input pins as in the previous embodiment. The AND gate with a larger flip rate can be an AND gate in the partial product operation logic of the stage before the input terminal of the logic gate circuit in the longest path of the carry chain caused by accumulation. For example, if the electronic device 200 is a Wallace multiplier, the two-input pin AND gate with a larger flip rate in the Wallace multiplier can be replaced with an AND gate with four input pins as in the previous embodiment. The AND gate with a larger flip rate can be an AND gate in the partial product operation logic of the stage before the circuit logic.
[0095] In the operational logic of digital circuits, such as the partial product generation circuit in a multiplier, which includes a large number of two-input NAND and NOR gates, optimizing this unit can significantly reduce glitches in the operational logic, thereby optimizing and eliminating glitches in the overall circuit. It's important to understand that this approach can be applied to many operational logic devices besides multipliers.
[0096] It should be noted that some two-input logic gates with large glitches in the logic gate circuits of electronic devices can be replaced with four-input logic gates. The specific number of replacements can be set according to the actual application and is not limited here.
[0097] In one embodiment of this application, the size of the glitches generated by a two-input logic gate device can be eliminated by replacing it with a four-input logic gate device. However, if the input of the four-input logic gate device increases after replacement, causing the glitches to widen, then the glitches cannot be eliminated. In other words, the glitches vary depending on the input size of the electronic device in which the logic gate circuit is located.
[0098] The electronic device provided in this application embodiment can replace the original two-input logic gate device in the logic gate circuit of the electronic device with a four-input logic gate device. By cooperating with the output pin of the four-input logic gate device, the glitches generated by the two-input logic gate device itself can be eliminated. Furthermore, by introducing two additional pins to input high and low levels, the function of the logic gate device itself is not affected.
[0099] This application also provides a method for eliminating signal glitches, which can be applied to the logic gate circuit provided in this application. The method for eliminating signal glitches provided in this application can be executed by the logic gate device 100 in the logic gate circuit 10.
[0100] Figure 12 A flowchart illustrating a method for eliminating signal glitches provided in an embodiment of this application. Figure 12 As shown, the method for eliminating signal glitches may include:
[0101] Step 1210: Identify at least one logic gate to be replaced inside the electronic device, wherein the logic gate to be replaced is one of a NOR gate, OR gate, NAND gate and AND gate with two input pins, and the logic gate to be replaced is a logic gate in the circuit logic stage with a toggle rate greater than a preset value.
[0102] It is understood that the logic gate to be replaced can be a logic gate with two input pins that generate large glitches inside the electronic device; the logic gate in the circuit's pre-stage can be understood as the logic gate in the pre-stage near the input terminal of the logic gate circuit 10; the logic gate with a toggle rate greater than a preset value can be understood as a logic gate with a toggle number greater than a preset number within the same period, wherein a signal transition from 0 to 1 or from 1 to 0 can be called a toggle; the magnitude of the preset value can be set according to actual experience and is not limited here.
[0103] Step 1220: Replace the logic gate to be replaced with a logic gate device with four input pins. Any two of the four input pins of the logic gate device are connected to a high level or a low level to eliminate glitches generated by the signal passing through the logic gate to be replaced.
[0104] In this embodiment of the application, connecting any two of the four input pins of the logic gate device to a high level or a low level does not affect the function of the logic gate device itself, so that the replaced four-input-pin logic gate device can eliminate the glitches generated by the signal passing through the logic gate to be replaced.
[0105] The method for eliminating signal glitches provided in this application differs from existing technologies that add extra logic units to the circuit. It modifies the original structure of the logic gate device in the logic gate circuit by adding two parallel third and fourth pins to the original first and second pins of the logic gate device. Depending on the type of the logic gate, the two additional pins are connected to either a high or low level. The four input pins cooperate with the output pins to eliminate glitches generated by the signal passing through the logic gate to be replaced. Unlike existing technologies that introduce complex logic units into the circuit, this method solves the problem of increased power consumption caused by existing glitch elimination methods, making it a more practical method for filtering glitches. Furthermore, it does not affect the functionality of the logic gate device itself in the logic gate circuit.
[0106] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0107] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0108] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0109] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0110] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.
[0111] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.
[0112] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.
[0113] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0114] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0115] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
Claims
1. A logic gate circuit, characterized in that, include: First electronic device, second electronic device, third electronic device, and logic gate device; The logic gate device includes: a logic gate body, four input pins connected to the logic gate body: a first pin, a second pin, a third pin, and a fourth pin, and an output pin connected to the logic gate body: a fifth pin; The third and fourth pins are connected in parallel. The first pin is connected to the output of the first electronic device, the second pin is connected to the output of the second electronic device, and the fifth pin is connected to the input of the third electronic device. The four input pins cooperate to eliminate glitches in the signal output from the fifth pin. Specifically, when the input levels of the first and second pins are both high at the same time, the input levels of the third and fourth pins are also high. Conversely, when the input levels of the first and second pins are both low at the same time, the input levels of the third and fourth pins are also low.
2. The logic gate circuit according to claim 1, characterized in that, The logic gate body is a NAND gate, or an AND gate; both the third pin and the fourth pin are connected to a high level.
3. The logic gate circuit according to claim 1, characterized in that, The logic gate body is a NOR gate, OR gate, or OR gate; the third pin and the fourth pin are both connected to a low level.
4. The logic gate circuit according to claim 2, characterized in that, When the input level of the first pin changes, the output level of the fifth pin experiences a falling delay; when the input level of the second pin changes, the output level of the fifth pin experiences a rising delay; the end time of the falling delay is after the end time of the rising delay.
5. The logic gate circuit according to claim 3, characterized in that, When the input level of the first pin changes, the output level of the fifth pin experiences a falling delay; when the input level of the second pin changes, the output level of the fifth pin experiences a rising delay; the end time of the rising delay is after the end time of the falling delay.
6. The logic gate circuit according to claim 4 or 5, characterized in that, The difference between the end time of the rising delay and the start time of the rising delay is a fixed value; the difference between the end time of the falling delay and the start time of the falling delay is a fixed value.
7. An electronic device, characterized in that, Includes the logic gate circuits described in any one of claims 1-6.
8. The electronic device according to claim 7, characterized in that, All target logic gates inside the electronic device are four-input pin logic gate devices, or at least one key logic gate inside the electronic device is a four-input pin logic gate device. Wherein, the target logic gate and the key logic gate are one of NOR gate, OR gate, NAND gate and AND gate, respectively. The key logic gate is a logic gate in the circuit logic pre-stage with a flip rate greater than a preset value. The logic gate in the circuit logic pre-stage is the logic gate in the pre-stage of the logic gate circuit that is close to the input terminal of the logic gate circuit.
9. The electronic device according to claim 8, characterized in that, In the case that the electronic device is an array multiplier, the key logic gate includes the AND gate in the partial product operation logic of the circuit logic preceding it; In the case that the electronic device is a Wallace multiplier, the key logic gate includes the AND gate in the partial product operation logic of the circuit logic preceding it.
10. A method for eliminating signal glitches, applied to the electronic device of claim 7, characterized in that, The method includes: Identify at least one logic gate to be replaced inside the electronic device, wherein the logic gate to be replaced is one of a NOR gate, OR gate, NAND gate and AND gate with two input pins, and the logic gate to be replaced is a logic gate in the circuit logic stage with a toggle rate greater than a preset value. The logic gate to be replaced is replaced with a logic gate device with four input pins, wherein any two of the four input pins of the logic gate device are connected to a high level or a low level to eliminate glitches generated by the signal passing through the logic gate to be replaced.