Receiver circuit and signal processing method

Abstract

The application discloses a receiver circuit and a signal processing method. The receiver circuit comprises a comparison circuit, a filtering circuit, a filtering time length control circuit and a driving stage circuit. The comparison circuit is used for obtaining a receiver input signal and comparing the receiver input signal with a first threshold voltage and a second threshold voltage respectively to obtain a first voltage comparison result and a second voltage comparison result. The filtering circuit comprises a first filtering circuit and a second filtering circuit and is used for filtering the first voltage comparison result. The filtering time length control circuit is used for controlling a state of the second filtering circuit according to the second voltage comparison result to adjust a total filtering time length of the filtering circuit. The driving stage circuit is used for generating a receiver output signal according to the filtered first voltage comparison result and outputting the receiver output signal through an output port of the receiver. The application prolongs the total filtering time length of the filtering circuit, enhances the anti-interference capability of the receiver and solves the problem that the receiver is easily affected by ISO pulses. In addition, the whole circuit structure is simple and the cost is low.

Description

Technical Field

[0001] This invention relates to the field of receiver anti-interference technology, specifically to a receiver circuit and signal processing method. Background Technology

[0002] A typical receiver circuit generally includes a comparator circuit, a filter circuit, and a driver stage circuit. The comparator compares the input signal with a threshold voltage and outputs the comparison result; the filter circuit filters the comparison result output by the comparator to remove glitches; and the driver stage circuit generates the receiver output signal. However, because the transmission time of the receiver circuit is limited by the communication protocol, the interference immunity achieved by the filter circuit is limited.

[0003] Existing technology (such as CN202364205U) proposes a receiver circuit that adds an input comparator, a signal conditioning circuit, and a limiting circuit. The input comparator detects a low voltage on the input signal, and the signal conditioning circuit drives the filtered signal to a specific value to shorten the length of short-time pulse waveform interference at the output of the first comparator. Simultaneously, the limiting circuit detects and removes short-time pulse waveform interference to generate a limiter output signal. The limiter output signal is received by a driver block, which outputs the receiver output signal. The receiver output signal does not contain short-time pulse waveform interference and has a delay of no more than 7.5μs, thus providing immunity to ISO pulses. However, the added signal conditioning and limiting circuits require additional high-voltage transistors and diodes, sacrificing cost.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a receiver circuit and signal processing method to solve the technical problem that existing receivers are susceptible to ISO pulses.

[0006] To achieve the above objectives, embodiments of the present invention provide a receiver circuit, the receiver circuit comprising:

[0007] The comparator circuit is connected to the input port of the receiver and is used to acquire the receiver input signal and compare the receiver input signal with the first threshold voltage and the second threshold voltage respectively to obtain the first voltage comparison result and the second voltage comparison result.

[0008] A filtering circuit is connected to a comparison circuit. The filtering circuit includes a first filtering circuit and a second filtering circuit. Both the first filtering circuit and the second filtering circuit are used to filter the first voltage comparison result.

[0009] The filtering duration control circuit is connected to the second filtering circuit and is used to control the state of the second filtering circuit according to the second voltage comparison result, so as to adjust the total filtering duration of the filtering circuit.

[0010] The driver stage circuit is connected to the filter circuit and the output port of the receiver, respectively. It is used to generate the receiver output signal based on the first voltage comparison result after filtering and output it through the receiver output port.

[0011] In one or more embodiments of the present invention, the comparison circuit includes a first comparator Comp1 and a second comparator Comp2; wherein,

[0012] The non-inverting input of the first comparator Comp1 is connected to the input port of the receiver to acquire the receiver input signal, and the inverting input of the first comparator Comp1 is used to acquire the first threshold voltage V. th1 The output of the first comparator Comp1 is connected to the filter circuit;

[0013] The inverting input of the second comparator Comp2 is connected to the input port of the receiver to acquire the receiver input signal, and the non-inverting input of the second comparator Comp2 is used to acquire the second threshold voltage V. th2 The output of the second comparator Comp2 is connected to the filter duration control circuit;

[0014] Wherein, the first threshold voltage V th1 The second threshold voltage V is greater than 0. th2 Less than 0.

[0015] In one or more embodiments of the present invention, the first filter circuit includes a filter resistor R1 and a filter capacitor C1. The first end of the filter resistor R1 is connected to a comparator circuit to receive a first voltage comparison result. The second end of the filter resistor R1 and the first plate of the filter capacitor C1 are both connected to the input terminal of the drive stage circuit. The second plate of the filter capacitor C1 is connected to ground potential.

[0016] In one or more embodiments of the present invention, the second filter circuit includes a delay resistor R2, which is connected in parallel with the filter duration control circuit, and the first end of the delay resistor R2 is connected to the second end of the filter resistor R1, and the second end of the delay resistor R2 is connected to the input terminal of the driver stage circuit.

[0017] In one or more embodiments of the present invention, the filtering duration control circuit includes a control switch S1, which is connected in parallel with a delay resistor R2. The control terminal of the control switch S1 receives a second voltage comparison result so that the control switch S1 is turned on or off according to the second voltage comparison result.

[0018] In one or more embodiments of the present invention, the second filter circuit includes a delay capacitor C2, which is connected in parallel with the filter capacitor C1. The first plate of the delay capacitor C2 is connected to the filter duration control circuit, and the second plate of the delay capacitor C2 is connected to the ground potential.

[0019] In one or more embodiments of the present invention, the filtering duration control circuit includes a control switch S2, which is connected in series with a delay capacitor C2. The control terminal of the control switch S2 receives a second voltage comparison result so that the control switch S2 is turned on or off according to the second voltage comparison result.

[0020] In one or more embodiments of the present invention, the second filter circuit includes a delay resistor R2 and a delay capacitor C2. The delay resistor R2 is connected in parallel with the filter duration control circuit, and the first end of the delay resistor R2 is connected to the second end of the filter resistor R1. The second end of the delay resistor R2 is connected to the input terminal of the drive stage circuit. The delay capacitor C2 is connected in parallel with the filter capacitor C1, and the first plate of the delay capacitor C2 is connected to the filter duration control circuit. The second plate of the delay capacitor C2 is connected to ground potential.

[0021] In one or more embodiments of the present invention, the filtering duration control circuit includes a control switch S1 and a control switch S2. The control switch S1 is connected in parallel with the delay resistor R2, and the control switch S2 is connected in series with the delay capacitor C2. The control terminals of the control switches S1 and S2 both receive a second voltage comparison result so that the control switches S1 and S2 are turned on or off according to the second voltage comparison result.

[0022] Wherein, the delay capacitor C2 is one of MIM capacitor, MOM capacitor, MOS capacitor or VAR capacitor; the control switch S1 and control switch S2 are one of NMOS switch, PMOS switch or CMOS complementary switch.

[0023] In another aspect of the invention, a signal processing method is also provided, the method comprising:

[0024] S1. Compare the receiver input signal with the first threshold voltage and the second threshold voltage respectively to obtain the first voltage comparison result and the second voltage comparison result, wherein the first threshold voltage is greater than 0 and the second voltage threshold voltage is less than 0;

[0025] S2. Filter the first voltage comparison result and control the total filtering time according to the second voltage comparison result;

[0026] S3. Generate the receiver output signal based on the filtered first voltage comparison result and output it through the receiver's output port.

[0027] Compared with the prior art, the receiver circuit and signal processing method according to the embodiments of the present invention enhance the anti-interference capability of the receiver by detecting the negative voltage of the receiver input signal and adjusting the total filtering time of the entire filtering circuit according to the detection result, thus solving the problem that the receiver is susceptible to ISO pulses; moreover, the entire circuit structure is simple and the cost is low. Attached Figure Description

[0028] Figure 1a The waveform diagram of the ISO-1 pulse in the prior art;

[0029] Figure 1b This is an exemplary parameter configuration table for ISO-1 pulse testing in the prior art;

[0030] Figure 2 This is a schematic diagram of the receiver circuit in this invention;

[0031] Figure 3 This is a flowchart of the signal processing method in this invention;

[0032] Figure 4 This is a schematic diagram of the filtering duration control circuit in Embodiment 1 of the present invention;

[0033] Figure 5 This is a schematic diagram of the filtering duration control circuit in Embodiment 2 of the present invention;

[0034] Figure 6 This is a schematic diagram of the filtering duration control circuit in Embodiment 3 of the present invention;

[0035] Figure 7 This is a waveform comparison diagram of a receiver circuit in the prior art and the receiver circuit of the present invention when subjected to ISO pulse interference. Detailed Implementation

[0036] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0037] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0038] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuits. When an element or circuit is said to be "connected to" another element, or "linked" to another element, or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements, and the connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means there are no intermediate elements between the two.

[0039] A Local Interconnect Network (LIN) generally implements a transmitter and a receiver for communication within the network. The receiver circuit is vulnerable to interference on the input signal, which can cause incorrect receiver output. Specifically, the receiver is vulnerable to Radio Frequency (RF) pulses and ISO pulses, resulting in incorrect low states on the receiver output signal.

[0040] ISO pulses are defined in ISO 7637-2, and at the same time, IEC 62228-2 clearly specifies the types of pulses that a LIN receiver needs to be immune to and the interference levels, specifically including ISO-1, ISO-2a, ISO-3a, ISO-3b, etc. Exemplarily, Figure 1a A waveform diagram of an ISO-1 pulse is shown, Figure 1b An exemplary parameter configuration chart for ISO-1 pulse testing is shown. As can be seen from the figure, the ISO-1 pulse is a negative pulse, and this negative pulse will cause the receiver to produce an incorrect low output.

[0041] To solve the problem that the above receiver is vulnerable to ISO pulses, the present invention detects the negative voltage of the receiver input signal and adjusts the total filtering duration of the entire filtering circuit according to the detection result, thereby enhancing the anti-interference ability of the receiver.

[0042] As shown in the figure Figure 2 The present invention specifically discloses a receiver circuit, which includes:

[0043] A comparison circuit 10, connected to the input port of the receiver, for obtaining the receiver input signal and comparing the receiver input signal with a first threshold voltage and a second threshold voltage respectively to obtain a first voltage comparison result and a second voltage comparison result;

[0044] A filtering circuit 20, connected to the comparison circuit 10. The filtering circuit 20 includes a first filtering circuit 21 and a second filtering circuit 22, and both the first filtering circuit 21 and the second filtering circuit 22 are used to filter the first voltage comparison result;

[0045] The filtering duration control circuit 30, connected to the second filtering circuit 22, is configured to control the state of the second filtering circuit 22 according to the second voltage comparison result, so as to adjust the total filtering duration of the filtering circuit 20;

[0046] The driving stage circuit 40, connected to the filtering circuit 20 and the output port of the receiver respectively, is configured to generate a receiver output signal according to the filtered first voltage comparison result and output it through the output port of the receiver.

[0047] See Figure 3 As shown, the present invention also specifically discloses a signal processing method, which includes:

[0048] S1. Compare the receiver input signal with a first threshold voltage and a second threshold voltage respectively to obtain a first voltage comparison result and a second voltage comparison result, wherein the first threshold voltage is greater than 0 and the second voltage threshold is less than 0;

[0049] S2. Filter the first voltage comparison result and control the total filtering duration according to the second voltage comparison result;

[0050] S3. Generate a receiver output signal according to the filtered first voltage comparison result and output it through the output port of the receiver.

[0051] The receiver circuit and the signal processing method of the present invention will be further described below in conjunction with specific embodiments.

[0052] Embodiment 1:

[0053] See Figure 2 As shown, the comparison circuit 10 in this embodiment includes a first comparator Comp1. The non-inverting input terminal of the first comparator Comp1 is connected to the input port of the receiver for obtaining the receiver input signal, and the inverting input terminal of the first comparator Comp1 is used for obtaining the first threshold voltage V th1 , and the output terminal of the first comparator Comp1 is connected to the filtering circuit 20.

[0054] Among them, the first threshold voltage V th1 is greater than 0. Therefore, the first comparator Comp1 is mainly configured to compare the positive voltage signal in the receiver input signal with the first threshold voltage V th1 and output the first voltage comparison result.

[0055] The magnitude of the positive voltage in the receiver input signal is 0 to V BAT , V BAT is the power supply voltage. In this embodiment, the power supply voltage V BAT is 12V; the first threshold voltage V th1 is V BAT / 2.

[0056] The comparator circuit 10 also includes a second comparator Comp2. The inverting input of the second comparator Comp2 is connected to the input port of the receiver to acquire the receiver input signal, and the non-inverting input of the second comparator Comp2 is used to acquire the second threshold voltage V. th2 The output of the second comparator Comp2 is connected to the filter duration control circuit.

[0057] Wherein, the second threshold voltage V th2 The value is less than 0. Therefore, the second comparator Comp2 mainly compares the negative voltage signal in the receiver input signal with the second threshold voltage V. th2 The comparison is performed, and the second voltage comparison result is output.

[0058] In this embodiment, the second threshold voltage V th2 It can be -100V or below.

[0059] In this embodiment, the total filtering time of the filter circuit 20 is controlled by the first filter circuit 21 and the second filter circuit 22. By default, only the first filter circuit 21 participates in filtering. The filtering time control circuit 30 is mainly used to control whether the second filter circuit 22 participates in filtering. When the filtering time control circuit 30 controls the second filter circuit 22 to participate in filtering, the total filtering time of the filter circuit 20 will be extended.

[0060] Specific reference Figure 4 As shown, the first filter circuit 21 in this embodiment adopts an RC filter circuit, which specifically includes a filter resistor R1 and a filter capacitor C1. The first end of the filter resistor R1 is connected to the comparison circuit to receive the first voltage comparison result. The second end of the filter resistor R1 and the first plate of the filter capacitor C1 are both connected to the input end of the drive stage circuit. The second plate of the filter capacitor C1 is connected to the ground potential.

[0061] The first filter circuit 21 is used to filter the first voltage comparison result output by the comparator circuit 10 to filter out glitches. In some other embodiments, the first filter circuit 21 may also adopt a resistor with a capacitor connected in parallel across it, or a resistor with an inductor connected in series, or a circuit structure composed of a capacitor and an inductor, etc., which will not be described in detail here.

[0062] Continue to participate Figure 4 As shown, the second filter circuit 22 in this embodiment includes a delay resistor R2, which is connected in parallel with the filter duration control circuit 30. The first end of the delay resistor R2 is connected to the second end of the filter resistor R1, and the second end of the delay resistor R2 is connected to the input terminal of the driver stage circuit 40.

[0063] The filtering duration control circuit 30 in this embodiment includes a control switch S1. The control switch S1 is arranged in parallel with a delay resistor R2. The control end of the control switch S1 receives the second voltage comparison result so that the control switch S1 is turned on or off according to the second voltage comparison result.

[0064] When the control switch S1 is closed and turned on, the delay resistor R2 participates in filtering, increasing the resistance value in the filtering circuit 20 (becoming the sum of the resistance values of the filtering resistor R1 and the delay resistor R2), thereby increasing the time constant of the filtering circuit 20, extending the total filtering duration of the filtering circuit 20, and further enhancing the anti-interference ability of the receiver.

[0065] Specifically, Figure 7 As shown, due to the limitation of the communication protocol (ISO 17987-4), the transmission duration of the LIN receiver cannot exceed 6 us. Therefore, although the first filtering circuit 21 makes the receiver circuit have a certain anti-interference ability, the anti-interference ability is limited. When the receiver input bus is interfered by ISO pulses, the worst case often occurs when the bus is dominant and is affected by a positive ISO pulse and when the bus is recessive and is affected by a negative ISO pulse. The larger the pulse amplitude and the larger the pulse width, the higher the requirement for the anti-interference ability of the receiver.

[0066] In this embodiment, taking the case of being interfered by an ISO-1 pulse in the bus recessive state as an example, the ISO-1 pulse will drop from 0V to -100V in about 1 us, which will cause the bus to drop from V BAT to -31.7V in 1-2 us. At this time, the duration of the low level output by the first comparator Comp1 lasts for about 5 us. After the second comparator Comp2 detects the negative voltage of the bus, it outputs a high level until the bus exits the negative voltage state. During this period, the control switch S1 of the filtering duration control circuit 30 is closed, increasing the time constant of the filtering circuit 20, extending the total filtering duration of the filtering circuit 20, enabling the receiver to obtain a stronger anti-interference ability, and avoiding the receiver from outputting an error signal.

[0067] Furthermore, the control switch S1 in this embodiment can be an NMOS switch tube, or a PMOS switch tube, or a CMOS complementary switch.

[0068] [[ID=,19]]Embodiment 2:

[0069] The receiver circuit in this embodiment is basically the same as the receiver circuit in Embodiment 1, except that:

[0070] Refer to Figure 5As shown, the second filter circuit 22 in this embodiment includes a delay capacitor C2. The delay capacitor C2 is connected in parallel with the filter capacitor C1. The first plate of the delay capacitor C2 is connected to the filter duration control circuit 30, and the second plate of the delay capacitor C2 is connected to the ground potential.

[0071] The filter duration control circuit 30 in this embodiment includes a control switch S2. The control switch S2 is connected in series with the delay capacitor C2. The control terminal of the control switch S2 receives the second voltage comparison result so that the control switch S2 conducts or turns off according to the second voltage comparison result.

[0072] Similarly, when the control switch S2 is closed and conducts, the delay capacitor C2 participates in filtering, increasing the capacitance value in the filter circuit 20, thereby increasing the time constant of the filter circuit 20, extending the total filtering duration of the filter circuit 20, and further enhancing the anti-interference ability of the receiver.

[0073] Furthermore, the delay capacitor C2 in this embodiment can be a MIM capacitor, or a MOM capacitor, or a MOS capacitor, or a VAR capacitor, etc. The control switch S2 can also be an NMOS switch tube, or a PMOS switch tube, or a CMOS complementary switch.

[0074] Embodiment 3:

[0075] The receiver circuit in this embodiment is basically the same as the receiver circuit in Embodiment 1, except that:

[0076] Refer Figure 6 As shown, the second filter circuit 22 in this embodiment includes a delay resistor R2 and a delay capacitor C2. The delay resistor R2 is connected in parallel with the filter duration control circuit 30. The first end of the delay resistor R2 is connected to the second end of the filter resistor R1, and the second end of the delay resistor R2 is connected to the input end of the drive stage circuit 40; the delay capacitor C2 is connected in parallel with the filter capacitor C1. The first plate of the delay capacitor C2 is connected to the filter duration control circuit 30, and the second plate of the delay capacitor C2 is connected to the ground potential.

[0077] The filter duration control circuit 30 in this embodiment includes a control switch S1 and a control switch S2. The control switch S1 is connected in parallel with the delay resistor R2. The control switch S2 is connected in series with the delay capacitor C2. The control terminals of the control switch S1 and the control switch S2 both receive the second voltage comparison result so that the control switch S1 and the control switch S2 conduct or turn off according to the second voltage comparison result.

[0078] Similarly, when both the control switch S1 and the control switch S2 are closed and conduct, both the delay resistor R2 and the delay capacitor C2 participate in filtering, increasing the time constant of the filter circuit 20, extending the total filtering duration of the filter circuit 20, and further enhancing the anti-interference ability of the receiver.

[0079] Furthermore, in this embodiment, the delay capacitor C2 can also be a MIM capacitor, or a MOM capacitor, or a MOS capacitor, or a VAR capacitor, etc.; the control switch S1 and the control switch S2 can both be NMOS switches, or PMOS switches, or CMOS complementary switches.

[0080] In the above embodiments, the purpose of setting the second filter circuit 22 (delay resistor R or delay capacitor C) is to increase the time constant of the filter circuit 20, thereby extending the total filtering time of the filter circuit 20 and enabling the receiver to have stronger anti-interference capability.

[0081] The filter duration control circuit 30 (control switch) is mainly used to control whether the second filter circuit 22 participates in filtering. When the control switch is closed, the corresponding delay resistor R / delay capacitor C will participate in filtering, thereby extending the total filtering duration of the filter circuit 20.

[0082] As can be seen from the above technical solution, the present invention has the following beneficial effects:

[0083] According to the receiver circuit and signal processing method of the present invention, when the circuit is subjected to an ISO pulse, the negative voltage of the receiver input signal is detected by the second comparator, and the switching transistor in the filtering duration control circuit is closed according to the detection result. At this time, the delay resistor and / or delay capacitor in the filtering duration control circuit will increase the time constant of the filtering circuit, thereby extending the total filtering duration of the filtering circuit, enhancing the anti-interference capability of the receiver, and solving the problem that the receiver is susceptible to ISO pulses; moreover, the entire circuit structure is simple and the cost is low.

[0084] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A receiver circuit, characterized by The receiver circuit comprises: The comparison circuit is connected with the input port of the receiver, and is used for obtaining a receiver input signal, comparing a positive voltage signal of the receiver input signal with a first threshold voltage to obtain a first voltage comparison result, and comparing a negative voltage signal of the receiver input signal with a second threshold voltage to obtain a second voltage comparison result, wherein the first threshold voltage is greater than 0, and the second threshold voltage is less than 0. The filter circuit is connected with the comparison circuit, and comprises a first filter circuit and a second filter circuit, both of which are used for filtering the first voltage comparison result. The filter time length control circuit is connected with the second filter circuit, and is used for controlling a state of the second filter circuit according to the second voltage comparison result, so as to adjust a total filter time length of the filter circuit. The drive stage circuit is connected with the filter circuit and the output port of the receiver respectively, and is used for generating a receiver output signal according to the filtered first voltage comparison result and outputting the receiver output signal through the output port of the receiver.

2. The receiver circuit of claim 1, characterized in that The comparison circuit comprises a first comparator Comp1 and a second comparator Comp2. The in-phase input end of the first comparator Comp1 is connected with the input port of the receiver, for obtaining the receiver input signal, the reverse input end of the first comparator Comp1 is used for obtaining the first threshold voltage V th1 , and the output end of the first comparator Comp1 is connected with the filter circuit. The inverting input end of the second comparator Comp2 is connected with the input port of the receiver, for obtaining the input signal of the receiver, the non-inverting input end of the second comparator Comp2 is used for obtaining the second threshold voltage V th2 , and the output end of the second comparator Comp2 is connected with the filter time length control circuit. the first threshold voltage V th1 greater than 0, the second threshold voltage V th2 less than 0.

3. The receiver circuit of claim 1, wherein, The first filter circuit comprises a filter resistor R1 and a filter capacitor C1, a first end of the filter resistor R1 is connected with the comparison circuit to receive the first voltage comparison result, a second end of the filter resistor R1 and a first plate of the filter capacitor C1 are both connected with an input end of the drive stage circuit, and a second plate of the filter capacitor C1 is connected with a ground potential.

4. The receiver circuit of claim 3, characterized in that The second filter circuit comprises a delay resistor R2, the delay resistor R2 is connected with the filter time length control circuit in parallel, a first end of the delay resistor R2 is connected with the second end of the filter resistor R1, and a second end of the delay resistor R2 is connected with the input end of the drive stage circuit.

5. The receiver circuit of claim 4, characterized in that The filter time length control circuit comprises a control switch S1, the control switch S1 is connected with the delay resistor R2 in parallel, and a control end of the control switch S1 receives the second voltage comparison result so that the control switch S1 is turned on or turned off according to the second voltage comparison result.

6. The receiver circuit of claim 3, wherein, The second filter circuit comprises a delay capacitor C2, the delay capacitor C2 is connected with the filter capacitor C1 in parallel, a first plate of the delay capacitor C2 is connected with the filter time length control circuit, and a second plate of the delay capacitor C2 is connected with the ground potential.

7. The receiver circuit of claim 6, characterized in that The filter time length control circuit comprises a control switch S2, the control switch S2 is connected with the delay capacitor C2 in series, and a control end of the control switch S2 receives the second voltage comparison result so that the control switch S2 is turned on or turned off according to the second voltage comparison result.

8. The receiver circuit of claim 3, wherein, The second filter circuit comprises the delay resistor R2 and the delay capacitor C2, the delay resistor R2 is connected with the filter time length control circuit in parallel, a first end of the delay resistor R2 is connected with the second end of the filter resistor R1, and a second end of the delay resistor R2 is connected with the input end of the drive stage circuit; the delay capacitor C2 is connected with the filter capacitor C1 in parallel, a first plate of the delay capacitor C2 is connected with the filter time length control circuit, and a second plate of the delay capacitor C2 is connected with the ground potential.

9. The receiver circuit of claim 8, characterized in that, The filter duration control circuit comprises control switch S1 and control switch S2, the control switch S1 is arranged in parallel with delay resistor R2, the control switch S2 is arranged in series with delay capacitor C2, and the control ends of the control switch S1 and the control switch S2 all receive the second voltage comparison result so that the control switch S1 and the control switch S2 are turned on or turned off according to the second voltage comparison result.

10. A signal processing method characterized by, The method comprises: S1, comparing a positive voltage signal of a receiver input signal with a first threshold voltage to obtain a first voltage comparison result, and comparing a negative voltage signal of the receiver input signal with a second threshold voltage to obtain a second voltage comparison result, wherein the first threshold voltage is greater than 0, and the second voltage threshold is less than 0; S2, filtering the first voltage comparison result, and controlling the total filter duration according to the second voltage comparison result; S3, generating a receiver output signal according to the filtered first voltage comparison result and outputting the receiver output signal through an output port of the receiver.

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